CY7C1347-100ACT_技术文档

347

CY7C1347

128K x 36 Synchronous-Pipelined Cache RAM

The CY7C1347 I/O pins can operate at either the 2.5V or the

3.3V level, the I/O pins are 3.3V tolerant when V_DDQ= 2.5V.

Features

• Supports 100-MHz bus for Pentium and PowerPC™

operations with zero wait states

• Fully registered inputs and outputs for pipelined oper-

ation

• 128K by 36 common I/O architecture

• 3.3V core power supply

• 2.5V/3.3V I/O operation

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 5.5 ns (for 100-MHz device)

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise is 3.5 ns (166-MHz

device).

The CY7C1347 supports either the interleaved burst se-

quence used by the Intel Pentium processor or a linear burst

sequence used by processors such as the PowerPC. The

burst sequence is selected through the MODE pin. Accesses

can be initiated by asserting either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC) at

clock rise. Address advancement through the burst sequence

is controlled by the ADV input. A 2-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

• User-selectable burst counter supporting Intel Pen-

tium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100 TQFP pinout

• “ZZ” Sleep Mode option and Stop Clock option

• Available in Industrial and Commercial Temperature

ranges

Byte write operations are qualified with the four Byte Write

Select (BW_[3:0]) inputs. A Global Write Enable (GW) overrides

all byte write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed write cir-

cuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to provide prop-

er data during depth expansion, OE is masked during the first

clock of a read cycle when emerging from a deselected state.

Functional Description

The CY7C1347 is a 3.3V, 128K by 36 synchronous-pipelined

cache SRAM designed to support zero-wait-state secondary

cache with minimal glue logic.

MODE

Logic Block Diagram

2

(A_[1;0]

)

Q

CLK

ADV

ADSC

0

BURST

COUNTER

CE

CLR

1

ADSP

Q

15

17

ADDRESS

REGISTER

CE

D

128KX36

MEMORY

ARRAY

A_[16:0]

GW

17

15

DQ[31:24], DP[3]

BYTEWRITE

REGISTERS

D

Q

BWE

BW

3

DQ[23:16], DP[2]

BYTEWRITE

REGISTERS

D

BW

2

DQ[15:8], DP[1]

BYTEWRITE

REGISTERS

Q

BW

1

DQ[7:0], DP[0]

BYTEWRITE

REGISTERS

BW

0

36

CE

1

2

CE

D

Q

ENABLE CE

REGISTER

CE

3

Q

OUTPUT

INPUT

ENABLE DELAY

REGISTER

REGISTERS

CLK

OE

ZZ

SLEEP

CONTROL

DQ_[31:0]

DP_[3:0]

Pentium and Intel are registered trademarks of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05086 Rev. **

Revised September 5, 2001

CY7C1347

Pin Configuration

DP

2

DP

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQ

16

17

DQ

V

15

14

V

DDQ

SSQ

V

SSQ

V

DQ

18

19

DQ

13

12

BYTE2

BYTE1

20

11

21

9

10

V

SSQ

DDQ

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SSQ

DDQ

DQ

22

DQ

V

9

8

23

NC

100-Pin TQFP

CY7C1347

SS

V

DD

NC

V

DD

V

SS

ZZ

DQ

V

DQ

24

25

7

6

V

DDQ

SSQ

V

SSQ

V

DQ

26

27

DQ

V

5

4

3

2

BYTE3

BYTE0

28

29

V

SSQ

DDQ

V

DDQ

V

DQ

30

31

DQ

DP

1

0

DP

3

0

Selection Guide

7C1347-166

7C1347-133

7C1347-100

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

3.5

420

10

4.0

375

10

5.5

325

10

Commercial

Document #: 38-05086 Rev. **

Page 2 of 16

CY7C1347

Pin Definitions

Pin Number

Name

I/O

Description

Address Inputs used to select one of the 64K address locations. Sampled at the

50–44, 81,

82, 99, 100,

32–37

A_[16:0]

Input-

Synchronous rising edge of the CLK if ADSP or ADSC is active LOW, and CE₁, CE₂, and CE₃

are sampled active. A_[1:0]feed the 2-bit counter.

96–93

BW_[3:0]

GW

Input-

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes

Synchronous to the SRAM. Sampled on the rising edge of CLK.

88

Input- Global Write Enable Input, active LOW. When asserted LOW on the rising edge of

Synchronous CLK, a global write is conducted (ALL bytes are written, regardless of the values

on BW_[3:0]and BWE).

87

89

98

BWE

CLK

CE₁

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This

Synchronous signal must be asserted LOW to conduct a byte write.

Input-Clock

Input-

Clock Input. Used to capture all synchronous inputs to the device. Also used to

increment the burst counter when ADV is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

Synchronous conjunction with CE₂and CE₃to select/deselect the device. ADSP is ignored if

CE₁is HIGH.

97

92

86

CE₂

CE₃

OE

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

Synchronous conjunction with CE₁and CE₃to select/deselect the device.

Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

Synchronous conjunction with CE₁and CE₂to select/deselect the device.

Input- Output Enable, asynchronous input, active LOW. Controls the direction of the I/O

Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O

pins are three-stated, and act as input data pins. OE is masked during the first

clock of a read cycle when emerging from a deselected state.

83

84

ADV

Input-

Advance Input signal, sampled on the rising edge of CLK. When asserted, it auto-

Synchronous matically increments the address in a burst cycle.

ADSP

Input- Address Strobe from Processor, sampled on the rising edge of CLK. When assert-

Synchronous ed LOW, A_[16:0]is captured in the address registers. A_[1:0]are also loaded into the

burstcounter. When ADSP andADSCarebothasserted, only ADSPisrecognized.

ASDP is ignored when CE₁is deasserted HIGH.

85

64

ADSC

ZZ

Input-

Address Strobe from Controller, sampled on the rising edge of CLK. When assert-

Synchronous ed LOW, A_[16:0]is captured in the address registers. A_[1:0]are also loaded into the

burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical

Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has

to be LOW or left floating.

30–28,

DQ_[31:0]

DP_[3:0]

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that

25–22, 19,

18, 13, 12,

9–6, 3–1,

80–78,

75–72, 69,

68, 63, 62

59–56, 53–51

Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained

in the memory location specified by A_[16:0]during the previous clock rise of the

read cycle. The direction of the pins is controlled by OE. When OE is asserted

LOW, the pins behave as outputs. When HIGH, DQ_[31:0]and DP_[3:0]are placed in

a three-state condition.

15, 41, 65, 91 V_DD

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power

supply.

17, 40, 67, 90 V_SS

Ground

Ground for the core of the device. Should be connected to ground of the system.

4, 11, 20, 27, V_DDQ

54, 61, 70, 77

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power

supply.

5, 10, 21, 26, V_SSQ

55, 60, 71, 76

I/O Ground

Ground for the I/O circuitry. Should be connected to ground of the system.

Document #: 38-05086 Rev. **

Page 3 of 16

CY7C1347

Pin Definitions

Pin Number

31

Name

MODE

I/O

Description

Input-

Static

Selects burst order. When tied to GND selects linear burst sequence. When tied

to V_DDQor left floating selects interleaved burst sequence. This is a strap pin and

should remain static during device operation.

14, 16, 38, 39, NC

42, 43, 66

No Connects.

Single Write Accesses Initiated by ADSP

Introduction

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise (t_CO) is 3.5 ns

(166-MHz device).

CE₁, CE₂, CE₃are all asserted active. The address presented

to A_[16:0]is loaded into the Address Register and the address

advancement logic while being delivered to the RAM core. The

write signals (GW, BWE, and BW_[3:0]) and ADV inputs are ig-

nored during this first cycle.

The CY7C1347 supports secondary cache in systems utilizing

either a linear or interleaved burst sequence. The interleaved

burst order supports Pentium and i486 processors. The linear

burst sequence is suited for processors that utilize a linear

burst sequence. The burst order is user selectable, and is de-

termined by sampling the MODE input. Accesses can be initi-

ated with either the Processor Address Strobe (ADSP) or the

Controller Address Strobe (ADSC). Address advancement

through the burst sequence is controlled by the ADV input. A

two-bit on-chip wraparound burst counter captures the first ad-

dress in a burst sequence and automatically increments the

address for the rest of the burst access.

ADSP-triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ_[31:0]and DP_[3:0]inputs is written into

the corresponding address location in the RAM core. If GW is

HIGH, then the write operation is controlled by BWE and

BW_[3:0]signals. The CY7C1347 provides byte write capability

that is described in the Write Cycle Description table. Assert-

ing the Byte Write Enable input (BWE) with the selected Byte

Write (BW_[3:0]) input will selectively write to only the desired

bytes.

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self-timed write mechanism has

been provided to simplify the write operations.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW_[3:0]) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip synchro-

nous self-timed write circuitry.

Because the CY7C1347 is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ_[31:0]and DP_[3:0]inputs. Doing so will three-state the

output drivers. As a safety precaution, DQ_[31:0]and DP_[3:0]are

automatically three-stated whenever a write cycle is detected,

regardless of the state of OE.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. ADSP is ignored if CE₁

is HIGH.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) CE₁, CE₂, CE₃are all asserted active,

and (4) the appropriate combination of the write inputs (GW,

BWE, and BW_[3:0]) are asserted active to conduct a write to

the desired byte(s). ADSC-triggered write accesses require a

single clock cycle to complete. The address presented to

A_[16:0]is loaded into the address register and the address ad-

vancement logic while being delivered to the RAM core. The

ADV input is ignored during this cycle. If a global write is con-

ducted, the data presented to the DQ_[31:0]and DP_[3:0]is written

into the corresponding address location in the RAM core. If a

byte write is conducted, only the selected bytes are written.

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self-timed write mechanism has

been provided to simplify the write operations.

Single Read Accesses

This access is initiated when the following conditions are sat-

isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

CE₁, CE₂, CE₃are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE₁

is HIGH. The address presented to the address inputs (A_[16:0]

)

is stored into the address advancement logic and the Address

Register while being presented to the memory core. The cor-

responding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the OutputRegister and onto

the data bus within 3.5 ns (166-MHz device) if OE is active

LOW. The only exception occurs when the SRAM is emerging

from a deselected state to a selected state, its outputs are

always three-stated during the first cycle of the access. After

the first cycle of the access, the outputs are controlled by the

OE signal. Consecutive single read cycles are supported.

Once the SRAM is deselected at clock rise by the chip select

and either ADSP or ADSC signals, its output will three-state

immediately.

Because the CY7C1347 is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ_[31:0]and DP_[3:0]inputs. Doing so will three-state the

output drivers. As a safety precaution, DQ_[31:0]and DP_[3:0]are

automatically three-stated whenever a write cycle is detected,

regardless of the state of OE.

Document #: 38-05086 Rev. **

Page 4 of 16

CY7C1347

Burst Sequences

Linear Burst Sequence

The CY7C1347 provides a two-bit wraparound counter, fed by

A_[1:0], that implements either an interleaved or linear burst se-

quence. The interleaved burst sequence is designed specifi-

cally to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a lin-

ear burst sequence. The burst sequence is user-selectable

through the MODE input.

First

Second

Third

Address

Fourth

Address

A_[1:0]

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ plac-

es the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered

valid nor is the completion of the operation guaranteed. The

device must be deselected prior to entering the “sleep” mode.

CE₁, CE₂, CE₃, ADSP, and ADSC must remain inactive for the

duration of t_ZZRECafter the ZZ input returns LOW.

Interleaved Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A_[1:0]

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

ZZ Mode Electrical Characteristics

Parameter

I_DDZZ

Description

Test Conditions

Min.

Max.

Unit

Snooze mode standby

current

ZZ > V_DD− 0.2V

10

mA

t_ZZS

Device operation to ZZ

ZZ recovery time

ZZ > V_DD− 0.2V

2t_CYC

ns

t_ZZREC

ZZ < 0.2V

2t_CYC

Document #: 38-05086 Rev. **

Page 5 of 16

CY7C1347

Cycle Descriptions^{[1, 2, 3]}

Next Cycle

Unselected

Add. Used

None

ZZ

L

H

CE₃

X

1

CE₂

X

0

CE₁

1

ADSP

X

0

ADSC

ADV

X

0

OE

X

1

DQ

Hi-Z

DQ

Write

X

0

X

0

X

0

1

0

1

X

Unselected

None

0

X

Unselected

None

X

1

0

X

Unselected

None

X

0

1

X

Unselected

None

X

0

1

X

Begin Read

External

0

X

Begin Read

0

1

0

1

Read

Write

X

Continue Read

Suspend Read

Begin Write

X

0

X

1

X

1

0

X

1

0

1

Hi-Z

DQ

0

Current

External

X

1

Hi-Z

DQ

1

0

X

1

Hi-Z

DQ

1

0

X

1

X

Hi-Z

Begin Write

X

1

Begin Write

0

X

0

Continue Write

Suspend Write

X

1

0

Current

None

X

1

X

1

ZZ “Sleep”

X

Notes:

1. X = “Don't Care,” 1 = HIGH, 0 = LOW.

2. Write is defined by BWE, BW_[3:0], and GW. See Write Cycle Descriptions Table.

3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

Document #: 38-05086 Rev. **

Page 6 of 16

CY7C1347

Write Cycle Descriptions^{[4, 5, 6]}

Function

GW

1

BWE

1

BW₃

X

1

BW₂

X

1

BW₁

BW₀

X

1

Read

X

1

0

1

0

1

0

1

0

X

Read

1

0

Write Byte 0 - DQ_[7:0]

Write Byte 1 - DQ_[15:8]

Write Bytes 1, 0

Write Byte 2 - DQ_[23:16]

Write Bytes 2, 0

Write Bytes 2, 1

Write Bytes 2, 1, 0

Write Byte 3 - DQ_[31:24]

Write Bytes 3, 0

Write Bytes 3, 1

Write Bytes 3, 1, 0

Write Bytes 3, 2

Write Bytes 3, 2, 0

Write Bytes 3, 2, 1

Write All Bytes

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Write All Bytes

0

X

Static Discharge Voltage .......................................... >2001V

(per MIL-STD-883, Method 3015)

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-Up Current.................................................... >200 mA

Storage Temperature ..................................... −65°C to +150°C

Operating Range

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Ambient

Range Temperature^[8]

V_DD

V_DDQ

Supply Voltage on V_DDRelative to GND.........−0.5V to +4.6V

Com’l

0°C to +70°C

3.3V

−5%/+10%

2.5V −5%

3.3V /+10%

DC Voltage Applied to Outputs

in High Z State^[7]....................................... −0.5V to V_DD+ 0.5V

Ind’l

–40°C to +85°C

3.3V

−5%/+10%

2.5V −5%

3.3V /+10%

DC Input Voltage^[7].................................... −0.5V to V_DD+ 0.5V

Current into Outputs (LOW).........................................20 mA

Notes:

4. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.

5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW_[3:0]. Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is

a don't care for the remainder of the write cycle.

6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ_[31:0]; DP_[3:0]= High-Z when OE

is inactive or when the device is deselected, and DQ_[31:0]; DP_[3:0]= data when OE is active

7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.

8. T_Ais the case temperature.

Document #: 38-05086 Rev. **

Page 7 of 16

CY7C1347

Electrical Characteristics Over the Operating Range

Parameter

V_DD

Description

Test Conditions

Min.

3.135

2.375

2.4

Max.

3.6

Unit

V

Power Supply Voltage 3.3V −5%/+10%

V_DDQ

I/O Supply Voltage

2.5V −5% to 3.3V +10%

3.6

V

V_OH

Output HIGH Voltage

V_DDQ= 3.3V, V_DD= Min., I_OH= –4.0 mA

V_DDQ= 2.5V, V_DD= Min., I_OH= –2.0 mA

V_DDQ= 3.3V, V_DD= Min., I_OL= 8.0 mA

V_DDQ= 2.5V, V_DD= Min., I_OL= 2.0 mA

VDDQ = 3.3V

V

2.0

V

V_OL

Output LOW Voltage

0.4

0.7

V

V_IH

V_IL

I_X

Input HIGH Voltage

Input LOW Voltage^[7]

2.0

1.7

V_DD+ 0.3V

0.8

V

VDDQ = 2.5V

V

VDDQ = 3.3V

–0.3

−5

V

VDDQ = 2.5V

0.7

V

Input Load Current

GND ≤ V_I≤ V_DDQ

5

µA

except ZZ and MODE

Input Current of MODE Input = V_SS

Input = V_DDQ

–30

–5

µA

5

Input Current of ZZ

Input = V_SS

Input = V_DDQ

30

5

I_OZ

I_DD

Output Leakage

Current

GND ≤ V_I≤ V_DDQ,Output Disabled

−5

V_DDOperating Supply V_DD= Max., I_OUT= 0 mA,

6-ns cycle, 166 MHz

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

6-ns cycle, 166 MHz

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

All speeds

420

375

325

150

125

115

10

mA

Current

f = f_MAX= 1/t_CYC

I_SB1

Automatic CS

Power-Down

Max. V_DD, Device Deselected,

V_IN≥ V_IHor V_IN≤ V_IL

Current—TTL Inputs

f = f_MAX= 1/t_CYC

I_SB2

Automatic CS

Power-Down

Max. V_DD, Device Deselected,

V_IN≤ 0.3V or V_IN> V_DDQ– 0.3V,

Current—CMOS Inputs f = 0

I_SB3

Automatic CS

Power-Down

Current—CMOS Inputs f = f_MAX= 1/t_CYC

Max. V_DD, Device Deselected, or 6-ns cycle, 166 MHz

120

95

mA

V_IN≤ 0.3V or V_IN> V_DDQ– 0.3V

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

85

I_SB4

Automatic CS

Power-Down

Max. V_DD, Device Deselected,

V_IN≥ V_IHor V_IN≤ V_IL, f = 0

18

Current—TTL Inputs

Capacitance^[9]

Parameter

Description

Input Capacitance

Test Conditions

Max.

Unit

C_IN

T_A= 25°C, f = 1 MHz,

V_DD= 3.3V,

V_DDQ= 3.3V

6

8

pF

C_CLK

Clock Input Capacitance

Input/Output Capacitance

C_I/O

Note:

9. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-05086 Rev. **

Page 8 of 16

CY7C1347

AC Test Loads and Waveforms

R=317Ω

3.3V

[10]

OUTPUT

ALL INPUT PULSES

90%

OUTPUT

2.5V

GND

90%

10%

Z =50Ω

0

R =50Ω

10%

L

5 pF

R=351Ω

≤ 2.5 ns

V = 1.5V

L

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

Switching Characteristics Over the Operating Range^{[11, 12, 13]}

-166

-133

Max.

-100

Parameter

t_CYC

Description

Clock Cycle Time

Min.

6.0

1.7

2.0

0.5

Max.

Min.

7.5

1.9

2.5

0.5

Min.

Max.

Unit

ns

10

3.5

2.5

0.5

t_CH

Clock HIGH

t_CL

Clock LOW

t_AS

Address Set-Up Before CLK Rise

Address Hold After CLK Rise

Data Output Valid After CLK Rise

Data Output Hold After CLK Rise

ADSP, ADSC Set-Up Before CLK Rise

ADSP, ADSC Hold After CLK Rise

BWE, GW, BW_[3:0]Set-Up Before CLK Rise

BWE, GW, BW_[3:0]Hold After CLK Rise

ADV Set-Up Before CLK Rise

ADV Hold After CLK Rise

t_AH

t_CO

3.5

4.0

5.5

t_DOH

t_ADS

t_ADH

t_WES

t_WEH

t_ADVS

t_ADVH

t_DS

1.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.0

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

Data Input Set-Up Before CLK Rise

Data Input Hold After CLK Rise

Chip Select Set-Up

t_DH

t_CES

t_CEH

t_CHZ

t_CLZ

t_OEHZ

t_OELZ

Chip Select Hold After CLK Rise

Clock to High-Z^[12]

3.5

4.0

3.5

5.5

Clock to Low-Z^[12]

0

OE HIGH to Output High-Z^{[12, 13]}

OE LOW to Output Low-Z^{[12, 13]}

OE LOW to Output Valid^[12]

t_OEV

Notes:

10. Input waveform should have a slew rate of 1 V/ns.

11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output

loading of the specified I_OL/I_OHand load capacitance. Shown in (a) and (b) of AC Test Loads.

12.

t_CHZ, t_CLZ, t_EOV, t_EOLZ, and t_EOHZare specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from

steady-state voltage.

13. At any given voltage and temperature, t_EOHZis less than t_EOLZand t_CHZis less than t_CLZ

.

Document #: 38-05086 Rev. **

Page 9 of 16

CY7C1347

1

Switching Waveforms

Write Cycle Timing^{[14, 15]}

Single Write

Burst Write

Pipelined Write

t

Unselected

CH

t

CYC

CLK

t

ADH

t

ADS

t

ADSP ignored with CE inactive

CL

1

ADSP

ADSC

ADV

t

ADH

t

ADSC initiated write

ADS

t

ADVH

ADVS

t

ADV Must Be Inactive for ADSP Write

WD2

AS

WD3

ADD

GW

WE

WD1

t

AH

t

WH

t

WH

t

WS

t

WS

t

CES

CE masks ADSP

CEH

1

CE

1

t

CEH

CES

Unselected with CE

2

CE

2

CE

3

t

CES

t

CEH

OE

t

DH

t

DS

High-Z

Data

In

3a

2a

= UNDEFINED

1a

2b

2c

2d

= DON’T CARE

Notes:

14. WE is the combination of BWE, BW_[3:0], and GW to define a write cycle (see Write Cycle Descriptions table).

15. WDx stands for Write Data to Address X.

Document #: 38-05086 Rev. **

Page 10 of 16

CY7C1347

Switching Waveforms (continued)

Read Cycle Timing^{[14, 16]}

Burst Read

Single Read

Unselected

t_CYC

t_CH

Pipelined Read

CLK

t_ADH

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

t_ADS

ADSC initiated read

ADSC

ADV

t_ADVS

t_ADH

Suspend Burst

t_ADVH

t_AS

ADD

GW

RD3

RD1

RD2

t_AH

t_WS

t_WH

WE

t_CES

t_CEH

t_WH

CE₁masks ADSP

CE₁

Unselected with CE₂

CE₂

t_CES

t_CEH

CE₃

OE

t_CES

t_EOV

t_CEH

t_OEHZ

t_DOH

t_CO

Data Out

2c

1a

3a

2d

2a

2b

t_CLZ

t_CHZ

= DON’T CARE

= UNDEFINED

Note:

16. RDx stands for Read Data from Address X.

Document #: 38-05086 Rev. **

Page 11 of 16

CY7C1347

Switching Waveforms (continued)

Read/Write Cycle Timing^{[14, 15, 16, 17]}

Single Read

t_CYC

Single Write

t_CH

Unselected

Burst Read

Pipelined Read

CLK

t_ADH

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

ADSC

ADV

t_ADS

t_ADVS

t_ADH

t_AS

t_ADVH

WD2

ADD

RD1

RD3

t_AH

GW

WE

CE₁

t_WS

t_WH

t_CES

t_CEH

t_WH

CE₁masks ADSP

CE₂

CE₃

t_CES

t_CEH

t_EOV

t_CES

t_CEH

OE

t_EOHZ

t_DS

t_DH

t_DOH

See Note 17

t_EOLZ

t_CO

3b

Out

2a

3a

Out

3c

Out

3d

Out

Data In/Out

1a

2a

In

Out

t_CHZ

= UNDEFINED

= DON’T CARE

Note:

17. Data bus is driven by SRAM, but data is not guaranteed.

Document #: 38-05086 Rev. **

Page 12 of 16

CY7C1347

Switching Waveforms (continued)

Pipeline Timing^{[18, 19]}

t_CYC

t_CL

t_CH

CLK

t_AS

WD1

WD2

WD3

WD4

RD1

RD2

RD3

RD4

ADD

t_ADS

t_ADH

ADSC initiated Reads

ADSC

ADSP initiated Reads

ADSP

ADV

t_CEH

t_CES

CE₁

CE

t_WES

t_WEH

WE

OE

ADSP ignored

with CE₁HIGH

t_CLZ

Data In/Out

1a

In

1a

2a

3a

4a

2a

In

3a

In

4a

D(C)

Out Out Out Out

In

t_CO

t_DOH

Back to Back Reads

t_CHZ

= UNDEFINED

= DON’T CARE

Notes:

18. Device originally deselected.

19. CE is the combination of CE₂and CE₃. All chip selects need to be active in order to select the device.

Document #: 38-05086 Rev. **

Page 13 of 16

CY7C1347

Switching Waveforms (continued)

ZZ Mode Timing ^{[20, 21]}

CLK

ADSP

HIGH

ADSC

CE₁

LOW

CE₂

HIGH

CE₃

ZZ

t_ZZS

I_DD

I_DD(active)

t_ZZREC

I_DDZZ

I/Os

Three-state

Notes:

20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

21. I/Os are in three-state when exiting ZZ sleep mode.

Document #: 38-05086 Rev. **

Page 14 of 16

CY7C1347

Ordering Information

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

Package Type

166

CY7C1347-166AC

CY7C1347-133AC

CY7C1347-100AC

CY7C1347-100AI

A101

100-Lead Thin Quad Flat Pack

Commercial

133

100

A101

100-Lead Thin Quad Flat Pack

Industrial

Package Diagram

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

Document #: 38-05086 Rev. **

Page 15 of 16

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1347

Document Title: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM

Document Number: 38-05086

Issue

ECN NO. Date

Orig. of

Change

REV.

Description of Change

**

107346

09/15/01

SZV

Change Spec number from: 38-00727 to 38-05086

Document #: 38-05086 Rev. **

Page 16 of 16


型号：	CY7C1347-100ACT
厂家：	CYPRESS
描述：	Cache SRAM, 128KX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 静态存储器内存集成电路
文件：	总16页 (文件大小：297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1347-100ACT [CYPRESS]

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