CY7C1297A [CYPRESS]
64K X 18 Synchronous Burst SRAM; 64K X 18同步突发SRAM
| 型号： | CY7C1297A |
| 厂家： | 
CYPRESS |
| 描述： | 64K X 18 Synchronous Burst SRAM |
| 文件： | 总13页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
297A
CY7C1297A/
GVT7164B18
64K X 18 Synchronous Burst SRAM
The CY7C1297A/GVT7164B18 SRAM integrates 65536 × 18
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
Features
• Fast access times: 9 and 10 ns
• Fast clock speed: 66 and 50 MHz
• Provide high performance 2-1-1-1 access rate
• Fast OE access times: 5 and 6 ns
• Single +3.3V –5% and +10% power supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSSQ at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
inputs
include
all
addresses,
all
data
inputs,
address-pipelining Chip Enable (CE), depth-expansion Chip
Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (WEL, WEH, and BWE), and Global
Write (GW).
Asynchronous inputs include the Output Enable (OE), Burst
Mode Control (MODE), and Sleep Mode Control (ZZ). The
data outputs (DQ), enabled by OE, are also asynchronous.
• Three chip enables for depth expansion and address
pipeline
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
pin (ADV).
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
Address, data inputs, and Read controls are registered
on-chip to initiate self-timed Write cycle. Write cycles can be
one or two bytes wide as controlled by the Read control inputs.
Individual byte enables allow individual bytes to be written.
WEL controls DQ1–DQ8 and DQP1. WEH controls
DQ9–DQ16 and DQP2. WEL and WEH can be active only with
BWE being LOW. GW being LOW causes all bytes to be
written.
• Automatic power-down for portable applications
• High-density, high-speed packages
• Low-capacitive bus loading
• High 30-pF output drive capability at rated access time
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
double-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1297A/GVT7164B18 operates from a +3.3V power
supply. All inputs and outputs are TTL-compatible. The device
is ideally suited for 486, Pentium®, 680 × 0, and PowerPC™
systems and for systems that benefit from a wide synchronous
data bus.
Selection Guide
7C1297A-66
7164B18-9
7C1297A-50
7164B18-10
7C1297A1-50
7164B18-12
Unit
ns
Maximum Access Time
9.0
240
2
10.0
240
2
10.0
240
2
Maximum Operating Current
Maximum CMOS Standby Current
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05204 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised January 19, 2003
CY7C1297A/
GVT7164B18
Functional Block Diagram—64Kx18[1]
UPPER BYTE
WRITE
WEH#
BWE#
D
Q
CLK
LOWER BYTE
WRITE
WEL#
GW#
D
Q
ENABLE
CE#
CE2
D
Q
CE2#
Power-down Logic
ZZ
OE#
ADSP#
Input
Register
A15-A2
Address
Register
ADSC#
DQ1-DQ16
DQP1
CLR
DQP2
ADV#
A1-A0
MODE
Binary
Counter
and Logic
Note:
1. The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
Document #: 38-05204 Rev. *A
Page 2 of 13
CY7C1297A/
GVT7164B18
Pin Configuration
100-pin TQFP
Top View
NC
NC
NC
VCCQ
VSSQ
NC
A10
NC
NC
VCCQ
VSSQ
NC
DQP1
DQ8
DQ7
VSSQ
VCCQ
DQ6
DQ5
VSS
NC
VCC
ZZ
DQ4
DQ3
VCCQ
VSSQ
DQ2
DQ1
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ9
DQ10
VSSQ
VCCQ
DQ11
DQ12
NC
VCC
NC
VSS
DQ13
DQ14
VCCQ
VSSQ
DQ15
DQ16
DQP2
NC
VSSQ
VCCQ
NC
NC
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1297A/GVT7164B18
NC
VSSQ
VCCQ
NC
NC
NC
Pin Descriptions
QFP Pins
Pin Name
Type
Input-
Description
Addresses: These inputs are registered and must meet the set-up and hold
37, 36, 35, 34, 33,
32, 100, 99, 82, 81,
80, 48, 47, 46, 45,
44
A0–A16
Synchronous times around the rising edge of CLK. The burst counter generates internal
addresses associated with A0 and A1, during burst and wait cycles.
93, 94
WEL, WEH
Input-
Byte Write Enables: A byte Read enable is LOW for a Write cycle and HIGH
Synchronous for a Read cycle. WEL controls DQ1–DQ8 and DQP1. WEH controls
DQ9–DQ16 and DQP2. Data I/O are high impedance if either of these inputs
are LOW, conditioned by BWE LOW.
87
88
BWE
GW
Input-
Write Enable: This active LOW input gates byte Read operations and must
Synchronous meet the set-up and hold times around the rising edge of CLK.
Input- Global Write: This active LOW input allows a full 18-bit Write to occur
Synchronous independent of the BWE and WEn lines and must meet the set-up and hold
times around the rising edge of CLK.
89
CLK
Input-
Clock: This signal registers the addresses, data, chip enables, Write control
Synchronous and burst control inputs on its rising edge. All synchronous inputs must meet
set-up and hold times around the clock’s rising edge.
98
92
97
CE
Input-
Synchronous ADSP.
Chip Enable: This active LOW input is used to enable the device and to gate
CE2
CE2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device.
Input-
Synchronous
Chip Enable: This active HIGH input is used to enable the device.
Document #: 38-05204 Rev. *A
Page 3 of 13
CY7C1297A/
GVT7164B18
Pin Descriptions (continued)
QFP Pins
Pin Name
Type
Description
86
OE
Input
Output Enable: This active LOW asynchronous input enables the data
output drivers.
83
84
85
ADV
ADSP
ADSC
Input-
Address Advance: This active LOW input is used to control the internal
Synchronous burst counter. A HIGH on this pin generates wait cycle (no address
advance).
Input-
Address Status Processor: This active LOW input, along with CE being
Synchronous LOW, causes a new external address to be registered and a Read cycle is
initiated using the new address.
Input-
Address Status Controller: This active LOW input causes device to be
Synchronous deselected or selected along with new external address to be registered. A
Read or Write cycle is initiated depending upon Write control inputs.
31
64
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin selects
Linear Burst. A NC or HIGH on this pin selects Interleaved Burst.
Input-
Snooze: This active HIGH input puts the device in low power consumption
Asynchronous standby mode. For normal operation, this input has to be either LOW or NC
(No Connect).
58, 59, 62, 63, 68, DQ1–DQ16
69, 72, 73, 8, 9, 12,
Input/
Output
Data Inputs/Outputs: Low Byte is DQ1–DQ8. High Byte is DQ9–DQ16.
Input data must meet set-up and hold times around the rising edge of CLK.
13, 18, 19, 22, 23
74, 24
DQP1,
DQP2
Input/
Output
Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity
bit for DQ9–DQ16.
15, 41, 65, 91
VCC
VSS
Supply
Ground
Power Supply: +3.3V –5% and +10%
Ground: GND.
14, 17, 40, 67, 90
4, 11, 20, 27, 54, 61,
70, 77
VCCQ
I/O Supply
Output Buffer Supply: +2.375 to 3.6V
5, 10, 21, 26, 55, 60,
71, 76
VSSQ
NC
I/O Ground Output Buffer Ground: GND
No Connect: These signals are not internally connected.
1–3, 6, 7, 14, 16, 25,
28–30, 38, 39, 42,
43, 49–53, 56, 57,
66, 75, 78, 79, 80,
95, 96
–
Burst Address Table (MODE = GND)
Burst Address Table (MODE = NC/V
)
CC
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Document #: 38-05204 Rev. *A
Page 4 of 13
CY7C1297A/
GVT7164B18
Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Used
Operation
CE CE2 CE2 ADSP ADSC
ADV WRITE OE
CLK
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
None
L
X
L
L
None
L
H
H
L
None
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
External
External
External
External
External
Next
L
X
X
L
Read Cycle, Begin Burst
L
L
L
H
X
L
High-Z
D
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Q
Read Cycle, Begin Burst
L
L
L
H
L
High-Z
Q
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
Partial Truth Table for Read/Write
Function
Read
GW
BWE
WEH
WEL
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
Read
Write one byte
Write all bytes
L
Write all bytes
X
X
Notes:
2. X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means
[BWE + WEL*WEH]*GW equals HIGH.
3. WEL enables Write to DQ1–DQ8 and DQP1. WEH enables Write to DQ9–DQ16 and DQP2.
4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5. Suspending burst generates wait cycle.
6. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW along with chip being selected always initiates a Read cycle at the L–H edge of CLK. A Write cycle can be performed by setting WRITE LOW for
the CLK L–H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Document #: 38-05204 Rev. *A
Page 5 of 13
CY7C1297A/
GVT7164B18
Power Dissipation.......................................................... 1.4W
Short Circuit Output Current...................................... 100 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V
VIN ...........................................................–0.5V to VCC+0.5V
Storage Temperature (plastic) ....................–55°C to +125°C
Junction Temperature ...............................................+125°C
Ambient
[10,11]
Range
Com’l
Temperature[9]
VCC
0°C to +70°C
3.3V −5%/+10%
Electrical Characteristics Over the Operating Range[12]
Parameter
VIH
Description
Input High (Logic 1) Voltage[13, 14]
Input Low (Logic 0) Voltage[13, 14]
Input Leakage Current[15]
Output Leakage Current
Output High Voltage[13, 16]
Output Low Voltage[13, 16]
Supply Voltage[13]
Test Conditions
Min.
2.0
Max.
Unit
VCCQ+0.3
V
V
VIl
–0.3
–2
0.8
2
ILI
0V < VIN < VCC
µA
µA
V
ILO
Output(s) disabled, 0V < VOUT < VCC
IOH = –4.0 mA
–2
2
VOH
VOL
2.4
IOL = 8.0 mA
0.4
3.6
V
VCC
3.1
V
66 MHz 50 MHz 50 MHz
Parameter
Description
Conditions
Typ.
-9
-10
-12
Unit
ICC
Power Supply Current: Device selected; all inputs < VILor > VIH;
150
240
240
200
mA
Operating[17, 18, 19]
cycle time > tKC min.; VCC = Max.;
outputs open
ISB1
ISB2
ISB3
ISB4
Power Supply Current: Device selected; ADSC, ADSP, ADV, GW,
15
0.2
4
40
2
40
2
30
2
mA
mA
mA
mA
Idle[18, 19]
BWE >VIH; all other inputs < VILor > VIH; VCC
= Max.; cycle time > tKC min.; outputs open
CMOS Standby[18, 19] Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or >VCC – 0.2;
all inputs static; CLK frequency = 0
TTL Standby[18, 19]
Clock Running[18, 19]
Device deselected; all inputs < VIL
or > VIH; all inputs static;
VCC = Max.; CLK frequency = 0
10
40
10
40
10
30
Device deselected;
15
all inputs < VIL or > VIH; VCC = Max.;
CLK cycle time > tKC min.
Capacitance[20]
Parameter
Description
Test Conditions
Typ.
Max.
Unit
CI
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 3.3V
3
6
4
7
pF
pF
CO
Input/Output Capacitance (DQ)
Notes:
9. TA is the case temperature.
10. Please refer to waveform (d)
11. Power Supply ramp-up should be monotonic.
12. Values in table are associated with the operating frequencies listed.
13. All voltages referenced to VSS (GND).
14. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2.
Undershoot:VIL ≤ –2.0V for t ≤ tKC /2.
15. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA.
16. AC I/O curves are available upon request.
17. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
18. “Device Deselected” means the device is in Power-down mode as defined in the truth table. “Device Selected” means the device is active.
19. Typical values are measured at 3.3V, 25°C, and 20-ns cycle time.
20. This parameter is sampled.
Document #: 38-05204 Rev. *A
Page 6 of 13
CY7C1297A/
GVT7164B18
Thermal Resistance
Description
Test Conditions
Symbol
ΘJA
TQFP Typ.
Unit
°C/W
°C/W
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
Still Air, soldered on a 4.25 x 1.125 inch,
four-layer PCB
20
91
ΘJC
AC Test Loads and Waveforms[21]
+3.3V
317
tPU
=
200us
DQ
Ω
ALL INPUT PULSES
90%
Vcctyp
Vccmin
Z0 = 50
Ω
50Ω
30 pF
DQ
3.0V
90%
10%
For proper RESET
bring Vcc down to 0V
351Ω
5 pF
10%
1.5 ns
0V
Vt = 1.5V
≤
1.5 ns
≤
(a)
(b)
(c)
(d)
Capacitance Derating[22]
Description
Symbol
Typ.
Max.
Unit
Clock to Output Valid
∆ tKQ
0.016
ns / pF
Switching Characteristics Over the Operating Range[23]
66 MHz
-9
50 MHz
-10
50 MHz
-12
Parameter
Clock
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
tKC
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
15
4
15
5
20
6
ns
ns
ns
tKH
tKL
4
5
6
Output Times
tKQ
Clock to Output Valid
9
10
12
ns
ns
ns
ns
ns
ns
ns
tKQX
Clock to Output Invalid
3
3
3
3
3
3
tKQLZ
tKQHZ
tOEQ
Clock to Output in Low-Z[24, 25]
Clock to Output in High-Z[24, 25]
OE to Output Valid[26]
OE to Output in Low-Z[24, 25]
OE to Output in High-Z[24, 25]
5
5
5
5
6
6
tOELZ
tOEHZ
Set-up Times
tS
0
0
0
5
5
6
Address, Controls, and Data In[27]
Address, Controls, and Data In[27]
2.5
0.5
2.5
0.5
3
ns
ns
Hold Times
tH
0.5
Document #: 38-05204 Rev. *A
Page 7 of 13
CY7C1297A/
GVT7164B18
Switching Characteristics Over the Operating Range[23]
66 MHz
-9
50 MHz
-10
50 MHz
-12
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
Notes:
21. Overshoot: VIH(AC) <VDD + 1.5V for t <tTCYC/2; undershoot: VIL(AC) < 0.5V for t <tTCYC/2; power-up: VIH < 2.6V and VDD <2.4V and VDDQ < 1.4V for
t<200 ms.)
22. Capacitance derating applies to capacitance different from the load capacitance shown in part (a) of AC Test Loads. Values in table are associated with the
operating frequencies listed.
23. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
24. Output loading is specified with CL = 5 pF as in AC Test Loads.
25. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ
.
26. OE is a “don’t care” when a byte Write enable is sampled LOW.
27. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t care” as defined in the truth table.
Document #: 38-05204 Rev. *A
Page 8 of 13
CY7C1297A/
GVT7164B18
Timing Diagrams
Read Timing[28]
t
KC
t
KL
CLK
ADSP#
t
t
S
KH
t
H
ADSC#
t
S
ADDRESS
A1
A2
t
H
WEH#, WEL#,
BWE#, GW#
CE#
ADV#
OE#
DQ
t
S
t
H
t
t
t
KQ
KQ
OEQ
t
t
KQLZ
OELZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
Q(A2+2)
SINGLE READ
BURST READ
Note:
28. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active.
Document #: 38-05204 Rev. *A
Page 9 of 13
CY7C1297A/
GVT7164B18
Timing Diagrams (continued)
Write Timing[28]
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
A3
tH
WEL#, WEH#,
BWE#
GW#
CE#
tS
ADV#
OE#
DQ
tH
tOEHZ
tKQX
Q
D(A1)
D(A2) D(A2+1) D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1) D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
Document #: 38-05204 Rev. *A
Page 10 of 13
CY7C1297A/
GVT7164B18
Timing Diagrams (continued)
Read/Write Timing[28]
CLK
t
S
ADSP#
ADSC#
t
H
t
S
ADDRESS
A2
A3
A4
A5
A1
t
H
WEH#, WEL#,
BWE#, GW#
CE#
ADV#
OE#
DQ
Q(A1)
Q(A2)
D(A3)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
D(A5)
D(A5+1)
Single
Reads
Single Write
Burst Read
Burst Write
Document #: 38-05204 Rev. *A
Page 11 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1297A/
GVT7164B18
Ordering Information
Package
Name
Operating
Range
Speed (MHz)
Ordering Code
Package Type
66
CY7C1297A-66AC/
GVT7164B18T-9
A101
A101
A101
100-lead Thin Quad Flat Pack
Commercial
Commercial
Commercial
50
CY7C1297A-50AC/
GVT7164B18T-10
100-lead Thin Quad Flat Pack
100-lead Thin Quad Flat Pack
CY7C1297A1-50AC/
GVT7164B18T-12
Package Diagram
100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101
51-85050-A
Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of International Business Machines, Inc. All
products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05204 Rev. *A
Page 12 of 13
CY7C1297A/
GVT7164B18
Document Title: CY7C1297A/GVT7164B18 64K × 18 Synchronous Burst SRAM
Document Number: 38-05204
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
112434
Description of Change
02/06/02
01/19/03
KOM
RBI
Change CY part number from CY7C1314A to CY7C1297A
*A
123141
Add Power up Requirements to Operating Conditions Information
Document #: 38-05204 Rev. *A
Page 13 of 13
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