CY7C1297F [CYPRESS]
1-Mbit (64K x 18) Flow-Through Sync SRAM; 1兆位（ 64K ×18 ）流通型同步SRAM
| 型号： | CY7C1297F |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mbit (64K x 18) Flow-Through Sync SRAM |
| 文件： | 总15页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1297F
1-Mbit (64K x 18) Flow-Through Sync SRAM
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Features
• 64K x 18 common I/O
• 3.3V –5% and +10% core power supply (VDD
• 3.3V I/O supply (VDDQ
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
)
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:B], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
)
• Provide high-performance 2-1-1-1 access rate
The CY7C1297F allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V I/O level
• Offered in JEDEC-standard 100-pin TQFP
• “ZZ” Sleep Mode option
Functional Description[1]
The CY7C1297F is a 131,072 x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
The CY7C1297F operates from a +3.3V core power supply
while all outputs may operate with either a +3.3V supply. All
inputs and outputs are JEDEC-standard JESD8-5-compatible.
Logic Block Diagram
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQPB
DQ
B,DQPB
WRITE DRIVER
WRITE REGISTER
BW
B
A
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQPA
DQA,DQPA
WRITE REGISTER
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05429 Rev. *B
Revised December 21, 2004
CY7C1297F
Selection Guide
133 MHz
6.5
117 MHz
7.5
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
225
40
220
40
mA
mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of this part.
Pin Configuration
100-Pin TQFP
NC
NC
NC
VDDQ
VSS
NC
1
2
3
4
5
6
7
8
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1297F
VDD
NC
BYTE A
BYTE B
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
NC
VSS
VDDQ
NC
NC
NC
Document #: 38-05429 Rev. *B
Page 2 of 15
CY7C1297F
Pin Descriptions
Name
TQFP
I/O
Description
A0, A1, A
37,36,32,
33,34,35,
44,45,46,
47,48,80,
81,82,99,100
Input-
Address Inputs used to select one of the 64K address locations. Sampled at
Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB
GW
93,94
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes
Synchronous to the SRAM. Sampled on the rising edge of CLK.
88
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
Synchronous of CLK, a global Write is conducted (ALL bytes are written, regardless of the values
on BW[A:B] and BWE).
BWE
CLK
CE1
87
89
98
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
Synchronous signal must be asserted LOW to conduct a Byte Write.
Input-
Clock
Input-
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE and CE to select/deselect the device. ADSP is ignored
if CE1
2
3
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
Input- Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
CE2
CE3
OE
97
92
86
Input-
Asynchronou pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
s
are three-stated, and act as input data pins. OE is masked during the first clock of a
Read cycle when emerging from a deselected state.
ADV
83
84
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when
deasserted HIGH
CE1 is
ADSC
85
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
64
Input-
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronou non-time-critical “sleep” condition with data integrity preserved. For normal opera-
s
tion, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs
58,59,62,
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
DQPA, DQPB 63,68,69,
Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by the addresses presented during the previous clock
rise of the Read cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are
placed in a three-state condition.
72,73,8,9,12,
13,18,19,22,
23,74,24
VDD
VSS
15,41,65, 91
Power
Supply
Ground
Power supply inputs to the core of the device.
5,10,17,21,
26,40,55,60,
67,71,76,90
Ground for the device.
VDDQ
4,11,20,27,
54,61,70,77
I/O Power Power supply for the I/O circuitry.
Supply
Document #: 38-05429 Rev. *B
Page 3 of 15
CY7C1297F
Pin Descriptions (continued)
Name
MODE
TQFP
I/O
Description
31
Input-
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to VDD or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
Static
NC
1,2,3,6,7,14,
16,25,28,29,
30,38,39,42,
43,51,52,53,
56,57,66,75,
78,79,95,96
No Connects. Not Internally connected to the die.
latched and written into the device. Byte Writes are allowed.
During byte writes, BWA controls DQA and BWB controls DQB.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133-MHz device).
All I/Os are three-stated during a Byte Write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be three-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are three-stated once a Write cycle is detected,
regardless of the state of OE.
The CY7C1297F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the Write input signals (GW, BWE, and BW[A:B]
)
indicate a write access. ADSC is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:B] will be
written into the specified address location. Byte Writes are
allowed. During Byte Writes, BWA controls DQA and BWB
controls DQB. All I/Os are three-stated when a write is
detected, even a Byte Write. Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be three-stated prior to the presentation of
data to DQs. As a safety precaution, the data lines are
three-stated once a Write cycle is detected, regardless of the
state of OE.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Read Accesses
Burst Sequences
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
The CY7C1297F provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[A:B]) are ignored during this first
clock cycle. If the Write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
Write) on the next clock rise, the appropriate data will be
Document #: 38-05429 Rev. *B
Page 4 of 15
CY7C1297F
Interleaved Burst Address Table (MODE = Floating or VDD
)
Linear Burst Address Table (MODE = GND)
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
First
Address
A1,A0
Second
Address
A1,A0
Third
Address
A1,A0
Fourth
Address
A1,A0
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
40
2tCYC
Unit
mA
ns
ns
ns
2tCYC
7
0
2tCYC
tRZZI
ns
Truth Table [2, 3, 4, 5, 6]
Address
Used
Cycle Description
CE1 CE3 CE2 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle,
None
None
None
None
None
H
L
L
L
X
X
X
H
X
X
X
L
L
L
L
L
X
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
Power-down
Deselected Cycle,
Power-down
L
L
Deselected Cycle,
X
L
L
Power-down
Deselected Cycle,
Power-down
H
H
Deselected Cycle,
X
Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
None
External
External
External
External
External
Next
Next
Next
Next
Next
X
L
L
L
L
X
L
L
L
L
X
H
H
H
H
H
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
X
X
X
L
H
H
H
H
H
H
L
X
L
H
X
L
H
L
H
L
H
X
X
L
X
L-H
Three-State
Q
L-H Three-State
L-H
L-H
H
H
H
H
H
X
X
H
X
H
D
Q
L
L
L-H Three-State
L-H
L-H Three-State
L-H
L-H Three-State
L-H
L-H
L-H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
Q
Q
D
D
Q
Next
Current
L
H
L
H
Read Cycle, Suspend Burst
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW , BW ) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BW , BW ),
A
B
A
B
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A: B]
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the Write cycle.
6.
is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE
OE is
OE
inactive or when the device is deselected, and all data bits behave as output when
is active (LOW)
Document #: 38-05429 Rev. *B
Page 5 of 15
CY7C1297F
Truth Table (continued)[2, 3, 4, 5, 6]
Address
Cycle Description
Used
CE1 CE3 CE2 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Current
Current
Current
Current
Current
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
X
X
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
X
X
L-H Three-State
L-H
Q
L-H Three-State
L-H
L-H
D
D
L
Truth Table for Read/Write[2, 3]
Function
GW
H
BWE
H
BWB
X
BWA
X
Read
Read
H
H
H
H
L
L
L
L
L
X
H
H
L
L
X
H
L
H
L
Write Byte (A, DQPA)
Write Byte (B, DQPB)
Write All Bytes
Write All Bytes
X
Document #: 38-05429 Rev. *B
Page 6 of 15
CY7C1297F
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Range
Temperature]
VDD
VDDQ
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Commercial
0°C to +70°C
3.3V
3.3V –5%
DC Voltage Applied to Outputs
−5%/+10%
to VDD
in Three-State ..................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range [7, 8]
CY7C1297F
Parameter
VDD
VDDQ
VOH
VOL
VIH
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[7]
Test Conditions
Min.
3.135
3.135
2.4
Max.
3.6
3.6
Unit
V
V
V
V
V
V
µA
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 3.3V
0.4
2.0 VDD + 0.3V
–0.3
−5
VIL
IX
VDDQ = 3.3V
GND ≤ VI ≤ VDDQ
0.8
5
Input Load Current
(except ZZ and MODE)
Input Current of MODE
Input = VSS
Input = VDD
Input = VSS
–30
–5
µA
µA
µA
5
Input Current of ZZ
Input = VDD
GND ≤ VI ≤ VDD, Output Disabled
VDD = Max., VOUT = GND
30
5
–300
225
220
90
µA
µA
IOZ
IOS
IDD
Output Leakage Current
Output Short Circuit Current
VDD Operating Supply Current
–5
mA
mA
mA
mA
mA
VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
f = fMAX= 1/tCYC
8.0-ns cycle, 117 MHz
7.5-ns cycle, 133 MHz
8.0-ns cycle, 117 MHz
ISB1
ISB2
ISB3
Automatic CE Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
V
IN ≥ VIH or VIN ≤ VIL, f = fMAX,
85
inputs switching
Automatic CE Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
All speeds
40
mA
V
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
Automatic CE Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
7.5-ns cycle, 133 MHz
8.0-ns cycle, 117 MHz
75
70
mA
mA
V
IN ≥VDDQ – 0.3V or VIN ≤ 0.3V,
f = fMAX, inputs switching
ISB4
Automatic CE Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
All speeds
45
mA
V
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
Notes:
7. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
8. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
,
DD
Power-up
DD
IH
DD
DDQ
Document #: 38-05429 Rev. *B
Page 7 of 15
CY7C1297F
Thermal Resistance[9]
TQFP
Parameter
ΘJA
Description
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
Package
Unit
°C/W
Thermal Resistance
41.83
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
9.99
°C/W
Capacitance[9]
Parameter
Description
Input Capacitance
Test Conditions
Max.
5
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
V
DD = 3.3V.
VDDQ = 3.3V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
5
5
pF
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
R = 317Ω
3.3V
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
INCLUDING
JIG AND
SCOPE
V = 1.5V
L
(a)
(b)
(c)
Note:
9. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05429 Rev. *B
Page 8 of 15
CY7C1297F
Switching Characteristics Over the Operating Range [10, 11]
133 MHz
117 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
VDD(Typical) to the First Access[12]
Min.
1
Max.
Min.
1
Max.
Unit
ms
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
2.5
2.5
8.5
3.0
3.0
ns
ns
ns
Output Times
tCDV
tDOH
tCLZ
tCHZ
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z[13, 14, 15]
6.5
7.5
ns
ns
ns
ns
ns
ns
ns
3.0
0
3.0
0
Clock to High-Z[13, 14, 15]
3.5
3.5
3.5
3.5
tOEV
OE LOW to Output Valid
OE LOW to Output Low-Z[13, 14, 15]
OE HIGH to Output High-Z[13, 14, 15]
tOELZ
tOEHZ
Set-up Times
tAS
tADS
tADVS
tWES
0
0
3.5
3.5
Address Set-up before CLK Rise
ADSP, ADSC Set-up before CLK Rise
ADV Set-up before CLK Rise
GW, BWE, BW[A:B] Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-up
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
tDS
tCES
Hold Times
tAH
tADH
tWEH
tADVH
tDH
Address Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ADSP, ADSC Hold after CLK Rise
GW, BWE, BW[A:B] Hold after CLK Rise
ADV Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
tCEH
Notes:
10. Timing reference level is 1.5V when V
= 3.3V.
DDQ
11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation
DD
POWER
13. t
, t
,t
, and t
are specified with AC test conditions shown in (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
14. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
Document #: 38-05429 Rev. *B
Page 9 of 15
CY7C1297F
Timing Diagrams
Read Cycle Timing[16]
t
CYC
t
CLK
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
[A:B]
CE
Deselect Cycle
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst.
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
16. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05429 Rev. *B
Page 10 of 15
CY7C1297F
Timing Diagrams (continued)
Write Cycle Timing[16, 17]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst.
t
t
t
ADH
ADS
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst.
t
t
WEH
WES
BWE,
BW[A:B]
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst.
OE
t
t
DH
DS
Data in (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
17.
Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
[A:B]
Document #: 38-05429 Rev. *B
Page 11 of 15
CY7C1297F
Timing Diagrams (continued)
Read/Write Timing[16, 18, 19]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE, BW[A:B]
CE
t
t
WEH
WES
t
t
CEH
CES
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
Back-to-Back READs
Single WRITE
BURST READ
WRITEs
DON’T CARE
UNDEFINED
Notes:
18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
19.
GW is HIGH.
Document #: 38-05429 Rev. *B
Page 12 of 15
CY7C1297F
Timing Diagrams (continued)
ZZ Mode Timing[20, 21]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
Package
Name
A101
Operating
(MHz)
Ordering Code
CY7C1297F-117AC
Package Type
100-Lead Thin Quad Flat Pack
Range
117
Commercial
Please contact your local Cypress Sales representative for availability of 133-MHz speed grade option.
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05429 Rev. *B
Page 13 of 15
CY7C1297F
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05429 Rev. *B
Page 14 of 15
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1297F
Document History Page
Document Title: CY7C1297F 1-Mbit (64K x 18) Flow-Through Sync SRAM
Document Number: 38-05429
Orig. of
REV.
**
*A
ECN NO. Issue Date Change
Description of Change
200780
213321
311934
See ECN
See ECN
See ECN
NJY
VBL
DIM
New Data Sheet
Shaded selection guide and characteristics, added explanation
Changed tDOH spec from 2.0 ns to 3.0 ns for 133-MHz and 117-MHz speed
*B
grades.
Document #: 38-05429 Rev. *B
Page 15 of 15
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