CY7C1264XV18-450BZXC [CYPRESS]
QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, FBGA-165;
| 型号： | CY7C1264XV18-450BZXC |
| 厂家： | 
CYPRESS |
| 描述： | QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, FBGA-165 时钟 静态存储器 内存集成电路 |
| 文件： | 总29页 (文件大小：1012K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1262XV18
CY7C1264XV18
36-Mbit QDR® II+ Xtreme SRAM Two-Word
Burst Architecture (2.5 Cycle Read Latency)
36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Configurations
■ Separate independent read and write data ports
❐ Supports concurrent transactions
With Read Cycle Latency of 2.5 cycles:
CY7C1262XV18 – 2 M × 18
■ 450 MHz clock for high bandwidth
CY7C1264XV18 – 1 M × 36
■ Two-word burst for reducing address bus frequency
Functional Description
■ DoubleDataRate(DDR)interfacesonbothreadandwriteports
(data transferred at 900 MHz) at 450 MHz
The CY7C1262XV18, and CY7C1264XV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR® II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common I/O devices. Access to each port is through
a common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ Xtreme read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with two 18-bit
words (CY7C1262XV18), or 36-bit words (CY7C1264XV18) that
burst sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR™-II+ Xtreme operates with 2.5 cycle read latency when
DOFF is asserted HIGH
■ Operates similar to QDR-I device with 1 cycle read latency
when DOFF is asserted LOW
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■ Available in x18, and x36 configurations
■ Full data coherency, providing most current data
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Core VDD = 1.8 V ± 0.1 V; I/Os VDDQ = 1.4 V to 1.6 V
❐ Supports 1.5 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in Pb-free packages
For a complete list of related documentation, click here.
■ JTAG 1149.1 compatible test access port
■ Phase-Locked Loop (PLL) for accurate data placement
Selection Guide
Description
Maximum Operating Frequency
450 MHz
450
366 MHz Unit
366
970
MHz
mA
Maximum Operating Current
× 18
× 36
1205
1445
1165
Cypress Semiconductor Corporation
Document Number: 001-70327 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 22, 2017
CY7C1262XV18
CY7C1264XV18
Logic Block Diagram – CY7C1262XV18
18
D
[17:0]
Write
Reg
Write
Reg
20
Address
Register
A
(19:0)
20
Address
Register
A
(19:0)
RPS
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
CQ
CQ
36
18
V
REF
18
18
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
18
18
Q
[17:0]
[1:0]
QVLD
Logic Block Diagram – CY7C1264XV18
36
D
[35:0]
Write
Reg
Write
Reg
19
Address
Register
A
(18:0)
19
Address
Register
A
(18:0)
RPS
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
CQ
CQ
72
36
V
REF
36
36
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
36
36
Q
[35:0]
[3:0]
QVLD
Document Number: 001-70327 Rev. *G
Page 2 of 29
CY7C1262XV18
CY7C1264XV18
Contents
Pin Configuration .............................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Read Operations .........................................................6
Write Operations .........................................................6
Byte Write Operations .................................................6
Concurrent Transactions .............................................7
Depth Expansion .........................................................7
Programmable Impedance ..........................................7
Echo Clocks ................................................................7
Valid Data Indicator (QVLD) ........................................7
PLL ..............................................................................7
Application Example ........................................................8
Truth Table ........................................................................9
Write Cycle Descriptions .................................................9
Write Cycle Descriptions ...............................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11
Disabling the JTAG Feature ......................................11
Test Access Port .......................................................11
Performing a TAP Reset ...........................................11
TAP Registers ...........................................................11
TAP Instruction Set ...................................................11
TAP Controller State Diagram .......................................13
TAP Controller Block Diagram ......................................14
TAP Electrical Characteristics ......................................14
TAP AC Switching Characteristics ...............................15
TAP Timing and Test Conditions ..................................16
Identification Register Definitions ................................17
Scan Register Sizes .......................................................17
Instruction Codes ...........................................................17
Boundary Scan Order ....................................................18
Power Up Sequence in QDR II+ Xtreme SRAM ............19
Power Up Sequence .................................................19
PLL Constraints .........................................................19
Maximum Ratings ...........................................................20
Neutron Soft Error Immunity .........................................20
Operating Range .............................................................20
Electrical Characteristics ...............................................20
DC Electrical Characteristics .....................................20
AC Electrical Characteristics .....................................21
Capacitance ....................................................................21
Thermal Resistance ........................................................21
AC Test Loads and Waveforms .....................................22
Switching Characteristics ..............................................23
Switching Waveforms ....................................................24
Read/Write/Deselect Sequence ................................24
Ordering Information ......................................................25
Ordering Code Definitions .........................................25
Package Diagram ............................................................26
Acronyms ........................................................................27
Document Conventions .................................................27
Units of Measures .....................................................27
Document History Page .................................................28
Sales, Solutions, and Legal Information ......................29
Worldwide Sales and Design Support .......................29
Products ....................................................................29
PSoC® Solutions ......................................................29
Cypress Developer Community .................................29
Technical Support .....................................................29
Document Number: 001-70327 Rev. *G
Page 3 of 29
CY7C1262XV18
CY7C1264XV18
Pin Configuration
The pin configurations for CY7C1262XV18, and CY7C1264XV18 follow. [1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1262XV18 (2 M × 18)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
3
4
5
BWS1
NC
A
6
K
7
NC/288M
BWS0
A
8
9
A
10
NC/72M
NC
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
A
WPS
A
RPS
A
D9
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
Q7
D11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
D6
Q12
D13
VREF
NC
NC
G
H
J
NC
VREF
Q4
K
L
NC
D3
Q15
NC
NC
M
N
P
R
Q1
D17
NC
NC
A
QVLD
NC
A
D0
TCK
A
A
A
A
TMS
CY7C1264XV18 (1 M × 36)
1
2
3
4
5
BWS2
BWS3
A
6
K
7
BWS1
BWS0
A
8
9
10
NC/144M
Q17
Q7
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
CQ
NC/288M NC/72M
WPS
A
RPS
A
A
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
K
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
D15
D6
Q14
D13
VREF
Q4
G
H
J
K
L
D3
Q11
Q1
M
N
P
R
D9
A
QVLD
NC
A
D0
A
A
A
A
A
TMS
Note
1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-70327 Rev. *G
Page 4 of 29
CY7C1262XV18
CY7C1264XV18
Pin Definitions
Pin Name
I/Os
Pin Description
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
D[x:0]
Input-
Synchronous CY7C1262XV18 D[17:0]
CY7C1264XV18 D[35:0]
WPS
Input-
Write Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]
.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte Write Select 0, 1, 2 and 3 Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1262XV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1264XV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during
Synchronous active read and write operations. These address inputs are multiplexed for both read and write operations.
Internally, the device is organized as 2 M × 18 (2 arrays each of 1 M × 18) for CY7C1262XV18, and
1 M × 36 (2 arrays each of 512 K × 36) for CY7C1264XV18. Therefore, only 20 address inputs for
CY7C1262XV18, and 19 address inputs for CY7C1264XV18. These inputs are ignored when the
appropriate port is deselected. The address pins (A) can be assigned any bit order.
Q[x:0]
Output-
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
Synchronous driven out on the rising edge of the K and K clocks during read operations. When the read port is
deselected, Q[x:0] are automatically tristated.
CY7C1262XV18 Q[17:0]
CY7C1264XV18 Q[35:0]
RPS
Input-
Read Port Select Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
K clock. Each read access consists of a burst of two sequential transfers.
QVLD
K
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0]
.
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+ Xtreme. The timing for the echo clocks is shown in the Switching Characteristics on
page 23.
CQ
ZQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+ Xtreme. The timing for the echo clocks is shown in the Switching Characteristics on
page 23.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the minimum
impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation,
connect this pin to a pull up through a 10 k or less pull up resistor. The device behaves in QDR-I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR-I timing.
Document Number: 001-70327 Rev. *G
Page 5 of 29
CY7C1262XV18
CY7C1264XV18
Pin Definitions (continued)
Pin Name
TDO
I/Os
Output
Input
Input
Input
N/A
Pin Description
TDO Pin for JTAG
TCK Pin for JTAG
TDI Pin for JTAG
TMS Pin for JTAG
TCK
TDI
TMS
NC
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
NC/72M
NC/144M
NC/288M
VREF
Input
Input
Input
Input-
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Reference
VDD
VSS
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device
Power Supply Power Supply Inputs for the Outputs of the Device
VDDQ
RPS active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. The address
presented to the address inputs is stored in the read address
register. Following the next two K clock rise, the corresponding
lowest order 18-bit word of data is driven onto the Q[17:0] using
K as the output timing reference. On the subsequent rising edge
Functional Overview
The CY7C1262XV18, and CY7C1264XV18 are synchronous
pipelined Burst SRAMs equipped with a read port and a write
port. The read port is dedicated to read operations and the write
port is dedicated to write operations. Data flows into the SRAM
through the write port and flows out through the read port. These
devices multiplex the address inputs to minimize the number of
address pins required. By having separate read and write ports,
the QDR II+ Xtreme completely eliminates the need to “turn
around” the data bus and avoids any possible data contention,
thereby simplifying system design. Each access consists of two
18-bit data transfers in the case of CY7C1262XV18, and two
36-bit data transfers in the case of CY7C1264XV18 in one clock
cycle.
of K, the next 18-bit data word is driven onto the Q[17:0]
.
When the read port is deselected, the CY7C1262XV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the negative input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
These devices operate with a read latency of two and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to VSS then the device behaves in QDR-I mode with
a read latency of one clock cycle.
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D[17:0] is latched and stored into the
lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is also stored into the write data register,
provided BWS[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified location.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input and output timing
are referenced from the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the input clocks (K and K) as well.
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
Byte Write Operations
Byte write operations are supported by the CY7C1262XV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
CY7C1262XV18 is described in the following sections. The
same basic descriptions apply to CY7C1264XV18.
Read Operations
The CY7C1262XV18 is organized internally as two arrays of
1 M × 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
Document Number: 001-70327 Rev. *G
Page 6 of 29
CY7C1262XV18
CY7C1264XV18
simplify read, modify, or write operations to a byte write
operation.
Echo Clocks
Echo clocks are provided on the QDR II+ Xtreme to simplify data
capture on high speed systems. Two echo clocks are generated
by the QDR II+ Xtreme. CQ is referenced with respect to K and
CQ is referenced with respect to K. These are free running clocks
and are synchronized to the input clock of the QDR II+ Xtreme.
The timing for the echo clocks is shown in Switching
Characteristics on page 23.
Concurrent Transactions
The read and write ports on the CY7C1262XV18 operate
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. The user can start reads and writes in the same clock cycle.
If the ports access the same location at the same time, the SRAM
delivers the most recent information associated with the
specified address location. This includes forwarding data from a
write cycle that was initiated on the previous K clock rise.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR II+ Xtreme to simplify data capture
on high speed systems. The QVLD is generated by the QDR II+
Xtreme device along with data output. This signal is also
edge-aligned with the echo clock and follows the timing of any
data pin. This signal is asserted half a cycle before valid data
arrives.
Depth Expansion
The CY7C1262XV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
100 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 100 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in QDR-I mode (with one cycle latency and a longer
access time). For information, refer to the application note, PLL
Considerations in QDRII/DDRII/QDRII+/DDRII+.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Document Number: 001-70327 Rev. *G
Page 7 of 29
CY7C1262XV18
CY7C1264XV18
Application Example
Figure 2 shows two QDR II+ Xtreme SRAMs used in an application.
Figure 2. Application Example (Width Expansion)
ZQ
CQ/CQ
Q[x:0]
ZQ
SRAM#1
SRAM#2
CQ/CQ
RQ
Q[x:0]
RQ
D[x:0]
D[x:0]
A
RPS WPS BWS
K
K
A
RPS WPS BWS
K
K
DATA IN[2x:0]
DATA OUT [2x:0]
ADDRESS
RPS
WPS
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
SOURCE K
SOURCE K
FPGA / ASIC
Document Number: 001-70327 Rev. *G
Page 8 of 29
CY7C1262XV18
CY7C1264XV18
Truth Table
The truth table for CY7C1262XV18, and CY7C1264XV18 follows. [2, 3, 4, 5, 6, 7, 8]
Operation
K
RPS WPS
DQ
DQ
Write Cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
L–H
X
L
L
D(A) at K(t)
D(A + 1) at K(t)
Read Cycle: (2.5 cycle Latency)
Load address on the rising edge of K;
L–H
X
Q(A) at K(t + 2)
Q(A + 1) at K(t + 3)
wait two and half cycles; read data on K and K rising edges.
NOP: No Operation
L–H
H
X
H
X
D = X
Q = High Z
D = X
Q = High Z
Standby: Clock Stopped
Stopped
Previous State
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1262XV18 follows. [2, 8]
BWS0 BWS1
K
Comments
K
L
L
L–H
–
During the data portion of a write sequence
CY7C1262XV18 both bytes (D[17:0]) are written into the device.
L
L
–
L–H
–
L–H During the data portion of a write sequence:
CY7C1262XV18 both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the data portion of a write sequence:
CY7C1262XV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C1262XV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence
CY7C1262XV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C1262XV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
7. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
8. Is based on a write cycle that was initiated in accordance with Truth Table. BWS , BWS , BWS and BWS can be altered on different portions of a write cycle, as long
0
1
2
3
as the setup and hold requirements are achieved.
Document Number: 001-70327 Rev. *G
Page 9 of 29
CY7C1262XV18
CY7C1264XV18
Write Cycle Descriptions
The write cycle description table for CY7C1264XV18 follows. [9, 10]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Notes
9. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
10. Is based on a write cycle that was initiated in accordance with Truth Table. BWS , BWS , BWS and BWS can be altered on different portions of a write cycle, as long
0
1
2
3
as the setup and hold requirements are achieved.
Document Number: 001-70327 Rev. *G
Page 10 of 29
CY7C1262XV18
CY7C1264XV18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V I/Os logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The section Boundary Scan Order on page 18 shows the order
in which the bits are connected. Each bit corresponds to one of
the bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-70327 Rev. *G
Page 11 of 29
CY7C1262XV18
CY7C1264XV18
IDCODE
BYPASS
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
SAMPLE/PRELOAD
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate”, is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set LOW to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
Document Number: 001-70327 Rev. *G
Page 12 of 29
CY7C1262XV18
CY7C1264XV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [11]
TEST-LOGIC
1
RESET
0
1
1
1
SELECT
TEST-LOGIC/
SELECT
0
IR-SCAN
IDLE
DR-SCAN
0
0
1
1
CAPTURE-DR
0
CAPTURE-IR
0
0
0
1
SHIFT-DR
1
SHIFT-IR
1
1
0
EXIT1-DR
0
EXIT1-IR
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
0
UPDATE-DR
1
1
0
Note
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-70327 Rev. *G
Page 13 of 29
CY7C1262XV18
CY7C1264XV18
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
TDI
Selection
TDO
Instruction Register
Circuitry
Circuitry
31 30
29
.
.
2
Identification Register
.
108
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range
Parameter [12, 13, 14]
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
IOH =2.0 mA
Min
1.4
1.6
–
Max
–
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
IOH =100 A
–
V
IOL = 2.0 mA
0.4
0.2
V
IOL = 100 A
–
V
–
–
0.65 × VDD VDD + 0.3
V
VIL
–0.3
–5
0.35 × VDD
5
V
IX
Input and Output Load Current GND VI VDD
A
Notes
12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 20.
13. Overshoot: V < V + 0.35 V (Pulse width less than t /2), Undershoot: V /2).
> 0.3 V (Pulse width less than t
IH(AC)
DD
TCYC
IL(AC)
TCYC
14. All Voltage referenced to Ground.
Document Number: 001-70327 Rev. *G
Page 14 of 29
CY7C1262XV18
CY7C1264XV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [15, 16]
Description
Min
50
–
Max
–
Unit
ns
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
tTF
20
–
MHz
ns
tTH
20
20
tTL
TCK Clock LOW
–
ns
Setup Times
tTMSS
tTDIS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
Notes
15. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
16. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 V/ns.
R
F
Document Number: 001-70327 Rev. *G
Page 15 of 29
CY7C1262XV18
CY7C1264XV18
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [17]
Figure 3. TAP Timing and Test Conditions
0.9 V
50
ALL INPUT PULSES
1.8 V
0.9 V
TDO
0 V
Slew Rate = 1 V/ns
Z = 50
0
C = 20 pF
L
tTL
tTH
GND
(a)
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Note
17. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 V/ns.
R
F
Document Number: 001-70327 Rev. *G
Page 16 of 29
CY7C1262XV18
CY7C1264XV18
Identification Register Definitions
Value
Instruction Field
Description
CY7C1262XV18
CY7C1264XV18
000
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
000
Version number.
11010010000010100
00000110100
11010010000100100
00000110100
Defines the type of SRAM.
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-70327 Rev. *G
Page 17 of 29
CY7C1262XV18
CY7C1264XV18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
Bit #
84
Bump ID
1J
1
6P
5B
5A
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
4A
87
3J
4
7N
5C
4B
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
3A
90
2L
7
8P
2A
91
3L
8
9R
1A
92
1M
1L
9
11P
10P
10N
9P
2B
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
3B
94
3N
1C
1B
95
3M
1N
96
10M
11N
9M
9D
3D
3C
1D
2C
3E
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
2D
2E
3R
4R
10L
11K
10K
9J
1E
4P
8B
2F
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document Number: 001-70327 Rev. *G
Page 18 of 29
CY7C1262XV18
CY7C1264XV18
PLL Constraints
Power Up Sequence in QDR II+ Xtreme SRAM
■ PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var
QDR II+ Xtreme SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
.
■ The PLL functions at frequencies down to 120 MHz.
Power Up Sequence
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 100 s of stable clock
to relock to the desired clock frequency.
■ Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ
.
❐ Apply VDDQ before VREF or at the same time as VREF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 100
s to lock the PLL.
Figure 4. Power Up Waveforms
Document Number: 001-70327 Rev. *G
Page 19 of 29
CY7C1262XV18
CY7C1264XV18
Maximum Ratings
Neutron Soft Error Immunity
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Test
Conditions
Parameter Description
Typ Max* Unit
Storage Temperature ............................... –65 °C to +150 °C
Supply Voltage on VDD Relative to GND .....–0.5 V to +2.9 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Applied to Outputs in High Z ......–0.5 V to VDDQ + 0.3 V
DC Input Voltage [18] ...........................–0.5 V to VDD + 0.3 V
Current into Outputs (LOW) ........................................ 20 mA
LSBU
LMBU
SEL
Logical
Single-Bit
Upsets
25 °C
25 °C
85 °C
260 271
FIT/
Mb
Logical
Multi-Bit
Upsets
0
0
0.01 FIT/
Mb
Single Event
Latchup
0.1
FIT/
Dev
Static Discharge Voltage
(MIL-STD-883, M. 3015) ..........................................> 2001V
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”
Latch up Current ....................................................> 200 mA
Maximum Junction Temperature ............................... 125 °C
Operating Range
Ambient
Temperature (TA)
[19]
[19]
Range
VDD
VDDQ
Commercial
Industrial
0 °C to +70 °C
1.8 ± 0.1 V 1.4 V to 1.6 V
–40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [20]
VDD
Description
Power Supply Voltage
I/Os Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
1.7
Typ
1.8
1.5
–
Max
Unit
V
1.9
VDDQ
VOH
1.4
1.6
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
V
Note 21
Note 22
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
V
VOL
–
V
VOH(LOW)
VOL(LOW)
VIH
IOH =0.1 mA, Nominal Impedance
–
V
IOL = 0.1 mA, Nominal Impedance
–
0.2
V
VREF + 0.1
–0.15
–
VDDQ + 0.15
VREF – 0.1
2
V
VIL
–
V
IX
Input Leakage Current
Output Leakage Current
Input Reference Voltage
VDD Operating Supply
GND VI VDDQ
2
–
A
A
V
IOZ
GND VI VDDQ, Output Disabled
Typical Value = 0.75 V
2
–
2
VREF
0.68
0.75
–
0.86
[23]
IDD
VDD = Max,
450 MHz (× 18)
(× 36)
–
–
–
–
1205
mA
IOUT = 0 mA,
f = fMAX = 1/tCYC
–
1445
366 MHz (× 18)
(× 36)
–
970
mA
–
1165
Notes
18. Overshoot: V
19. Power up: Assumes a linear ramp from 0 V to V
20. All Voltage referenced to Ground.
V
+ 0.35 V (Pulse width less than t
/2), Undershoot: V
0.3 V (Pulse width less than t
/2).
IH(AC)
DDQ
CYC
IL(AC)
CYC
within 200 ms. During this time V < V and V
V
.
DD
DD(min)
IH
DD
DDQ
21. Output are impedance controlled. I = (V
/2)/(RQ/5) for values of 175 ohms RQ 350 ohms.
DDQ
DDQ
OH
22. Output are impedance controlled. I = (V
/2)/(RQ/5) for values of 175 ohms RQ 350 ohms.
OL
23. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-70327 Rev. *G
Page 20 of 29
CY7C1262XV18
CY7C1264XV18
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [20]
Description
Test Conditions
Min
–
Typ
–
Max
1205
1445
970
Unit
ISB1
Automatic Power down
Current
Max VDD
,
450 MHz (× 18)
(× 36)
mA
BothPortsDeselected,
VIN VIH or VIN VIL
–
–
366 MHz (× 18)
(× 36)
–
–
mA
f = fMAX = 1/tCYC
Inputs Static
,
–
–
1165
AC Electrical Characteristics
Over the Operating Range
Parameter [24]
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
VREF + 0.2
–0.24
Typ
–
Max
Unit
V
VIH
VIL
VDDQ + 0.24
VREF – 0.2
–
V
Capacitance
Parameter [25]
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
4
Unit
pF
CIN
CO
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
4
pF
Thermal Resistance
165-ballFBGA
Package
Parameter [25]
Description
Test Conditions
Unit
JA (0 m/s)
JA (1 m/s)
JA (3 m/s)
Thermal resistance
(junction to ambient)
Socketed on a 170 × 220 × 2.35 mm, eight-layer printed circuit
board
14.43
13.40
12.66
11.38
°C/W
°C/W
°C/W
°C/W
JB
Thermal resistance
(junction to board)
JC
Thermal resistance
(junction to case)
3.30
°C/W
Notes
24. Overshoot: V
< V
+ 0.35 V (Pulse width less than t
/2), Undershoot: V
> 0.3 V (Pulse width less than t
/2).
IH(AC)
DDQ
CYC
IL(AC)
CYC
25. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-70327 Rev. *G
Page 21 of 29
CY7C1262XV18
CY7C1264XV18
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF = 0.75 V
0.75 V
VREF
VREF
0.75 V
R = 50
OUTPUT
[26]
ALL INPUT PULSES
1.25 V
Z = 50
0
DEVICE
R = 50
L
OUTPUT
0.75 V
UNDER
DEVICE
UNDER
0.25 V
TEST
5 pF
VREF = 0.75 V
SLEW RATE= 2 V/ns
ZQ
TEST
ZQ
RQ =
RQ =
250
250
INCLUDING
JIG AND
SCOPE
(b)
(a)
Note
26. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V
= 1.5 V, input
DDQ
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5.
OL OH
Document Number: 001-70327 Rev. *G
Page 22 of 29
CY7C1262XV18
CY7C1264XV18
Switching Characteristics
Over the Operating Range
Parameters [27, 28]
450 MHz
366 MHz
Unit
Description
Cypress Consortium
Parameter Parameter
Min
Max
Min
Max
tPOWER
tCYC
VDD(Typical) to the First Access [29]
K Clock Cycle Time
1
–
8.4
–
1
–
8.4
–
ms
ns
ns
ns
ns
tKHKH
tKHKL
tKLKH
tKHKH
2.2
0.4
0.4
2.73
0.4
tKH
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
tKL
–
0.4
–
tKHKH
Setup Times
tSA
K Clock Rise to K Clock Rise (rising edge to rising edge) 0.94
–
1.16
–
tAVKH
tIVKH
tIVKH
Address Setup to K Clock Rise
Control Setup to K Clock Rise
0.275
0.275
0.275
–
–
–
0.4
0.4
0.4
–
–
–
ns
ns
ns
tSC
(RPS, WPS)
tSCDDR
DDR Control Setup to Clock (K/K) Rise (BWS0, BWS1,
BWS2, BWS3)
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.275
–
0.4
–
ns
Hold Times
tHA
tKHAX
tKHIX
tKHIX
Address Hold after K Clock Rise
0.275
0.275
–
–
–
0.4
0.4
0.4
–
–
–
ns
ns
ns
tHC
Control Hold after K Clock Rise
(RPS, WPS)
tHCDDR
DDR Control Hold after Clock (K/K) Rise (BWS0, BWS1, 0.275
BWS2, BWS3)
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.275
–
0.4
–
ns
Output Times
tCCQO
tCQOH
tCQD
tCHCQV
–
0.45
–
–
0.45
–
ns
ns
ns
ns
ns
ns
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
tCQHCQH
–0.45
–
–0.45
–
0.13
–
0.15
–
tCQDOH
tCQH
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH [30]
–0.13
1.02
1.02
–0.15
1.285
1.285
–
–
tCQHCQH
CQ Clock Rise to CQ Clock Rise
edge) [30]
–
–
(rising edge to rising
tCHZ
tCHQZ
Clock (
) Rise to High Z (Active to High Z) [31, 32]
) Rise to Low Z [31, 32]
–
0.45
–
–
0.45
–
ns
ns
ns
K/K
K/K
tCLZ
tCHQX1
tCQHQVLD
Clock (
–0.45
–0.15
–0.45
–0.20
tQVLD
Echo Clock High to QVLD Valid [33]
0.15
0.20
PLL Timing
tKC Var
tKC lock
tKC Reset
tKC Var
Clock Phase Jitter
–
0.15
–
–
0.15
–
ns
s
ns
tKC lock
tKC Reset
PLL Lock Time (K)
K Static to PLL Reset [34]
100
30
100
30
–
–
Notes
27. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V
= 1.5 V, input
DDQ
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5 on page 22.
OL OH
28. When a part with a maximum frequency above 366 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
29. This part has a voltage regulator internally; t
is the time that the power must be supplied above V minimum initially before initiating a read or write operation.
DD
POWER
30. These parameters are extrapolated from the input timing parameters (t
/2 – 80 ps, where 80 ps is the internal jitter). These parameters are only guaranteed by
CYC
design and are not tested in production.
31. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of Figure 5 on page 22. Transition is measured 100 mV from steady state voltage.
CHZ CLZ
32. At any voltage and temperature t
is less than t
.
CHZ
CLZ
33. t
spec is applicable for both rising and falling edges of QVLD signal.
QVLD
34. Hold to >V or <V
.
IH
IL
Document Number: 001-70327 Rev. *G
Page 23 of 29
CY7C1262XV18
CY7C1264XV18
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Waveform for 2.5 Cycle Read Latency [35, 36, 37]
Notes
35. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
36. Outputs are disabled (High Z) one clock cycle after a NOP.
37. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-70327 Rev. *G
Page 24 of 29
CY7C1262XV18
CY7C1264XV18
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page
at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the
office closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
450 CY7C1262XV18-450BZXC
CY7C1264XV18-450BZXC
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Commercial
CY7C1264XV18-450BZXI
165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Industrial
366 CY7C1262XV18-366BZXC
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY 7 C 12XX X V18 - XXX BZ
X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
BZ = 165-ball FBGA
Frequency Range: XXX = 450 MHz or 366 MHz
V18 = 1.8 V
Die Revision X = Xtreme
Part Identifier:
12XX = 1262 or 1264
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-70327 Rev. *G
Page 25 of 29
CY7C1262XV18
CY7C1264XV18
Package Diagram
Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 001-70327 Rev. *G
Page 26 of 29
CY7C1262XV18
CY7C1264XV18
Acronyms
Document Conventions
Units of Measures
Acronym
Description
DDR
EIA
Double Data Rate
Symbol
°C
Unit of Measure
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
High Speed Transceiver Logic
Input/Output
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
nanosecond
ohm
FBGA
HSTL
I/O
MHz
µA
µs
JEDEC
JTAG
LMBU
LSB
Joint Electron Devices Engineering Council
Joint Test Action Group
Logical Multi-Bit Upsets
Least Significant Bit
Logical Single-Bit Upsets
Most Significant Bit
mA
mm
ms
ns
LSBU
MSB
PLL
%
percent
Phase Locked Loop
Quad Data Rate
pF
ps
picofarad
picosecond
volt
QDR
SEL
Single Event Latch-up
Static Random Access Memory
Test Access Port
V
SRAM
TAP
W
watt
TCK
Test Clock
TDI
Test Data-In
TDO
TMS
Test Data-Out
Test Mode Select
Document Number: 001-70327 Rev. *G
Page 27 of 29
CY7C1262XV18
CY7C1264XV18
Document History Page
Document Title: CY7C1262XV18/CY7C1264XV18, 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle
Read Latency)
Document Number: 001-70327
Submission
Date
Orig. of
Change
Rev.
ECN
Description of Change
**
3377025
3532213
09/20/2011
02/22/2012
VIDB
New data sheet.
*A
PRIT /
GOPA
Changed status from Preliminary to Final.
*B
3774109
10/11/2012
PRIT
Updated Application Example (Updated Figure 2).
Updated TAP Electrical Characteristics (Updated Note 13).
Updated TAP AC Switching Characteristics (Updated Note 16).
Updated TAP Timing and Test Conditions (Updated Note 17 and updated
Figure 3).
Updated Thermal Resistance (Changed value of JA parameter from
26.64 °C/W to 14.84 °C/W for 165-ball FBGA Package, changed value of JC
parameter from 4.31 °C/W to 5.1 °C/W for 165-ball FBGA Package).
Updated Package Diagram (spec 51-85180 (Changed revision from *E to *F)).
*C
*D
4283422
4436366
02/17/2014
07/10/2014
PRIT
PRIT
Updated Operating Range:
Included Industrial Temperature Range related information.
Updated Ordering Information (Updated part numbers).
Updated to new template.
Updated Application Example:
Updated Figure 2.
Updated Thermal Resistance:
Updated values of JA and JC parameters.
Included JB parameter and its details.
*E
*F
4574060
4976464
11/19/2014
10/20/2015
PRIT
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85180 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*G
6003078
12/22/2017 AESATMP8 Updated logo and Copyright.
Document Number: 001-70327 Rev. *G
Page 28 of 29
CY7C1262XV18
CY7C1264XV18
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Memory
cypress.com/support
cypress.com/memory
cypress.com/mcu
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2011-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-70327 Rev. *G
Revised December 22, 2017
Page 29 of 29
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