CY7C1089DV33_12 [CYPRESS]
64-Mbit (8 M Ã 8) Static RAM; 64兆位（ 8米?? 8 ）静态RAM
| 型号： | CY7C1089DV33_12 |
| 厂家： | 
CYPRESS |
| 描述： | 64-Mbit (8 M Ã 8) Static RAM |
| 文件： | 总11页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1089DV33
64-Mbit (8 M × 8) Static RAM
Features
Functional Description
■ High speed
❐ tAA = 12 ns
The CY7C1089DV33 is a high-performance CMOS static RAM
organized as 8,388,608 words by 8 bits.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A22).
■ Low active power
❐ ICC = 300 mA at 12 ns
■ Low complementary metal oxide semiconductor (CMOS)
standby power
❐ ISB2 = 100 mA
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) LOW and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. Under these conditions, the contents
of the memory location specified by the address pins appear on
the I/O pins. See Truth Table on page 9 for a complete
description of Read and Write modes.
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0-V data retention
■ Automatic power-down when deselected
■ Transistor-transistor logic (TTL)-compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2 features
■ Available in Pb-free 48-ball fine ball grid array (FBGA) package
The input and output pins (I/O0 through I/O7) are placed in a high
impedance state when the device is deselected (CE1 LOW or
CE2 HIGH), the outputs are disabled (OE HIGH), or during a
write operation (CE1 LOW, CE2 HIGH and WE LOW).
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
I/O0 – I/O7
8M x 8
A4
ARRAY
A5
A6
A7
A8
A9
WE
OE
COLUMN
DECODER
CE
2
CE
1
Selection Guide
Description
Maximum access time
–12
12
Unit
ns
Maximum operating current
Maximum CMOS standby current
300
100
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-53993 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 22, 2012
CY7C1089DV33
Contents
Pin Configuration ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
DC Electrical Characteristics ...........................................4
Capacitance .......................................................................4
Thermal Resistance ..........................................................4
Data Retention Characteristics ........................................5
AC Switching Characteristics ..........................................6
Switching Waveforms .......................................................7
Truth Table ........................................................................9
Ordering Information ........................................................9
Ordering Code Definition .............................................9
Package Diagram ............................................................10
Acronyms ........................................................................10
Document Conventions .................................................10
Units of Measure .......................................................10
Document History Page .................................................11
Sales, Solutions, and Legal Information ......................11
Worldwide Sales and Design Support .......................11
Products ....................................................................11
PSoC Solutions .........................................................11
Document Number: 001-53993 Rev. *C
Page 2 of 11
CY7C1089DV33
Pin Configuration
Figure 1. 48-Ball FBGA (Top View) [1]
1
2
3
4
6
5
A0
A1
A2
CE2
A22
A
B
C
OE
NC
A4
A6
A3
A5
NC
I/O4
VCC
VSS
CE1
NC
NC
I/O0 NC
I/O1
VSS
A7 I/O5
D
E
F
A17
A18
VCC
I/O2
A16 I/O6
A14
A15
NC
I/O7
NC
I/O3 NC
A12 A13
A9
A21
A8
NC
A19
WE
G
H
A10 A11
A20
Note
1. NC pins are not connected to the die.
Document Number: 001-53993 Rev. *C
Page 3 of 11
CY7C1089DV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage............................................>2001 V
(MIL-STD-883, Method 3015)
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied ........................................... –55 C to +125 C
Latch up current.......................................................>140 mA
Supply voltage on VCC relative to GND[2].....–0.5 V to +4.6 V
Operating Range
DC voltage applied to outputs
Ambient
Temperature
Range
VCC
in high-Z state[2]...................................–0.5 V to VCC + 0.5 V
DC input voltage[2]...............................–0.5 V to VCC + 0.5 V
Industrial
–40 C to +85 C
3.3V 0.3V
DC Electrical Characteristics
Over the Operating Range
–12
Parameter
Description
Test Conditions
Unit
Min
2.4
–
Max
VOH
VOL
VIH
VIL
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage[2]
Input leakage current
Output leakage current
VCC = Min, IOH = –4.0 mA
VCC = Min, IOL = 8.0 mA
–
0.4
V
V
2.0
–0.3
–1
–1
–
VCC + 0.3
0.8
V
V
IIX
GND < VIN < VCC
GND < VOUT < VCC, Output disabled
= 0 mA CMOS levels
+1
A
A
mA
mA
IOZ
ICC
ISB1
+1
VCC operating supply current VCC = Max, f = fMAX = 1/tRC, OUT
Automatic CE power-down Max VCC, CE1 > VIH, CE2 < VIL,
current — TTL inputs VIN > VIH or VIN < VIL, f = fMAX
Automatic CE power-down Max VCC, CE1 > VCC – 0.3V, CE2 < 0.3V,
current —CMOS inputs IN > VCC – 0.3V, or VIN < 0.3V, f = 0
I
300
–
120
ISB2
–
100
mA
V
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
COUT
Description
Input capacitance
I/O capacitance
Test Conditions
FBGA
32
Unit
TA = 25 C, f = 1 MHz, VCC = 3.3 V
pF
pF
40
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
FBGA
Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
55
C/W
JC
Thermal resistance
(junction to case)
23.04
C/W
Note
2.
V
(min) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IH CC
IL
Document Number: 001-53993 Rev. *C
Page 4 of 11
CY7C1089DV33
Figure 2. AC Test Loads and Waveforms[3]
High-Z characteristics
50
R1 317
3.3 V
= 1.5 V
OUTPUT
VTH
OUTPUT
Z = 50
30 pF*
0
R2
351
5 pF*
(a)
ALL INPUT PULSES
90%
INCLUDING
JIG AND
SCOPE
* Capacitive load consists
of all components of the
test environment
3.0 V
90%
10%
(b)
10%
GND
Rise Time > 1 V/ns
Fall Time:
> 1 V/ns
(c)
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for data retention
Conditions
Min
Typ
Max
–
Unit
2
–
V
ICCDR
Data retention current
VCC = 2 V, CE1 > VCC – 0.2 V, CE2 < 0.2 V,
IN > VCC – 0.2 V or VIN < 0.2 V
100
mA
–
–
V
[4]
tCDR
Chip deselect to data retention time
Operation recovery time
0
–
–
–
–
ns
ns
[ 5]
tR
12
Figure 3. Data Retention Waveform
DATA RETENTION MODE
3.0V
tCDR
3.0V
V
DR
> 2V
VCC
CE1
CE2
t
R
Notes
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). 100 s (t
) after reaching the minimum operating
DD
power
V
, normal SRAM operation begins including reduction in V to the data retention (V , 2.0V) voltage.
DD
DD
CCDR
4. Tested initially and after any design or process changes that may affect these parameters.
5. Full device operation requires linear V ramp from V to V
> 50 s or stable at V > 50 s.
CC
DR
CC(min.)
CC(min.)
Document Number: 001-53993 Rev. *C
Page 5 of 11
CY7C1089DV33
AC Switching Characteristics
Over the Operating Range [6]
–12
Parameter
Description
Unit
Max
Min
Read Cycle
tpower
VCC(typical) to the first access[7]
100
12
–
–
–
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read cycle time
tAA
Address to data valid
12
–
tOHA
Data hold from address change
CE1 LOW and CE2 HIGH to data valid
OE LOW to data valid
3
tACE
–
12
7
tDOE
–
tLZOE
OE LOW to low-Z
OE HIGH to high-Z [8]
CE1 LOW and CE2 HIGH to low-Z [8]
CE1 HIGH and CE2 LOW to high-Z [8]
CE1 LOW and CE2 HIGH to power-up [9]
CE1 HIGH and CE2 LOW to power-down [9]
1
–
tHZOE
–
7
tLZCE
3
–
tHZCE
–
7
tPU
0
–
tPD
–
12
Write Cycle [10, 11]
tWC
tSCE
tAW
Write cycle time
12
9
–
–
–
–
–
–
–
–
–
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW and CE2 HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
9
tHA
0
tSA
0
tPWE
tSD
9
Data setup to write end
Data hold from write end
WE HIGH to low-Z[8]
7
tHD
0
tLZWE
tHZWE
3
WE LOW to high-Z[8]
–
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output
loading shown in part a) of AC Test Loads and Waveforms[3], unless specified otherwise.
7.
8.
t
gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
POWER CC
t
, t
, t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms[3].
HZOE HZCE HZWE LZOE LZCE
LZWE
9. These parameters are guaranteed by design and are not tested.
10. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . Chip enables must be active and WE must be LOW to initiate a write,
1
IL
2
IH
and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document Number: 001-53993 Rev. *C
Page 6 of 11
CY7C1089DV33
Switching Waveforms
Figure 4. Read Cycle No. 1 [12, 13, 14]
tRC
ADDRESS
t
AA
t
OHA
DATA I/O
PREVIOUS DATA VALID
DATAOUT VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [12, 14, 15]
t
RC
ADDRESS
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA I/O
VCC
SUPPLY
CURRENT
DATAOUT VALID
t
LZCE
t
PD
ICC
ISB
t
PU
50%
50%
Notes
12. CE refers to the internal logical combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other combinations, CE is HIGH.
1
2
1
2
13. The device is continuously selected. CE = V
14. WE is HIGH for read cycle.
.
IL
15. Address valid before or similar to CE transition LOW.
Document Number: 001-53993 Rev. *C
Page 7 of 11
CY7C1089DV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (CE Controlled) [16, 17, 18]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
t
SD
HD
DATAIN VALID
DATA I/O
Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [16, 17, 18]
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
HZWE
t
t
SD
HD
DATAIN VALID
DATA I/O
t
LZWE
Notes
16. CE refers to the internal logical combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other combinations, CE is HIGH.
1
2
1
2
17. Data I/O is high impedance if OE = V
.
IH
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 001-53993 Rev. *C
Page 8 of 11
CY7C1089DV33
Truth Table
CE1
H
CE2
X
OE
X
WE
X
I/O0 – I/O7
High-Z
Mode
Power
Power down
Power down
Read all bits
Write all bits
Standby (ISB
)
)
X
L
X
X
High-Z
Standby (ISB
L
H
L
H
Data Out
Data In
High-Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
H
X
L
L
H
H
H
Selected, Outputs disabled
Ordering Information
Speed
Package
Operating
Range
Ordering Code
(ns)
Package Type
48-ball FBGA (8 × 9.5 × 1.4 mm) (Pb-free)
Diagram
12
Ordering Code Definition
CY 7 1 08 9 D V33 - xx xxx
CY7C1089DV33-12BAXI
001-50044
Industrial
C
x
Temperature Range: x = I
I = Industrial
Package Type: xxx = BAX
BAX = 48-ball FBGA (Pb-free)
Speed: xx = 12 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
9 = Data width × 8 bits
08 = 64-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Document Number: 001-53993 Rev. *C
Page 9 of 11
CY7C1089DV33
Package Diagram
Figure 8. 48-Ball FBGA (8 x 9.5 x 1.4 mm) (001-50044)
001-50044 *C
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CMOS
FBGA
I/O
complementary metal oxide semiconductor
fine ball grid array
Symbol
Unit of Measure
°C
A
mA
MHz
ns
degrees Celsius
input/output
microampere
milliampere
megahertz
nanosecond
picofarad
volt
SRAM
TTL
static random access memory
transistor-transistor logic
pF
V
ohm
W
watt
Document Number: 001-53993 Rev. *C
Page 10 of 11
CY7C1089DV33
Document History Page
Document Title: CY7C1089DV33, 64-Mbit (8 M × 8) Static RAM
Document Number: 001-53993
Submission
Date
Orig. of
Change
Revision
ECN
Description of Change
**
2746867
3100499
07/31/2009
12/02/2010
VKN/AESA New Data sheet
*A
PRAS
Updated Note 12.
Changed datasheet status from Preliminary to Final.
Updated Package Diagram and Sales, Solutions, and Legal Information.
Added Acronyms, Document Conventions and Ordering Code Definition.
*B
*C
3178259
3720118
21/02/2011
08/22/2012
PRAS
TAVA
Post to external web.
Minor Text edits.
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© Cypress Semiconductor Corporation, 2009-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53993 Rev. *C
Revised August 22, 2012
Page 11 of 11
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