CY7C109-15ZI [CYPRESS]
Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, TSOP1-32;
| 型号： | CY7C109-15ZI |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, TSOP1-32 静态存储器 光电二极管 |
| 文件： | 总11页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C109
CY7C1009
128K x 8 Static RAM
able (OE), and three-state drivers. Writing to the device is ac-
Features
complished by taking Chip Enable One (CE ) and Write En-
1
• High speed
able (WE) inputs LOW and Chip Enable Two (CE ) input HIGH.
2
Data on the eight I/O pins (I/O through I/O ) is then written
0
7
— t = 10 ns
AA
into the location specified on the address pins (A through
0
• Low active power
A
).
16
— 1017 mW (max., 12 ns)
Reading from the device is accomplished by taking Chip En-
• Low CMOS standby power
able One (CE ) and Output Enable (OE) LOW while forcing
1
Write Enable (WE) and Chip Enable Two (CE ) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
— 55 mW (max.), 4 mW (Low-power version)
• 2.0V Data Retention (Low-power version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
2
The eight input/output pins (I/O through I/O ) are placed in a
0
7
high-impedance state when the device is deselected (CE
1
• Easy memory expansion with CE , CE , and OE options
1
2
HIGH or CE LOW), the outputs are disabled (OE HIGH), or
2
during a write operation (CE LOW, CE HIGH, and WE LOW).
1
2
Functional Description
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
The CY7C109 / CY7C1009 is a high-performance CMOS stat-
ic RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE ),
1
an active HIGH Chip Enable (CE ), an active LOW Output En-
2
Logic Block Diagram
Pin Configurations
SOJ
Top View
V
NC
32
31
30
1
CC
A
16
A
14
A
12
A
15
2
3
4
CE
2
29
28
WE
5
A
A
A
A
7
13
27
26
A
6
6
8
A
5
7
9
25
24
23
22
21
A
A
3
8
9
10
11
12
13
4
A
11
OE
I/O
A
A
10
2
0
A
1
CE
INPUT BUFFER
1
I/O
7
A
0
I/O
I/O
I/O
0
I/O
1
I/O
2
I/O
6
20
19
1
2
A
0
I/O
5
14
15
16
A
1
I/O
I/O
4
18
17
A
2
GND
3
109–2
A
3
4
A
A
A
WE
CE
1
2
32
31
11
OE
I/O
I/O
I/O
3
4
5
512 x 256 x 8
ARRAY
A
A
A
9
10
5
6
3
4
5
6
7
8
A
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CE
I/O
A
13
7
A
7
8
I/O
6
I/O
5
A
2
A
15
I/O
I/O
TSOP I
4
V
Top View
CC
3
NC
9
GND
(not to scale)
A
16
I/O
2
I/O
I/O
10
11
12
13
14
15
16
6
7
POWER
DOWN
I/O
1
COLUMN
DECODER
A
14
CE
2
1
CE
A
I/O
12
0
A
A
6
A
A
A
0
7
WE
A
1
A
2
5
109–1
A
3
OE
4
109–3
Selection Guide
7C109-10
7C109-12
7C109-15
7C109-20
7C109-25
7C109-35
7C1009-10 7C1009-12 7C1009-15 7C1009-20 7C1009-25 7C1009-35
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low-Power Version
10
195
10
2
12
185
10
2
15
155
10
2
20
140
10
25
135
10
35
125
10
—
—
—
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
September 7, 1999
CY7C109
CY7C1009
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Ambient
[2]
[1]
Range
Commercial
Industrial
Temperature
0°C to +70°C
−40°C to +85°C
V
CC
Supply Voltage on V to Relative GND .... –0.5V to +7.0V
CC
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
[1]
in High Z State ....................................–0.5V to V + 0.5V
CC
[1]
DC Input Voltage .................................–0.5V to V + 0.5V
CC
Current into Outputs (LOW).........................................20 mA
[3]
Electrical Characteristics Over the Operating Range
7C109-10
7C1009-10
7C109-12
7C1009-12
7C109-15
7C1009-15
Parameter
Description
Test Conditions
= Min.,
CC
Min.
Max.
Min.
Max.
Min. Max. Unit
V
Output HIGH Voltage
V
I
2.4
2.4
2.4
V
V
V
OH
OL
IH
= –4.0 mA
OH
V
V
V
Output LOW Voltage
Input HIGH Voltage
V
I
= Min.,
0.4
0.4
0.4
CC
= 8.0 mA
OL
2.2
V
2.2
V
2.2
V
CC
CC
CC
+ 0.3
0.8
+1
+ 0.3
0.8
+1
+ 0.3
[1]
Input LOW Voltage
–0.3
–1
–0.3
–1
–0.3
–1
0.8
+1
+5
V
IL
I
I
Input Load Current
GND < V < V
CC
µA
µA
IX
I
Output Leakage
Current
GND < V < V ,
CC
–5
+5
–5
+5
–5
OZ
OS
CC
I
Output Disabled
I
I
Output Short
Circuit Current
V
V
= Max.,
–300
–300
–300 mA
CC
[3]
= GND
OUT
V
Operating
Supply Current
V
I
= Max.,
= 0 mA,
195
185
155
40
mA
mA
CC
CC
OUT
f = f
= 1/t
MAX
RC
I
I
Automatic CE
Power-Down Current or CE < V ,
—TTL Inputs
Max. V , CE > V
45
45
SB1
SB2
CC
1
IH
2
IL
V
V
> V or
IN
IN
IH
< V , f = f
IL
MAX
Automatic CE
Power-Down Current CE > V – 0.3V,
—CMOS Inputs
Max. V
,
10
2
10
2
10
2
mA
CC
1
CC
L
or CE < 0.3V,
2
V
> V – 0.3V,
CC
IN
or V < 0.3V, f = 0
IN
Shaded areas contain preliminary information.
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
CY7C109
CY7C1009
Electrical Characteristics Over the Operating Range (continued)
7C109-20
7C109-25
7C1009-25
7C109-35
7C1009-35
7C1009-20
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
Output HIGH Voltage
V
= Min.,
CC
= –4.0 mA
2.4
2.4
2.4
V
OH
OL
IH
I
OH
V
V
V
Output LOW Voltage
Input HIGH Voltage
V
= Min.,
0.4
0.4
0.4
V
V
CC
I
= 8.0 mA
OL
2.2
V
2.2
V
2.2
V
CC
CC
CC
+ 0.3
0.8
+1
+ 0.3
0.8
+1
+ 0.3
0.8
+1
[1]
Input LOW Voltage
–0.3
–1
–0.3
–1
–0.3
–1
V
IL
I
I
Input Load Current
GND < V < V
CC
µA
µA
IX
I
Output Leakage
Current
GND < V < V ,
CC
Output Disabled
–5
+5
–5
+5
–5
+5
OZ
OS
CC
I
I
I
Output Short
Circuit Current
V
= Max.,
–300
–300
–300
mA
mA
CC
[3]
V
= GND
OUT
V
Operating
V
= Max.,
= 0 mA,
140
135
125
CC
CC
Supply Current
I
OUT
f = f
= 1/t
MAX
RC
I
I
Automatic CE
Power-Down Current
—TTL Inputs
Max. V , CE > V
30
10
30
10
25
10
mA
mA
SB1
SB2
CC
1
IH
or CE < V ,
2 IL
> V or
IH
V
V
IN
IN
< V , f = f
IL
MAX
Automatic CE
Max. V
,
CC
Power-Down Current
—CMOS Inputs
CE > V – 0.3V,
1 CC
or CE < 0.3V,
2
V
> V – 0.3V,
IN
CC
or V < 0.3V, f = 0
IN
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
9
8
pF
pF
IN
A
V
= 5.0V
CC
OUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 480
ALL INPUT PULSES
90%
Ω
R1 480
Ω
5V
5V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
10%
R2
255
R2
255
30 pF
5 pF
Ω
Ω
3ns
3 ns
≤
≤
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
109–4
(a)
109–5
THÉ
VENIN EQUIVALENT
Equivalent to:
167
Ω
1.73V
OUTPUT
3
CY7C109
CY7C1009
Switching Characteristics[3, 5] Over the Operating Range
7C109-10
7C1009-10
7C109-12
7C1009-12
7C109-15
7C1009-15
Parameter
Description
Min.
Max.
Min.
Max.
Min. Max.
Unit
READ CYCLE
t
t
t
t
Read Cycle Time
10
3
12
3
15
3
ns
ns
ns
ns
RC
Address to Data Valid
10
12
15
AA
Data Hold from Address Change
OHA
ACE
CE LOW to Data Valid, CE HIGH to Data
10
5
12
6
15
7
1
2
Valid
t
t
t
t
t
t
OE LOW to Data Valid
OE LOW to Low Z
ns
ns
ns
ns
ns
ns
DOE
LZOE
HZOE
LZCE
HZCE
PU
0
3
0
0
3
0
0
3
0
[6, 7]
OE HIGH to High Z
5
5
6
6
7
7
[7]
CE LOW to Low Z, CE HIGH to Low Z
1
2
[6, 7]
CE HIGH to High Z, CE LOW to High Z
1
2
CE LOW to Power-Up, CE HIGH to
1
2
Power-Up
t
CE HIGH to Power-Down, CE LOW to
10
12
15
ns
PD
1
2
Power-Down
[8, 9]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
CE LOW to Write End, CE HIGH to Write End
10
8
12
10
10
0
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
SCE
AW
1
2
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
0
HA
0
0
0
SA
8
10
7
12
8
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
6
0
0
0
HD
[7]
WE HIGH to Low Z
3
3
3
LZWE
[6, 7]
WE LOW to High Z
5
6
7
HZWE
Shaded areas contain preliminary information.
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OL/IOH and 30-pF load capacitance.
I
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
4
CY7C109
CY7C1009
Switching Characteristics[3, 5] Over the Operating Range (continued)
7C109-20
7C109-25
7C1009-25
7C109-35
7C1009-35
7C1009-20
Parameter
Description
Min. Max.
Min.
Max.
Min. Min.
Unit
READ CYCLE
t
t
t
t
Read Cycle Time
20
3
25
5
35
5
ns
ns
ns
ns
RC
Address to Data Valid
20
25
35
AA
Data Hold from Address Change
OHA
ACE
CE LOW to Data Valid, CE HIGH to Data
20
8
25
10
35
15
1
2
Valid
t
t
t
t
t
t
OE LOW to Data Valid
OE LOW to Low Z
ns
ns
ns
ns
ns
ns
DOE
LZOE
HZOE
LZCE
HZCE
PU
0
3
0
0
5
0
0
5
0
[6, 7]
OE HIGH to High Z
8
8
10
10
15
15
[7]
CE LOW to Low Z, CE HIGH to Low Z
1
2
[6, 7]
CE HIGH to High Z, CE LOW to High Z
1
2
CE LOW to Power-Up, CE HIGH to
1
2
Power-Up
t
CE HIGH to Power-Down, CE LOW to
Power-Down
20
25
35
ns
PD
1
2
[8]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
CE LOW to Write End, CE HIGH to Write End
20
15
15
0
25
20
20
0
35
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
SCE
AW
1
2
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
0
SA
12
10
0
15
15
0
20
20
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[7]
WE HIGH to Low Z
3
5
5
LZWE
HZWE
[6, 7]
WE LOW to High Z
8
10
15
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter Description Conditions
for Data Retention No input may exceed V + 0.5V
Min.
Max
Unit
V
V
V
2.0
DR
CCDR
CDR
R
CC
CC
V
= V = 2.0V,
CC
1
DR
I
t
t
Data Retention Current
50
µA
ns
CE > V – 0.3V or CE < 0.3V,
V
CC
2
Chip Deselect to Data Retention Time
Operation Recovery Time
0
> V – 0.3V or V < 0.3V
IN
CC IN
t
ns
RC
5
CY7C109
CY7C1009
Data Retention Waveform
DATA RETENTION MODE
> 2V
V
CC
4.5V
4.5V
V
DR
t
t
R
CDR
CE
109-6
Switching Waveforms
[10, 11]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
109–7
[11, 12]
Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
109–8
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
6
CY7C109
CY7C1009
Switching Waveforms (continued)
[13, 14]
Write Cycle No. 1 (CE or CE Controlled)
1
2
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
109–9
[13, 14]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 15
t
HZOE
109–10
Notes:
13. Data I/O is high impedance if OE = VIH
.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
7
CY7C109
CY7C1009
Switching Waveforms (continued)
[14]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 15
DATA I/O
DATA VALID
t
t
LZWE
HZWE
109–11
Note:
15. During this period the I/Os are in the output state and input signals should not be applied.
Truth Table
CE
H
X
CE
X
OE
X
WE
X
I/O – I/O
7
Mode
Power
1
2
0
High Z
Power-Down
Power-Down
Read
Standby (I
Standby (I )
SB
)
SB
L
X
X
High Z
L
H
L
H
Data Out
Data In
High Z
Active (I
Active (I
Active (I
)
CC
L
H
X
L
Write
)
CC
L
H
H
H
Selected, Outputs Disabled
)
CC
8
CY7C109
CY7C1009
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead TSOP Type I
10
CY7C109-10VC
CY7C1009-10VC
CY7C1009L-10VC
CY7C109-12VC
CY7C1009-12VC
CY7C1009L-12VC
CY7C109-12ZC
CY7C109-15VC
CY7C1009-15VC
CY7C1009L-15VC
CY7C109-15ZC
CY7C109-15VI
CY7C109L-15VI
CY7C1009-15VI
CY7C109-15ZI
CY7C109-20VC
CY7C1009-20VC
CY7C109-20VI
CY7C109-20ZC
CY7C109-20ZI
CY7C109-25VC
CY7C1009-25VC
CY7C109-25VI
CY7C109-25ZC
CY7C109-25ZI
CY7C109-35VC
CY7C1009-35VC
CY7C109-35VI
V33
V32
V32
V33
V32
V32
Z32
V33
V32
V32
Z32
V33
V33
V32
Z32
V33
V32
V33
Z32
Z32
V33
V32
V33
Z32
Z32
V33
V32
V33
Commercial
12
15
Commercial
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead TSOP Type I
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead TSOP Type I
Industrial
20
25
35
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead TSOP Type I
Commercial
Industrial
Commercial
Industrial
32-Lead TSOP Type I
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead TSOP Type I
Commercial
Industrial
Commercial
Industrial
32-Lead TSOP Type I
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
Commercial
Industrial
Shaded areas contain preliminary information.
Document #: 38–00140–K
9
CY7C109
CY7C1009
Package Diagrams
32-Lead (300-Mil) Molded SOJ V32
51-85041-A
32-Lead (400-Mil) Molded SOJ V33
51-85033-A
10
CY7C109
CY7C1009
Package Diagrams (continued)
32-Lead Thin Small Outline Package Z32
51-85056-B
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
CY7C109-25DMB
Standard SRAM, 128KX8, 25ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
CYPRESS
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