CY7C1062AV25-10BGC [CYPRESS]
512K x 32 Static RAM; 512K ×32静态RAM
| 型号： | CY7C1062AV25-10BGC |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 32 Static RAM |
| 文件： | 总9页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1062AV25
512K x 32 Static RAM
Features
Functional Description
• High speed
The CY7C1062AV25 is a high-performance CMOS Static
RAM organized as 524,288 words by 32 bits.
— tAA = 10 ns
Writing to the device is accomplished by enabling the chip
(CE1, CE2 and CE3 LOW) and forcing the Write Enable (WE)
input LOW. If Byte Enable A (BA) is LOW, then data from I/O
pins (I/O0 through I/O7), is written into the location specified on
the address pins (A0 through A18). If Byte Enable B (BB) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23
and I/O24 to I/O31, respectively.
• Low active power
— 745 mW (max.)
• Operating voltages of 2.5 ± 0.2V
• 1.5V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and CE3
features
Reading from the device is accomplished by enabling the chip
(CE1, CE2, and CE3 LOW) while forcing the Output Enable
(OE) LOW and Write Enable (WE) HIGH. If the first Byte
Enable (BA) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
Enable B (BB) is LOW, then data from memory will appear on
I/O8 to I/O15. Similarly, Bc and BD correspond to the third and
fourth bytes. See the truth table at the back of this data sheet
for a complete description of read and write modes.
• Available in non Pb-free 119-ball pitch ball grid array
package
The input/output pins (I/O0 through I/O31) are placed in a
high-impedance state when the device is deselected (CE1,
CE2or CE3 HIGH), the outputs are disabled (OE HIGH), the
byte selects are disabled (BA-D HIGH), or during a write
operation (CE1, CE2, and CE3 LOW, and WE LOW).
The CY7C1062AV25 is available in a 119-ball pitch ball grid
array (PBGA) package.
WE
CE1
CE2
Logic Block Diagram
CE3
INPUT BUFFERS
OE
BA
BB
BC
A
A
A
A
A
0
1
2
3
4
BD
512K x 32
ARRAY
I/O0–I/O31
A
A
5
6
A
A
A
7
8
9
COLUMN
DECODER
Cypress Semiconductor Corporation
Document #: 38-05333 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 10, 2006
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CY7C1062AV25
Selection Guide
–10
10
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Com’l/Ind’l
Com’l/Ind’l
275
50
mA
mA
Pin Configuration
119-ball PBGA
(Top View)
1
2
3
4
5
6
7
I/O16
A
A
A
A
A
I/O0
A
I/O17
I/O18
I/O19
A
A
CE1
A
A
I/O1
I/O2
I/O3
B
C
D
Bc
CE2
VSS
NC
CE3
VSS
Ba
VDD
VSS
VDD
I/O20
I/O21
I/O22
I/O23
NC
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
I/O4
I/O5
E
F
I/O6
G
H
J
I/O7
VSS
VDD
DNU
I/O8
I/O24
I/O25
I/O26
I/O27
I/O28
VSS
VDD
VSS
VDD
VSS
K
L
I/O9
I/O10
I/O11
I/O12
M
N
P
I/O29
I/O30
I/O31
A
A
A
Bd
A
NC
Bb
A
A
A
A
I/O13
I/O14
I/O15
R
T
WE
OE
A
A
U
Document #: 38-05333 Rev. *A
Page 2 of 9
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CY7C1062AV25
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current......................................................>200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VCC Relative to GND[1] .... –0.5V to +3.6V
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
2.5V ± 0.2V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
–10
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[1]
Input Leakage Current
Output Leakage Current
Test Conditions
VCC = Min., IOH = –1.0 mA
Min.
Max.
Unit
V
2.0
VOL
VIH
VIL
IIX
VCC = Min., IOL = 1.0 mA
0.4
V
2.0
–0.3
–1
VCC + 0.3
0.8
V
V
GND < VI < VCC
+1
µA
µA
mA
IOZ
ICC
GND < VOUT < VCC, Output Disabled
–1
+1
VCC Operating
Supply Current
VCC = Max., f = fMAX = 1/tRC
Com’l/Ind’l
275
ISB1
ISB2
Automatic CE Power-down Max. VCC, CE > VIH, VIN > VIH or Com’l/Ind’l
Current—TTL Inputs VIN < VIL, f = fMAX
100
50
mA
mA
Automatic CE Power-down Max. VCC, CE > VCC – 0.2V,
Com’l/Ind’l
Current —CMOS Inputs
VIN > VCC – 0.2V, or VIN < 0.2V, f = 0
Capacitance[2]
Parameter
CIN
Description
Test Conditions
Max.
8
Unit
Input Capacitance
I/O Capacitance
TA = 25°C, f = 1 MHz, VCC = 2.5V
pF
pF
COUT
10
AC Test Loads and Waveforms[3]
50Ω
ALL INPUT PULSES
90%
= VDD/2
OUTPUT
VTH
2.3V
90%
Z = 50Ω
30 pF
0
10%
10%
(a)
Including all Components
of Test Equipment
GND
R1 317Ω
Fall time:
> 1 V/ns
Rise time > 1 V/ns
2.5V
OUTPUT
Including
Jig and
Scope
VENIN EQUIVALENT
THÉ
R2
5 pF
167Ω
351Ω
1.73V
OUTPUT
(b)
(c)
Notes:
1. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
2. Tested initially and after any design or process changes that may affect these parameters.
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (2.3V). As soon as 1ms (T
) after reaching the
power
DD
minimum operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 1.5V) voltage.
CCDR
DD
DD
Document #: 38-05333 Rev. *A
Page 3 of 9
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CY7C1062AV25
AC Switching Characteristics Over the Operating Range[4]
–10
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Unit
VCC (typical) to the first access[5]
Read Cycle Time
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
tAA
Address to Data Valid
10
tOHA
tACE
Data Hold from Address Change
CE1, CE2, or CE3 LOW to Data Valid
OE LOW to Data Valid
3
10
5
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Low-Z[6]
OE HIGH to High-Z[6]
1
3
0
5
5
CE1, CE2, or CE3 LOW to Low-Z[6]
CE1, CE2, or CE3 HIGH to High-Z[6]
CE1, CE2, or CE3 LOW to Power-up[7]
CE1, CE2, or CE3 HIGH to Power-down[7]
Byte Enable to Data Valid
tPD
10
5
tDBE
tLZBE
tHZBE
Write Cycle[8, 9]
tWC
Byte Enable to Low-Z[6]
Byte Disable to High-Z[6]
1
5
Write Cycle Time
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1, CE2, or CE3 LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
7
tHA
0
tSA
0
tPWE
tSD
7
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[6]
5.5
0
tHD
tLZWE
tHZWE
tBW
3
WE LOW to High-Z[6]
5
Byte Enable to End of Write
7
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.3V, and output loading of the specified
I
/I and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise.
OL OH
5. This part has a voltage regulator that steps down the voltage from 2.3V to 2V internally. t
started.
time has to be provided initially before a read/write operation is
power
6. t
, t
, t
, t
, and t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
LZBE
HZOE HZCE HZWE HZBE
LZOE LZCE LZWE
± 200 mV from steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE 2 HIGH, CE3 LOW, and WE LOW. The chip enables must be active and WE
must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced
to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05333 Rev. *A
Page 4 of 9
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CY7C1062AV25
Data Retention Waveform
DATA RETENTION MODE
> 1.5V
2.3V
2.3V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[11,12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[11,13]
ADDRESS
t
RC
CE1, CE3
CE2
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BA, BB, BC, BD
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
ISB
Notes:
10. Full device operation requires linear V ramp from V to V
> 100 µs or stable at V > 100 µs
CC(min.)
CC
DR
CC(min.)
11. Device is continuously selected. OE, CE, B , B , B , B = V .
A
B
C
D
IL
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05333 Rev. *A
Page 5 of 9
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CY7C1062AV25
Switching Waveforms
Write Cycle No. 1 (CE Controlled)[14,15,16]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BA, BB, BC, BD
t
t
SD
HD
DATAI/O
Write Cycle No. 2 (BLE or BHE Controlled)[14,15,16]
t
WC
ADDRESS
t
SA
t
BW
BA, BB, BC, BD
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
Notes:
14. CE indicates a combination of all three chip enables. When ACTIVE LOW, CE indicates the CE , CE and CE are LOW.
1
2
3
15. Data I/O is high-impedance if OE or B , B , B , B = V .
A
B
C
D
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05333 Rev. *A
Page 6 of 9
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CY7C1062AV25
Switching Waveforms
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BA, BB, BC, BD
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
I/O0–
I/O7
I/O8–
I/O15
I/O16–
I/O23
I/O24
–
CE1 CE2 CE3 OE WE BA BB
Bc
X
BD
X
I/O31
Mode
Power
H
L
L
L
H
H
L
H
L
L
L
X
X
L
L
X
X
H
H
X
X
L
L
X
X
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Power Down (ISB
)
)
X
X
Power Down (ISB
L
L
Data Out Data Out Data Out Data Out Read All Bits (ICC
)
)
L
H
H
H
Data Out High-Z
High-Z
High-Z
Read Byte A (ICC
Bits Only
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
L
H
H
L
High-Z
High-Z
High-Z
Data Out High-Z
High-Z
Read Byte B (ICC
Bits Only
)
)
)
High-Z
High-Z
Data Out High-Z
Read Byte C (ICC
Bits Only
H
High-Z
Data Out Read Byte D (ICC
Bits Only
L
L
L
L
L
L
X
X
L
L
L
L
L
L
L
Data In
Data In
Data In
High-Z
Data In
High-Z
Data In
High-Z
Write All Bits (ICC
)
)
H
H
H
Write Byte A (ICC
Bits Only
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
H
L
L
H
H
H
X
L
H
H
X
H
L
H
H
L
High-Z
High-Z
High-Z
High-Z
Data In
High-Z
High-Z
High-Z
High-Z
Data In
High-Z
High-Z
High-Z
High-Z
Data In
High-Z
Write Byte B (ICC
Bits Only
)
)
)
)
Write Byte C (ICC
Bits Only
L
H
X
Write Byte D (ICC
Bits Only
H
X
Selected,
Outputs
(ICC
Disabled
Document #: 38-05333 Rev. *A
Page 7 of 9
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CY7C1062AV25
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
10
CY7C1062AV25-10BGC 51-85115 119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1062AV25-10BGI
Commercial
Industrial
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05333 Rev. *A
Page 8 of 9
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CY7C1062AV25
Document History Page
Document Title: CY7C1062AV25 512K x 32 Static RAM
Document Number: 38-05333
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
119626
Description of Change
01/29/03
See ECN
DFP
NXR
New Data Sheet
*A
493565
Converted from Preliminary to Final
Removed -8 and -10 speed bins
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated the ordering information table
Document #: 38-05333 Rev. *A
Page 9 of 9
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