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CY7C1062AV25-8BGI [CYPRESS]

Standard SRAM, 512KX32, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119;
CY7C1062AV25-8BGI
型号： CY7C1062AV25-8BGI
厂家： CYPRESS    CYPRESS
描述：

Standard SRAM, 512KX32, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

静态存储器 内存集成电路
文件： 总9页 (文件大小：188K)
中文：  中文翻译
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PRELIMINARY  
CY7C1062AV25  
512K x 32 Static RAM  
the address pins (A0 through A18). If Byte Enable B (BB) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written  
into the location specified on the address pins (A0 through  
A18). Likewise, BC and BD correspond with the I/O pins I/O16  
to I/O23 and I/O24 to I/O31, respectively.  
Features  
• High speed  
— tAA = 8, 10, 12 ns  
• Low active power  
Reading from the device is accomplished by enabling the chip  
(CE1, CE2, and CE3 LOW) while forcing the Output Enable  
(OE) LOW and Write Enable (WE) HIGH. If the first Byte  
Enable (BA) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
Enable B (BB) is LOW, then data from memory will appear on  
I/O8 to I/O15. Similarly, Bc and BD correspond to the third and  
fourth bytes. See the truth table at the back of this data sheet  
for a complete description of read and write modes.  
— 1080 mW (max.)  
• Operating voltages of 2.5 ± 0.2V  
• 1.5V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2, and CE3  
features  
Functional Description  
The input/output pins (I/O0 through I/O31) are placed in a  
high-impedance state when the device is deselected (CE1,  
CE2or CE3 HIGH), the outputs are disabled (OE HIGH), the  
byte selects are disabled (BA-D HIGH), or during a write  
operation (CE1, CE2, and CE3 LOW, and WE LOW).  
The CY7C1062AV25 is a high-performance CMOS Static  
RAM organized as 524,288 words by 32 bits.  
Writing to the device is accomplished by enabling the chip  
(CE1, CE2 and CE3 LOW) and forcing the Write Enable (WE)  
input LOW. If Byte Enable A (BA) is LOW, then data from I/O  
pins (I/O0 through I/O7), is written into the location specified on  
The CY7C1062AV25 is available in a 119-ball pitch ball grid  
array (PBGA) package.  
WE  
CE1  
CE2  
Logic Block Diagram  
CE3  
INPUT BUFFERS  
OE  
BA  
BB  
BC  
A
A
A
A
A
0
1
2
3
4
BD  
512K x 32  
ARRAY  
I/O0–I/O31  
A
A
5
6
4096 x 4096  
A
A
A
7
8
9
COLUMN  
DECODER  
Selection Guide  
-8  
8
-10  
10  
-12  
12  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Com’l  
300  
300  
50  
275  
275  
50  
260  
260  
50  
mA  
Ind’l  
Maximum CMOS Standby Current  
Com’l/Ind’l  
mA  
Cypress Semiconductor Corporation  
Document #: 38-05333 Rev. **  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 27, 2003  
PRELIMINARY  
CY7C1062AV25  
Pin Configuration  
119-ball PBGA  
(Top View)  
1
2
3
4
5
6
7
I/O  
A
A
A
A
A
I/O  
A
16  
0
I/O  
I/O  
I/O  
A
A
CE  
V
CE  
A
CE  
V
A
I/O  
I/O  
I/O  
B
C
D
E
F
17  
18  
19  
1
1
2
3
B
NC  
B
a
c
2
3
V
V
V
DD  
DD  
SS  
DD  
SS  
SS  
DD  
I/O  
I/O  
I/O  
I/O  
V
V
V
V
V
I/O  
I/O  
I/O  
I/O  
20  
21  
22  
23  
SS  
SS  
SS  
4
5
6
7
V
V
V
V
V
V
V
DD  
SS  
SS  
SS  
DD  
V
V
V
V
V
G
H
J
SS  
DD  
SS  
DD  
SS  
V
V
V
DD  
SS  
SS  
DD  
SS  
NC  
V
V
V
V
V
DNU  
SS  
DD  
DD  
SS  
DD  
SS  
DD  
I/O  
I/O  
I/O  
I/O  
I/O  
V
V
V
V
V
V
V
I/O  
K
L
24  
25  
26  
SS  
SS  
SS  
8
V
V
V
V
I/O  
SS  
DD  
SS  
DD  
SS  
9
V
V
V
V
I/O  
M
N
P
DD  
SS  
DD  
SS  
SS  
DD  
DD  
10  
V
V
V
V
V
V
I/O  
27  
28  
29  
30  
31  
SS  
SS  
SS  
DD  
11  
V
V
V
V
I/O  
DD  
A
SS  
SS  
SS  
12  
I/O  
I/O  
I/O  
B
NC  
B
A
A
A
I/O  
R
T
d
b
13  
A
A
A
I/O  
14  
WE  
OE  
A
A
A
I/O  
U
15  
Document #: 38-05333 Rev. **  
Page 2 of 9  
PRELIMINARY  
CY7C1062AV25  
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Current into Outputs (LOW)......................................... 20 mA  
Operating Range  
Storage Temperature .................................–65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +3.6V  
Ambient  
Range  
Commercial  
Industrial  
Temperature  
0°C to +70°C  
–40°C to +85°C  
VCC  
2.5V ± 0.2V  
DC Voltage Applied to Outputs  
in High-Z State[1] ....................................–0.5V to VCC + 0.5V  
DC Electrical Characteristics Over the Operating Range  
-8  
-10  
-12  
Parameter  
Description  
Test Conditions  
VCC = Min.,  
IOH = –1.0mA  
Min. Max. Min. Max. Min. Max. Unit  
VOH  
Output HIGH Voltage  
2.0  
2.0  
2.0  
V
V
V
VOL  
VIH  
Output LOW Voltage  
Input HIGH Voltage  
VCC = Min.,  
IOL = 1.0 mA  
0.4  
0.4  
0.4  
2.0  
VCC  
2.0  
VCC  
2.0  
VCC  
+ 0.3  
+ 0.3  
+ 0.3  
VIL  
IIX  
Input LOW Voltage[1]  
Input Load Current  
–0.3 0.8  
–0.3  
–1  
0.8  
+1  
+1  
–0.3  
–1  
0.8  
+1  
+1  
V
GND < VI < VCC  
–1  
–1  
+1  
+1  
µA  
µA  
IOZ  
Output Leakage Current GND < VOUT < VCC, Output  
Disabled  
–1  
–1  
ICC  
VCC Operating  
Supply Current  
VCC = Max., f = fMAX Com’l  
300  
300  
100  
275  
275  
100  
260 mA  
260 mA  
100 mA  
= 1/tRC  
Ind’l  
ISB1  
Automatic CE  
Power-down Current  
Max. VCC, CE > VIH  
VIN > VIH or  
—TTL Inputs  
VIN < VIL, f = fMAX  
ISB2  
Automatic CE  
Power-down Current  
—CMOS Inputs  
Max. VCC  
,
Com’l/Ind’l  
50  
50  
50  
mA  
CE > VCC – 0.2V,  
VIN > VCC – 0.2V,  
or VIN < 0.2V, f = 0  
Capacitance[2]  
Parameter  
CIN  
Description  
Test Conditions  
TA = 25°C, f = 1 MHz, VCC = 2.5V  
Max.  
Unit  
pF  
Input Capacitance  
I/O Capacitance  
8
COUT  
10  
pF  
Notes:  
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.  
2. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05333 Rev. **  
Page 3 of 9  
PRELIMINARY  
CY7C1062AV25  
AC Test Loads and Waveforms[3]  
50Ω  
ALL INPUT PULSES  
90%  
10%  
= V /2  
OUTPUT  
VTH  
DD  
2.5V  
90%  
10%  
Z = 50Ω  
30 pF  
0
(a)  
Including all Components  
of Test Equipment  
GND  
R1 317Ω  
Fall time:  
> 1 V/ns  
Rise time > 1 V/ns  
2.5V  
OUTPUT  
THÉ  
VENIN EQUIVALENT  
Including  
Jig and  
Scope  
167Ω  
R2  
351Ω  
1.73V  
OUTPUT  
5 pF  
(b)  
(c)  
AC Switching Characteristics Over the Operating Range[4]  
-8  
-10  
-12  
Parameter  
Read Cycle  
tpower  
tRC  
Description  
Min. Max. Min. Max. Min. Max.  
Unit  
VCC (typical) to the first access[5]  
Read Cycle Time  
1
8
1
1
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10  
12  
tAA  
Address to Data Valid  
8
10  
12  
tOHA  
Data Hold from Address Change  
CE1, CE2, or CE3 LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low-Z[6]  
OE HIGH to High-Z[6]  
CE1, CE2, or CE3 LOW to Low-Z[6]  
CE1, CE2, or CE3 HIGH to High-Z[6]  
CE1, CE2, or CE3 LOW to Power-up[7]  
CE1, CE2, or CE3 HIGH to Power-down[7]  
Byte Enable to Data Valid  
3
3
3
tACE  
8
5
10  
5
12  
6
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
1
3
0
1
3
0
1
3
0
5
5
5
5
6
6
tPD  
8
5
10  
5
12  
6
tDBE  
tLZBE  
tHZBE  
Write Cycle[8, 9]  
Byte Enable to Low-Z[6]  
Byte Disable to High-Z[6]  
1
1
1
5
5
6
tWC  
tSCE  
tAW  
tHA  
Write Cycle Time  
8
6
6
0
0
6
5
0
3
10  
7
12  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE1, CE2, or CE3 LOW to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
7
8
0
0
tSA  
0
0
tPWE  
tSD  
7
8
Data Set-up to Write End  
Data Hold from Write End  
WE HIGH to Low-Z[6]  
5.5  
0
6
tHD  
0
tLZWE  
3
3
Notes:  
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (2.3V). As soon as 1ms (Tpower) after reaching the  
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5V) voltage.  
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.3V, and output loading of the specified  
IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise.  
5. This part has a voltage regulator that steps down the voltage from 2.3V to 2V internally. tpower time has to be provided initially before a read/write operation is  
started.  
6. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured  
± 200 mV from steady-state voltage.  
7. These parameters are guaranteed by design and are not tested.  
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE 2 HIGH, CE3 LOW, and WE LOW. The chip enables must be active and WE  
must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced  
to the leading edge of the signal that terminates the write.  
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD  
.
Document #: 38-05333 Rev. **  
Page 4 of 9  
PRELIMINARY  
CY7C1062AV25  
AC Switching Characteristics Over the Operating Range[4] (continued)  
-8  
-10  
-12  
Parameter  
tHZWE  
tBW  
Description  
WE LOW to High-Z[6]  
Byte Enable to End of Write  
Min. Max. Min. Max. Min. Max.  
Unit  
ns  
5
5
6
6
7
8
ns  
Data Retention Waveform  
DATA RETENTION MODE  
> 1.5V  
2.3V  
2.3V  
V
V
CC  
DR  
t
t
R
CDR  
CE  
Switching Waveforms  
Read Cycle No. 1[10, 11]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 (OE Controlled) [11, 12]  
ADDRESS  
t
RC  
CE , CE  
1
3
CE  
2
t
ACE  
OE  
t
HZOE  
t
DOE  
t
B , B , B , B  
D
LZOE  
A
B
C
t
HZCE  
t
DBE  
t
LZBE  
t
HZBE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
I
t
CC  
PU  
V
CC  
50%  
50%  
SUPPLY  
I
CURRENT  
SB  
Notes:  
10. Device is continuously selected. OE, CE, BA, BB, BC, BD= VIL.  
11. WE is HIGH for read cycle.  
12. Address valid prior to or coincident with CE transition LOW.  
Document #: 38-05333 Rev. **  
Page 5 of 9  
PRELIMINARY  
CY7C1062AV25  
Switching Waveforms (continued)  
Write Cycle No. 1 (CE Controlled)[13, 14, 15]  
t
WC  
ADDRESS  
t
SA  
t
SCE  
CE  
t
AW  
t
HA  
t
PWE  
WE  
t
BW  
B , B , B , B  
D
A
B
C
t
t
SD  
HD  
DATAI/O  
Write Cycle No. 2 (BLE or BHE Controlled)[13, 14, 15]  
t
WC  
ADDRESS  
t
t
BW  
SA  
B , B , B , B  
A
B
C
D
t
AW  
t
HA  
t
PWE  
WE  
CE  
t
SCE  
t
t
HD  
SD  
DATAI/O  
Notes:  
13. CE indicates a combination of all three chip enables. When ACTIVE LOW, CE indicates the CE1, CE2 and CE3 are LOW.  
14. Data I/O is high-impedance if OE or BA, BB, BC, BD = VIH  
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
Document #: 38-05333 Rev. **  
Page 6 of 9  
PRELIMINARY  
CY7C1062AV25  
Switching Waveforms (continued)  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
AW  
t
HA  
t
SA  
t
PWE  
WE  
t
BW  
B , B , B , B  
D
A
B
C
t
HZWE  
t
t
SD  
HD  
DATA I/O  
t
LZWE  
Truth Table  
I/O0–  
I/O8–  
I/O16–  
I/O23  
I/O24  
–
CE1 CE2 CE3 OE WE BA BB  
Bc  
X
BD  
X
I/O7  
I/O15  
I/O31  
Mode  
Power  
H
L
L
L
L
H
L
H
L
L
L
X
X
L
L
X
X
H
H
X
X
L
L
X
X
L
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Power Down  
Power Down  
(ISB  
)
)
X
X
(ISB  
L
L
Data Out Data Out Data Out Data Out Read All Bits  
(ICC  
(ICC  
)
)
L
H
H
H
Data Out High-Z  
High-Z  
High-Z  
Read Byte A  
Bits Only  
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
L
H
H
L
High-Z  
High-Z  
High-Z  
Data Out High-Z  
High-Z  
Read Byte B  
Bits Only  
(ICC  
(ICC  
(ICC  
)
)
)
High-Z  
High-Z  
Data Out High-Z  
Read Byte C  
Bits Only  
H
High-Z  
Data Out Read Byte D  
Bits Only  
L
L
L
L
L
L
X
X
L
L
L
L
L
L
L
Data In  
Data In  
Data In  
High-Z  
Data In  
High-Z  
Data In  
High-Z  
Write All Bits  
(ICC  
(ICC  
)
)
H
H
H
Write Byte A  
Bits Only  
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
H
L
L
H
H
H
X
L
H
H
X
H
L
H
H
L
High-Z  
High-Z  
High-Z  
High-Z  
Data In  
High-Z  
High-Z  
High-Z  
High-Z  
Data In  
High-Z  
High-Z  
High-Z  
High-Z  
Data In  
High-Z  
Write Byte B  
Bits Only  
(ICC  
(ICC  
(ICC  
(ICC  
)
)
)
)
Write Byte C  
Bits Only  
L
H
X
Write Byte D  
Bits Only  
H
X
Selected,  
Outputs  
Disabled  
Document #: 38-05333 Rev. **  
Page 7 of 9  
PRELIMINARY  
CY7C1062AV25  
Ordering Information  
Speed  
(ns)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
8
CY7C1062AV25-8BGC  
CY7C1062AV25-8BGI  
CY7C1062AV25-10BGC  
CY7C1062AV25-10BGI  
CY7C1062AV25-12BGC  
CY7C1062AV25-12BGI  
BG119  
14 x 22 mm 119-ball PBGA  
Commercial  
Industrial  
10  
12  
Commercial  
Industrial  
Commercial  
Industrial  
Package Diagram  
119-Lead PBGA (14 x 22 x 2.4 mm) BG119  
51-85115-*B  
All product and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05333 Rev. **  
Page 8 of 9  
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
PRELIMINARY  
CY7C1062AV25  
Document History Page  
Document Title: CY7C1062AV25 512K x 32 Static RAM  
Document Number: 38-05333  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
119626  
01/29/03  
DFP  
New Data Sheet  
Document #: 38-05333 Rev. **  
Page 9 of 9  

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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