CY7C10612DV33-10ZSXI [CYPRESS]
16-Mbit (1M x 16) Static RAM; 16兆位（ 1M ×16 ）静态RAM
| 型号： | CY7C10612DV33-10ZSXI |
| 厂家： | 
CYPRESS |
| 描述： | 16-Mbit (1M x 16) Static RAM |
| 文件： | 总10页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C10612DV33
16-Mbit (1M x 16) Static RAM
Features
Functional Description
■ High speed
❐ tAA = 10 ns
The CY7C10612DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A19). If Byte High
■ Low active power
❐ ICC = 175 mA at 10 ns
■ Low CMOS standby power
❐ ISB2 = 25 mA
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15
)
is written into the location specified on the address pins (A0
through A19).
■ Operating voltages of 3.3 ± 0.3V
■ 2.0V data retention
To read from the device, take Chip Enables (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the Truth Table on page 9 for a
complete description of Read and Write modes.
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 54-Pin TSOP II package
The input or output pins (IO0 through IO15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C10612DV33 is available in a 54-Pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
4
3
IO0 – IO7
1M x 16
ARRAY
A
A
5
IO8 – IO15
A
6
A
7
A
8
A
9
COLUMN
DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-49315 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 15, 2009
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CY7C10612DV33
Selection Guide
Description
–10
10
Unit
ns
Maximum Access Time
Maximum Operating Current
175
25
mA
mA
Maximum CMOS Standby Current
Pin Configuration
Figure 1. 54-Pin TSOP II (Top View) [1]
IO
V
IO
V
12
1
2
3
4
5
6
54
53
52
51
50
49
48
47
46
11
CC
SS
IO
IO
13
14
10
9
IO
V
IO
V
SS
CC
IO
15
IO
8
A
A
A
A
A
A
7
4
3
2
1
0
5
A
A
A
A
8
9
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
45
44
NC
BHE
CE
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
OE
V
V
CC
SS
WE
NC
NC
BLE
A
A
10
19
A
18
A
11
A
17
A
12
A
16
A
13
A
15
IO
0
A
14
IO
7
V
CC
V
SS
IO
6
IO
5
IO
1
IO
2
V
SS
V
CC
IO
3
IO
4
Note
1. NC pins are not connected on the die.
Document Number: 001-49315 Rev. *A
Page 2 of 10
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CY7C10612DV33
DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage.................................................>2001V
(MIL-STD-883, Method 3015)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Latch Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on VCC Relative to GND [2]....–0.5V to +4.6V
Operating Range
Ambient
DC Voltage Applied to Outputs
Range
VCC
Temperature
in High Z State [2]................................... –0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
3.3V ± 0.3V
DC Electrical Characteristics
Over the Operating Range
–10
Parameter
Description
Test Conditions
Unit
Min
Max
VOH
VOL
VIH
VIL
IIX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VCC = Min, IOH = –4.0 mA
VCC = Min, IOL = 8.0 mA
2.4
V
V
0.4
2.0
–0.3
–1
VCC + 0.3
0.8
V
Input LOW Voltage [2]
Input Leakage Current
Output Leakage Current
V
GND < VI < VCC
GND < VOUT < VCC, Output disabled
VCC = Max, f = fMAX = 1/tRC, OUT = 0 mA CMOS levels
+1
μA
μA
mA
IOZ
ICC
–1
+1
VCC Operating Supply
Current
I
175
ISB1
ISB2
Automatic CE Power Down Max VCC, CE > VIH,
Current — TTL Inputs IN > VIH or VIN < VIL, f = fMAX
30
25
mA
mA
V
Automatic CE Power Down Max VCC, CE > VCC – 0.3V,
Current —CMOS Inputs IN > VCC – 0.3V, or VIN < 0.3V, f = 0
V
Note
2.
V (min) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IL IH CC
Document Number: 001-49315 Rev. *A
Page 3 of 10
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CY7C10612DV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
IO Capacitance
Test Conditions
TSOP II
Unit
pF
TA = 25°C, f = 1 MHz, VCC = 3.3V
6
8
COUT
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
TSOP II
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
24.18
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
5.40
°C/W
The AC Test Loads and Waveforms diagram follows. [3]
Figure 2. AC Test Loads and Waveforms
HIGH-Z CHARACTERISTICS:
R1 317Ω
50
Ω
3.3V
= 1.5V
OUTPUT
VTH
OUTPUT
5 pF*
Z = 50
Ω
R2
351Ω
30 pF*
0
INCLUDING
JIG AND
SCOPE
(a)
(b)
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
GND
FALL TIME:
> 1 V/ns
RISE TIME:
> 1 V/ns
(c)
Note
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). 100 μs (t
) after reaching the minimum operating
power
DD
V
, normal SRAM operation begins including reduction in V to the data retention (V
, 2.0V) voltage.
CCDR
DD
DD
Document Number: 001-49315 Rev. *A
Page 4 of 10
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CY7C10612DV33
AC Switching Characteristics
Over the Operating Range [4]
–10
Parameter
Description
Unit
Min
Max
Read Cycle
tpower
tRC
VCC(Typical) to the First Access [5]
Read Cycle Time
100
10
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z [6]
CE LOW to Low Z [6]
CE HIGH to High Z [6]
CE LOW to Power Up [7]
CE HIGH to Power Down [7]
Byte Enable to Data Valid
Byte Enable to Low Z
10
tOHA
tACE
3
10
5
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
1
3
0
5
5
tPD
10
5
tDBE
tLZBE
tHZBE
Write Cycle [8, 9]
tWC
1
Byte Disable to High Z
5
Write Cycle Time
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tAW
7
tHA
0
tSA
0
tPWE
tSD
7
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z [6]
WE LOW to High Z [6]
Byte Enable to End of Write
5.5
0
tHD
tLZWE
tHZWE
tBW
3
5
7
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output
loading shown in part a) of AC Test Loads and Waveforms, unless specified otherwise.
5.
6.
t
t
gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
CC
POWER
, t
, t
, t
, t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±200 mV
HZOE HZCE HZWE HZBE LZOE LZCE LZWE
LZBE
from steady state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal write time of the memory is defined by the overlap of WE, CE = V . Chip enable must be active and WE and byte enables must be LOW to initiate a write,
IL
and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document Number: 001-49315 Rev. *A
Page 5 of 10
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CY7C10612DV33
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min
Typ
Max
Unit
V
2
ICCDR
Data Retention Current
VCC = 2V , CE > VCC – 0.2V,
25
mA
VIN > VCC – 0.2V or VIN < 0.2V
[10]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
[ 11]
tR
tRC
Data Retention Waveform
DATA RETENTION MODE
DR > 2V
3.0V
3.0V
VCC
CE
V
t
t
R
CDR
Switching Waveforms
Figure 3. Read Cycle No. 1 [12, 13]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear V ramp from V to V > 50 μs or stable at V > 50 μs.
CC(min.)
CC
DR
CC(min.)
12. The device is continuously selected. OE, CE = V , BHE, BLE or both = V
.
IL
IL
13. WE is HIGH for read cycle.
Document Number: 001-49315 Rev. *A
Page 6 of 10
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CY7C10612DV33
Switching Waveforms (continued)
Figure 4. Read Cycle No. 2 (OE Controlled) [13, 14]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
I
SB
Figure 5. Write Cycle No. 1 (CE Controlled) [15, 16]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA IO
Notes
14. Address valid before or similar to CE transition LOW.
15. Data IO is high impedance if OE, BHE, and/or BLE = V
.
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 001-49315 Rev. *A
Page 7 of 10
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CY7C10612DV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16]
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA IO
t
LZWE
Figure 7. Write Cycle No. 3 (BLE or BHE Controlled) [15]
t
WC
ADDRESS
BHE, BLE
t
SA
t
BW
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA IO
Document Number: 001-49315 Rev. *A
Page 8 of 10
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CY7C10612DV33
Truth Table
IO0–IO7
High-Z
IO8–IO15
High-Z
Mode
Power
CE
OE WE BLE
BHE
H
X
L
X
H
H
H
L
X
L
X
Power Down
Read All Bits
Standby (ISB)
L
L
L
L
L
L
L
L
H
L
Data Out
Data Out
High-Z
Data Out
High-Z
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
H
L
Data Out
Data In
High-Z
X
X
X
H
L
Data In
Data In
High-Z
L
L
H
L
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
H
X
Data In
High-Z
H
X
High-Z
Ordering Information
Speed
(ns)
Package
Diagram
Ordering Code
Package Type
Operating Range
10
CY7C10612DV33-10ZSXI
51-85160 54-Pin TSOP II (Pb-Free)
Industrial
Package Diagrams
Figure 8. 54-Pin TSOP Type II
51-85160-**
Document Number: 001-49315 Rev. *A
Page 9 of 10
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CY7C10612DV33
Document History Page
Document Title: CY7C10612DV33, 16-Mbit (1M x 16) Static RAM
Document Number: 001-49315
Orig. of
Change
Submission
Date
Rev. ECN No.
Description of Change
**
2589743 VKN/PYRS
2718906 VKN
10/15/08
New datasheet
*A
06/15/2009 Post to external web
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© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-49315 Rev. *A
Revised June 15, 2009
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