CY7C10612GE30-10ZSXIT [CYPRESS]
16-Mbit (1M Ã 16) Static RAM;
| 型号： | CY7C10612GE30-10ZSXIT |
| 厂家： | 
CYPRESS |
| 描述： | 16-Mbit (1M Ã 16) Static RAM |
| 文件： | 总19页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C10612G
CY7C10612GE
16-Mbit (1M × 16) Static RAM
16-Mbit (1M
× 16) Static RAM
Features
Functional Description
■ High speed
❐ tAA = 10 ns
The CY7C10612G and CY7C10612GE are high performance
CMOS fast static RAM devices with embedded ECC. These
devices are offered in single chip enable option. The
CY7C10612GE device includes an error indication pin that
signals an error-detection and correction event during a read
cycle.
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Low active power
❐ ICC = 90 mA typical
To write to the device, take Chip Enables (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
■ Low CMOS standby power
❐ ISB2 = 20 mA typical
■ Operating voltages of 3.3 ± 0.3 V
■ 1.0 V data retention
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See Truth Table on page 14 for a
complete description of Read and Write modes.
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ ERR pin to indicate 1-bit error detection and correction
■ Available in Pb-free 54-pin TSOP II package
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
On the CY7C10612GE devices the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = high). See the Truth Table
on page 14 for a complete description of read and write modes.
The CY7C10612G and CY7C10612GE are available in a 54-pin
TSOP II package.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum Access Time
-10
10
Unit
ns
Maximum Operating Current
110
30
mA
mA
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document Number: 001-88702 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 3, 2018
CY7C10612G
CY7C10612GE
Logic Block Diagram – CY7C10612G
INPUT BUFFER
A
0
A
1
A
2
A
4
3
I/O0 – I/O7
I/O8 – I/O15
1M x 16
ARRAY
A
A
5
6
A
A
7
A
8
A
9
COLUMN
DECODER
BHE
WE
CE
OE
BLE
Logic Block Diagram – CY7C10612GE
Document Number: 001-88702 Rev. *F
Page 2 of 19
CY7C10612G
CY7C10612GE
Contents
Pin Configurations ...........................................................4
Maximum Ratings .............................................................6
Operating Range ...............................................................6
DC Electrical Characteristics ..........................................6
Capacitance ......................................................................7
Thermal Resistance ..........................................................7
AC Test Loads and Waveforms .......................................7
Data Retention Characteristics .......................................8
Data Retention Waveform ................................................8
AC Switching Characteristics .........................................9
Switching Waveforms ....................................................10
Truth Table ......................................................................14
ERR Output – CY7C10612GE ........................................14
Ordering Information ......................................................15
Ordering Code Definitions .........................................15
Package Diagrams ..........................................................16
Acronyms ........................................................................17
Document Conventions .................................................17
Units of Measure .......................................................17
Document History Page .................................................18
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products ....................................................................19
PSoC® Solutions ......................................................19
Cypress Developer Community .................................19
Technical Support .....................................................19
Document Number: 001-88702 Rev. *F
Page 3 of 19
CY7C10612G
CY7C10612GE
Pin Configurations
Figure 1. 54-pin TSOP II pinout (Top View) [1]
CY7C10612G
I/O
V
I/O
V
12
1
2
3
4
5
6
54
53
52
51
50
49
48
47
46
11
CC
SS
I/O
I/O
I/O
V
13
14
10
9
I/O
V
SS
CC
I/O
I/O
A
5
15
8
A
7
4
3
2
1
0
A
A
A
A
A
6
8
9
A
7
A
8
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
45
44
NC
BHE
CE
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
OE
V
V
CC
SS
WE
NC
NC
BLE
A
19
A
10
A
18
A
11
A
17
A
12
A
16
A
13
A
15
A
14
I/O
7
I/O
0
V
CC
V
SS
I/O
6
I/O
5
I/O
1
I/O
2
V
SS
V
CC
I/O
3
I/O
4
Note
1. NC pins are not connected on the die.
Document Number: 001-88702 Rev. *F
Page 4 of 19
CY7C10612G
CY7C10612GE
Pin Configurations (continued)
Figure 2. 54-pin TSOP II pinout with ERR (Top View) [2, 3]
CY7C10612GE
Note
2. NC pins are not connected on the die.
3. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-88702 Rev. *F
Page 5 of 19
CY7C10612G
CY7C10612GE
DC Input Voltage[4] ............................. –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................> 2001 V
Storage Temperature ............................... –65 C to +150 C
Latch Up Current ...................................................> 200 mA
Ambient Temperature
with Power Applied .................................. –55 C to +125 C
Operating Range
Supply Voltage
on VCC Relative to GND[4] ..................–0.5 V to VCC + 0.5 V
Range
Ambient Temperature
VCC
DC Voltage Applied to Outputs
Industrial
–40 C to +85 C
3.3 V 0.3 V
in High Z State[4] .................................–0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
10 ns
Typ [5]
Parameter
VOH
Description
Test Conditions
Unit
Min
2.2
2.4
–
Max
–
Output HIGH
Voltage
2.2 V to 2.7 V VCC = Min, IOH = –4.0 mA
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA
–
–
V
–
VOL
Output LOW Voltage
Input HIGH Voltage
VCC = Min, IOL = 8 mA
–
0.4
V
V
[4]
VIH
–
2.0
–0.3
–1.0
–1.0
–
–
VCC + 0.3
0.8
[4]
VIL
IIX
Input LOW Voltage
–
–
V
Input Leakage Current
Output Leakage Current
Operating Supply Current
GND < VIN < VCC
–
+1.0
+1.0
110.0
80.0
A
A
mA
mA
IOZ
ICC
GND < VOUT < VCC, Output disabled
–
VCC = Max,
OUT = 0 mA,
CMOS levels
f = 100 MHz
f = 66.7 MHz
90.0
70.0
I
–
[5]
ISB1
ISB2
Automatic CE Power-down
Current – TTL Inputs
Max VCC, CE > VIH
,
–
–
–
40.0
30.0
mA
mA
VIN > VIH or VIN < VIL, f = fMAX
Max VCC, CE > VCC – 0.2 V [5]
IN > VCC – 0.2 V or VIN < 0.2 V, f = 0
Automatic CE Power-down
Current – CMOS Inputs
,
20.0
V
Notes
4.
V
= –2.0 V and V
= V + 2 V for pulse durations of less than 20 ns.
IH(max) CC
IL(min)
5. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),
CC
CC
V
= 3 V (for a V range of 2.2 V–3.6 V), and V = 5 V (for a V range of 4.5 V–5.5 V), T = 25 °C.
CC CC CC A
CC
Document Number: 001-88702 Rev. *F
Page 6 of 19
CY7C10612G
CY7C10612GE
Capacitance
Parameter [6]
Description
Input Capacitance
I/O Capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
54-pin TSOP II Unit
CIN
10
pF
COUT
Thermal Resistance
Parameter [6]
Description
Test Conditions
54-pin TSOP II Unit
JA
Thermal Resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
93.63
C/W
JC
Thermal Resistance
(junction to case)
21.58
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [7]
HIGH Z CHARACTERISTICS:
R1 317
50
3.3 V
= 1.5 V
VTH
OUTPUT
OUTPUT
5 pF*
Z = 50
R2
351
30 pF*
0
INCLUDING
JIG AND
SCOPE
(a)
(b)
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
ALL INPUT PULSES
3.0 V
90%
10%
90%
10%
GND
FALL TIME:
> 1 V/ns
RISE TIME:
> 1 V/ns
(c)
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full-device AC operation assumes a 100-µs ramp time from 0 to V (min) and 100-µs wait time after V stabilizes to its operational value.
CC
CC
Document Number: 001-88702 Rev. *F
Page 7 of 19
CY7C10612G
CY7C10612GE
Data Retention Characteristics
Over the Operating Range –45 C to 85 C
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min
1.0
–
Typ [8]
Max
–
Unit
V
–
–
–
ICCDR
Data Retention Current
VCC = 2 V, CE VCC – 0.2 V,
VIN VCC – 0.2 V or VIN 0.2 V
30.0
mA
[9]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
–
–
0.0
–
–
–
–
ns
ns
[9, 10]
tR
10.0
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
3.0 V
3.0 V
VCC
CE
VDR > 1 V
t
t
R
CDR
Notes
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
9. This parameter is guaranteed by design and is not tested.
10. Full device operation requires linear V ramp from V to V
100 s or stable at V
100 s.
CC
DR
CC(min.)
CC(min.)
Document Number: 001-88702 Rev. *F
Page 8 of 19
CY7C10612G
CY7C10612GE
AC Switching Characteristics
Over the Operating Range
-10
Parameter [11]
Description
Unit
Min
Max
Read Cycle
tPOWER
tRC
VCC to the first access [12]
Read cycle time
100.0
10.0
–
–
–
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
10.0
–
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data hold from address change
CE LOW to data valid
3.0
–
10.0
5.0
–
OE LOW to data valid
–
OE LOW to low Z [13, 14, 15]
OE HIGH to high Z [13, 14, 15]
CE LOW to low Z [13, 14, 15]
CE HIGH to high Z [13, 14, 15]
CE LOW to power-up [16]
CE HIGH to power-down [16]
Byte enable to data valid
Byte enable to low Z
0.0
–
5.0
–
3.0
–
5.0
–
0.0
–
tPD
10.0
5.0
–
tDBE
tLZBE
tHZBE
–
1.0
–
Byte disable to high Z
6.0
Write Cycle [17, 18]
tWC
tSCE
tAW
Write cycle time
10.0
7.0
7.0
0.0
0.0
7.0
5.0
0.0
3.0
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
tHA
–
tSA
–
tPWE
tSD
–
Data setup to write end
Data hold from write end
WE HIGH to low Z [13, 14, 15]
WE LOW to high Z [13, 14, 15]
Byte enable to end of write
–
tHD
–
tLZWE
tHZWE
tBW
–
5.0
–
7.0
Notes
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading shown in part a) of Figure 3 on page 7, unless specified otherwise.
12. t
13. t
gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
CC
POWER
, t
, t
, t
, t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 7. Transition is measured 200 mV from steady
HZOE HZCE HZWE HZBE LZOE LZCE LZWE
LZBE
state voltage.
14. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
15. Tested initially and after any design or process changes that may affect these parameters.
16. These parameters are guaranteed by design and are not tested.
17. The internal write time of the memory is defined by the overlap of WE, CE = V . Chip enable must be active and WE and byte enables must be LOW to initiate a write,
IL
and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
18. The minimum write cycle time for Write Cycle No. 2 (WE Controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document Number: 001-88702 Rev. *F
Page 9 of 19
CY7C10612G
CY7C10612GE
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) for CY7C10612G [19, 20]
tRC
ADDRESS
DATA I/O
t
AA
t
OHA
PREVIOUS DATA VALID
DATA OUT VALID
Figure 6. Read Cycle No. 1 (Address Transition Controlled) for CY7C10612GE [20, 21]
Notes
19. The device is continuously selected. OE, CE = V , BHE, BLE or both = V
.
IL
IL
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE transition LOW.
Document Number: 001-88702 Rev. *F
Page 10 of 19
CY7C10612G
CY7C10612GE
Switching Waveforms (continued)
Figure 7. Read Cycle No. 2 (OE Controlled) [22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
tHZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
tLZCE
tPU
DATA I/O
DATAOUT VALID
VCC
SUPPLY
CURRENT
ISB
Notes
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE transition LOW.
Document Number: 001-88702 Rev. *F
Page 11 of 19
CY7C10612G
CY7C10612GE
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (CE Controlled) [24, 25, 26]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA IN VALID
DATA I/O
Figure 9. Write Cycle No. 2 (WE Controlled, OE LOW) [24, 25, 26]
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
Note 27
DATA IN VALID
DATA I/O
t
LZWE
Notes
24. Data I/O is high impedance if OE, BHE, and/or BLE = V
.
IH
25. The internal write time of the memory is defined by the overlap of WE = V , CE = V and BHE or BLE = V . These signals must be LOW to initiate a write, and the
IL
IL
IL
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
26. The minimum write cycle pulse width should be equal to the sum of t
and t
.
HZWE
SD
27. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-88702 Rev. *F
Page 12 of 19
CY7C10612G
CY7C10612GE
Switching Waveforms (continued)
Figure 10. Write Cycle No. 3 (BLE or BHE Controlled) [28, 29]
t
WC
ADDRESS
BHE, BLE
t
t
BW
SA
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
Note 30
DATA IN VALID
DATA I/O
Notes
28. Data I/O is high impedance if OE, BHE, and/or BLE = V
.
IH
29. The internal write time of the memory is defined by the overlap of WE = V , CE = V and BHE or BLE = V . These signals must be LOW to initiate a write, and the
IL
IL
IL
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
30. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-88702 Rev. *F
Page 13 of 19
CY7C10612G
CY7C10612GE
Truth Table
I/O0–I/O7
High Z
I/O8–I/O15
High Z
Mode
Power-down
Power
CE OE WE BLE BHE
H
L
L
L
L
L
L
L
X
L
X
H
H
H
L
X
L
X
L
Standby (ISB)
Data Out
Data Out
High Z
Data Out
High Z
Read all bits
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
H
L
Read lower bits only
Read upper bits only
Write all bits
L
H
L
Data Out
Data In
High Z
X
X
X
H
L
Data In
Data In
High Z
L
L
H
L
Write lower bits only
Write upper bits only
L
H
X
Data In
High Z
H
X
High Z
Selected, outputs disabled Active (ICC
ERR Output – CY7C10612GE
Output[31]
Mode
0
1
Read Operation, no error in the stored data.
Read Operation, single-bit error detected and corrected.
Device deselected or Outputs disabled or Write Operation.
High-Z
Note
31. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-88702 Rev. *F
Page 14 of 19
CY7C10612G
CY7C10612GE
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type (Pb-free)
10
CY7C10612G30-10ZSXI
CY7C10612G30-10ZSXIT
CY7C10612GE30-10ZSXI
CY7C10612GE30-10ZSXIT
51-85160 54-pin TSOP II
Industrial
54-pin TSOP II, Tape and Reel
54-pin TSOP II, with ERR Pin
54-pin TSOP II, with ERR Pin, Tape and Reel
Ordering Code Definitions
X
- 10 ZS
30
I
X
C
7
CY
1
2
G
E
1
06
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
ZS = 54-pin TSOP II
Speed Grade: 10 ns
Voltage Range: 30 = 3 V to 3.6 V
X = blank or E
blank = without ERR output;
E = with ERR output, Single bit error correction indicator
Process Technology: G = 65 nm
Single chip enable
Bus Width: 1 = × 16
Density: 06 = 16-Mbit
Fast asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-88702 Rev. *F
Page 15 of 19
CY7C10612G
CY7C10612GE
Package Diagrams
Figure 11. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
51-85160 *E
Document Number: 001-88702 Rev. *F
Page 16 of 19
CY7C10612G
CY7C10612GE
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
BHE
BLE
Description
Table 2. Units of Measure
Byte High Enable
Byte Low Enable
Chip Enable
Symbol
°C
Unit of Measure
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
millivolt
MHz
µA
s
CE
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
mA
mm
mV
ns
OE
Output Enable
SRAM
TSOP
TTL
Static Random Access Memory
Thin Small Outline Package
Transistor-Transistor Logic
Write Enable
nanosecond
ohm
WE
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 001-88702 Rev. *F
Page 17 of 19
CY7C10612G
CY7C10612GE
Document History Page
Document Title: CY7C10612G/CY7C10612GE, 16-Mbit (1M × 16) Static RAM
Document Number: 001-88702
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*D
*E
4865557
5437839
NILE
NILE
07/31/2015 Changed status from Preliminary to Final.
09/15/2016 Updated Maximum Ratings:
Updated Note 4 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Removed all values corresponding to VOH parameter.
Included Operating Ranges “2.2 V to 2.7 V” and “2.7 V to 3.0 V” and all values
corresponding to VOH parameter.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
Completing Sunset Review.
*F
6011828 AESATMP8 01/03/2018 Updated logo and Copyright.
Document Number: 001-88702 Rev. *F
Page 18 of 19
CY7C10612G
CY7C10612GE
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
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© Cypress Semiconductor Corporation, 2013-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
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Document Number: 001-88702 Rev. *F
Revised January 3, 2018
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