CY7C1020-15ZC [CYPRESS]
32K x 16 Static RAM; 32K ×16静态RAM
| 型号： | CY7C1020-15ZC |
| 厂家： | 
CYPRESS |
| 描述： | 32K x 16 Static RAM |
| 文件： | 总9页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
7C10
CY7C1020
32K x 16 Static RAM
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is
Features
1
8
written into the location specified on the address pins (A
0
• 5.0V operation (± 10%)
• High speed
through A ). If Byte High Enable (BHE) is LOW, then data
14
from I/O pins (I/O through I/O ) is written into the location
9
16
specified on the address pins (A through A ).
0
14
— t = 10 ns
AA
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
• Low active power
— 825 mW (max., 10 ns, “L” version)
• Very Low standby power
will appear on I/O to I/O . If Byte High Enable (BHE) is LOW,
1
8
— 550 W (max., “L” version)
µ
then data from memory will appear on I/O to I/O . See the
9
16
• Automatic power-down when deselected
• Independent Control of Upper and Lower bytes
• Available in 44-pin TSOP II and 400-mil SOJ
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O through I/O ) are placed in a
1
16
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1020 is a high-performance CMOS static RAM or-
ganized as 32,768 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
The CY7C1020 is available in standard 44-pin TSOP type II
and 400-mil-wide SOJ packages.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
DATA IN DRIVERS
Top View
44
NC
1
A
0
43
42
41
40
39
38
A
A
A
2
OE
BHE
BLE
I/O
I/O
I/O
2
3
4
5
6
14
1
A
13
A
11
A6
A5
A4
12
A
CE
I/O
I/O
I/O
32K x 16
RAM Array
I/O1 – I/O8
I/O9 – I/O16
7
1
A3
16
37
36
35
34
33
8
2
3
15
14
13
A2
A1
A0
9
10
11
12
13
I/O
V
I/O
4
V
SS
CC
V
V
SS
CC
I/O
32
I/O
I/O
5
6
7
8
12
11
I/O
I/O
I/O
WE 17
A
31
30
29
28
14
15
16
I/O
I/O
10
9
COLUMN DECODER
NC
18
27
26
25
A
3
10
BHE
19
A
4
A
9
WE
CE
OE
20
A
A
8
5
21
22
A
6
A
24
23
7
1020-2
NC
NC
BLE
1020-1
Selection Guide
7C1020-10
10
7C1020-12
7C1020-15
7C1020-20
Maximum Access Time (ns)
12
170
140
3
15
160
130
3
20
160
130
3
Maximum Operating Current (mA)
180
150
3
L
L
Maximum CMOS Standby Current (mA)
0.1
0.1
0.1
0.1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 18, 1999
CY7C1020
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
[1]
Ambient
Supply Voltage on V to Relative GND .... –0.5V to +7.0V
CC
[2]
Range
Temperature
V
CC
DC Voltage Applied to Outputs
[1]
Commercial
0°C to +70°C
4.5V–5.5V
in High Z State .....................................–0.5V to V +0.5V
CC
[1]
DC Input Voltage ..................................–0.5V to V +0.5V
CC
Electrical Characteristics Over the Operating Range
7C1020-10
7C1020-12
7C1020-15
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = –4.0 mA
Min. Max. Min. Max. Min. Max. Unit
V
V
V
2.4
2.4
2.4
V
V
OH
CC
CC
OH
V
= Min., I = 8.0 mA
0.4
6.0
0.8
+1
0.4
6.0
0.8
+1
0.4
6.0
0.8
+1
OL
OL
V
2.2
–0.5
–1
2.2
–0.5
–1
2.2
–0.5
–1
V
IH
IL
[1]
V
Input LOW Voltage
V
I
Input Load Current
GND < V < V
CC
µA
µA
IX
I
I
Output Leakage
Current
GND < V < V ,
CC
–2
+2
–2
+2
–2
+2
OZ
I
Output Disabled
I
I
I
V
Operating
V
= Max.,
= 0 mA,
180
150
170
140
160
130
mA
mA
CC
CC
CC
Supply Current
I
OUT
L
L
L
f = f
= 1/t
MAX
RC
Automatic CE
Power-Down Current
—TTL Inputs
Max. V , CE > V
IH
V
V
20
10
20
10
20
10
SB1
SB2
CC
> V or
IN
IN
IH
< V , f = f
IL
MAX
Automatic CE
Power-Down Current
—CMOS Inputs
Max. V
CE > V – 0.3V,
V
,
3
3
3
mA
CC
CC
100
100
100
µA
> V – 0.3V,
CC
IN
or V < 0.3V, f = 0
IN
Notes:
1. IL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the case temperature.
V
2
CY7C1020
Electrical Characteristics Over the Operating Range (continued)
7C1020-20
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = –4.0 mA
Min.
Max.
Unit
V
V
V
V
2.4
OH
CC
CC
OH
V
= Min., I = 8.0 mA
0.4
6.0
0.8
+1
V
OL
OL
V
V
2.2
–0.5
–1
V
IH
IL
[1]
Input LOW Voltage
V
I
I
I
Input Load Current
GND < V < V
CC
µA
µA
mA
IX
I
Output Leakage Current
GND < V < V , Output Disabled
–2
+2
OZ
CC
I
CC
V
Operating
V
= Max.,
= 0 mA,
160
130
CC
CC
Supply Current
I
OUT
L
L
L
f = f
= 1/t
MAX
RC
I
I
Automatic CE
Power-Down Current
—TTL Inputs
Max. V , CE > V
IH
20
10
mA
SB1
SB2
CC
V
V
> V or
IN
IN
IH
< V , f = f
IL
MAX
Automatic CE
Power-Down Current
—CMOS Inputs
Max. V
,
3
mA
CC
CE > V – 0.3V,
CC
100
µA
V
> V – 0.3V,
CC
IN
or V < 0.3V, f = 0
IN
Capacitance[3]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
Input Capacitance
Output Capacitance
8
8
IN
A
V
= 5.0V
CC
pF
OUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R 481
Ω
R 481
Ω
ALL INPUT PULSES
90%
5V
5V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
10%
R2
255
R2
255
30 pF
5 pF
Ω
Ω
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
<3 ns
<3 ns
(b)
1020-3
(a)
1020-4
167
Ω
1.73V
OUTPUT
Equivalent to:
THÉVENIN
EQUIVALENT
30 pF
3
CY7C1020
Switching Characteristics[4] Over the Operating Range
7C1020-10
7C1020-12
7C1020-15
7C1020-20
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
10
3
12
3
15
3
20
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
10
12
15
20
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
10
5
12
5
15
7
20
9
0
3
0
0
3
0
0
3
0
0
3
0
[5, 6]
OE HIGH to High Z
5
5
6
6
7
7
8
8
[6]
CE LOW to Low Z
[5, 6]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte enable to Data Valid
Byte enable to Low Z
12
5
12
6
15
7
20
9
PD
DBE
LZBE
HZBE
0
0
0
0
Byte disable to High Z
5
6
7
9
[7]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
10
8
12
9
15
10
10
0
12
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
SCE
AW
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
8
0
0
HA
0
0
0
0
SA
7
8
10
10
0
12
10
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
5
6
0
0
HD
[6]
WE HIGH to Low Z
3
3
3
3
LZWE
HZWE
BW
[5, 6]
WE LOW to High Z
5
6
7
9
Byte enable to end of write
7
8
9
12
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
t
OL/IOH and 30-pF load capacitance.
5.
HZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CELOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
4
CY7C1020
Switching Waveforms
[8, 9]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1020-5
[9, 10]
Read Cycle No. 2(OE Controlled)
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
CC
V
PU
CC
50%
50%
SUPPLY
CURRENT
I
SB
1020-6
Notes:
8. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
9. WE is HIGH for read cycle.
10. Address valid prior to or coincident with CE transition LOW.
5
CY7C1020
Switching Waveforms (continued)
[11, 12]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATAI/O
1020-7
Write Cycle No. 2 (BLEor BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
1020-8
Notes:
11. Data I/O is high impedance if OE or BHE and/or BLE= VIH
.
12. If CEgoes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
6
CY7C1020
Switching Waveforms (continued)
Write Cycle No.3
Controlled, OE LOW)
(WE
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
SD
t
HD
DATA I/O
t
LZWE
1020-10
Truth Table
CE OE WE BLE BHE
I/O –I/O
I/O –I/O
16
Mode
Power
1
8
9
H
L
X
L
X
H
X
L
X
L
High Z
High Z
Data Out
High Z
Data Out
Data In
High Z
Data In
High Z
High Z
Power-Down
Read - All bits
Standby (I
)
SB
Data Out
Data Out
High Z
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
)
CC
L
H
L
Read - Lower bits only
Read - Upper bits only
Write - All bits
)
CC
H
L
)
CC
L
X
L
L
Data In
Data In
High Z
)
CC
L
H
L
Write - Lower bits only
Write - Upper bits only
)
CC
H
X
H
)
CC
L
L
H
X
H
X
X
H
High Z
Selected, Outputs Disabled
Selected, Outputs Disabled
)
CC
High Z
)
CC
7
CY7C1020
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
10
CY7C1020-10VC
CY7C1020L-10VC
CY7C1020-10ZC
CY7C1020L-10ZC
CY7C1020-12VC
CY7C1020L-12VC
CY7C1020-12ZC
CY7C1020L-12ZC
CY7C1020-15VC
CY7C1020L-15VC
CY7C1020-15ZC
CY7C1020L-15ZC
CY7C1020-20VC
CY7C1020L-20VC
CY7C1020-20ZC
CY7C1020L-20ZC
V34
V34
Z44
Z44
V34
V34
Z44
Z44
V34
V34
Z44
Z44
V34
V34
Z44
Z44
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
44-Lead TSOP Type II
12
15
20
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
Document #: 38-00542-C
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
8
CY7C1020
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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