CY7C1020B [CYPRESS]
32K x 16 Static RAM; 32K ×16静态RAM
| 型号： | CY7C1020B |
| 厂家： | 
CYPRESS |
| 描述： | 32K x 16 Static RAM |
| 文件： | 总10页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
020B
CY7C1020B
32K x 16 Static RAM
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Features
• High speed
— tAA = 12, 15 ns
• CMOS for optimum speed/power
• Low active power
— 825 mW (max.)
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
• Low CMOS standby power (L version only)
— 2.75 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020B is a high-performance CMOS static RAM or-
ganized as 32,768 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
The CY7C1020B is available in standard 44-pin TSOP Type II
and 400-mil-wide SOJ packages.
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
DATA IN DRIVERS
Top View
44
1
2
3
4
5
6
NC
A
5
43
42
41
40
39
38
A
A
3
6
A
2
A
7
A
A
A
7
6
5
4
OE
A
1
A
BHE
BLE
I/O
0
32K x 16
CE
A
A
A
A
I/O –I/O
RAM Array
I/O
1
8
7
1
16
37
36
35
34
33
3
2
I/O
I/O
8
I/O
I/O
2
3
15
14
13
I/O –I/O
9
9
16
10
11
12
I/O
V
SS
I/O
1
0
4
CC
V
SS
A
V
V
CC
I/O
32
31
30
29
28
27
I/O
I/O
13
5
6
7
8
12
11
I/O
I/O
I/O
14
15
16
I/O
I/O
10
9
COLUMN DECODER
WE 17
18
NC
A
A
A
A
15
14
13
8
BHE
19
20
21
22
26
25
A
9
10
11
WE
CE
OE
A
A
A
12
24
23
NC
NC
BLE
Selection Guide
7C1020B-12
7C1020B-15
Maximum Access Time (ns)
Commercial
Commercial
Commercial
L
12
140
3
15
130
3
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
0.5
0.5
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05171 Rev. *A
Revised August 20, 2002
CY7C1020B
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
Range
Commercial
Industrial
Temperature[2]
0°C to +70°C
VCC
DC Voltage Applied to Outputs
5V ± 10%
5V ± 10%
in High Z State[1] ......................................–0.5V to VCC+0.5V
–40°C to +85°C
DC Input Voltage[1]...................................–0.5V to VCC+0.5V
Electrical Characteristics Over the Operating Range
7C1020B-12
7C1020B-15
Test
Conditions
Parameter
VOH
Description
Min.
Max.
Min.
Max.
Unit
Output HIGH Voltage
VCC = Min.,
OH = –4.0 mA
2.4
2.4
V
I
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
0.4
V
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage[1]
Input Load Current
2.2
–0.5
–1
6.0
0.8
+1
2.2
–0.5
–1
6.0
0.8
+1
V
V
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VI < VCC
,
–1
+1
–1
+1
Output Disabled
IOS
ICC
Output Short
VCC = Max.,
VOUT = GND
–300
–300
mA
mA
Circuit Current[3]
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
140
130
ISB1
Automatic CE
Power-Down
Max. VCC
CE > VIH
,
20
20
mA
Current—TTL Inputs
VIN > VIH or
IN < VIL,
V
f = fMAX
ISB2
Automatic CE
Power-Down
Current—CMOS Inputs VCC – 0.3V, VIN
Max. VCC
CE >
,
3
3
mA
mA
L
0.5
0.5
>
VCC – 0.3V,
or VIN < 0.3V, f = 0
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the case temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05171 Rev. *A
Page 2 of 10
CY7C1020B
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
pF
CIN
8
8
COUT
pF
AC Test Loads and Waveforms
R 481Ω
R 481Ω
ALL INPUT PULSES
5V
5V
OUTPUT
3.0V
90%
10%
90%
10%
OUTPUT
R2
255Ω
R2
255Ω
GND
30 pF
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(b)
(a)
167
30 pF
1.73V
OUTPUT
Equivalent to:
THÉVENIN
EQUIVALENT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05171 Rev. *A
Page 3 of 10
CY7C1020B
Switching Characteristics[5] Over the Operating Range
7C1020B-12
7C1020B-15
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
12
3
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
12
15
tOHA
tACE
12
6
15
7
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
6
6
7
7
tPD
12
6
15
7
tDBE
tLZBE
tHZBE
Write Cycle[8]
tWC
0
0
6
7
Write Cycle Time
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
tHA
0
tSA
0
0
tPWE
8
10
8
tSD
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
6
tHD
0
0
tLZWE
tHZWE
3
3
WE LOW to High Z[6, 7]
6
7
tBW
Byte Enable to End of Write
8
9
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to theleading edge of the signal that terminates the write.
Document #: 38-05171 Rev. *A
Page 4 of 10
CY7C1020B
Switching Waveforms
Read Cycle No. 1[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
(OEControlled)[10, 11]
Read Cycle No. 2
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
CC
PU
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL
.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05171 Rev. *A
Page 5 of 10
CY7C1020B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled) [12, 13]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Write Cycle No. 2 (BLEor BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes:
12. Data I/O is high impedance if OE or BHE and/or BLE= VIH
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05171 Rev. *A
Page 6 of 10
CY7C1020B
Switching Waveforms (continued)
Write Cycle No. 3
Controlled) OE LOW)
(WE
t
WC
ADDRESS
t
SCE
CE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE OE WE BLE BHE
I/O1–I/O8
High Z
I/O9–I/O16
High Z
Mode
Power
H
L
X
L
X
H
X
L
X
L
Power-Down
Read – All bits
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
Data Out
Data Out
High Z
Data Out
High Z
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
Data Out
Data In
High Z
)
L
X
L
L
Data In
Data In
High Z
)
L
H
L
Write – Lower bits only
Write – Upper bits only
)
H
X
H
Data In
High Z
)
L
L
H
X
H
X
X
H
High Z
Selected, Outputs Disabled
Selected, Outputs Disabled
)
High Z
High Z
)
Document #: 38-05171 Rev. *A
Page 7 of 10
CY7C1020B
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
12
CY7C1020B-12VC
CY7C1020BL-12VC
CY7C1020B-12ZC
CY7C1020BL-12ZC
CY7C1020B-15VC
CY7C1020BL-15VC
CY7C1020B-15ZC
CY7C1020BL-15ZC
V34
V34
Z44
Z44
V34
V34
Z44
Z44
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
44-Lead TSOP Type II
15
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
Document #: 38-05171 Rev. *A
Page 8 of 10
CY7C1020B
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05171 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1020B
Document Title: CY7C1020B 32K x 16 Static RAM
Document #: 38-05171
Issue
Orig. of
Change
REV.
**
*A
ECN NO. Date
Description of Change
New Data Sheet
115439
116869
05/09/02
08/21/02
DSG
DFP
Added L-Power Specifications.
Document #: 38-05171 Rev. *A
Page 10 of 10
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