CY7C09369A-7AC [CYPRESS]
16K x16/18 Synchronous Dual Port Static RAM; 16K X16 / 18同步双端口静态RAM
| 型号： | CY7C09369A-7AC |
| 厂家： | 
CYPRESS |
| 描述： | 16K x16/18 Synchronous Dual Port Static RAM |
| 文件： | 总18页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
25/0251
CY7C09269A
CY7C09369A
16K x16/18 Synchronous
Dual Port Static RAM
• Low operating power
Features
—Active = 195 mA (typical)
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
—Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
—Shorten cycle times
• Two Flow-Through/Pipelined devices
— 16K x 16/18 organization (CY7C09269A/369A)
• Three Modes
—Minimize bus noise
— Flow-Through
—Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast 100-
MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speedclocktodataaccess6.5[1]/7.5/9/12ns(max.)
• Commercial temperature range
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to
IDT709269
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE0R
1
1
CE1L
LBL
CE1R
LBR
0
0
0/1
0/1
OEL
OER
1b 0b 1a 0a
0a 1a 0b 1b
0/1
0/1
b
a
a
b
FT/PipeL
FT/PipeR
8/9
8/9
8/9
8/9
[2]
[2]
I/O8/9L–I/O15/17L
I/O8/9R–I/O15/17R
I/O
Control
I/O
Control
[3]
[3]
I/O0L–I/O
I/O0R–I/O
7/8L
7/8R
14
14
A
0L–A13L
A0R–A13R
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
CLKL
CLKR
ADSR
True Dual-Ported
RAM Array
ADSL
CNTENL
CNTENR
CNTRSTR
CNTRSTL
Notes:
1. See page 6 for Load Conditions.
2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
3. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06050 Rev. *A
Revised December 27, 2002
CY7C09269A
CY7C09369A
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE0 LOW and CE1
HIGH to reactivate the outputs.
Functional Description
The CY7C09269A and CY7C09369A are high-speed synchro-
nous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.[4] Reg-
isters on control, address, and data lines allow for minimal set-
up and hold times. In pipelined output mode, data is registered
for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1]
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available tCD1 = 15 ns after the
address is clocked into the device. Pipelined output or flow-
through mode is selected via the FT/PIPE pin.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
1
75
74
73
72
A9R
2
A10R
A11R
A12R
3
A12L
A13L
NC
4
5
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A13R
NC
6
NC
7
NC
NC
8
NC
NC
9
NC
LBL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
LBR
UBL
UBR
CE0R
CE1R
CNTRSTR
GND
R/WR
OER
CE0L
CE1L
CNTRSTL
VCC
CY7C09269A (16K x 16)
R/WL
OEL
[5]
[5]
FT/PIPEL
GND
FT/PIPER
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O11L
I/O10L
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes:
4. When writing simultaneously to the same location, the final value cannot be guaranteed.
5. For CY7C09269A pin #18 connected to VCC is equivalent to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent to an IDT x16 flow-
through device.
Document #: 38-06050 Rev. *A
Page 2 of 17
CY7C09269A
CY7C09369A
Pin Configurations (continued)
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
A8R
2
A9R
A11L
3
A10R
A11R
A12R
A13R
NC
A12L
4
A13L
5
NC
6
NC
7
LBL
8
NC
UBL
9
LBR
CE0L
CE1L
CNTRSTL
R/WL
OEL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
UBR
CE0R
CE1R
CNTRSTR
R/WR
GND
CY7C09369A (16K x 18)
VCC
FT/PIPEL
I/O17L
I/O16L
GND
OER
FT/PIPER
I/O17R
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O16R
I/O15R
I/O14R
I/O13R
I/O11L
I/O10L
24
25
52
51
I/O12R
I/O11R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C09269A
CY7C09369A
-6[1]
CY7C09269A
CY7C09369A
-7
CY7C09269A
CY7C09369A
-9
CY7C09269A
CY7C09369A
-12
fMAX2 (MHz) (Pipelined)
100
6.5
83
67
9
50
12
Max Access Time (ns)
7.5
(Clock to Data, Pipelined)
Typical Operating Current ICC (mA)
250
45
235
40
215
35
195
30
Typical Standby Current for ISB1 (mA)
(Both Ports TTL Level)
Typical Standby Current for ISB3 (mA)
(Both Ports CMOS Level)
0.05
0.05
0.05
0.05
Document #: 38-06050 Rev. *A
Page 3 of 17
CY7C09269A
CY7C09369A
Pin Definitions
Left Port
A0L–A13L
ADSL
Right Port
Description
A0R–A13R
Address Inputs.
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
CE0L,CE1L
CE0R,CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKL
CLKR
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O17L
I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for x16 devices).
LBL
LBR
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte. (I/O0–I/O8 for x18, I/O0–I/O7 for x16) of the memory array. For read operations both
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
UBL
OEL
UBR
OER
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND
NC
Ground Input.
No Connect.
Power Input.
VCC
Maximum Ratings[6]
DC Input Voltage ............................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage............................................ >1100V
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage to Ground Potential............... –0.3V to +7.0V
Operating Range
Ambient
Temperature
DC Voltage Applied to
Outputs in High Z State.................................. –0.5V to +7.0V
Range
VCC
Commercial
0°C to +70°C
5V ± 10%
Note:
6. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
Document #: 38-06050 Rev. *A
Page 4 of 17
CY7C09269A
CY7C09369A
Electrical Characteristics Over the Operating Range
CY7C09269A
CY7C09369A
-6[1]
-7
-9
-12
Parameter
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH
Output HIGH Voltage
(VCC = Min., IOH = –4.0 mA)
2.4
2.4
2.4
2.4
V
VOL
Output LOW Voltage
(VCC = Min., IOH = +4.0 mA)
0.4
0.4
0.4
0.4
V
VIH
VIL
IOZ
ICC
Input HIGH Voltage
Input LOW Voltage
2.2
2.2
2.2
2.2
V
V
0.8
0.8
0.8
0.8
10
Output Leakage Current
–10
10 –10
250 450
10 –10
235 420
10 –10
215 360
µA
Operating Current
(VCC = Max.,
Com’l.
195 300 mA
IOUT = 0 mA)
Outputs Disabled
ISB1
StandbyCurrent(Both Com’l.
Ports TTL Level)[7]
CEL & CER ≥ VIH,
f = fMAX
45 115
40 105
35
95
30
85 mA
ISB2
Standby Current (One Com’l.
Port TTL Level)[7] CEL
| CER ≥ VIH, f = fMAX
175 235
0.05 0.5
160 220
0.05 0.5
145 205
0.05 0.5
125 190 mA
0.05 0.5 mA
ISB3
StandbyCurrent(Both Com’l.
Ports CMOS Level)[7]
CEL & CER ≥ VCC
–
0.2V, f = 0
ISB4
Standby Current (One Com’l.
Port CMOS Level)[7]
CEL | CER ≥ VIH,
160 200
145 185
130 170
110 150 mA
f = fMAX
Capacitance
Parameter
Description
Test Conditions
Max.
10
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
COUT
Note:
10
pF
7. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Document #: 38-06050 Rev. *A
Page 5 of 17
CY7C09269A
CY7C09369A
AC Test Loads
5V
5V
R
TH
= 250Ω
R1 = 893Ω
R2 = 347Ω
OUTPUT
C = 30 pF
OUTPUT
R1 = 893Ω
OUTPUT
C = 5 pF
C = 30 pF
R2 = 347Ω
V
TH
= 1.4V
(b) Thévenin Equivalent (Load 1)
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
AC Test Loads (Applicable to -6 only)[8]
ALL INPUTPULSES
90%
Z = 50
Ω
R = 50Ω
0
OUTPUT
3.0V
GND
90%
10%
C
10%
3 ns
3 ns
≤
V
TH
= 1.4V
≤
(a) Load 1 (-6 only)
0.60
0.50
0.40
0.30
0.20
0. 1 0
0.00
1 0
1 5
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Note:
8. Test Conditions: C = 10 pF.
Document #: 38-06050 Rev. *A
Page 6 of 17
CY7C09269A
CY7C09369A
Switching Characteristics Over the Operating Range
CY7C09269A
CY7C09369A
-6[1]
-7
-9
-12
Parameter
fMAX1
fMAX2
tCYC1
tCYC2
tCH1
tCL1
tCH2
tCL2
tR
Description
fMax Flow-Through
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
53
45
83
40
67
33
50
fMax Pipelined
100
Clock Cycle Time - Flow-Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow-Through
Clock LOW Time - Flow-Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
19
10
6.5
6.5
4
22
12
7.5
7.5
5
25
15
12
12
6
30
20
12
12
8
4
5
6
8
3
3
3
3
3
3
3
3
tF
Clock Fall Time
tSA
Address Set-Up Time
Address Hold Time
3.5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
tHA
tSC
Chip Enable Set-Up Time
Chip Enable Hold Time
R/W Set-Up Time
3.5
0
tHC
tSW
3.5
0
tHW
R/W Hold Time
tSD
Input Data Set-Up Time
Input Data Hold Time
3.5
0
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
ADS Set-Up Time
3.5
0
ADS Hold Time
CNTEN Set-Up Time
3.5
0
CNTEN Hold Time
CNTRST Set-Up Time
CNTRST Hold Time
3.5
0
Output Enable to Data Valid
OE to Low Z
8
9
10
12
[9, 10]
tOLZ
2
1
2
1
2
1
2
1
[9, 10]
tOZ
OE to High Z
7
7
7
20
9
7
tCD1
tCD2
tDC
Clock to Data Valid - Flow-Through
Clock to Data Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
15
6.5
18
7.5
25
12
2
2
2
2
2
2
2
2
2
2
2
2
[9, 10]
tCKHZ
9
9
9
9
[9, 10]
tCKLZ
Port to Port Delays
tCWDD Write Port Clock HIGH to Read Data Delay
tCCS Clock to Clock Set-Up Time
30
9
35
10
40
15
40
15
ns
ns
Notes:
9. Test conditions used are Load 2.
10. This parameter is guaranteed by design, but it is not production tested.
Document #: 38-06050 Rev. *A
Page 7 of 17
CY7C09269A
CY7C09369A
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[11, 12, 13, 14]
t
CYC1
t
t
CL1
CH1
CLK
CE
CE
0
1
t
t
t
t
HC
SC
HC
SC
R/W
t
t
t
t
SW
SA
HW
HA
A
A
A
A
n+3
n
n+1
n+2
ADDRESS
t
CKHZ
t
t
DC
CD1
DATA
OUT
Q
Q
t
Q
n
n+1
n+2
DC
t
t
CKLZ
t
OHZ
OLZ
OE
t
OE
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[11, 12, 13, 14]
t
CYC2
t
t
CL2
CH2
CLK
CE
CE
0
1
t
t
t
t
HC
SC
HC
SC
R/W
t
t
t
t
SW
SA
HW
HA
ADDRESS
A
A
A
A
n+3
n
n+1
n+2
t
1 Latency
t
DC
CD2
DATA
OUT
Q
Q
Q
n+2
n
n+1
t
OHZ
t
t
CKLZ
OLZ
OE
tOE
Notes:
11. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
12. ADS = VIL, CNTEN and CNTRST = VIH
13. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.
14. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
.
Document #: 38-06050 Rev. *A
Page 8 of 17
CY7C09269A
CY7C09369A
Switching Waveforms (continued)
Bank Select Pipelined Read[15, 16]
t
CYC2
t
t
CL2
CH2
CLK
L
t
t
t
HA
SA
ADDRESS
A
A
A
A
A
A
(B1)
3
4
5
0
1
2
t
HC
SC
CE
0(B1)
t
t
t
t
t
t
t
CD2
CD2
CD2
CKHZ
HC
CKHZ
SC
D
D
D
3
DATA
1
0
OUT(B1)
t
t
HA
SA
t
t
t
CKLZ
DC
DC
A
A
A
ADDRESS
A
0
A
A
3
4
5
(B2)
1
2
t
t
HC
SC
CE
0(B2)
t
t
t
CD2
t
CD2
CKHZ
t
SC
HC
DATA
OUT(B2)
D
D
4
2
t
t
CKLZ
CKLZ
Left Port Write to Flow-Through Right Port Read[17, 18, 19, 20]
CLK
R/W
L
L
t
t
HW
SW
t
t
HA
SA
NO
MATCH
ADDRESS
MATCH
VALID
L
t
t
HD
SD
DATA
INL
t
CCS
CLK
R
R
R
t
CD1
t
t
t
t
SW
SA
HW
HA
R/W
NO
MATCH
MATCH
ADDRESS
t
t
CWDD
CD1
DATA
VALID
VALID
OUTR
t
DC
t
DC
Notes:
15. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; each Bank consists of one Cypress dual-port device from this data sheet.
ADDRESS(B1) = ADDRESS(B2)
.
16. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH
.
17. The same waveforms apply for a right port write to flow-through left port read.
18. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH
.
19. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.
20. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
Document #: 38-06050 Rev. *A
Page 9 of 17
CY7C09269A
CY7C09369A
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[14, 21, 22, 23]
t
CYC2
t
t
CL2
CH2
CLK
CE
0
1
t
t
HC
SC
CE
t
t
HW
SW
R/W
t
t
HW
SW
A
A
A
A
A
A
n+4
n
n+1
n+2
n+2
n+3
ADDRESS
t
t
SD HD
t
t
HA
SA
DATA
D
IN
n+2
t
t
t
t
CD2
CD2
CKHZ
CKLZ
Q
Q
n+3
n
DATA
OUT
READ
NO OPERATION
WRITE
READ
Pipelined Read-to-Write-to-Read (OE Controlled)[14, 21, 22, 23]
t
CYC2
t
t
CL2
CH2
CLK
CE
0
1
t
t
HC
SC
CE
t
t
HW
SW
R/W
t
t
HW
SW
A
A
A
A
A
A
n+5
n
n+1
n+2
n+3
n+4
ADDRESS
t
t
HA
t
t
SA
SD HD
D
DATA
D
n+2
IN
n+3
t
t
t
CD2
CD2
CKLZ
DATA
Q
Q
n+4
OUT
n
t
OHZ
OE
READ
WRITE
READ
Notes:
21. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
22. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH
.
23. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document #: 38-06050 Rev. *A
Page 10 of 17
CY7C09269A
CY7C09369A
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[12, 14, 21, 22]
t
CYC1
t
t
CH1
CL1
CLK
CE
CE
0
1
t
t
HC
SC
t
t
HW
SW
R/W
t
t
HW
SW
A
A
A
A
D
A
A
n+4
n
n+1
n+2
n+2
n+3
ADDRESS
t
t
HD
SD
t
t
HA
SA
n+2
DATA
IN
t
t
t
t
CD1
CD1
CD1
CD1
DATA
Q
Q
Q
n+3
OUT
n
n+1
t
t
t
t
DC
DC
CKHZ
CKLZ
NO
OPERATION
READ
WRITE
READ
Flow-Through Read-to-Write-to-Read (OE Controlled)[12, 14, 21, 22]
t
CYC1
t
t
CH1
CL1
CLK
CE
CE
0
1
t
t
HC
SC
t
t
HW
SW
R/W
t
t
HW
SW
A
A
A
A
D
A
A
n+5
n
n+1
n+2
n+3
n+4
ADDRESS
t
t
HD
SD
t
t
HA
SA
D
n+2
n+3
t
DATA
t
OE
IN
DC
t
t
CD1
CD1
t
CD1
Q
Q
n+4
n
DATA
OUT
t
OHZ
t
t
DC
CKLZ
OE
READ
WRITE
READ
Document #: 38-06050 Rev. *A
Page 11 of 17
CY7C09269A
CY7C09369A
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[24]
t
CYC2
t
t
CH2
CL2
CLK
t
t
HA
SA
ADDRESS
A
n
t
t
t
t
SAD
HAD
ADS
t
t
t
t
SAD
HAD
CNTEN
SCN
HCN
SCN
HCN
t
CD2
DATA
OUT
Q
Q
Q
Q
Q
Q
n+3
x-1
x
n
n+1
n+2
t
READ
DC
COUNTER HOLD
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Flow-Through Read with Address Counter Advance[24]
t
CYC1
t
t
CH1
CL1
CLK
t
t
HA
SA
A
n
ADDRESS
t
t
t
SAD
HAD
ADS
t
t
t
t
SAD
HAD
CNTEN
t
SCN
HCN
SCN
HCN
t
CD1
Q
Q
Q
Q
Q
n+3
DATA
x
n
n+1
n+2
OUT
t
DC
READ
READ
WITH
COUNTER HOLD
READ WITH COUNTER
EXTERNAL
ADDRESS
COUNTER
Note:
24. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH
.
Document #: 38-06050 Rev. *A
Page 12 of 17
CY7C09269A
CY7C09369A
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[25, 26]
t
CYC2
t
t
CH2
CL2
CLK
t
t
HA
SA
A
ADDRESS
n
INTERNAL
ADDRESS
A
A
A
A
A
n+4
n
n+1
n+2
n+3
t
t
HAD
SAD
ADS
CNTEN
t
t
HCN
SCN
D
D
D
D
D
D
n+4
DATA
n
n+1
n+1
n+2
n+3
IN
t
t
HD
SD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Notes:
25. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH
.
26. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH
.
Document #: 38-06050 Rev. *A
Page 13 of 17
CY7C09269A
CY7C09369A
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[14, 26, 27, 28]
t
CYC2
t
t
CH2
CL2
CLK
t
t
HA
SA
A
A
ADDRESS
n
n+1
INTERNAL
ADDRESS
A
0
1
A
A
n+1
X
n
t
t
HW
SW
R/W
ADS
t
t
SAD
HAD
t
t
SCN
HCN
CNTEN
t
t
HRST
SRST
CNTRST
t
t
HD
SD
DATA
D
IN
0
DATA
Q
Q
Q
n
OUT
0
1
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Notes:
27. CE0, UB, and LB = VIL; CE1 = VIH
.
28. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Document #: 38-06050 Rev. *A
Page 14 of 17
CY7C09269A
CY7C09369A
Read/Write and Enable Operation[29, 30, 31]
Inputs
Outputs
I/O0–I/O17
High-Z
OE
CLK
CE0
CE1
R/W
Operation
X
H
X
X
Deselected[32]
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z
DIN
Deselected[32]
Write
H
X
DOUT
High-Z
Read[34]
H
X
Outputs Disabled
Address Counter Control Operation[29, 33, 34, 35]
Previous
Address Address CLK ADS CNTEN CNTRST
I/O
Mode
Operation
X
An
X
X
X
X
X
H
L
H
H
Dout(0)
Reset
Counter Reset to Address 0
X
L
Dout(n)
Dout(n)
Load
Hold
Address Load into Counter
An
H
External Address Blocked—Counter
Disabled
X
An
H
L
H
Dout(n+1) Increment Counter Enabled—Internal Address
Generation
Notes:
29. “X” = “Don’t Care,” “H” = VIH, “L” = VIL.
30. ADS, CNTEN, CNTRST = “Don’t Care.”
31. OE is an asynchronous input signal.
32. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
33. CE0 and OE = VIL; CE1 and R/W = VIH
.
34. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
35. Counter operation is independent of CE0 and CE1.
Document #: 38-06050 Rev. *A
Page 15 of 17
CY7C09269A
CY7C09369A
Ordering Information
16K x16 Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
6.5[1]
7.5
9
Ordering Code
CY7C09269A-6AC
CY7C09269A-7AC
CY7C09269A-9AC
CY7C09269A-12AC
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
A100
A100
A100
A100
Commercial
Commercial
Commercial
Commercial
12
16K x18 Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
6.5[1]
7.5
9
Ordering Code
CY7C09369A-6AC
CY7C09369A-7AC
CY7C09369A-9AC
CY7C09369A-12AC
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
A100
A100
A100
A100
Commercial
Commercial
Commercial
Commercial
12
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-B
Document #: 38-06050 Rev. *A
Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C09269A
CY7C09369A
Document Title: CY7C09269A/CY7C09369A 16K x 16/18 Synchronous Dual Port Static RAM
Document Number: 38-06050
Issue
Date
Orig. of
REV.
**
ECN NO.
110202
Change Description of Change
11/11/01
12/27/02
SZV
RBI
Change from Spec number: 38-00836 to 38-06050
Power up requirements added to Maximum Ratings Information
*A
122300
Document #: 38-06050 Rev. *A
Page 17 of 17
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相关型号：
CY7C09369V-6AXC
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