CY7C09369V-12AI [CYPRESS]
Dual-Port SRAM, 16KX18, 12ns, CMOS, PQFP100, PLASTIC, TQFP-100;
| 型号： | CY7C09369V-12AI |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 16KX18, 12ns, CMOS, PQFP100, PLASTIC, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：526K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
51
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
[1]
• High-speed clock to data access 7.5 /9/12 ns (max.)
Features
• 3.3V Low operating power
— Active= 115 mA (typical)
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
— Standby= 10 µA (typical)
• 6 Flow-Through/Pipelined devices
— 16K x 16/18 organization (CY7C09269V/369V)
— 32K x 16/18 organization (CY7C09279V/379V)
— 64K x 16/18 organization (CY7C09289V/389V)
• 3 Modes
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
— Flow-Through
— Pipelined
— Burst
• Pipelinedoutputmodeonboth portsallowsfast83-MHz
operation
• 0.35-micron CMOS for optimum speed/power
Logic Block Diagram
R/W
R/W
UB
L
R
R
UB
L
CE
CE
CE
CE
0L
1L
0R
1R
1
1
0
0
0/1
0/1
LB
LB
L
R
OE
OE
L
R
1b 0b 1a 0a
0a 1a 0b 1b
0/1
0/1
b
a
a
b
FT/Pipe
FT/Pipe
L
R
8/9
8/9
8/9
8/9
[2]
[2]
I/O
–I/O
I/O
–I/O
8/9R 15/17R
8/9L
15/17L
I/O
Control
I/O
Control
[3]
I/O –I/O
I/O –I/O[3]
0R 7/8R
0L
7/8L
14/15/16
14/15/16
A
–A[4]
A
–A[3]
13/14/15R
0L
13/14/15L
0R
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
CLK
CLK
ADS
L
R
R
R
R
True Dual-Ported
RAM Array
ADS
L
CNTEN
CNTEN
CNTRST
L
CNTRST
L
Notes:
1. Call for Availability.
2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
3. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.
4. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 23 1998
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
A HIGH on CE or LOW on CE for one clock cycle will power
Functional Description
0
1
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high speed 3.3V synchronous CMOS 16K, 32K, and 64K x
16/18 dual-port static RAMs. Two ports are provided permit-
ting independent, simultaneous access for reads and writes to
pipelined mode, one cycle is required with CE LOW and CE
0
1
HIGH to reactivate the outputs.
[5]
any location in memory. Registers on control, address, and
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s address strobe
(ADS). When the port’s count enable (CNTEN) is asserted, the
address counter will increment on each LOW to HIGH transi-
tion of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTEN is
deasserted. The counter can address the entire memory array
and will loop back to the start. Counter reset (CNTRST) is used
to reset the burst counter.
data lines allow for minimal set-up and hold times. In pipelined
output mode, data is registered for decreased cycle time.
Clock to data valid t
= 9 ns (pipelined). Flow-through mode
CD2
can also be used to bypass the pipelined output register to
eliminate access latency. In flow-through mode data will be
available t
= 18 ns after the address is clocked into the
CD1
device. Pipelined output or flow-through mode is selected via
the FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW
to HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A9R
A9L
A10L
A11L
A12L
A13L
A14L
A15L
NC
1
2
A10R
A11R
A12R
A13R
A14R
A15R
NC
3
4
5
[Note 6]
[Note 7]
[Note 6]
[Note 7]
6
7
8
NC
9
NC
LBL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
LBR
UBL
CE0L
CE1L
UBR
CE0R
CE1R
CY7C09289V (64K x 16)
CY7C09279V (32K x 16)
CY7C09269V (16K x 16)
CNTRSTL
VCC
CNTRSTR
GND
R/WL
R/WR
OEL
OER
[Note 8]
[Note 8]
FT/PIPEL
GND
FT/PIPER
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O11L
I/O10L
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes:
5. When writing simultaneously to the same location, the final value cannot
be guaranteed.
8. For CY7C09269V and CY7C09279V, pin #18 connected to VCC is pin com-
patible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to
GND is pin compatible to an IDT 5V x16 flow-through device.
6. This pin is NC for CY7C09269V.
7. This pin is NC for CY7C09269V and CY7C09279V.
2
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Pin Configurations (continued)
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
A14L
A15L
LBL
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
A8R
2
A9R
3
A10R
A11R
A12R
A13R
A14R
A15R
LBR
4
5
6
[Note 9]
[Note 9]
7
[Note 10]
[Note 10]
8
UBL
9
CE0L
CE1L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
UBR
CE0R
CE1R
CY7C09389V (64K x 18)
CY7C09379V (32K x 18)
CY7C09369V (16K x 18)
CNTRSTL
R/WL
CNTRSTR
R/WR
OEL
VCC
GND
FT/PIPEL
I/O17L
I/O16L
VSS
60
59
58
57
56
55
OER
FT/PIPER
I/O17R
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O16R
I/O15R
54
53
I/O14R
I/O13R
I/O11L
I/O10L
24
25
52
51
I/O12R
I/O11R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C09269V/79V/89V
CY7C09369V/79V/89V
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-9
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-12
[1]
-7
f
(MHz) (Pipelined)
83
67
9
50
12
MAX2
Max Access Time (ns) (Clock to data,
Pipelined)
7.5
Typical Operating Current I (mA)
155
25
135
20
115
20
CC
Typical Standby Current for I
(Both ports TTL Level)
(mA)
SB1
Typical Standby Current for I
(Both ports CMOS level)
(µA)
10 µA
10 µA
10 µA
SB3
Shaded area contains advance information.
Notes:
9. This pin is NC for CY7C09369V.
10. This pin is NC for CY7C09369V and CY7C09379V.
3
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Pin Definitions
Left Port
–A
Right Port
A –A
0R
Description
Address Inputs (A –A for 32K, A –A for 16K devices).
A
0L
15L
15R
0
14
0
13
ADS
ADS
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
L
R
CE ,CE
CE ,CE
Chip Enable Input. To select either the left or right port, both CE AND CE must be asserted
0 1
0L
1L
0R
1R
to their active states (CE ≤ V and CE ≥ V ).
0
IL
1
IH
CLK
CLK
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
.
L
R
MAX
CNTEN
CNTEN
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
L
R
CNTRST
CNTRST
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
L
R
I/O –I/O
I/O –I/O
Data Bus Input/Output (I/O –I/O for x16 devices).
0 15
0L
17L
0R
17R
LB
LB
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte. (I/O –I/O for x18, I/O –I/O for x16) of the memory array. For read operations both
L
R
0
8
0
7
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
UB
UB
R
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O –I/O ).
L
8/9L
15/17L
OE
OE
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
L
R
R/W
R/W
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
L
R
FT/PIPE
FT/PIPE
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
L
R
GND
NC
Ground Input.
No Connect.
Power Input.
V
CC
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >1100V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current...................................................... >200mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
DC Voltage Applied to
3.3V ± 300 mV
3.3V ± 300 mV
Outputs in High Z State ...........................–0.5V to V +0.5V
CC
DC Input Voltage......................................–0.5V to V +0.5V
CC
Shaded area contains advance information.
4
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Units
[1]
-7
-9
-12
Symbol
Parameter
Min Typ Max Min Typ
Max Min Typ
Max
V
V
V
V
Output HIGH Voltage (V =Min, I =–4.0 mA) 2.4
2.4
2.4
2.2
–10
V
OH
OL
IH
CC
OH
Output LOW Voltage (V =Min, I = +4.0 mA)
0.4
0.8
0.4
0.4
V
CC
OH
Input HIGH Voltage
Input LOW Voltage
2.2
2.2
V
0.8
10
0.8
10
V
IL
I
I
Output Leakage Current
Operating Current (V =Max,
–10
10 –10
275
µA
mA
mA
mA
mA
mA
mA
µA
µA
mA
mA
OZ
Com’l.
Indust.
Com’l.
Indust.
155
25
135
185
20
230
300
75
115
155
20
30
85
95
10
10
75
85
180
250
70
CC
CC
I
=0 mA) Outputs Disabled
OUT
I
I
I
I
Standby Current (Both Ports TTL
85
SB1
SB2
SB3
SB4
[11]
Level)
CE & CE ≥ V , f=f
L R IH MAX
35
85
80
Standby Current (One Port TTL Lev- Com’l.
105
10
165
100
125
95
155
165
100
100
115
125
140
150
100
100
100
110
[11]
el)
CE | CE ≥ V , f=f
L R IH MAX
Indust.
105
10
Standby Current (Both Ports CMOS Com’l.
[11]
Level)
CE & CE ≥ V – 0.2V, f=0
L R CC
Indust.
Com’l.
Indust.
10
Standby Current (One Port CMOS
95
85
[11]
Level)
CE | CE ≥ V , f=f
L R IH MAX
95
Shaded area contains advance information.
Capacitance
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
Input Capacitance
Output Capacitance
10
10
pF
pF
IN
A
V
= 3.3V
CC
OUT
AC Test Loads
3.3V
3.3V
R
TH
= 250
Ω
R1 = 590
Ω
Ω
OUTPUT
C = 30 pF
OUTPUT
R1 = 590
Ω
OUTPUT
C = 5 pF
C = 30 pF
R2 = 435
R2 = 435
Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c)Three-State Delay(Load 2)
(Used for t , t , & t
(b) Thévenin Equivalent (Load 1)
CKLZ OLZ
OHZ
including scope and jig)
ALL INPUTPULSES
3.0V
GND
90%
90%
10%
3 ns
10%
3 ns
≤
≤
Note:
11. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
5
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Switching Characteristics Over the Operating Range
CY7C09269V/79V/89V
CY7C09369V/79V/89V
[1]
-7
-9
-12
Symbol
Parameter
Flow-Through
Min
Max
45
Min
Max
40
Min
Max
33
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
MAX1
MAX2
CYC1
CYC2
CH1
CL1
CH2
CL2
R
Max
Max
Pipelined
83
67
50
Clock Cycle Time - Flow-Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow-Through
Clock LOW Time - Flow-Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
22
12
7.5
7.5
5
25
15
12
12
6
30
20
12
12
8
5
6
8
3
3
3
3
3
3
Clock Fall Time
F
Address Set-Up Time
4
0
4
1
4
1
4
1
4
1
4
1
5
1
4
1
4
1
4
1
4
1
4
1
4
1
5
1
4
1
SA
Address Hold Time
HA
Chip Enable Set-Up Time
Chip Enable Hold Time
R/W Set-Up Time
4
SC
0
HC
4
SW
R/W Hold Time
0
HW
Input Data Set-Up Time
Input Data Hold Time
4
SD
0
HD
ADS Set-Up Time
4
SAD
HAD
SCN
HCN
SRST
HRST
ADS Hold Time
0
CNTEN Set-Up Time
4.5
0
CNTEN Hold Time
CNTRST Set-Up Time
CNTRST Hold Time
4
0
Output Enable to Data Valid
OE to Low Z
9
10
12
OE
[12,13]
2
1
2
1
2
1
OLZ
[12,13]
OHZ
OE to High Z
7
7
20
9
7
Clock to Data Valid - Flow-Through
Clock to Data Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
18
7.5
25
12
CD1
CD2
DC
2
2
2
2
2
2
2
2
2
[12,13]
9
9
9
CKZ
[12,13]
CKZ
Port to Port Delays
t
t
Write Port Clock HIGH to Read Data Delay
Clock to Clock Set-Up Time
35
10
40
15
40
15
ns
ns
CWDD
CCS
Shaded area contains advance information.
Notes:
12. Test conditions used are Load 2.
13. This parameter is guaranteed by design, but it is not production tested.
6
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V )
[14,15,16,17]
IL
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSC
tHC
CE1
R/W
tSW
tSA
tHW
tHA
An
An+1
An+2
An+3
ADDRESS
DATAOUT
tCKHZ
Qn+2
tDC
tDC
Qn
tCD1
Qn+1
tCKLZ
tOHZ
tOLZ
OE
tOE
[14,15,16,17]
Read Cycle for Pipelined Operation (FT/PIPE = V )
IH
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
tSC
tHC
CE1
R/W
tSW
tSA
tHW
tHA
ADDRESS
DATAOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
tOHZ
Qn+2
tCKLZ
tOLZ
OE
tOE
Notes:
14. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
15. ADS = VIL, CNTEN and CNTRST = VIH
16. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.
.
17. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
7
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Switching Waveforms (continued)
[18,19]
Bank Select Pipelined Read
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
A3
ADDRESS(B1)
A4
A5
A0
A1
A2
tHC
tSC
CE0(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
D0
D3
D1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE0(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
D4
D2
tCKLZ
tCKLZ
[20,21,22,23]
Left Port Write to Flow-Through Right Port Read
CLKL
tHW
tSW
R/WL
tHA
tSA
NO
MATCH
ADDRESSL
MATCH
tHD
tSD
VALID
tCCS
DATAINL
CLKR
R/WR
tCD1
tSW tHW
tSA tHA
NO
MATCH
MATCH
ADDRESSR
tCWDD
tCD1
DATAOUTR
VALID
VALID
tDC
tDC
Notes:
18. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
ADDRESS(B1) = ADDRESS(B2)
.
19. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH
.
20. The same waveforms apply for a right port write to flow-through left port read.
21. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH
.
22. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
23. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
8
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = V )
[17,24,25,26]
IL
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD tHD
tSA
tHA
Dn+2
tCD2
tCD2
tCKHZ
tCKLZ
Qn
Qn+3
DATAOUT
READ
NO OPERATION
[17,24,25,26]
WRITE
READ
Pipelined Read-to-Write-to-Read (OE Controlled)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tHW
tSW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSA
tHA
tSD tHD
Dn+2
Dn+3
tCD2
tCKLZ
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Notes:
24. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
25. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH
.
26. During “No operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
9
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = V )
[15,17,25,26]
IL
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
tCD1
tCD1
tCD1
tCD1
DATAOUT
Qn
tDC
Qn+1
tCKHZ
Qn+3
tCKLZ
tDC
NO
OPERATION
READ
WRITE
READ
[15,17,24,25,26]
Flow-Through Read-to-Write-to-Read (OE Controlled)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
Dn+3
tOE
tCD1
tDC
tCD1
tCD1
Qn
Qn+4
tDC
DATAOUT
OE
tOHZ
tCKLZ
READ
WRITE
READ
10
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance
[27]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
DATAOUT
Qx-1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
Qn+3
READ
READ WITH COUNTER
[27]
READ WITH COUNTER
EXTERNAL
ADDRESS
Flow-Through Read with Address Counter Advance
tCYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD1
Qx
tDC
Qn
Qn+1
Qn+2
Qn+3
DATAOUT
READ
READ
COUNTER HOLD
READ WITH COUNTER
EXTERNAL
ADDRESS
WITH
COUNTER
Note:
27. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH
.
11
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)
[28,29]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Notes:
28. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH
.
29. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH
.
12
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Switching Waveforms (continued)
[17,24,30,31]
Counter Reset (Pipelined Outputs)
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
An+1
ADDRESS
INTERNAL
ADDRESS
AX
0
1
An
An+1
tSW tHW
R/W
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSRST
tHRST
CNTRST
DATAIN
tSD tHD
D0
DATAOUT
Q0
Q1
Qn
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Notes:
30. CE0, UB, and LB = VIL; CE1 = VIH
.
31. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
13
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Read/Write and Enable Operation[32,33,34]
Inputs
Outputs
I/O –I/O
17
OE
CLK
CE
CE
R/W
Operation
0
1
0
[35]
X
H
X
X
High-Z
Deselected
[35]
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z
Deselected
Write
D
IN
[35]
H
X
D
Read
OUT
H
X
High-Z
Outputs Disabled
Address Counter Control Operation[32,36,37,38]
Previous
Address Address CLK ADS CNTEN CNTRST
I/O
Mode
Operation
X
X
X
X
X
H
L
H
H
D
D
D
Reset
Counter Reset to Address 0
out(0)
A
X
L
Load
Hold
Address Load into Counter
n
out(n)
out(n)
X
X
A
H
External Address Blocked—Counter
Disabled
n
n
A
H
L
H
D
Increment Counter Enabled—Internal Address
Generation
out(n+1)
Notes:
32. “X” = Don’t Care, “H” = VIH, “L” = VIL
.
33. ADS, CNTEN, CNTRST = Don’t Care.
34. OE is an asynchronous input signal.
35. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
36. CE0 and OE = VIL; CE1 and R/W = VIH
.
37. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
38. Counter operation is independent of CE0 and CE1.
14
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Ordering Information
16K x16 3.3V Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
CY7C09269V–7AC
CY7C09269V–9AC
CY7C09269V–9AI
CY7C09269V–12AC
CY7C09269V–12AI
Package Type
Range
Commercial
Commercial
Industrial
[1]
7.5
A100
A100
A100
A100
A100
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
9
12
Commercial
Industrial
Shaded area contains advance information.
32K x16 3.3V Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C09279V–7AC
CY7C09279V–9AC
CY7C09279V–9AI
CY7C09279V–12AC
CY7C09279V–12AI
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1]
7.5
A100
A100
A100
A100
A100
Commercial
Commercial
Industrial
9
12
Commercial
Industrial
Shaded area contains advance information.
64K x16 3.3V Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C09289V–7AC
CY7C09289V–9AC
CY7C09289V–9AI
CY7C09289V–12AC
CY7C09289V–12AI
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1]
7.5
A100
A100
A100
A100
A100
Commercial
Commercial
Industrial
9
12
Commercial
Industrial
Shaded area contains advance information.
16K x18 3.3V Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C09369V–7AC
CY7C09369V–9AC
CY7C09369V–9AI
CY7C09369V–12AC
CY7C09369V–12AI
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1]
7.5
A100
A100
A100
A100
A100
Commercial
Commercial
Industrial
9
12
Commercial
Industrial
Shaded area contains advance information.
32K x18 3.3V Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C09379V–7AC
CY7C09379V–9AC
CY7C09379V–9AI
CY7C09379V–12AC
CY7C09379V–12AI
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1]
7.5
A100
A100
A100
A100
A100
Commercial
Commercial
Industrial
9
12
Commercial
Industrial
Shaded area contains advance information.
15
CY7C09269V/79V/89V
CY7C09369V/79V/89V
PRELIMINARY
Ordering Information (continued)
64K x18 3.3V Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
CY7C09389V–7AC
CY7C09389V–9AC
CY7C09389V–9AI
CY7C09389V–12AC
CY7C09389V–12AI
Package Type
100-Pin Thin Quad Flat Pack
Range
Commercial
Commercial
Industrial
[1]
7.5
A100
A100
A100
A100
A100
9
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
12
Commercial
Industrial
Shaded area contains advance information.
Document #: 38–00668–D
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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