CY7C0852AV-167AC [CYPRESS]
FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM; FLEx36TM 3.3V 32K / 64K / 128K / 256K ×36同步双端口RAM
| 型号： | CY7C0852AV-167AC |
| 厂家： | 
CYPRESS |
| 描述： | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| 文件： | 总31页 (文件大小：830K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K
Synchronous Dual-Port RAM
x 36 and 128K/256K x 18
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
TM
FLEx36 3.3V 32K/64K/128K/256K x 36
Synchronous Dual-Port RAM
Functional Description
Features
• True dual-ported memory cells that allow simultaneous
The FLEx36™ family includes 1M, 2M, 4M and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address,
and data lines allow for minimal set-up and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
access of the same memory location
• Synchronous pipelined operation
• Organization of 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit
devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 172-ball FBGA (1 mm pitch) (15 mm × 15 mm)
• 176-pin TQFP (24 mm × 24 mm × 1.4 mm)
• Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
The CY7C0853A device in this family has limited features.
Please see See “Address Counter and Mask Register
Operations[10]” on page 8. for details.
• Dual Chip Enables on both ports for easy depth
expansion
Table 1. Product Selection Guide
1-Mbit
2-Mbit
4-Mbit
9-Mbit
Density
(32K x 36)
CY7C0850AV
167
(64K x 36)
(128K x 36)
(256K x 36)
Part Number
Max. Speed (MHz)
CY7C0851AV
CY7C0852AV
CY7C0853AV
167
4.0
225
167
4.0
225
133
4.7
270
Max. Access Time - Clock to Data (ns)
Typical operating current (mA)
Package
4.0
225
176TQFP
176TQFP
176TQFP
172FBGA
172FBGA
172FBGA
172FBGA
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document #: 38-06070 Rev. *G
Revised August 15, 2005
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Logic Block Diagram[1]
OE
OE
R/W
L
R
R
R/W
L
B0
B1
B2
B3
B0
B1
B2
B3
L
L
L
L
R
R
R
R
CE
CE
CE
CE
0L
1L
0R
1R
9
9
9
9
DQ –DQ
DQ –DQ
27R
DQ –DQ
18R
DQ –DQ
9R
DQ –DQ
0R 8R
27L
35L
26L
35R
26R
17R
DQ –DQ
18L
I/O
I/O
9
9
9
9
DQ –DQ
Control
Control
9L
17L
DQ –DQ
0L
8L
Addr.
Read
Back
Addr.
Read
Back
True
Dual-Ported
RAM Array
18
18
A0L–A17L
CNT/MSKL
ADSL
A0R–A17R
CNT/MSKR
Mask Register
Mask Register
ADS
CNTEN
Counter/
Address
Register
Counter/
Address
Register
Address
Decode
Address
Decode
CNTENL
CNTRSTR
CLKR
CNTINTR
CNTRSTL
CLKL
CNTINTL
Mirror Reg
Mirror Reg
TMS
TDI
TCK
Reset
Logic
Interrupt
Logic
Interrupt
Logic
JTAG
TDO
MRST
INTL
INTR
Note:
1. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits.
Document #: 38-06070 Rev. *G
Page 2 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Pin Configurations
172-ball BGA
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DQ32L
DQ30L
CNTINTL
VSS
DQ13L
VDD
DQ11L
DQ11R
VDD
DQ13R
VSS
CNTINTR
DQ30R
DQ32R
A
B
C
D
E
F
A0L
NC
DQ33L
A1L
DQ29L
DQ31L
DQ35L
CE1L
A7L
DQ17L
DQ27L
DQ34L
B0L
DQ14L
INTL
DQ12L
DQ15L
DQ16L
VSS
DQ9L
DQ10L
VSS
DQ9R
DQ10R
VSS
DQ12R
DQ15R
DQ16R
VDD
DQ14R
INTR
DQ17R
DQ27R
DQ34R
B0R
DQ29R
DQ31R
DQ35R
CE1R
A7R
DQ33R
A1R
A0R
NC
A2L
A3L
DQ28L
VDD
DQ28R
VDD
A3R
A2R
A4L
A5L
A5R
A4R
VDD
A6L
B1L
VDD
VSS
B1R
A6R
VDD
CY7C0850V
CY7C0851V
CY7C0852V
OEL
B2L
B3L
CE0L
CE0R
CLKR
ADSR
B3R
B2R
OER
G
H
J
VSS
R/WL
A10L
A12L
A13L
A14L
DQ20L
DQ21L
A8L
CLKL
A8R
R/WR
A10R
A12R
A13R
A14R
DQ20R
DQ21R
VSS
A9L
VSS
ADSL
CNTRSTL
DQ26L
DQ18L
DQ6L
VSS
VSS
VDD
VDD
VDD
MRST
[2]
A9R
[2]
A11L
CNT/MSKL
A15L
VDD
DQ19L
DQ7L
DQ3L
VDD
VSS
DQ19R
DQ7R
DQ3R
VDD
CNTRSTR A15R
A11R
CNT/MSKR
K
L
CNTENL
DQ22L
DQ8L
DQ25L
TDI
VSS
DQ2L
DQ0L
DQ1L
VSS
DQ25R
TCK
DQ26R
DQ18R
DQ6R
VSS
CNTENR
[2]
[2]
A16L
DQ2R
DQ0R
DQ1R
DQ22R
DQ8R
TMS
A16R
M
N
P
DQ24L
DQ23L
DQ5L
DQ4L
DQ5R
DQ4R
DQ24R
DQ23R
TDO
Note:
2. For CY7C0851V, pins M1 and M14 are NC. For CY7C0850V, pins K3, K12 M1, and M14 are NC
Document #: 38-06070 Rev. *G
Page 3 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Pin Configurations (continued)
172-ball BGA
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DQ32L
DQ30L
NC
VSS
DQ13L
VDD
DQ12L
DQ15L
DQ16L
VSS
DQ11L
DQ11R
VDD
DQ13R
VSS
NC
DQ30R DQ32R
A
B
C
D
E
F
A0L
A17L
A2L
DQ33L
A1L
DQ29L
DQ31L
DQ35L
VDD
DQ17L
DQ27L
DQ34L
B0L
DQ14L
INTL
DQ9L
DQ10L
VSS
DQ9R
DQ12R DQ14R DQ17R DQ29R DQ33R
A0R
A17R
A2R
DQ10R DQ15R
INTR
DQ27R DQ31R
A1R
A3R
A3L
DQ28L
VDD
VSS
DQ16R DQ28R DQ34R DQ35R
A4L
A5L
VDD
VDD
VSS
B0R
B1R
VDD
A7R
A5R
A4R
VDD
OEL
A6L
A7L
B1L
VDD
A6R
VDD
OER
VSS
A9R
CY7C0853V
B2L
B3L
VSS
VSS
CLKR
VSS
VDD
B3R
B2R
G
H
J
VSS
R/WL
A10L
A12L
A13L
A14L
DQ20L
DQ21L
A8L
CLKL
VSS
A8R
R/WR
A10R
A12R
A13R
A14R
A9L
VSS
VSS
VDD
VDD
VDD
MRST
A15R
VSS
A11L
VDD
A16L
DQ24L
DQ23L
A15L
VSS
VDD
VDD
DQ19L
DQ7L
DQ3L
VDD
VSS
A11R
VDD
A16R
K
L
DQ26L
DQ18L
DQ6L
VSS
DQ25L
TDI
VSS
DQ2L
DQ0L
DQ1L
VSS
DQ19R DQ25R DQ26R
DQ22L
DQ8L
TDO
DQ2R
DQ0R
DQ1R
DQ7R
DQ3R
VDD
TCK
DQ18R DQ22R
M
N
P
DQ5L
DQ4L
DQ5R
DQ4R
DQ6R
VSS
DQ8R
TMS
DQ20R DQ24R
DQ21R DQ23R
Document #: 38-06070 Rev. *G
Page 4 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Pin Configurations (continued)
176-pin Thin Quad Flat Pack (TQFP)
Top View
DQ
DQ
NC
34R
35R
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
1
2
3
4
5
6
7
8
9
DQ
DQ
NC
34L
35L
A
0R
A
0L
A
1R
A
1L
A
2R
A
2L
A
V
3R
SS
A
V
3L
SS
V
DD
V
DD
A
A
A
A
4R
5R
6R
7R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A
A
A
A
4L
5L
6L
7L
B
B
0R
1R
B
0L
B
1L
CE
1R
CE
1L
B
B
2R
3R
B
2L
B
3L
OE
CE
R
OE
CE
L
0R
CY7C0850V
CY7C0851V
CY7C0852V
0L
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
R/W
CLK
MRST
ADS
CNTEN
R
R
R/W
CLK
L
L
V
SS
R
ADS
L
R
CNTEN
L
CNTRST
CNT/MSK
R
CNTRST
CNT/MSK
L
R
L
A
A
8R
A
A
8L
9R
9L
A
A
A
10R
11R
12R
A
A
A
10L
11L
12L
98
97
96
95
94
93
92
91
V
SS
V
V
A
SS
DD
13L
V
A
DD
13R
A
14R
A
A
A
14L
15L
16L
[2]
[2]
A
A
[2]
[2]
15R
16R
DQ
DQ
24R
20R
90
89
DQ
DQ
24L
20L
Document #: 38-06070 Rev. *G
Page 5 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Pin Definitions
Left Port
A0L–A17L
ADSL
Right Port
Description
[1]
[1]
A0R–A17R
Address Inputs.
[3]
[3]
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW
for the part using the externally supplied address on the address pins and for loading this
address into the burst address counter.
[3]
[3]
CE0L
CE0R
Active LOW Chip Enable Input.
[3]
[3]
CE1L
CE1R
Active HIGH Chip Enable Input.
CLKL
CNTENL
CLKR
CNTENR
Clock Signal. Maximum clock input rate is fMAX.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of
its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST
are asserted LOW.
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access
to the mask register. When tied HIGH, the mask register is not accessible and the address
counter operations are enabled based on the status of the counter control signals.
[3]
[3]
[3]
[3]
CNTRSTL
CNTRSTR
[3]
[3]
CNT/MSKL
CNT/MSKR
DQ0L–DQ35L
OEL
DQ0R–DQ35R
OER
Data Bus Input/Output.
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
[3]
[3]
CNTINTL
CNTINTR
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the
counter is incremented to all “1s.”
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
B0L–B3L
MRST
B0R–B3R
Byte Select Inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation
is required at power-up.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
TCK
TDO
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS
VDD
Ground Inputs.
Power Inputs.
Note:
3. These pins are not available for CY7C0853AV device.
Document #: 38-06070 Rev. *G
Page 6 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
shows that in order to set the INTR flag, a Write operation by
the left port to address 3FFFF will assert INTR LOW. At least
one byte has to be active for a Write to generate an interrupt.
A valid Read of the 3FFFF location by the right port will reset
INTR HIGH. At least one byte has to be active in order for a
Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to
is asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the contents of the mailbox. The interrupt flag
is set in a flow-thru mode (i.e., it follows the clock edge of the
writing port). Also, the flag is reset in a flow-thru mode (i.e., it
follows the clock edge of the reading port).
Master Reset
The FLEx36 family devices undergo a complete reset by
taking its MRST input LOW. The MRST input can switch
asynchronously to the clocks. The MRST initializes the
internal burst counters to zero, and the counter mask registers
to all ones (completely unmasked). The MRST also forces the
Mailbox Interrupt (INT) flags and the Counter Interrupt
(CNTINT) flags HIGH. The MRST must be performed on the
FLEx36 family devices after power-up.
Mailbox Interrupts
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CY7C0853AV.
The highest memory location, 3FFFF is the mailbox for the
right port and 3FFFE is the mailbox for the left port. Table 2
Table 2. Interrupt Operation Example[1, 4, 5, 6, 7]
Left Port
Right Port
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
R/WL
CEL
L
X
X
L
A0L–17L
3FFFF
X
INTL
X
X
L
H
R/WR
CER
X
L
L
X
A0R–17R
X
3FFFF
3FFFE
X
INTR
L
H
X
X
L
X
X
H
X
H
L
X
Reset Left INTL Flag
3FFFE
X
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)[8, 9]
CLK MRST CNT/MSK
CNTRST
ADS
CNTEN
Operation
Description
X
L
X
X
X
X
Master Reset
Reset address counter to all 0s and mask
register to all 1s.
H
H
H
H
L
X
L
X
L
Counter Reset
Counter Load
Reset counter unmasked portion to all 0s.
H
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter Readback Read out counter internal value on address
lines.
H
H
H
H
H
H
H
H
L
Counter Increment Internally increment address counter value.
H
Counter Hold
Constantly hold the address value for
multiple clock cycles.
H
H
L
L
L
X
L
X
L
Mask Reset
Mask Load
Reset mask register to all 1s.
H
Load mask register with value presented on
the address lines.
H
H
L
L
H
H
L
H
X
Mask Readback
Reserved
Read out mask register value on address
lines.
Operation undefined
H
Notes:
4. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK
0
1
and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
5. OE is “Don’t Care” for mailbox operation.
6. At least one of B0, B1, B2, or B3 must be LOW.
7. A16x is a NC for CY7C0851AV, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850AV, therefore the Interrupt Addresses
are 7FFF and 6FFF.
8. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
9. Counter operation and mask register operation is independent of chip enables.
Document #: 38-06070 Rev. *G
Page 7 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Counter Load Operation
Address Counter and Mask Register
Operations[10]
This section describes the features only apply to
CY7C0850AV/CY7C0851AV/CY7C0852AV devices, but not
to the CY7C0853AV device. Each port of these devices has a
programmable burst address counter. The burst counter
contains three registers: a counter register, a mask register,
and a mirror register.
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. Readback is pipelined; the address will be
valid tCA2 after the next rising edge of the port’s clock. If
address readback occurs while the port is enabled (CE0 LOW
and CE1 HIGH), the data lines (DQs) will be three-stated.
Figure 1 shows a block diagram of the operation.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
Counter Increment Operation
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load operation, and by the
MRST.
Table 3 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Table 3
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap.
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incre-
mented. The corresponding bit in the mask register must be
a “1” for a counter bit to change. The counter register is incre-
mented by 1 if the least significant bit is unmasked, and by 2
if it is masked. If all unmasked bits are “1,” the next increment
will wrap the counter back to the initially loaded value. If an
Increment results in all the unmasked bits of the counter being
“1s,” a counter interrupt flag (CNTINT) is asserted. The next
Increment will return the counter register to its initial value,
which was stored in the mirror register. The counter address
can instead be forced to loop to 00000 by externally
connecting CNTINT to CNTRST.[11] An increment that results
in one or more of the unmasked bits of the counter being “0”
will deassert the counter interrupt flag. The example in
Figure 2 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the
LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 1FFFFh. Setting the mask
register to this value allows the counter to access the entire
memory space. The address counter is then loaded with an
initial value of 8h. The base address bits (in this case, the 6th
address through the 16th address) are loaded with an address
value but do not increment once the counter is configured for
increment operation. The counter address will start at address
8h. The counter will increment its internal address value till it
reaches the mask register value of 3Fh. The counter wraps
around the memory block to location 8h at the next count.
CNTINT is issued when the counter reaches its maximum
value.
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Counter Reset Operation
All unmasked bits of the counter are reset to “0.” All masked
bits remain unchanged. The mirror register is loaded with the
value of the burst counter. A Mask Reset followed by a Counter
Reset will reset the counter and mirror registers to 00000, as
will master reset (MRST).
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset
and Mask Load operations, and by MRST.
Notes:
10. This section describes the CY7C0852V, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851V has 16 address bits, register
lengths of 16 bits, and a maximum address value of FFFF. The CY7C0850V has 15 address bits, register lengths of 15 bits, and a maximum address value of 7FFF
11. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document #: 38-06070 Rev. *G
Page 8 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Retransmit
operations. Permitted values are of the form 2n – 1 or 2n – 2.
From the most significant bit to the least significant bit,
permitted values have zero or more “0s,” one or more “1s,” or
one “0.” Thus 1FFFF, 003FE, and 00001 are permitted values,
but 1F0FF, 003FC, and 00000 are not.
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1
shows a block diagram of the operation.
Counting by Two
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit
of the counter. Master reset (MRST) also resets the mask
register to all “1s.”
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
CY7C0850AV/CY7C0851AV/CY7C0852AV as a 72-bit single
port SRAM in which the counter of one port counts even
addresses and the counter of the other port counts odd
addresses. This even-odd address scheme stores one half of
the 72-bit data in even memory locations, and the other half in
odd memory locations.
Mask Load Operation
The mask register is loaded with the address value presented
at the address lines. Not all values permit correct increment
Document #: 38-06070 Rev. *G
Page 9 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
CNT/MSK
CNTEN
ADS
Decode
Logic
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
CLK
Load/Increment
17
17
From
Address
Lines
Mirror
Counter
To Readback
and Address
Decode
1
0
1
0
From
Increment
Logic
Mask
17
Wrap
Register
17
17
17
Bit 0
From
Mask
From
Counter
+1
+2
Wrap
Wrap
To
1
0
Detect
17
1
0
Counter
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
Document #: 38-06070 Rev. *G
Page 10 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
CNTINT
H
Example:
Load
Counter-Mask
Register = 3F
0
0
0s
0
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Unmasked Address
Mask
Register
bit-0
Masked Address
Load
Address
Counter = 8
H
L
X
X
Xs
Xs
Xs
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Address
Counter
bit-0
Max
Address
Register
X
X
X
1
1
1
1 1
1
216 215
26 25 24 23 22 21 20
Max + 1
Address
Register
H
X
X
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[1, 12]
IEEE 1149.1 Serial Boundary Scan (JTAG)[13]
devices, and may be performed while the devices are
operating. An MRST must be performed on the devices after
power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the devices in a scan
test. Therefore the tester should be configured to never enter
the PAUSE-DR state.
The CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV
incorporates an IEEE 1149.1 serial boundary scan test access
port (TAP). The TAP controller functions in a manner that does
not conflict with the operation of other devices using
1149.1-compliant TAPs. The TAP operates using
JEDEC-standard 3.3V I/O logic levels. It is composed of three
input connections and one output connection required by the
test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
Table 4. Identification Register Definitions
Instruction Field
Revision Number (31:28)
Cypress Device ID (27:12)
Value
Description
0h
Reserved for version number.
C001h
C002h
C092h
034h
1
Defines Cypress part number for the CY7C0851AV
Defines Cypress part number for the CY7C0852AV and CY7C0853AV
Defines Cypress part number for the CY7C0850AV
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Notes:
12. The “X” in this diagram represents the counter upper bits.
13. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance
Document #: 38-06070 Rev. *G
Page 11 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Table 5. Scan Registers Sizes
Register Name
Bit Size
Instruction
4
Bypass
1
Identification
Boundary Scan
32
n[14]
Table 6. Instruction Identification Codes
Instruction
EXTEST
BYPASS
IDCODE
HIGHZ
Code
Description
0000
1111
1011
0111
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all CY7C0851AV/CY7C0852AV/
CY7C0853AV output drivers to a High-Z state.
CLAMP
0100
Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD 1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
NBSRST
1100
RESERVED
All other codes Other combinations are reserved. Do not use other than the above.
Note:
14. See details in the device BSDL files.
Document #: 38-06070 Rev. *G
Page 12 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
DC Input Voltage .............................. –0.5V to VDD + 0.5V[16]
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings[15]
(Above which the useful life may be impaired. For user guide-
Static Discharge Voltage...........................................> 2000V
lines, not tested.)
(JEDEC JESD22-A114-2000B)
Storage Temperature ................................ –65°C to + 150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground Potential.............. –0.5V to + 4.6V
Range
Commercial
Industrial
Ambient Temperature
VDD
3.3V ± 165 mV
3.3V ± 165 mV
DC Voltage Applied to
0°C to +70°C
–40°C to +85°C
Outputs in High-Z State..........................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range
-167
-133
-100
Parameter
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH
Output HIGH Voltage
2.4
2.4
2.4
V
(VDD = Min., IOH= –4.0 mA)
VOL
Output LOW Voltage
0.4
0.4
0.4
V
(VDD = Min., IOL= +4.0 mA)
VIH
VIL
IOZ
IIX1
IIX2
ICC
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Input Leakage Current Except TDI, TMS, MRST –10
Input Leakage Current TDI, TMS, MRST –0.1
Operating Current for
(VDD = Max.,IOUT = 0 mA),
Outputs Disabled
2.0
2.0
2.0
V
V
µA
µA
0.8
10
10
0.8
0.8
10
10
–10
–10
–10
10 –10
10 –10
1.0 –0.1
1.0 –0.1
225 300
1.0 mA
mA
CY7C0850AV
225 300
CY7C0851AV
CY7C0852AV
CY7C0853AV
Standby Current (Both Ports TTL Level)
270 400
90 115
200 310
90 115 mA
[18]
ISB1
90
160 210
55 75
160 210
115
CEL and CER ≥ VIH, f = fMAX
[18]
ISB2
Standby Current (One Port TTL Level)
160 210
55 75
160 210
70 100
160 210 mA
55 75 mA
160 210 mA
CEL | CER ≥ VIH, f = fMAX
[18]
ISB3
Standby Current (Both Ports CMOS Level)
CEL and CER ≥ VDD – 0.2V, f = 0
[18]
ISB4
Standby Current (One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
ISB5
Operating Current
CY7C0853AV
70
100 mA
(VDD = Max, IOUT = 0 mA, f = 0)
Outputs Disabled
Capacitance [17]
Part Number
Parameter
Description
Input Capacitance
Output Capacitance
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
pF
pF
pF
CY7C0850AV/7C0851AV CIN
TA = 25°C, f = 1 MHz,
13
10
22
20
/CY7C0852AV
VDD = 3.3V
COUT
CIN
COUT
CY7C0853AV
Note:
15. The voltage on any input or I/O pin can not exceed the power pin during power-up.
16. Pulse width < 20 ns.
17. C
also references C
.
OUT
SB1 SB2 SB3
I/O
18. I
, I
, I
and I
are not applicable for CY7C0853AV because it can not be powered down by using chip enable pins.
SB4
Document #: 38-06070 Rev. *G
Page 13 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
AC Test Load and Waveforms
3.3V
Z0 = 50Ω
R = 50Ω
OUTPUT
R1 = 590 Ω
OUTPUT
C = 10 pF
C = 5 pF
R2 = 435 Ω
VTH = 1.5V
(a) Normal Load (Load 1)
(b) Three-state Delay (Load 2)
3.0V
90%
10%
90%
10%
ALL INPUT PULSES
VSS
< 2 ns
< 2 ns
Switching Characteristics Over the Operating Range
-167
-133
-100
CY7C0850AV CY7C0850AV
CY7C0851AV CY7C0851AV
CY7C0852AV CY7C0852AV CY7C0853AV CY7C0853AV
Parameter
fMAX2
tCYC2
Description
Maximum Operating Frequency
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Min.
Max.
167
Min.
Max.
133
Min.
Max.
133
Min.
Max. Unit
100
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.0
2.7
2.7
7.5
3.0
3.0
7.5
3.0
3.0
10.0
4.0
4.0
tCH2
tCL2
[19]
tR
tF
Clock Rise Time
Clock Fall Time
2.0
2.0
2.0
2.0
2.0
2.0
3.0
3.0
[19]
tSA
tHA
tSB
tHB
tSC
tHC
tSW
tHW
tSD
Address Set-up Time
Address Hold Time
Byte Select Set-up Time
Byte Select Hold Time
Chip Enable Set-up Time
Chip Enable Hold Time
R/W Set-up Time
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
NA
NA
2.5
0.6
2.5
0.6
NA
NA
NA
NA
NA
NA
NA
NA
3.0
0.6
3.0
0.6
NA
NA
3.0
0.6
3.0
0.6
NA
NA
NA
NA
NA
NA
NA
NA
R/W Hold Time
Input Data Set-up Time
Input Data Hold Time
ADS Set-up Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tSCM
ADS Hold Time
CNTEN Set-up Time
CNTEN Hold Time
CNTRST Set-up Time
CNTRST Hold Time
CNT/MSK Set-up Time
CNT/MSK Hold Time
tHCM
Note:
19. Except JTAG signals (t and t < 10 ns [max.]).
r
f
Document #: 38-06070 Rev. *G
Page 14 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Characteristics Over the Operating Range (continued)
-167
-133
-100
CY7C0850AV CY7C0850AV
CY7C0851AV CY7C0851AV
CY7C0852AV CY7C0852AV CY7C0853AV CY7C0853AV
Parameter
Description
Output Enable to Data Valid
OE to Low Z
OE to High Z
Clock to Data Valid
Clock to Counter Address Valid
Clock to Mask Register Readback Valid
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Clock to INT Set Time
Clock to INT Reset Time
Clock to CNTINT Set Time
Clock to CNTINT Reset time
Min.
Max.
4.0
Min.
Max.
4.4
Min.
Max.
4.7
Min.
Max. Unit
tOE
tOLZ
tOHZ
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[20, 21]
0
0
0
0
0
0
0
0
[20, 21]
4.0
4.0
4.0
4.0
4.4
4.4
4.4
4.4
4.7
4.7
NA
NA
5.0
5.0
NA
NA
tCD2
tCA2
tCM2
tDC
tCKHZ
tCKLZ
1.0
0
1.0
0
1.0
0
1.0
0
[20, 21]
4.0
4.0
6.7
6.7
5.0
5.0
4.4
4.4
7.5
7.5
5.7
5.7
4.7
4.7
7.5
7.5
NA
NA
5.0
5.0
10
[20, 21]
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
NA
NA
1.0
0.5
0.5
NA
NA
tSINT
tRINT
tSCINT
tRCINT
10
NA
NA
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
6.0
8.0
ns
Master Reset Timing
tRS
tRSS
tRSR
tRSF
Master Reset Pulse Width
Master Reset Set-up Time
Master Reset Recovery Time
Master Reset to Outputs Inactive
7.0
6.0
6.0
7.5
6.0
7.5
7.5
6.0
7.5
10.0
8.5
10.0
ns
ns
ns
ns
ns
10.0
10.0
10.0
10.0
10.0
NA
10.0
NA
tRSCNTINT
Master Reset to Counter Interrupt Flag
Reset Time
Notes:
20. This parameter is guaranteed by design, but it is not production tested.
21. Test conditions used are Load 2.
Document #: 38-06070 Rev. *G
Page 15 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
JTAG Timing
167/133/100
Parameter
Description
Maximum JTAG TAP Controller Frequency
Min.
Max.
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
fJTAG
tTCYC
tTH
TCK Clock Cycle Time
TCK Clock HIGH Time
TCK Clock LOW Time
100
40
40
10
10
10
10
tTL
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
TMS Set-up to TCK Clock Rise
TMS Hold After TCK Clock Rise
TDI Set-up to TCK Clock Rise
TDI Hold After TCK Clock Rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
30
ns
ns
0
JTAG Switching Waveform
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Document #: 38-06070 Rev. *G
Page 16 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms
Master Reset
MRST
tRS
tRSF
ALL
ADDRESS/
DATA
tRSS
INACTIVE
LINES
tRSR
ALL
OTHER
INPUTS
ACTIVE
TMS
CNTINT
INT
TDO
Read Cycle[4, 22, 23, 24, 25]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
B0–B3
R/W
tSW
tSA
tHW
tHA
ADDRESS
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
DATAOUT
Qn
Qn+1
Qn+2
tOHZ
tCKLZ
tOLZ
OE
t
OE
Notes:
22. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
23. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
24. The output is disabled (high-impedance state) by CE = V following the next rising edge of the clock.
IH
25. Addresses do not have to be accessed sequentially since ADS = CNTEN = V with CNT/MSK = V constantly loads the address on the rising edge of the CLK.
IL
IH
Numbers are for reference only.
Document #: 38-06070 Rev. *G
Page 17 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms (continued)
Bank Select Read[26, 27]
tCYC2
tCH2
tCL2
CLK
tHA
tSA
A3
A4
ADDRESS(B1)
A5
A0
A1
A2
tHC
tSC
CE(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
Q0
Q3
Q1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
Read-to-Write-to-Read (OE = LOW)[25, 28, 29, 30, 31]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
tSD tHD
Dn+2
An+3
An+4
ADDRESS
DATAIN
tSA
tHA
tCD2
tCD2
tCD2
tCKHZ
Qn
Qn+3
Qn+1
DATAOUT
tCKLZ
WRITE
READ
NO OPERATION
READ
Notes:
26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851AV/CY7C0852AV device from this
data sheet. ADDRESS = ADDRESS
.
(B2)
(B1)
27. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
29. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
30. CE = OE = B0 – B3 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
0
1
1
31. CE = B0 – B3 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06070 Rev. *G
Page 18 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[25, 28, 30, 31]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tHW
tSW
R/W tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
tCD2
tCD2
DATAOUT
Qn
Qn+4
Qn+1
tOHZ
OE
READ
WRITE
READ
Read with Address Counter Advance[30]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
Qx–1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
DATAOUT
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Document #: 38-06070 Rev. *G
Page 19 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms (continued)
Write with Address Counter Advance [31]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
ADDRESS
Disabled-to-Read-to-Read-to-Read-to-Write
tCYC2
tCL2
tCH2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW tHW
tHA
tHA
tSA
tSA
An+4
An
An+3
An+1
An+2
ADDRESS
OE
tHD
tSD
DATAIN
Dn+3
tCD2
DATAOUT
Qn+1
Qn
Qn+2
DISABLED
READ
READ
READ
WRITE
READ
Document #: 38-06070 Rev. *G
Page 20 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms (continued)
Disabled-to-Write-to-Read-to-Write-to-Read
tCYC2
tCL2
tCH2
CLK
tSC
tHC
tHW
CE
tSW
R/W
tSA
tHA
An+4
An+3
tOE
An+2
ADDRESS
OE
An
An+1
tHD
tSD
Dn
DATAIN
Dn+2
tCD2
Qn+3
Qn+1
DATAOUT
DISABLED
WRITE
READ
READ
READ
WRITE
Disabled-to-Read-to-Disabled-to-Write
tCYC2
tCL2
tCH2
CLK
CE
tHC
tSC
R/W
tHW
tSW
An+4
An+3
ADDRESS
An+2
An+1
An
tSA tHA
tOE
OE
tOHZ
tHD
tSD
DATAIN
Dn+2
tCD2
DATAOUT
Qn+3
Qn
DISABLED
READ
DISABLED
WRITE
READ
READ
Document #: 38-06070 Rev. *G
Page 21 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms (continued)
Read-to-Readback-to-Read-to-Read (R/W = HIGH)
tCYC2
tCL2
tCH2
CLK
ADS
tHAD
tSAD
CNTEN
tSCN
tHCN
tSA
tHA
An+1
ADDRESS
COUNTER
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
OE
DATAOUT
Qn+1
Qn+3
Qn+2
READ
INCREMENT
NO OPERATION
READ
READ
READ
READBACK
INCREMENT
INCREMENT
INCREMENT
Document #: 38-06070 Rev. *G
Page 22 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms (continued)
Counter Reset[32, 33]
tCYC2
tCH2 tCL2
CLK
tHA
Am
tSA
Ap
An
ADDRESS
INTERNAL
Ax
Ap
An
1
0
Am
ADDRESS
tHW
tSW
R/W
ADS
CNTEN
CNTRST
tHRST
tSRST
tHD
D0
tSD
DATAIN
tCD2
tCD2
[34]
DATAOUT
Q0
Qn
Q1
tCKLZ
READ
ADDRESS 0
READ
ADDRESS 1
READ
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS Am
ADDRESS An
Notes:
32. CE = B0 – B3 = LOW; CE = MRST = CNT/MSK = HIGH.
0
1
33. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
34. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06070 Rev. *G
Page 23 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms (continued)
Readback State of Address Counter or Mask Register[35, 36, 37, 38]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA
tHA
EXTERNAL
An*
An
ADDRESS
A0–A16
INTERNAL
ADDRESS
An+4
An+1
An+2
An+3
An
tSAD
tHAD
ADS
CNTEN
tSCN
tHCN
tCD2
tCKHZ
Qn
tCKLZ
DATAOUT
Qn+1
Qx-1
Qn+2
Qx-2
Q
n+3
LOAD
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
EXTERNAL
ADDRESS
Notes:
35. CE = OE = B0 – B3 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
36. Address in output mode. Host must not be driving address bus after t
in next clock cycle.
CKLZ
37. Address in input mode. Host can drive address bus after t
.
CKHZ
38. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document #: 38-06070 Rev. *G
Page 24 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms (continued)
Left_Port (L_Port) Write to Right_Port (R_Port) Read[39, 40, 41]
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
L_PORT
An
ADDRESS
tSW
tHW
R/WL
tCKHZ
tSD
tHD
tCKLZ
L_PORT
DATAIN
Dn
tCCS
tCYC2
tCL2
CLKR
tCH2
tSA
tHA
R_PORT
An
ADDRESS
R/WR
tCD2
R_PORT
DATAOUT
Qn
tDC
Notes:
39. CE = OE = ADS = CNTEN = B0 – B3 = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
40. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
is violated, indeterminate data will be Read out.
CCS
CYC2
41. If t
< minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * t
+ t
) after the rising edge of R_Port's clock. If
CCS
CD2
t
> minimum specified value, then R_Port will Read the most recent data (written by L_Port) (t
+ t
) after the rising edge of R_Port's clock.
CCS
CYC2
CD2
Document #: 38-06070 Rev. *G
Page 25 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms (continued)
Counter Interrupt and Retransmit[34, 42, 43, 44, 45]
tCYC2
tCH2
tCL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
1FFFE
tSCINT
1FFFC
Last_Loaded
1FFFD
1FFFF
tRCINT
Last_Loaded +1
CNTINT
Notes:
42. CE = OE = B0 – B3 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
43. CNTINT is always driven.
44. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
45. The mask register assumed to have the value of 1FFFFh.
Document #: 38-06070 Rev. *G
Page 26 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Switching Waveforms (continued)
MailBox Interrupt Timing[46, 47, 48, 49, 50]
tCYC2
tCH2
tCL2
CLKL
tSA tHA
3FFFF
L_PORT
An+1
An
An+2
ADDRESS
An+3
tSINT
tRINT
INTR
tCYC2
tCL2
tCH2
CLKR
tSA tHA
Am
R_PORT
Am+1
3FFFF
Am+3
Am+4
ADDRESS
Table 7. Read/Write and Enable Operation (Any Port)[1, 8, 51, 52]
Inputs
Outputs
DQ0 – DQ35
High-Z
OE
CLK
CE0
CE1
R/W
Operation
X
H
X
X
Deselected
Deselected
Write
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z
DIN
H
X
DOUT
High-Z
Read
H
X
Outputs Disabled
Notes:
46. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
47. Address “3FFFF” is the mailbox location for R_Port of a 9M device.
48. L_Port is configured for Write operation, and R_Port is configured for Read operation.
49. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
50. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
51. OE is an asynchronous input signal.
52. When CE changes state, deselection and Read happen after one cycle of latency.
Document #: 38-06070 Rev. *G
Page 27 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Ordering Information
256K
×
36 (9M) 3.3V Synchronous CY7C0853AV Dual-Port SRAM
Package
Speed
Operating
(MHz)
Ordering Code
Name
BB172
BB172
BB172
BB172
Package Type
Range
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Industrial
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Industrial
133
100
CY7C0853AV-133BBC
CY7C0853AV-133BBI
CY7C0853AV-100BBC
CY7C0853AV-100BBI
128K
×
36 (4M) 3.3V Synchronous CY7C0852AV Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
CY7C0852AV-167BBC
CY7C0852AV-167AC
CY7C0852AV-133BBC
CY7C0852AV-133BBI
CY7C0852AV-133AC
CY7C0852AV-133AI
Name
BB172
A176
Package Type
167
133
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Commercial
176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Industrial
176-pin Flat Pack 24 mm × 24 mm (TQFP)
176-pin Flat Pack 24 mm × 24 mm (TQFP)
BB172
BB172
A176
Commercial
Industrial
A176
64K
× 36 (2M) 3.3V Synchronous CY7C0851AV Dual-Port SRAM
Speed
Package
Operating
Range
(MHz)
Ordering Code
CY7C0851AV-167BBC
CY7C0851AV-167AC
CY7C0851AV-133BBC
CY7C0851AV-133BBI
CY7C0851AV-133AC
CY7C0851AV-133AI
Name
Package Type
167
133
BB172
A176
BB172
BB172
A176
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Commercial
176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Industrial
176-pin Flat Pack 24 mm × 24 mm (TQFP)
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
Industrial
A176
32K
× 36 (1M) 3.3V Synchronous CY7C0850AV Dual-Port SRAM
Speed
Package
Operating
Range
(MHz)
Ordering Code
CY7C0850AV-167BBC
CY7C0850AV-167AC
CY7C0850AV-133BBC
CY7C0850AV-133BBI
CY7C0850AV-133AC
CY7C0850AV-133AI
Name
Package Type
167
133
BB172
A176
BB172
BB172
A176
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Commercial
176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA) Industrial
176-pin Flat Pack 24 mm × 24 mm (TQFP)
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
Industrial
A176
Document #: 38-06070 Rev. *G
Page 28 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Package Diagrams
176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176
51-85132-**
Document #: 38-06070 Rev. *G
Page 29 of 31
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Package Diagrams (continued)
172-Ball FBGA (15 x 15 x 1.25 mm) BB172
51-85114-*B
FLEx36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-06070 Rev. *G
Page 30 of 31
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document History Page
Document Title: CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV FLEx36™ 3.3V 32K/64K/128K/256K x 36 Syn-
chronous Dual-Port RAM
Document Number: 38-06070
Issue
Orig. of
REV.
ECN NO.
Date
Change Description of Change
**
127809
08/04/03
SPN
This data sheet has been extracted from another data sheet: the 2M/4M/9M
data sheet. The following changes have been made from the original as
pertains to this device:
Updated capacitance values
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Corrected 0853 pins L3 and L12
Added discussion of Pause/Restart for JTAG boundary scan
Power up requirements added to Maximum Ratings information
Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns
Updated Icc numbers
Updated tHA, tHB, tHD for -100 speed
Separated out from the 4M data sheet
Added 133-MHz Industrial device to Ordering Information table
*A
*B
*C
210948
216190
231996
See ECN
YDT
Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF.
See ECN YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change
See ECN
YDT
Removed “A particular port can write to a certain location while another port
is reading that location.” from Functional Description.
*D
238938
See ECN
WWZ
Merged 0853 (9Mx36) with 0852 (4Mx36) and 0851(2Mx36), add 0850 (1M
x36), to the data sheet.
Added product selection table.
Added JTAG ID code for 1M device.
Added note 14.
Updated boundary scan section.
Updated function description for the merge and addition.
*E
*F
329122
389877
See ECN
See ECN
SPN
KGH
Updated Marketing part numbers
Updated Read-to-Write-to-Read timing diagram to reflect accurate bus
turnaround scheme.
Added ISB5
Changed tRSCNTINT to 10ns
Changed tRSF to 10ns
Added figure Disabled-to-Read-to-Read-to-Read-to-Write
Added figure Disabled-to-Write-to-Read-to-Write-to-Read
Added figure Disabled-to-Read-to-Disabled-to-Write
Added figure Read-to-Readback-to-Read-to-Read (R/W = HIGH)
Updated Read-to-Write-to-Read timing diagram to correct the data out
schemes
Updated Disabled-to-Read-to-Read-to-Read-to-Write timing diagram to
correct the chip enable, data in, and data out schemes
Updated Disabled-to-Write-to-Read-to-Write-to-Read timing diagram to
correct the chip enable and output enable schemes
Updated Disabled-to-Read-to-Disabled-to-Write timing diagram to correct
the chip enable and output enable schemes
*G
391597
See ECN
SPN
Updated counter reset section to reflect mirror register behavior
Document #: 38-06070 Rev. *G
Page 31 of 31
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