CY7C04312BV-133 [CYPRESS]
10 Gb/s 3.3V QuadPort DSE Family; 10 Gb / s的3.3V QuadPort DSE系列
| 型号： | CY7C04312BV-133 |
| 厂家： | 
CYPRESS |
| 描述： | 10 Gb/s 3.3V QuadPort DSE Family |
| 文件： | 总37页 (文件大小：828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C0430BV
CY7C04312BV
CY7C04314BV
10 Gb/s 3.3V QuadPort™
DSE Family
• BIST (Built-In Self-Test) controller
• DualChipEnablesonallportsforeasydepthexpansion
• Separate upper-byte and lower-byte controls on all
ports
• Simple array partitioning (CY7C0430BV only)
— Internal maskregister controlscounter wrap-around
— Counter-Interrupt flags to indicate wrap-around
— Counter and mask registers readback on address
Features
• QuadPort™ datapath switching element (DSE) family
allows four independent ports of access for data path
management and switching
• High-bandwidth data throughput up to 10 Gb/s
• 133-MHz[1] port speed x 18-bit-wide interface × 4 ports
• High-speed clock to data access 4.2 ns (max.)
• Synchronous pipelined devices
— 1-Mb, ½-Mb, and ¼-Mb switch arrays
• 272-ball BGA package (27-mm × 27-mm × 1.27-mm ball
pitch)
— 64K/32K/16K × 18 device options
• 0.25-micron CMOS for optimum speed/power
• IEEE 1149.1 JTAG boundary scan
• Commercial and industrial temperature ranges
• 3.3V low operating power
— Active = 750 mA (maximum)
• Width and depth expansion capabilities
— Standby = 15 mA (maximum
QuadPort DSE Family Applications
PORT 1
PORT 3
PORT 2
PORT 4
BUFFERED SWITCH
PORT 2
PORT 3
PORT 4
PORT 1
REDUNDANT DATA MIRROR
Note:
1. fMAX2 for commercial is 135 MHz and for industrial is 133 MHz.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06027 Rev. *A
Revised May 14, 2002
CY7C0430BV
CY7C04312BV
CY7C04314BV
PORT 1
PORT 2
PORT 3
PORT 4
DATA PATH AGGREGATOR
Processor 1
QuadPort
Pre-processed DATA Path
Processed DATA Path
DSE Family
Processor 2
DATA PATH MANAGER FOR
PARALLEL PACKET PROCESSING
Queue #1
Queue #2
PORT 1
PORT 2
PORT 3
PORT 4
DATA CLASSIFICATION ENGINE
address register. After externally loading the counter with the
initial address the counter will self-increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
Functional Description
The CY7C043XXBV is a family of 10 Gb/s, true four-ported
Datapath Switching Elements with port speeds of up to
133 MHz[1]. The members of the family include 1-Mb
(64K ×18), ½-Mb (32K x18), and ¼-Mb (16K × 18) options. All
four ports may be clocked at independent frequencies from
one another. Simultaneous reads are allowed for accesses to
the same address location; however, simultaneous reading
and writing to the same address is not allowed. Any port can
write to a certain location while other ports are reading that
location simultaneously, if the timing spec for port to port delay
(tCCS) is met. The result of writing to the same location by more
than one port at the same time is undefined.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle is required with chip enables asserted
to reactivate the outputs.
The CY7C0430BV (64K × 18 device) is the only member of
the family which contains burst contains for simple array parti-
tioning. Counter enable inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast interleaved memory
Data is registered for decreased cycle time. Clock to data valid
tCD2 = 4.2 ns. Each port contains a burst counter on the input
Document #: 38-06027 Rev. *A
Page 2 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
applications. A port’s burst counter is loaded with an external
address when the port’s Counter Load pin (CNTLD) is
asserted LOW. When the port’s Counter Increment pin
(CNTINC) is asserted, the address counter will increment on
each subsequent LOW-to- HIGH transition of that port’s clock
signal. This will read/write one word from/into each successive
address location until CNTINC is deasserted. The counter can
address the entire switch array and will loop back to the start.
Counter Reset (CNTRST) is used to reset the burst counter.
A counter-mask register is used to control the counter wrap.
The counter and mask register operations are described in
more details in the following sections.
The counter or mask register values can be read back on the
bidirectional address lines by activating MKRD or CNTRD,
respectively.
The new features included for the QuadPort DSE family
include: readback of burst-counter internal address value on
address lines, counter-mask registers to control the counter
wrap-around, readback of mask register value on address
lines, interrupt flags for message passing, BIST, JTAG for
boundary scan, and asynchronous Master Reset.
Top Level Logic Block Diagram
Port 1 Operation-control Logic Blocks[2]
Reset
MRST
Logic
UBP1
LBP1
Port-1
R/WP1
TMS
Control
Logic
JTAG
OEP1
TCK
Controller
TDO
CE0P1
TDI
CE1P1
CLKP1
CLKBIST
BIST
18
Port 1
I/O0P1- I/O17P1
Port 4 Logic Blocks[3]
I/O
CLKP1
16
A0P1–A15P1
[4]
Port 1
Port 4
Port 1
MKLDP1
[4]
Counter/
Mask Reg/
Address
Decode
CNTLDP1
16K/32K/64K × 18
QuadPort DSE
Array
[4]
[4]
CNTINCP1
CNTRDP1
[4]
[4]
MKRDP1
CNTRSTP1
INTP1
[4]
CNTINTP1
Port 2
Port 3
Port 2 Logic Blocks[3]
Port 3 Logic Blocks[3]
Notes:
2. Port 1 Control Logic Block is detailed on page 4.
3. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
4. Counter functionality applies only to CY7C0430BV (64K × 18) device option. These pins are either GND or NC for CY7C04312BV and CY7C04314BV.
Document #: 38-06027 Rev. *A
Page 3 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Port 1 Operation-Control Logic Block Diagram
(Address Readback is independent of CEs)
R/WP1
W
UBP1
CE0P1
CE1P1
LBP1
OEP1
9
I/O9P1–I/O17P1
Port-1
I/O
Control
9
I/O0P1–I/O8P1
Addr.
Read
Port 1
Readback
Register
MRST
16
A0P1–A15P1
Port 1
Mask Register
[4]
CNTRDP1
MKRDP1
Port 1
Priority
Decision
Logic
[4]
16K/32K/64K × 18
QuadPort
DSE Array
Address
Decode
[4]
MKLDP1
Port 1
Counter/
Address
Register
[4]
CNTINCP1
[4]
CNTLDP1
[4]
CNTRSTP1
CLKP1
LBP1
UBP1
R/WP1
CE0P1
CE1P1
Port 1
Interrupt
Logic
MRST
CNTINTP1
[4]
INTP1
OEP1
CLKP1
MRST
Document #: 38-06027 Rev. *A
Page 4 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Pin Configuration
272-ball Grid Array (BGA)
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LB
P1
I/O17
P2
I/O15
P2
I/O13
P2
I/O11
P2
I/O9
P2
I/O16
P1
I/O14
P1
I/O12
P1
I/O10
P1
I/O10
P4
I/O12
P4
I/O14
P4
I/O16
P4
I/O9
P3
I/O11
P3
I/O13
P3
I/O15
P3
I/O17
P3
LB
P4
A
B
VDD1
UB
P1
I/O16
P2
I/O14
P2
I/O12
P2
I/O10
P2
I/O17
P1
I/O13
P1
I/O11
P1
TMS
TCK
VSS
TDI
TDO
VSS
I/O11
P4
I/O13
P4
I/O17
P4
I/O10
P3
I/O12
P3
I/O14
P3
I/O16
P3
UB
P4
VDD1
A14
A15
CE1
P1
CE0
P1
R/W
P1
I/O15
P1
VSS2
VSS2
VSS2
VDD2
I/O9
P1
I/O9
P4
VSS2
VDD2
VSS2
VSS2
I/O15
P4
R/W
P4
CE0
P4
CE1
P4
A15
A14
[9]
[8]
[8]
[9]
C
P1
P1
P4
P4
VSS1
A12
P1
A13
P1
OE
P1
VDD2
VSS2
VDD
VDD
VSS2
VDD2
OE
P4
A13
P4
A12
P4
VSS1
D
A10
P1
A11
P1
MKRD
P1
CNTRD
CNTRD MKRD
A11
P4
A10
P4
[6]
[6]
E
P1
P4
P4
A7
P1
A8
P1
A9
P1
CNTINT
CNTINT
A9
P4
A8
P4
A7
P4
[7]
[7]
F
P1
P4
VSS1
A5
P1
A6
P1
CNTINC
CNTINC
A6
P4
A5
P4
VSS1
[6]
[6]
G
H
P1
P4
A3
P1
A4
P1
MKLD
P1
CNTLD
CNTLD
MKLD
A4
P4
A3
P4
[6]
[6]
[6]
P1
P4
P4
[5]
[5]
[5]
[5]
VDD1
A1
P1
A2
P1
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
A2
P4
A1
P4
VDD1
J
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
A0
P1
INT
P1
CNTRST
CLK
P1
CLK
P4
CNTRST
INT
P4
A0
P4
[6]
[6]
K
P1
P4
A0
P2
INT
P2
CNTRST
VSS
VSS
CNTRST
INT
P3
A0
P3
[6]
[6]
L
P2
P3
VDD1
A1
P2
A2
P2
CLK
P2
CLK
P3
A2
P3
A1
P3
VDD1
M
N
A3
P2
A4
P2
MKLD
P2
CNTLD
CNTLD
MKLD
A4
P3
A3
P3
[6]
[6]
[6]
P2
P3
P3
VSS1
A5
P2
A6
P2
CNTINC
CNTINC
A6
P3
A5
P3
VSS1
[6]
[6]
P
P2
P3
A7
P2
A8
P2
A9
P2
CNTINT
CNTINT
A9
P3
A8
P3
A7
P3
[7]
[7]
R
P2
P3
A10
P2
A11
P2
MKRD
P2
CNTRD
CNTRD MKRD
[6] [6]
A11
P3
A10
P3
[6]
T
P2
P3
P3
VSS1
A12
P2
A13
P2
OE
P2
VDD2
VSS2
VSS2
VSS2
VDD2
VSS2
VDD
VSS
NC
VSS
NC
VDD
VDD2
VSS2
VSS2
VSS2
VSS2
VDD2
OE
A13
P3
A12
P3
VSS1
U
P3
A14
A15
CE1
P2
CE0
P2
R/W
P2
I/O6
P2
I/O0
P2
I/O0
P3
I/O6
P3
R/W
P3
CE0
P3
CE1
P3
A15
A14
[9]
[8]
[8]
[9]
V
P2
P2
P3
P3
VDD1
UB
P2
I/O7
P1
I/O5
P1
I/O3
P1
I/O1
P1
I/O8
P2
I/O4
P2
I/O2
P2
MRST CLKBIST
I/O2
P3
I/O4
P3
I/O8
P3
I/O1
P4
I/O3
P4
I/O5
P4
I/O7
P4
UB
P3
VDD1
W
Y
LB
P2
I/O8
P1
I/O6
P1
I/O4
P1
I/O2
P1
I/O0
P1
1/O7
P2
I/O5
P2
I/O3
P2
I/O1
P2
I/O1
P3
I/O3
P3
I/O5
P3
I/O7
P3
I/O0
P4
I/O2
P4
I/O4
P4
I/O6
P4
I/O8
P4
LB
P3
Notes:
5. Central Leads are for thermal dissipation only. They are connected to device VSS
6. Pin is VSS for CY7C04312BV and CY7C04314BV devices.
.
7. Pin is NC for CY7C04312BV and CY7C04314BV devices.
8. Pin is VSS for CY7C04312BV and CY7C04314BV devices.
9. Pin is VSS for CY7C04314BV devices.
Document #: 38-06027 Rev. *A
Page 5 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Selection Guide
CY7C04312BV
-133
CY7C04312BV
-100
Unit
MHz
ns
fMAX2
133[1]
100
5.0
600
150
15
Max Access Time (Clock to Data)
Max Operating Current ICC
4.2
750
200
15
mA
mA
mA
Max Standby Current for ISB1 (All ports TTL Level)
Max Standby Current for ISB3 (All ports CMOS Level)
Pin Definitions
Port 1
Port 2
Port 3
Port 4
Description
Address Input/Output.
A0P1–A15P1
A0P2–A15P2
A0P3–A15P3
A0P4–A15P4
I/O0P1–I/O17P1 I/O0P2–I/O17P2 I/O0P3–I/O17P3 I/O0P4–I/O17P4 Data Bus Input/Output.
CLKP1
CLKP2
CLKP3
CLKP4
Clock Input. This input can be free running or strobed.
Maximum clock input rate is fMAX
.
LBP1
LBP2
LBP3
LBP4
Lower Byte Select Input. Asserting this signal LOW
enables read and write operations to the lower byte. For
read operations both the LB and OE signals must be
asserted to drive output data on the lower byte of the data
pins.
UBP1
UBP2
UBP3
UBP4
Upper Byte Select Input. Same function as LB, but to
the upper byte.
CE0P1,CE1P1
CE0P2,CE1P2
CE0P3,CE1P3
CE0P4,CE1P4
Chip Enable Input. To select any port, both CE0 AND
CE1 must be asserted to their active states (CE0 ≤ VIL
and CE1 ≥ VIH).
OEP1
OEP2
OEP3
OEP4
Output EnableInput. ThissignalmustbeassertedLOW
to enable the I/O data lines during read operations. OE
is asynchronous input.
R/WP1
MRST
R/WP2
R/WP3
R/WP4
Read/Write Enable Input. This signal is asserted LOW
to write to the dual port memory array. For read opera-
tions, assert this pin HIGH.
Master Reset Input. This is one signal for All Ports.
MRST is an asynchronous input. Asserting MRST LOW
performsalloftheresetfunctionsasdescribedinthe text.
A MRST operation is required at power-up.
[6]
[6]
[6]
[6]
CNTRSTP1
CNTRSTP2
CNTRSTP3
CNTRSTP4
Counter Reset Input. Asserting this signal LOW resets
the burst address counter of its respective port to zero.
CNTRST is second to MRST in priority with respect to
counter and mask register operations.
[6]
[6]
[6]
[6]
MKLDP1
MKLDP2
MKLDP3
MKLDP4
Mask Register Load Input. Asserting this signal LOW
loads the mask register with the external address
available on the address lines. MKLD operation has
higher priority over CNTLD operation.
[6]
[6]
[6]
[6]
CNTLDP1
CNTLDP2
CNTLDP3
CNTLDP4
Counter Load Input. Asserting this signal LOW loads
the burst counter with the external address present on
the address pins.
[6]
[6]
[6]
[6]
CNTINCP1
CNTINCP2
CNTINCP3
CNTINCP4
Counter Increment Input. Asserting this signal LOW
increments the burst address counter of its respective
port on each rising edge of CLK.
Document #: 38-06027 Rev. *A
Page 6 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Pin Definitions (continued)
Port 1
Port 2
Port 3
Port 4
Description
[6]
[6]
[6]
[6]
CNTRDP1
CNTRDP2
CNTRDP3
CNTRDP4
Counter Readback Input. When asserted LOW, the
internal address value of the counter will be read back on
the address lines. During CNTRD operation, both
CNTLD and CNTINC must be HIGH. Counter readback
operationhashigherpriorityovermaskregisterreadback
operation. Counter readback operation is independent of
port chip enables. If address readback operation occurs
with chip enables active (CE0 = LOW, CE1 = HIGH), the
datalines (I/Os)willbe three-stated. The readback timing
will be valid after one no-operation cycle plus tCD2 from
the rising edge of the next cycle.
[6]
[6]
[6]
[6]
MKRDP1
MKRDP2
MKRDP3
MKRDP4
Mask Register Readback Input. When asserted LOW,
the value of the mask register will be readback on
address lines. During mask register readback operation,
all counter and MKLD inputs must be HIGH (see Counter
and Mask Register Operations truth table). Mask register
readback operation is independent of port chip enables.
If address readback operation occurs with chip enables
active (CE0 = LOW, CE1 = HIGH), the data lines (I/Os)
will be three-stated. The readback will be valid after one
no-operation cycle plus tCD2 from the rising edge of the
next cycle.
[7]
[7]
[7]
[7]
CNTINTP1
CNTINTP2
INTP2
CNTINTP3
CNTINTP4
INTP4
Counter Interrupt Flag Output. Flag is asserted LOW
for one clock cycle when the counter wraps around to
location zero.
INTP1
INTP3
Interrupt Flag Output. Interrupt permits communica-
tions between all four ports. The upper four memory
locations can be used for message passing. Example of
operation: INTP4 is asserted LOW when another port
writes to the mailbox location of Port 4. Flag is cleared
when Port 4 reads the contents of its mailbox. The same
operation is applicable to ports 1, 2, and 3.
TMS
JTAG Test Mode Select Input. It controls the advance
of JTAG TAP state machine. State machine transitions
occur on the rising edge of TCK.
TCK
TDI
JTAG Test Clock Input. This can be CLK of any port or
an external clock connected to the JTAG TAP.
JTAG Test Data Input. This is the only data input. TDI
inputs will shift data serially in to the selected register.
TDO
JTAG Test Data Output. This is the only data output.
TDO transitions occur on the falling edge of TCK. TDO
normally three-stated except when captured data is
shifted out of the JTAG TAP.
CLKBIST
GND
VSS
BIST Clock Input.
Thermal Ground for Heat Dissipation.
Ground Input.
VDD
Power Input.
VSS1
VDD1
VSS2
VDD2
Address Lines Ground Input.
Address Lines Power Input.
Data Lines Ground Input.
Data Lines Power Input.
Document #: 38-06027 Rev. *A
Page 7 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ..........................................> 2200V
Latch-up Current.....................................................> 200 mA
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground Potential.............. –0.5V to + 4.6V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VDD
DC Voltage Applied to
Outputs in High-Z State .........................–0.5V to VCC + 0.5V
3.3V ± 150 mV
3.3V ± 150 mV
–40°C to +85°C
DC Input Voltage....................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
CY7C043XXBV
-100
-133
Parameter
Description
Output HIGH Voltage
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
VOH
2.4
2.4
V
(VCC = Min., IOH = –4.0 mA)
VOL
Output LOW Voltage
(VCC = Min., IOH = +4.0 mA)
0.4
0.4
V
VIH
VIL
IOZ
ICC
Input HIGH Voltage
Input LOW Voltage
2.0
2.0
V
V
0.8
10
0.8
10
Output Leakage Current
–10
–10
µA
mA
Operating Current (VCC = Max., IOUT = 0 mA)
Outputs Disabled, CE = VIL, f = fmax
350
80
700
300
60
550
ISB1
Standby Current (four ports toggling at TTL
Levels,0 active)
CE1-4 ≥ VIH, f = fMAX
200
300
150
250
mA
mA
ISB2
Standby Current (four ports toggling at TTL
Levels, 1 active) CE1 | CE2 | CE3 | CE4 < VIL,
f = fMAX
150
125
ISB3
ISB4
Standby Current (four ports CMOS Level, 0
active) CE1–4 ≥ VIH, f = 0
1.5
15
1.5
85
15
mA
mA
Standby Current (four ports CMOS Level, 1
active and toggling) CE1 | CE2 | CE3 | CE4 <
VIL, f = fMAX
110
290
240
JTAG TAP Electrical Characteristics Over the Operating Range
Parameter
VOH1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
IOH = −4.0 mA
Min.
Max.
Unit
V
2.4
VOL1
VIH
VIL
IX
IOL = 4.0 mA
0.4
V
2.0
V
0.8
V
Input Leakage Current
GND ≤ VI ≤ VDD
–100
100
µA
Capacitance
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
pF
CIN (All Pins)
Input Capacitance
Output Capacitance
Input Capacitance
Output Capacitance
10
10
15
15
COUT (All Pins)
CIN (CLK Pins)
COUT (CLK Pins)
pF
pF
pF
Document #: 38-06027 Rev. *A
Page 8 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
AC Test Load
Z0 = 50
Ω
R = 50Ω
Z0 = 50
Ω
R = 50Ω
OUTPUT
OUTPUT
[10]
C
5 pF
V
TH
= 1.5V
V
TH
= 1.5V
(a) Normal Load
Z0 = 50
Ω
R = 50Ω
OUTPUT
5 pF
V
TH
= 3.3V
1.5V
(b) Three-State Delay
50Ω
TDO
Z =50Ω
0
C = 10 pF
3.0V
GND
90%
10%
90%
10%
GND
t
t
F
R
(c) TAP Load
All Input Pulses
Note:
10. Test conditions: C = 10 pF.
Document #: 38-06027 Rev. *A
Page 9 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
[11]
Switching Characteristics Over the Industrial Operating Range
CY7C04312BV
-133
-100
Parameter
Description
Min.
Max.
Min.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[12]
fMAX2
Maximum Frequency
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Clock Rise Time
133
100
[12]
tCYC2
7.5
3
10
4
tCH2
tCL2
3
4
tR
2
2
3
3
tF
Clock Fall Time
tSA
Address Set-up Time
Address Hold Time
2.3
0.7
2.3
0.7
2.3
0.7
2.3
0.7
2.3
0.7
2.3
0.7
2.3
0.7
2.3
0.7
2.3
0.7
2.3
0.7
2.3
0.7
3
0.7
3
tHA
tSC
Chip Enable Set-up Time
Chip Enable Hold Time
R/W Set-up Time
tHC
0.7
3
tSW
tHW
R/W Hold Time
0.7
3
tSD
Input Data Set-up Time
Input Data Hold Time
Byte Set-up Time
tHD
0.7
3
tSB
tHB
Byte Hold Time
0.7
3
tSCLD
tHCLD
tSCINC
tHCINC
tSCRST
tHCRST
tSCRD
tHCRD
tSMLD
tHMLD
tSMRD
tHMRD
tOE
CNTLD Set-up Time
CNTLD Hold Time
0.7
3
CNTINC Set-up Time
CNTINC Hold Time
0.7
3
CNTRST Set-up Time
CNTRST Hold Time
0.7
3
CNTRD Set-up Time
CNTRD Hold Time
0.7
3
MKLD Set-up Time
MKLD Hold Time
0.7
3
MKRD Set-up Time
MKRD Hold Time
0.7
Output Enable to Data Valid
OE to Low-Z
6.5
8
[13]
tOLZ
1
1
1
1
[13]
tOHZ
OE to High-Z
6
7
5
5
5
tCD2
tCA2
tCM2
tDC
Clock to Data Valid
4.2
4.7
4.7
Clock to Counter Address Readback Valid
Clock to Mask Register Readback Valid
Data Output Hold After Clock HIGH
Clock HIGH to Output High-Z
Clock HIGH to Output Low-Z
1
1
1
1
1
1
[14]
tCKHZ
4.8
6.8
[14]
tCKLZ
Notes:
11. If data is simultaneously written and read to the same address location and tCCS is violated, the data read from the address, as well as the subsequent data
remaining in the address is undefined.
12.
fMAX2 for commercial is 135 MHz. tCYC2 Min. for commercial is 7.4 ns.
13. This parameter is guaranteed by design, but it is not production tested.
14. Valid for both address and data outputs.
Document #: 38-06027 Rev. *A
Page 10 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Switching Characteristics Over the Industrial Operating Range (continued)[11]
CY7C04312BV
-133
-100
Parameter
tSINT
Description
Clock to INT Set Time
Min.
Max.
7.5
Min.
Max.
10
Unit
ns
1
1
1
1
1
1
1
1
tRINT
Clock to INT Reset Time
Clock to CNTINT Set Time
Clock to CNTINT Reset Time
7.5
10
ns
tSCINT
tRCINT
7.5
10
ns
7.5
10
ns
Master Reset Timing
tRS
Master Reset Pulse Width
7.5
7.5
10
10
ns
ns
ns
tRSR
tROF
Master Reset Recovery Time
Master Reset to Output Flags Reset Time
6.5
8
Port to Port Delays
[11]
tCCS
Clock to Clock Set-up Time (time required after a write
before you can read the same address location)
6.5
9
ns
JTAG Timing and Switching Waveforms
CY7C043XXBV
–133/–100
Parameter
fJTAG
tTCYC
tTH
Description
Maximum JTAG TAP Controller Frequency
TCK Clock Cycle Time
Min.
Max.
Unit
MHz
ns
10
100
40
40
20
20
20
20
TCK Clock High Time
ns
tTL
TCK Clock Low Time
ns
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
fBIST
tBH
TMS Set-up to TCK Clock Rise
TMS Hold After TCK Clock Rise
TDI Set-up to TCK Clock Rise
TDI Hold after TCK Clock Rise
TCK Clock Low to TDO Valid
TCK Clock Low to TDO Invalid
Maximum CLKBIST Frequency
CLKBIST High Time
ns
ns
ns
ns
20
50
ns
0
ns
MHz
ns
6
6
tBL
CLKBIST Low Time
ns
Document #: 38-06027 Rev. *A
Page 11 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
tTH
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Switching Waveforms
Master Reset[15]
t
CYC2
t
t
CL2
CH2
CLK
t
RS
MRST
t
RSF
ALL
ADDRESS/
DATA
LINES
t
t
S
RSR
ALL
OTHER
INPUTS
INACTIVE
ACTIVE
[16]
TMS
CNTINT
INT
TDO
Notes:
15. tS is the set-up time required for all input control signals.
16. To Reset the test port without resetting the device, TMS must be held low for five clock cycles.
Document #: 38-06027 Rev. *A
Page 12 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Switching Waveforms (continued)
Read Cycle[17, 18, 19, 20, 21]
t
CYC2
t
t
CL2
CH2
CLK
CE
t
t
t
t
HC
SC
HC
SC
LB
t
SB
t
HB
UB
R/W
t
t
t
t
SW
SA
HW
HA
ADDRESS
A
A
A
A
n+3
n
n+1
n+2
t
1 Latency
t
DC
CD2
DATA
OUT
Q
Q
Q
n+2
n
n+1
t
OHZ
t
t
CKLZ
OLZ
OE
tOE
Notes:
17. OE is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge.
18. CNTLD = VIL, MKLD = VIH, CNTINC = x, and MRST = CNTRST = VIH
19. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
.
20. Addresses do not have to be accessed sequentially. Note 18 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are for reference
only.
21. CE is internal signal. CE = VIL if CE0 = VIL and CE1 = VIH
.
Document #: 38-06027 Rev. *A
Page 13 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Switching Waveforms (continued)
Bank Select Read[22, 23]
t
CYC2
t
t
CL2
CH2
CLK
t
t
t
HA
SA
ADDRESS
A
A
A
A
A
A
3
4
(B1)
(B1)
5
0
1
2
t
HC
SC
CE
t
t
t
t
t
t
t
CD2
CD2
CD2
CKHZ
HC
CKHZ
SC
Q
Q
Q
3
DATA
0
1
OUT(B1)
t
t
HA
SA
t
t
t
CKLZ
DC
DC
A
A
4
A
ADDRESS
CE
A
0
A
A
3
5
(B2)
1
2
t
t
HC
SC
(B2)
t
t
t
CD2
t
CD2
CKHZ
t
SC
HC
DATA
OUT(B2)
Q
Q
4
2
t
t
CKLZ
CKLZ
Read-to-Write-to-Read (OE = VIL)[24, 25, 26, 27]
t
CYC2
t
t
CL2
CH2
CLK
CE
t
t
HC
SC
t
t
HW
SW
R/W
t
t
HW
SW
A
A
A
A
A
A
n+4
n
n+1
n+2
n+2
n+3
ADDRESS
t
t
SD HD
t
t
HA
SA
DATA
D
IN
n+2
t
t
t
CD2
CD2
CKHZ
Q
Q
n
n+3
DATA
OUT
t
CKLZ
Read
No Operation
Write
Read
Notes:
22. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each bank consists of one QuadPort DSE device from this data sheet.
ADDRESS(B1) = ADDRESS(B2)
23. LB = UB = OE = CNTLD = VIL; MRST = CNTRST= MKLD = VIH
24. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
.
.
25. LB = UB = CNTLD = VIL; MRST = CNTRST = MKLD = VIH
.
26. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference only.
27. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document #: 38-06027 Rev. *A
Page 14 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[24, 25, 26, 27]
t
CYC2
t
t
CL2
CH2
CLK
CE
t
t
HC
SC
t
t
HW
SW
R/W
t
t
HW
SW
A
A
A
A
A
A
n+5
n
n+1
n+2
n+3
n+4
ADDRESS
t
t
HA
t
t
SA
SD HD
D
DATA
D
n+2
IN
n+3
t
t
CD2
CD2
DATA
Q
t
OUT
Q
n
n+4
t
OHZ
CKLZ
OE
Read
Write
Read
Read with Address Counter Advance[28, 29]
t
CYC2
t
t
CH2
CL2
CLK
t
t
HA
SA
ADDRESS
A
n
t
t
HCLD
SCLD
CNTLD
t
t
SCINC
HCINC
CNTINC
t
CD2
DATA
OUT
Q
Q
Q
Q
Q
Q
n+3
x–1
x
n
n+1
n+2
t
Read
DC
Counter Hold
Read with Counter
Read with Counter
External
Address
Notes:
28. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH
.
29. The “Internal Address” is equal to the “External Address” when CNTLD = VIL.
Document #: 38-06027 Rev. *A
Page 15 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Switching Waveforms (continued)
Write with Address Counter Advance [29, 30, 31]
t
CYC2
t
t
CH2
CL2
CLK
t
t
HA
SA
A
ADDRESS
n
INTERNAL
ADDRESS
A
A
A
A
A
n+4
n
n+1
n+2
n+3
t
t
HCLD
SCLD
CNTLD
CNTINC
t
t
HCINC
SCINC
D
D
D
D
D
D
n+4
DATA
n
n+1
n+1
n+2
n+3
IN
t
t
HD
SD
Write External
Address
Write with
Counter
Write Counter
Hold
Write with Counter
Notes:
30. CE0 = LB = UB = R/W = VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH.
31. Counter operation is only available on the CY7C0430BV. The CY7C04312BV and CY7C04314BV do not support the counter functions.
Document #: 38-06027 Rev. *A
Page 16 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Switching Waveforms (continued)
Counter Reset [26, 31, 32, 33]
t
CYC2
t
t
CH2
CL2
CLK
t
t
HA
SA
A
A
ADDRESS
n
n+1
INTERNAL
ADDRESS
A
A
A
A
A
n+1
X
0
1
n
t
t
HW
SW
R/W
t
t
HCLD
SCLD
CNTLD
CNTINC
CNTRST
A
t
t
n+2
SCRST
HCRST
t
t
HD
SD
DATA
D
IN
0
DATA
Q
Q
Q
n
OUT
0
1
Counter
Reset
Write
Address 0
Read
Address 0
Read
Address 1
Read
Address n
Notes:
32. CE0 = LB = UB = VIL; CE1 = MRST = MKLD = MKRD = CNTRD = VIH
.
33. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
Document #: 38-06027 Rev. *A
Page 17 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Switching Waveforms (continued)
Load and Read Address Counter[31, 34]
t
CYC2
t
t
CH2
CL2
Note 35
Note 36
CLK
t
t
t
CA2
HA
SA
t
t
CKHZ
CKLZ
A0-A15
[37]
A
A
n
n+2
t
t
HCLD
SCLD
CNTLD
CNTINC
t
t
SCINC
HCINC
t
t
HCRD
SCRD
CNTRD
INTERNAL
ADDRESS
A
A
A
n+2
A
A
n
n+1
n+2
n+2
t
DC
t
t
CD2
t
CKLZ
CKHZ
DATA
OUT
Q
Q
Q
Q
Q
Q
n+2
x–1
x
n
n+1
n+2
Load
Read Data with Counter
Read
External
Address
Internal
Address
Notes:
34. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = VIH
35. Address in output mode. Host must not be driving address bus after time tCKLZ in next clock cycle.
36. Address in input mode. Host can drive address bus after tCKHZ
.
.
37. This is the value of the address counter being read out on the address lines.
Document #: 38-06027 Rev. *A
Page 18 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Switching Waveforms (continued)
Load and Read Mask Register [31, 38]
t
CYC2
t
t
CH2
CL2
Note 35
t
Note 36
CLK
t
t
t
CA2
HA
SA
t
CKHZ
CKLZ
A0-A15
[39]
A
A
n
n
t
t
HMLD
SMLD
MKLD
MKRD
t
t
HMRD
SMRD
MASK
INTERNAL
VALUE
A
A
A
n
A
A
n
n
n
n
Read
Load
Mask Register
Value
Mask Register
Value
Notes:
38. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =VIH
39. This is the value of the Mask Register read out on the address lines.
.
Document #: 38-06027 Rev. *A
Page 19 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Switching Waveforms (continued)
Port 1 Write to Port 2 Read[40, 41, 42]
t
CYC2
t
t
CH2
CL2
CLK
P1
t
HA
t
SA
PORT-1
ADDRESS
A
n
t
t
HW
SW
R/W
P1
t
CKHZ
t
SD
t
HD
t
CKLZ
PORT-1
DATA
D
n
IN
t
CCS
t
CYC2
t
CL2
CLK
P2
t
CH2
t
t
SA
HA
PORT-2
ADDRESS
A
n
R/W
P2
t
CD2
PORT-2
DATA
Q
n
OUT
t
DC
Notes:
40. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =VIH
.
41. This timing is valid when one port is writing, and one or more of the three other ports is reading the same location at the same time. If tCCS is violated, indeterminate
data will be read out.
42. If tCCS< minimum specified value, then Port 2 will read the most recent data (written by Port 1) only (2*tCYC2 + tCD2) after the rising edge of Port 2’s clock. If
t
CCS > minimum specified value, then Port 2 will read the most recent data (written by Port 1) (tCYC2 + tCD2) after the rising edge of Port 2’s clock.
Document #: 38-06027 Rev. *A
Page 20 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Switching Waveforms (continued)
Counter Interrupt [31, 43, 44, 45]
t
CYC2
t
t
CH2
CL2
CLK
EXTERNAL
ADDRESS
007Fh
xx7Dh
t
t
HMLD
SMLD
MKLD
t
SCLD
t
HCLD
CNTLD
t
t
HCINC
SCINC
CNTINC
COUNTER
INTERNAL
ADDRESS
xx7Dh
A
xx7Eh
xx7Fh
xx00h
xx00h
n
t
SCINT
t
RCINT
CNTINT
Mailbox Interrupt Timing[46, 47, 48, 49, 50]
tCYC2
tCH2
tCL2
CLKP1
t
t
HA
SA
PORT-1
ADDRESS
A
FFFE
A
n
A
A
n+3
n+1
n+2
t
SINT
t
INT
RINT
P2
t
CYC2
t
t
CH2
CL2
CLK
P2
t
t
HA
SA
PORT-2
ADDRESS
FFFE
A
A
m+1
A
A
m+4
m
m+3
Notes:
43. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTRD = MKRD = VIH
.
44. CNTINT is always driven.
45. CNTINC goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h. The “x” is “Don’t Care.”
46. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = CNTRD = CNTINC = MKRD = MKLD =VIH
.
47. Address “FFFE” is the mailbox location for Port 2.
48. Port 1 is configured for Write operation, and Port 2 is configured for Read operation.
49. Port 1 and Port 2 are used for simplicity. All four ports can write to or read from any mailbox.
50. Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock.
Document #: 38-06027 Rev. *A
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CY7C0430BV
CY7C04312BV
CY7C04314BV
Table 1. Read/Write and Enable Operation (Any Port)[51, 52, 53]
Inputs
Outputs
I/O0–I/O17
High-Z
OE
CLK
CE0
CE1
R/W
Operation
X
H
X
X
Deselected
Deselected
Write
X
X
L
X
L
L
L
L
X
L
High-Z
DIN
H
H
H
H
X
DOUT
High-Z
Read
H
X
Outputs Disabled
Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port)[31, 51, 54, 55]
CLK MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD Mode Operation
Master- Counter/Address Register Reset and Mask
X
L
X
X
X
X
X
X
Reset
Register Set (resets entire chip as per reset
state table)
H
H
H
L
H
H
X
L
X
X
L
X
X
X
X
X
X
X
X
X
Reset
Load
Load
Counter/Address Register Reset
Load of Address Lines into Mask Register
H
LoadofAddressLinesintoCounter/Address
Register
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
L
X
X
L
Increment Counter Increment
H
H
H
Readback Readback Counter on Address Lines
Readback Readback Mask Register on Address Lines
H
H
H
Hold
Counter Hold
Notes:
51. “X” = “Don’t Care,” “H” = VIH, “L” = VIL
.
52. OE is an asynchronous input signal.
53. When CE changes state, deselection and read happen after one cycle of latency.
54. CE0 = OE = VIL; CE1 = R/W = VIH
.
55. Counter operation and mask register operation are independent of Chip Enables.
Document #: 38-06027 Rev. *A
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CY7C0430BV
CY7C04312BV
CY7C04314BV
the mailbox for Port 1, FFFE is the mailbox for Port 2, FFFD is
the mailbox for Port 3, and FFFC is the mailbox for Port 4.
Table 3 shows that in order to set Port 1 INTP1 flag, a write by
any other port to address FFFF will assert INTP1 LOW. A read
of FFFF location by Port 1 will reset INTP1 HIGH. When one
port writes to the other port’s mailbox, the Interrupt flag (INT)
of the port that the mailbox belongs to is asserted LOW. The
Interrupt is reset when the owner (port) of the mailbox reads
the contents of the mailbox. The interrupt flag is set in a
flow-through mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-through mode (i.e., it
follows the clock edge of the reading port).
Master Reset
The QuadPort DSE device undergoes a complete reset by
taking its Master Reset (MRST) input LOW. The Master Reset
input can switch asynchronously to the clocks. A Master Reset
initializes the internal burst counters to zero, and the counter
mask registers to all ones (completely unmasked). A Master
Reset also forces the Mailbox Interrupt (INT) flags and the
Counter Interrupt (CNTINT) flags HIGH, resets the BIST
controller, and takes all registered control signals to a
deselected read state.[56] A Master Reset must be performed
on the QuadPort DSE device after power-up.
Each port can read the other port’s mailbox without resetting
the interrupt. If an application does not require message
passing, INT pins should be treated as no-connect and should
be left floating. When two ports or more write to the same
mailbox at the same time INT will be asserted but the contents
of the mailbox are not guaranteed to be valid.
Interrupts
The upper four memory locations may be used for message
passing and permit communications between ports. Table 3
shows the interrupt operation for all ports. For the 1-Mb
QuadPort DSE device, the highest memory location FFFF is
Table 3. Interrupt Operation Example
Port 1
Port 2
Port 3
A0P3–15P3
Port 4
A0P4–15P4
INTP
4
Function
A0P1–15P1
INTP1
A0P2–15P2
FFFF
X
INTP2
INTP3
Set Port 1 INTP1 Flag
Reset Port 1 INTP1 Flag
Set Port 2 INTP2 Flag
Reset Port 2 INTP2 Flag
Set Port 3 INTP3 Flag
Reset Port 3 INTP3 Flag
Set Port 4 INTP4 Flag
X
FFFF
FFFE
X
L
H
X
X
X
X
X
X
X
X
L
FFFF
X
X
X
X
X
L
FFFF
X
X
X
X
X
X
X
L
X
FFFE
X
FFFE
X
FFFE
FFFD
X
H
X
X
X
X
FFFD
X
X
FFFD
X
FFFD
FFFC
X
H
X
X
FFFC
X
FFFC
X
X
Reset Port 4 INTP4 Flag
FFFC
H
Note:
56. During Master Reset the control signals will be set to a deselected read state: CE0I = LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI =
CNTINCI = VIH; CE1I = VIL. The “I” suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals.
Address Counter Control Operations[31]
Figure 1 provides a block diagram of the readback operation.
Table 2 lists control signals required for counter operations.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for the fast interleaved memory applications.
A port’s burst counter is loaded with the port’s Counter Load
pin (CNTLD). When the port’s Counter Increment (CNTINC) is
asserted, the address counter will increment on each LOW to
HIGH transition of that port’s clock signal. This will read/write
one word from/into each successive address location until
CNTINC is deasserted. Depending on the mask register state,
the counter can address the entire memory array and will loop
back to start. Counter Reset (CNTRST) is used to reset the
Burst Counter (the Mask Register value is unaffected). When
using the counter in readback mode, the internal address
value of the counter will be read back on the address lines
when Counter Readback Signal (CNTRD) is asserted.
The signals are listed based on their priority. For example,
Master Reset takes precedence over Counter Reset, and
Counter Load has lower priority than Mask Register Load
(described below). All counter operations are independent of
Chip Enables (CE0 and CE1). When the address readback
operation is performed the data I/Os are three-stated (if CEs
are active) and one-clock cycle (no-operation cycle) latency is
experienced. The address will be read at time tCA2 from the
rising edge of the clock following the no-operation cycle. The
read back address can be either of the burst counter or the
mask register based on the levels of Counter Read signal
(CNTRD) and Mask Register Read signal (MKRD). Both
signals are synchronized to the port's clock as shown in
Table 2. Counter read has a higher priority than mask read.
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Readback
Register
CNTRD
MKRD
Addr.
Readback
MKLD = 1
Memory
Array
Mask
Register
Bidirectional
Address Lines
Counter/
Address
Register
CNTINC = 1
CNTLD = 1
CNTRST = 1
CLK
Figure 1. Counter and Mask Register Read Back on Address Lines
Counter-Mask Register[31]
CNTINT
H
Example:
Load
Counter-Mask
Register = 3F
0
0
0’s
0
1
1
1
1
1
1
215 214
26 25 24 23 22 21 20
Counter Address
Mask
Register
bit-0
Blocked Address
Load
Address
Counter = 8
H
H
L
X
X
X’s
X’s
X’s
X
0
0
1
0
0
0
1
215 214
26 25 24 23 22 21 20
Address
Counter
bit-0
Max
Address
Register
X
X
X
1
1
1
1
1
215 214
26 25 24 23 22 21 20
Max + 1
Address
Register
X
X
X
0
0
0
0
0
0
215 214
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[57]
The burst counter has a mask register that controls when and
where the counter wraps. An interrupt flag (CNTINT) is
asserted for one clock cycle when the unmasked portion of the
counter address wraps around from all ones (CNTINC must be
asserted) to all zeros. The example in Figure 2 shows the
counter mask register loaded with a mask value of 003F
unmasking the first 6 bits with bit “0” as the LSB and bit “15”
as the MSB. The maximum value the mask register can be
loaded with is FFFF. Setting the mask register to this value
allows the counter to access the entire memory space. The
address counter is then loaded with an initial value of XXX8.
The “blocked” addresses (in this case, the 6th address through
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the 15th address) are loaded with an address but do not
increment once loaded. The counter address will start at
address XXX8. With CNTINC asserted LOW, the counter will
increment its internal address value till it reaches the mask
register value of 3F and wraps around the memory block to
location XXX0. Therefore, the counter uses the mask-register
to define wrap-around point. The mask register of every port
is loaded when MKLD (mask register load) for that port is
LOW. When MKRD is LOW, the value of the mask register can
be read out on address lines in a manner similar to counter
read back operation (see Table 2 for required conditions).
readback) or tCM2 (for mask readback) from the following
port's clock rising edge. Address readback operation is in-
dependent of the port's chip enables (CE0 and CE1). If ad-
dress readback occurs while the port is enabled (chip en-
ables active), the data lines (I/Os) will be three-stated.
4. Hold operation: In order to hold the value of the address
counter at certain address, all signals in Table 2 have to be
HIGH. This operation has the least priority. This operation
is useful in many applications where wait states are needed
or when address is available few cycles ahead of data.
The counter and mask register operations are totally
independent of port chip enables.
When the burst counter is loaded with an address higher than
the mask register value, the higher addresses will form the
masked portion of the counter address and are called blocked
addresses. The blocked addresses will not be changed or
affected by the counter increment operation. The only
exception is mask register bit 0. It can be masked to allow the
address counter to increment by two. If the mask register bit 0
is loaded with a logic value of “0,” then address counter bit 0
is masked and can not be changed during counter increment
operation. If the loaded value for address counter bit 0 is “0,”
the counter will increment by two and the address values are
even. If the loaded value for address counter bit 0 is “1,” the
counter will increment by two and the address values are odd.
This operations allows the user to achieve a 36-bit interface
using any two ports, where the counter of one port counts even
addresses and the counter of the other port counts odd
addresses. This even-odd address scheme stores one half of
the 36-bit word in even memory locations, and the other half
in odd memory locations. CNTINT will be asserted when the
unmasked portion of the counter wraps to all zeros. Loading
mask register bit 0 with “1” allows the counter to increment the
address value sequentially.
IEEE 1149.1 Serial Boundary Scan (JTAG) and
Memory Built-In-Self-Test (MBIST)
The CY7C0430BV incorporates a serial boundary scan test
access port (TAP). This port is fully compatible with IEEE
Standard 1149.1-2001[58]. The TAP operates using JEDEC
standard 3.3V I/O logic levels. It is composed of three input
connections and one output connection required by the test
logic defined by the standard. Memory BIST circuitry will also
be controlled through the TAP interface. All MBIST instructions
are compliant to the JTAG standard. An external clock
(CLKBIST) is provided to allow the user to run BIST at speeds
up to 50 MHz. CLKBIST is multiplexed internally with the ports
clocks during BIST operation.
Disabling the JTAG Feature
It is possible to operate the QuadPort DSE device without
using the JTAG feature. To disable the TAP controller, TCK
must be tied LOW (VSS) to prevent clocking of the device. TDI
and TMS are internally pulled up and may be unconnected.
They may alternately be connected to VDD through a pull-up
resistor. TDO should be left unconnected. CLKBIST must be
tied LOW to disable the MBIST. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
Table 2 groups the operations of the mask register with the
operations of the address counter. Address counter and mask
register signals are all synchronized to the port's clock CLK.
Master reset (MRST) is the only asynchronous signal listed on
Table 2. Signals are listed based on their priority going from
left column to right column with MRST being the highest. A
LOW on MRST will reset both counter register to all zeros and
mask register to all ones. On the other hand, a LOW on
CNTRST will only clear the address counter register to zeros
and the mask register will remain intact.
Test Access Port (TAP)–Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
There are four operations for the counter and mask register:
Test Mode Select
1. Load operation: When CNTLD or MKLD is LOW, the ad-
dress counter or the mask register is loaded with the ad-
dress value presented at the address lines. This value rang-
es from 0 to FFFF (64K). The mask register load operation
has a higher priority over the address counter load opera-
tion.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
2. Increment: Once the address counter is loaded with an ex-
ternal address, the counter can internally increment the ad-
dress value by asserting CNTINC LOW. The counter can
address the entire memory array (depend on the value of
the mask register) and loop back to location 0. The incre-
ment operation is second in priority to load operation.
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
3. Readback: the internal value of either the burst counter or
themaskregistercanbereadoutontheaddresslineswhen
CNTRD or MKRD is LOW. Counter readback has higher
priority over mask register readback. A no-operation delay
cycle is experienced when readback operation is per-
formed. The address will be valid after tCA2 (for counter
Notes:
57. The “X” in this diagram represents the counter upper-bits.
58. Master Reset will reset the JTAG controller.
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Test Data Out (TDO)
TAP Instruction Set
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram (FSM)). The output changes on the falling edge of
TCK. TDO is connected to the least significant bit (LSB) of any
register.
Sixteen different instructions are possible with the 4-bit
instruction register. All combinations are listed in Table 6,
Instruction Codes. Seven of these instructions (codes) are
listed as RESERVED and should not be used. The other nine
instructions are described in detail below.
The TAP controller used in this QuadPort DSE device is fully
compatible[58] with the 1149.1 convention. The TAP controller
can be used to load address, data or control signals into the
QuadPort DSE device and can preload the Input or output
buffers. The QuadPort DSE device implements all of the
1149.1 instructions except INTEST. Table 6 lists all instruc-
tions.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the QuadPort DSE device and may be performed while the
device is operating. At power-up, the TAP is reset internally to
ensure that TDO comes up in a High-Z state.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the QuadPort DSE
device test circuitry. Only one register can be selected at a
time through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK. Data is output on
the TDO pin on the falling edge of TCK.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all 0s.
EXTEST allows circuitry external to the QuadPort DSE device
package to be tested. Boundary-scan register cells at output pins
are used to apply test stimuli, while those at input pins capture
test results.
Instruction Register
Four-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the following JTAG/BIST
Controller diagram. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset state
as described in the previous section.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the identification register. It also places the
identification register between the TDI and TDO pins and
allows the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state. The IDCODE
instruction is loaded into the instruction register upon
power-up or whenever the TAP controller is given a test logic
reset state.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain devices. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
QuadPort DSE device with minimal delay. The bypass register
is set LOW (VSS) when the BYPASS instruction is executed.
High-Z
The High-Z instruction causes the bypass register to be
connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all QuadPort
DSE device outputs into a High-Z state.
Boundary Scan Register
SAMPLE/PRELOAD
The boundary scan register is connected to all the input and
output pins on the QuadPort DSE device. The boundary scan
register is loaded with the contents of the QuadPort DSE
device Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, and SAMPLE/PRELOAD instructions can be
used to capture the contents of the Input and Output ring.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the QuadPort DSE
device clock operates more than an order of magnitude faster.
Because there is a large difference in the clock frequencies, it
is possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the QuadPort DSE device and can be shifted out when the
TAP controller is in the Shift-DR state. The ID register has a
vendor code and other information described in the Identifi-
cation Register Definitions table.
To guarantee that the boundary scan register will capture the
correct value of a signal, the QuadPort DSE device signal
must be stabilized long enough to meet the TAP controller’s
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capture set-up plus hold times. Once the data is captured, it is
possible to shift out the data by putting the TAP into the
Shift-DR state. This places the boundary scan register
between the TDI and TDO pins. If the TAP controller goes into
the Update-DR state, the sampled data will be updated.
connected between TDI and TDO during the internal scan
(INT_SCAN) operation. The MRR will contain the total number
of fail read cycles of the entire MBIST sequence. MRR[0] (bit
0) is the Pass/Fail bit. A “1” indicates some type of failure
occurred, and a “0” indicates entire memory pass.
In order to run BIST in non-debug mode, the two-bit MBIST
Control Register (MCR) is loaded with the default value “00”,
and the TAP controller’s finite state machine (FSM), which is
synchronous to TCK, transitions to Run Test/Idle state. The
entire MBIST test will be performed with a deterministic
number of TCK cycles depending on the TCK and CLKBIST
frequency.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
tCYC[CLKBIST]
--------------------------------------------
× m + SPC
tCYC
=
t
CYC[TCK]
CLAMP
The optional CLAMP instruction allows the state of the signals
driven from QuadPort DSE device pins to be determined from
the boundary-scan register while the BYPASS register is
selected as the serial path between TDI and TDO. CLAMP
controls boundary cells to 1 or 0.
tCYC is total number of TCK cycles required to run MBIST.
SPC is the Synchronization Padding Cycles (4–6 cycles).
m is a constant represents the number of read and write opera-
tions required to run MBIST algorithms (31195136).
Once the entire MBIST sequence is completed, supplying
extra TCK or CLKBIST cycles will have no effect on the MBIST
controller state or the pass-fail status.
CYBIST
CYBIST instruction provides the user with a means of running
a user-accessible self-test function within the QuadPort DSE
device as a result of a single instruction. This permits all
components on a board that offer the CYBIST instruction to
execute their self-tests concurrently, providing a quick check
for the board. The QuadPort DSE device MBIST provides two
modes of operation once the TAP controller is loaded with the
CYBIST instruction:
Debug Mode
With the CYBIST instruction loaded and the MCR loaded with
the value of “01,” and the FSM transitions to RUN_TEST/IDLE
state, the MBIST goes into CYBIST-debug mode. The debug
mode will be used to provide complete failure analysis infor-
mation at the board level. It is recommended that the user runs
the non-debug mode first and then the debug mode in order to
save test time and to set an upper bound on the number of
scan outs that will be needed. The failure data will be scanned
out automatically once a failure occurs using the JTAG TAP
interface. The failure data will be represented by a 100-bit
packet given below. The 100-bit Memory Debug Register
(MDR) will be connected between TDI and TDO, and will be
shifted out on TDO, which is synchronized to TCK.
Non-Debug Mode (Go-NoGo)
The non-debug mode is a go-nogo test used simply to run
BIST and obtain pass-fail information after the test is run. In
addition to that, the total number of failures encountered can
be obtained. This information is used to aid the debug mode
(explained next) of operation. The pass-fail information and
failure count is scanned out using the JTAG interface. An
MBIST Result Register (MRR) will be used to store the
pass-fail results. The MRR is a 25-bit register that will be
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99
98
1
1
62
26
97
P4_IO(17-9)
P3_IO(17-9)
P3_IO(8-0)
P2_IO(17-9)
P2_IO(8-0)
P1_IO(17-9)
P1_IO(8-0)
61
P4_IO(8-0)
25
10
A(15-0)
4
9
MBIST_State
3
P/F
2
TD
1
0
1
1
Figure 3. MBIST Debug Register Packet
Figure 3 is a representation of the 100-bit MDR packet. The
packet follows a two-bit header that has a logic “1” value, and
represents two TCK cycles. MDR[97:26] represent the BIST
comparator values of all four ports (each port has 18 data
lines). A value of “1” indicates a bit failure. The scanned out
data is from LSB to MSB. MDR[25:10] represent the failing
address (MSB to LSB). The state of the BIST controller is
scanned out using MDR[9:4]. Bit 2 is the Test Done bit. A “0”
in bit 2 means test not complete. The user has to monitor this
bit at every packet to determine if more failure packets need
to be scanned out at the end of the BIST operations. If the
value is “0” then BIST must be repeated to capture the next
failing packet. If it is “1,” it means that the last failing packets
have been scanned out. A trailer similar to the header repre-
sents the end of a packet.
(upon master reset) is “00.” Shift_DR state will allow modifying
the MCR to extend the MBIST functionality.
MBIST Control States
Thirty-five states are listed in Table 7. Four data algorithms are
used in debug mode: moving inversion (MIA), march_2 (M2A),
checkerboard (CBA), and unique address algorithm (UAA).
Only Port 1 can write MIA, M2A, and CBA data to the memory.
All four ports can read any algorithm data from the QuadPort
DSE device memory. Ports 2, 3, and 4 will only write UAA data.
Boundary Scan Cells (BSC)
Table 9 lists all QuadPort DSE family I/Os with their associated
BSC. Note that the cells have even numbers. Every I/O has
two boundary scan cells. Bidirectional signals (address lines,
datalines) require two cells so that one (the odd cell) is used
to control a three-state buffer. Input only and output only
signals have an extra dummy cell (odd cells) that are used to
ease device layout.
MCR_SCAN
This instruction will connect the Memory BIST Control
Register (MCR) between TDI and TDO. The default value
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TAP Controller State Diagram (FSM)[59]
TEST-LOGIC
1
RESET
0
1
1
1
RUN_TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
59. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK.
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JTAG/BIST TAP Controller Block Diagram
0
Bypass Register (BYR)
1
0
MBIST Control Register (MCR)
3 2
1
0
Instruction Register (IR)
24 23
0
Selection
Circuitry
MBIST Result Register (MRR)
TDI
TDO
31 30 29
0
Identification Register (IDR)
(MUX)
99
0
MBIST Debug Register (MDR)
0
391
Boundary Scan Register (BSR)
BIST
CONTROLLER
TAP
CONTROLLER
TCK
CLKBIST
TMS
MRST
MEMORY
CELL
Table 4. Identification Register Definitions
Instruction Field
Value
Description
Reserved for version number
Defines Cypress part number
Revision Number (31:28)
Cypress Device ID (27:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
1h
C000h
34h
1
Allows unique identification of QuadPort DSE device vendor
Indicate the presence of an ID register
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Table 5. Scan Registers Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
Identification (IDR)
MBIST Control (MCR)
MBIST Result (MRR)
MBIST Debug (MDR)
Boundary Scan (BSR)
32
2
25
100
392
Table 6. Instruction Identification Codes
Instruction Code
EXTEST
Description
0000
Captures the Input/Output ring contents. Places the boundary scan register (BSR)
between the TDI and TDO.
BYPASS
IDCODE
1111
0111
Places the bypass register (BYR) between TDI and TDO.
Loads the ID register (IDR) with the vendor ID code and places the register
between TDI and TDO.
HIGHZ
0110
0101
Places the BYR between TDI and TDO. Forces all QuadPort DSE device output
drivers to a High-Z state.
CLAMP
Controls boundary to 1/0. Uses BYR.
SAMPLE/PRELOAD 0001
Captures the Input/Output ring contents. Places the boundary scan register (BSR)
between TDI and TDO.
CYBIST
1000
0010
Invokes MBIST. Places the MBIST Debug register (MDR) between TDI and TDO.
INT_SCAN
Scansout pass-fail information. Places MBIST Result Register (MRR) between TDI
and TDO.
MCR_SCAN
RESERVED
0011
Presets CYBIST mode. Places MBIST Control Register (MCR) between TDI and
TDO.
All other codes Seven combinations are reserved. Do not use other than the above.
Table 7. MBIST Control States
States Code
State Name
Description
000001
movi_zeros
Port 1 write all zeros to the QuadPort DSE device memory using Moving
Inversion Algorithm (MIA).
000011
000010
movi_1_upcnt
Up count from 0 to 64K (depth of QuadPort DSE device). All ports read 0s,
then Port 1 writes 1s to all memory locations using MIA, then all ports read
1s. MIA read0_write1_read1 (MIA_r0w1r1).
movi_0_upcnt
Up count from 0 to 64K. All ports read 1s, then Port 1 writes 0s, then all ports
read 0s (MIA_r1w0r0).
000110
000111
000101
movi_1_downcnt
movi_0_downcnt
movi_read
Down count from 64K to 0. MIA_r0w1r1.
Down count MIA_r1w0r0.
Read all 0s.
000100
001100
001101
001111
mar2_zeros
Port 1 write all zeros to memory using March2 Algorithm (M2A).
Up count M2A_r0w1r1.
mar2_1_upcnt
mar2_0_upcnt
mar2_1_downcnt
Up count M2A_r1w0r0.
Down count M2A_r0w1r1.
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CY7C0430BV
CY7C04312BV
CY7C04314BV
Table 7. MBIST Control States (continued)
States Code
001110
State Name
mar2_0_downcnt
mar2_read
Description
Down count M2A_r1w0r0.
Read all 0s.
001010
001011
001001
001000
011000
chkr_w
Port 1 writes topological checkerboard data to memory.
All ports read topological checkerboard data.
chkr_r
n_chkr_w
n_chkr_r
Port 1 write inverse topological checkerboard data.
All ports read inverse topological checkerboard data.
011001
011011
011010
011110
011111
011101
uaddr_zeros2
uaddr_write2
uaddr_read2
uaddr_ones2
n_uaddr_write2
n_uaddr_read2
Port 2 write all zeros to memory using Unique Address Algorithm (UAA).
Port 2 writes every address value into its memory location (UAA).
All ports read UAA data.
Port 2 writes all ones to memory.
Port 2 writes inverse address value into memory.
All ports read inverse UAA data.
011001
011011
011010
011110
011111
011101
uaddr_zeros3
uaddr_write3
uaddr_read3
uaddr_ones3
n_uaddr_write3
n_uaddr_read3
Port 3 write all zeros to memory using Unique Address Algorithm (UAA).
Port 3 writes every address value into its memory location (UAA).
All ports read UAA data.
Port 3 writes all ones to memory.
Port 3 writes inverse address value into memory.
All ports read inverse UAA data.
011001
011011
011010
011110
011111
011101
uaddr_zeros4
uaddr_write4
uaddr_read4
uaddr_ones4
n_uaddr_write4
n_uaddr_read4
Port 4 write all zeros to memory using Unique Address Algorithm (UAA).
Port 4 writes every address value into its memory location (UAA).
All ports read UAA data.
Port 4 writes all ones to memory.
Port 4 writes inverse address value into memory.
All ports read inverse UAA data.
110010
complete
Test complete.
Table 9. Boundary Scan Order (continued)
Table 8. MBIST Control Register (MCR)
MCR[1:0]
Cell #
16
Signal Name
A7_P4
Bump (Ball) ID
Mode
00
01
10
11
Non-Debug
Debug
F20
F19
F18
E20
E19
D19
D18
C20
C19
F17
K18
H18
H17
18
20
22
24
26
28
30
32
34
36
38
40
A8_P4
Reserved
Reserved
A9_P4
A10_P4
A11_P4
Table 9. Boundary Scan Order
A12_P4
Cell #
Signal Name
A0_P4
Bump (Ball) ID
A13_P4
2
4
6
8
K20
J19
A14_P4
A1_P4
A2_P4
A3_P4
A4_P4
A5_P4
A6_P4
A15_P4
J18
CNTINT_P4
CNTRST_P4
MKLD_P4
CNTLD_P4
H20
H19
G19
G18
10
12
14
Document #: 38-06027 Rev. *A
Page 32 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
42 CNTINC_P4
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
124 CLK_P3
G17
E17
E18
A20
B19
D17
C16
C18
C17
K19
K17
L20
M19
M18
N20
N19
P19
P18
R20
R19
R18
T20
T19
U19
U18
V20
V19
R17
L18
N18
N17
P17
T17
T18
Y20
W19
U17
V16
V18
V17
L19
M17
Y15
W15
Y16
W16
Y17
W17
Y18
W18
Y19
V12
Y11
W12
Y12
W13
Y13
V15
Y14
W14
Y6
44
CNTRD_P4
MKRD_P4
LB_P4
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
IO0_P4
IO1_P4
IO2_P4
IO3_P4
IO4_P4
IO5_P4
IO6_P4
IO7_P4
IO8_P4
IO0_P3
IO1_P3
IO2_P3
IO3_P3
IO4_P3
IO5_P3
IO6_P3
IO7_P3
IO8_P3
IO0_P1
IO1_P1
IO2_P1
IO3_P1
IO4_P1
IO5_P1
IO6_P1
IO7_P1
IO8_P1
IO0_P2
IO1_P2
IO2_P2
IO3_P2
IO4_P2
IO5_P2
IO6_P2
IO7_P2
IO8_P2
A0_P2
46
48
50
UB_P4
52
OE_P4
54
R/W_P4
CE1_P4
CE0_P4
INT_P4
56
58
60
62
CLK_P4
A0_P3
64
66
A1_P3
68
A2_P3
70
A3_P3
72
A4_P3
74
A5_P3
76
A6_P3
78
A7_P3
80
A8_P3
82
A9_P3
W6
Y5
84
A10_P3
A11_P3
A12_P3
A13_P3
A14_P3
A15_P3
CNTINT_P3
CNTRST_P3
MKLD_P3
CNTLD_P3
CNTINC_P3
CNTRD_P3
MKRD_P3
LB_P3
86
W5
Y4
88
90
W4
Y3
92
94
W3
Y2
96
98
V9
100
102
104
106
108
110
112
114
116
118
120
122
Y10
W9
Y9
W8
Y8
V6
UB_P3
Y7
OE_P3
W7
L1
R/W_P3
CE1_P3
CE0_P3
INT_P3
A1_P2
M2
A2_P2
M3
A3_P2
N1
Document #: 38-06027 Rev. *A
Page 33 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
206 A4_P2
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
288 A14_P1
N2
P2
P3
R1
R2
R3
T1
T2
U2
U3
V1
V2
R4
L3
C1
C2
F4
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
264
266
268
270
272
274
276
278
280
282
284
286
A5_P2
290
292
294
296
298
300
302
304
306
308
310
312
314
316
318
320
322
324
326
328
330
332
334
336
338
340
342
344
346
348
350
352
354
356
358
360
362
364
366
368
A15_P1
A6_P2
CNTINT_P1
CNTRST_P1
MKLD_P1
CNTLD_P1
CNTINC_P1
CNTRD_P1
MKRD_P1
LB_P1
A7_P2
K3
H3
H4
G4
E4
E3
A1
B2
D4
C5
C3
C4
K2
K4
A6
B6
A5
B5
A4
B4
A3
B3
A2
C9
A10
B9
A9
B8
A8
C6
A7
B7
A15
B15
A16
B16
A17
B17
A8_P2
A9_P2
A10_P2
A11_P2
A12_P2
A13_P2
A14_P2
A15_P2
CNTINT_P2
CNTRST_P2
MKLD_P2
CNTLD_P2
CNTINC_P2
CNTRD_P2
MKRD_P2
LB_P2
UB_P1
OE_P1
R/W_P1
CE1_P1
CE0_P1
INT_P1
N3
N4
P4
T4
T3
Y1
W2
U4
V5
V3
V4
L2
CLK_P1
IO9_P2
IO10_P2
IO11_P2
IO12_P2
IO13_P2
IO14_P2
IO15_P2
IO16_P2
IO17_P2
IO9_P1
UB_P2
OE_P2
R/W_P2
CE1_P2
CE0_P2
INT_P2
CLK_P2
A0_P1
M4
K1
J2
IO10_P1
IO11_P1
IO12_P1
IO13_P1
IO14_P1
IO15_P1
IO16_P1
IO17_P1
IO9_P3
A1_P1
A2_P1
J3
A3_P1
H1
H2
G2
G3
F1
F2
F3
E1
E2
D2
D3
A4_P1
A5_P1
A6_P1
A7_P1
A8_P1
A9_P1
IO10_P3
IO11_P3
IO12_P3
IO13_P3
IO14_P3
A10_P1
A11_P1
A12_P1
A13_P1
Document #: 38-06027 Rev. *A
Page 34 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
370 IO15_P3
A18
B18
A19
C12
A11
B12
A12
B13
A13
C15
A14
B14
372
374
376
378
380
382
384
386
388
390
392
IO16_P3
IO17_P3
IO9_P4
IO10_P4
IO11_P4
IO12_P4
IO13_P4
IO14_P4
IO15_P4
IO16_P4
IO17_P4
Ordering Information
10 Gb/s 3.3V QuadPort DSE Family 1 Mb (64K × 18)
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C0430BV-133BGC
CY7C0430BV-133BGI
CY7C0430BV-100BGC
CY7C0430BV-100BGI
Package Type
272-ball Grid Array (BGA)
133
BG272
BG272
BG272
BG272
Commercial
Industrial
272-ball Grid Array (BGA)
272-ball Grid Array (BGA)
272-ball Grid Array (BGA)
100
Commercial
Industrial
10 Gb/s 3.3V QuadPort DSE Family 1/2 Mb (32K x 18)
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C04312BV-133BGC
CY7C04312BV-100BGC
Package Type
133
100
BG272
BG272
272-ball Grid Array (BGA)
272-ball Grid Array (BGA)
Commercial
10 Gb/s 3.3V QuadPort DSE Family 1/4 Mb (16K x 18)
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C04314BV-133BGC
CY7C04314BV-100BGC
Package Type
133
100
BG272
BG272
272-ball Grid Array (BGA)
272-ball Grid Array (BGA)
Commercial
Document #: 38-06027 Rev. *A
Page 35 of 37
CY7C0430BV
CY7C04312BV
CY7C04314BV
Package Diagram
272-ball Ball Grid Array (27 x 27 x 1.27 mm) BG272
51-85130
QuadPort is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-06027 Rev. *A
Page 36 of 37
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document Title: CY7C430BV, CY7C04312BV, CY7C04314BV 10 Gb/s 3.3V QuadPort DSE Family
Document Number: 38-06027
Issue
Orig. of
Change
REV.
**
ECN NO.
109906
115042
Date
Description of Change
09/10/01
05/23/02
SZV
FSG
Change from Spec number: 38-01052 to 38-06027
*A
Remove Preliminary, TM from DSE.
Change RUNBIST to CYBIST.
Updated ISB values.
Added notes 9 and 14.
Increased commercial prime bin to 135 MHz.
Document #: 38-06027 Rev. *A
Page 37 of 37
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