CY7C0431V18-167BBI_技术文档

CY7C0452V18/0451V18/0450V18

CY7C0431V18/0430V18

PRELIMINARY

QuadPort™ Datapath Switching Element (DSE) Family

• Simple array partitioning (except CY7C0452V18)

— Internal mask register for burst counter control

Features

• The QuadPort™ Datapath Switching Element (DSE)

allows four independent ports of access for data path

management and switching.

— Counter-Interrupt flags to indicate terminal count

— Block Retransmit Capability

• Synchronous pipelined device

— 128K x 40 (5 Mb) CY7C0452V18

— 64K x 40 (2 Mb) CY7C0451V18

— 32K x 40 (1 Mb) CY7C0450V18

— 128K x 20 (2 Mb) CY7C0431V18

— Counter and mask register readback on address

lines

• DualChipEnablesonallportsforeasydepthexpansion

(except CY7C0452V18)

• Separate byte select controls on all ports

• BGA package (676 balls, 27 x 27 mm, 1.0 mm pitch)

• Commercial and Industrial temperature ranges

• IEEE 1149.1 JTAG boundary scan

— 64K x 20 (1 Mb) CY7C0430V18

• Clock operation up to 167 MHz

• High Bandwidth up to 27 Gbps

• LVTTL and SSTL2 I/O standard for I/O

• LVPECL differential clock inputs

• Impedance matching on data outputs

• 1.8V Supply Voltage

— Active = 1300 mA (maximum)

— Standby = 500 mA (maximum)

QuadPort DSE Applications

PORT 1

PORT 3

PORT 2

PORT 4

BUFFERED SWITCH

PORT 2

PORT 3

PORT 4

PORT 1

REDUNDANT DATA MIRROR

PORT 1

PORT 2

PORT 3

PORT 4

DATA PATH AGGREGATOR

Cypress Semiconductor Corporation

Document #: 38-06065 Rev. **

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised August 2, 2002

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Pin Configuration

676 Ball Grid Array (BGA) (CY7C0451V18)^[1]

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

VSS

AIO

P1

RWB

P1

VDD

C

VDD

C

VDD

A

P1

VDD

A

P1

VDD

A

P1

VDD

A

P1

VDD

A

P1

VDD

A

P1

VDD

A

P4

VDD

A

P4

VDD

A

P4

VDD

A

P4

VDD

A

P4

VDD

A

P4

VDD

C

VDD

C

RWB

P4

AIO

P4

VSS

A

DIO

P1

B2B

P1

B3B

P1

MKL

DB

RETX

B

CN-

TRDB

P1

WRP

0B

VDD

NC

CNTI

NTB

P1

A2

P1

A7

P1

A12

P1

A12

P4

A7

P4

A2

P4

CNTI

NTB

P4

VDD

NC

VDD

WRP

0B

CN-

TRDB

P4

RETX

B

MKL

DB

B3B

P4

B2B

P4

DIO

P4

B

C

B

C

P1

P4

B0B

P1

B1B

P1

CE1

P1

CE0B

P1

CN-

TRST

B

CNTL

DB

P1

CNTI

NCB

P1

MKR

DB

P1

INTB

P1

A3

P1

A8

P1

A13

P1

A13

P4

A8

P4

A3

P4

INTB

P4

MKR

DB

P4

CNTI

NCB

P4

CNTL

DB

P4

CN-

TRST

B

CE0B

P4

CE1

P4

B1B

P4

B0B

P4

P1

P4

VDD

Q

DQ0

P1

DQ1

P1

DQ2

P1

DQ3

P1

DQ4

P1

VSS

TRST

TMS

TCK

NC

TDI

REA

DYB

P1

A4

P1

A9

P1

A14

P1

A14

P4

A9

P4

A4

P4

REA

DYB

P4

NC

VSS

DQ4

P4

DQ3

P4

DQ2

P4

DQ1

P4

DQ0

P4

VDD

Q

D

E

D

E

P1

P4

VDD

Q

P1

DQ5

P1

DQ6

P1

DQ7

P1

DQ8

P1

DQ9

P1

A0

P1

A5

P1

A10

P1

A15

P1

A15

P4

A10

P4

A5

P4

A0

P4

NC

VSS

DQ9

P4

DQ8

P4

DQ7

P4

DQ6

P4

DQ5

P4

VDD

Q

P4

VDD

Q

P1

DQ10

P1

DQ11

P1

DQ12

P1

DQ13

P1

DQ14

P1

TDO

VSS

NC

A1

P1

A6

P1

A11

P1

NC

A11

P4

A6

P4

A1

P4

VSS

NC

DQ14

P4

DQ13

P4

DQ12

P4

DQ11

P4

DQ10

P4

VDD

Q

P4

F

VDD

Q

P1

DQ15

P1

DQ16

P1

DQ17

P1

DQ18

P1

DQ19

P1

VSS

DQ19

P4

DQ18

P4

DQ17

P4

DQ16

P4

DQ15

P4

VDD

Q

P4

G

H

G

H

VDD

C

ZQ

P1

OEB

P1

C+

P1

VSS

REFA

P1

REFA

P1

REFA

P1

REFA

P1

REFA

P4

REFA

P4

REFA

P4

REFA

P4

C+

P4

OEB

P4

ZQ

P4

VDD

C

VDD

Q

P1

VDD

DOFF

B

P1

C-

P1

VSS

C-

P4

DOFF

B

P4

VDD

Q

P4

J

VDD

Q

P1

DQ20

P1

DQ21

P1

DQ22

P1

DQ23

P1

DQ24

P1

REF

Q

P1

REF

Q

P4

DQ24

P4

DQ23

P4

DQ22

P4

DQ21

P4

DQ20

P4

VDD

Q

P4

K

VDD

Q

P1

DQ25

P1

DQ26

P1

DQ27

P1

DQ28

P1

DQ29

P1

REF

Q

P1

REF

Q

P4

DQ29

P4

DQ28

P4

DQ27

P4

DQ26

P4

DQ25

P4

VDD

Q

P4

L

VDD

Q

P1

DQ30

P1

DQ31

P1

DQ32

P1

DQ33

P1

DQ34

P1

REF

Q

P1

REF

Q

P4

DQ34

P4

DQ33

P4

DQ32

P4

DQ31

P4

DQ30

P4

VDD

Q

P4

M

N

M

N

VDD

Q

P1

DQ35

P1

DQ36

P1

DQ37

P1

DQ38

P1

DQ39

P1

REF

Q

P1

REF

Q

P4

DQ39

P4

DQ38

P4

DQ37

P4

DQ36

P4

DQ35

P4

VDD

Q

P4

VDD

Q

P2

DQ35

P2

DQ36

P2

DQ37

P2

DQ38

P2

DQ39

P2

REF

Q

P2

REF

Q

P3

DQ39

P3

DQ38

P3

DQ37

P3

DQ36

P3

DQ35

P3

VDD

Q

P3

P

VDD

Q

P2

DQ30

P2

DQ31

P2

DQ32

P2

DQ33

P2

DQ34

P2

REF

Q

P2

REF

Q

P3

DQ34

P3

DQ33

P3

DQ32

P3

DQ31

P3

DQ30

P3

VDD

Q

P3

R

VDD

Q

P2

DQ25

P2

DQ26

P2

DQ27

P2

DQ28

P2

DQ29

P2

REF

Q

P2

REF

Q

P3

DQ29

P3

DQ28

P3

DQ27

P3

DQ26

P3

DQ25

P3

VDD

Q

P3

T

VDD

Q

P2

DQ20

P2

DQ21

P2

DQ22

P2

DQ23

P2

DQ24

P2

REF

Q

P2

REF

Q

P3

DQ24

P3

DQ23

P3

DQ22

P3

DQ21

P3

DQ20

P3

VDD

Q

P3

U

VDD

Q

P2

VDD

DOFF

B

P2

C-

P2

VSS

C-

P3

DOFF

B

P3

VDD

Q

P3

VDD

V

VDD

C

ZQ

P2

OEB

P2

C+

P2

REFA

P2

REFA

P2

REFA

P2

REFA

P2

REFA

P3

REFA

P3

REFA

P3

REFA

P3

C+

P3

OEB

P3

ZQ

P3

VDD

C

W

Y

W

Y

VDD

Q

P2

DQ15

P2

DQ16

P2

DQ17

P2

DQ18

P2

DQ19

P2

MRS

TB

VSS

NC

VSS

NC

VSS

DQ19

P3

DQ18

P3

DQ17

P3

DQ16

P3

DQ15

P3

VDD

Q

P3

VDD

Q

P2

DQ10

P2

DQ11

P2

DQ12

P2

DQ13

P2

DQ14

P2

NC

A1

P2

A6

P2

A11

P2

A11

P3

A6

P3

A1

P3

DQ14

P3

DQ13

P3

DQ12

P3

DQ11

P3

DQ10

P3

VDD

Q

P3

AA

AB

AC

AD

AA

AB

AC

AD

VDD

Q

P2

DQ5

P2

DQ6

P2

DQ7

P2

DQ8

P2

DQ9

P2

NC

A0

P2

A5

P2

A10

P2

A15

P2

A15

P3

A10

P3

A5

P3

A0

P3

DQ9

P3

DQ8

P3

DQ7

P3

DQ6

P3

DQ5

P3

VDD

Q

P3

VDD

Q

P2

DQ0

P2

DQ1

P2

DQ2

P2

DQ3

P2

DQ4

P2

NC

REA

DYB

P2

A4

P2

A9

P2

A14

P2

A14

P3

A9

P3

A4

P3

REA

DYB

P3

DQ4

P3

DQ3

P3

DQ2

P3

DQ1

P3

DQ0

P3

VDD

Q

P3

B0B

P2

B1B

P2

CE1

P2

CE0B

P2

CN-

TRST

B

CNTL

DB

P2

CNTI

NCB

P2

MKR

DB

P2

NC

INTB

P2

A3

P2

A8

P2

A13

P2

A13

P3

A8

P3

A3

P3

INTB

P3

NC

MKR

DB

P3

CNTI

NCB

P3

CNTL

DB

P3

CN-

TRST

B

CE0B

P3

CE1

P3

B1B

P3

B0B

P3

P2

P3

DIO

P2

B2B

P2

B3B

P2

MKL

DB

RETX

B

CN-

TRDB

P2

WRP

0B

VDD

CNTI

NTB

P2

A2

P2

A7

P2

A12

P2

A12

P3

A7

P3

A2

P3

CNTI

NTB

P3

VDD

WRP

0B

CN-

TRDB

P3

RETX

B

MKL

DB

B3B

P3

B2B

P3

DIO

P3

AE

AF

AE

AF

P2

P3

VSS

AIO

P2

RWB

P2

VDD

C

VDD

C

VDD

A

P2

VDD

A

P2

VDD

A

P2

VDD

A

P2

VDD

A

P2

VDD

A

P2

VDD

A

P3

VDD

A

P3

VDD

A

P3

VDD

A

P3

VDD

A

P3

VDD

A

P3

VDD

C

VDD

C

RWB

P3

AIO

P3

VSS

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Note:

1. B Following a Pin name represents an active LOW signal. For example, B0B P1 = B0 P1.

Document #: 38-06065 Rev. **

Page 2 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)

Table 1. 676 BGA Pin Table (CY7C0451V18)

VSSPIN

B19

B20

B21

B22

B23

B24

B25

B26

C1

CY7C0451V18

VDD

VSSPIN

A1

CY7C0451V18

VSS

AIO P1

WRP0B P4

CNTRDB P4

RETXB P4

MKLDB P4

B3B P4

A2

A3

RWB P1

VDDC

A4

A5

VDDC

A6

VDDA P1

VDD

B2B P4

A7

DIO P4

A8

B0B P1

A9

VDD

C2

B1B P1

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B1

VDDA P1

VDDA P4

VDD

C3

CE1 P1

C4

CE0B P1

CNTRSTB P1

CNTLDB P1

CNTINCB P1

MKRDB P1

NC

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

INTB P1

A3 P1

VDD

A8 P1

VDDA P4

VDDC

A13 P1

A13 P4

A8 P4

VDDC

A3 P4

RWB P4

AIO P4

INTB P4

NC

VSS

MKRDB P4

CNTINCB P4

CNTLDB P4

CNTRSTB P4

CE0B P4

CE1 P4

DIO P1

B2B P1

B3B P1

MKLDB P1

RETXB P1

CNTRDB P1

WRP0B P1

VDD

B2

B3

B4

B5

B6

B1B P4

B7

B0B P4

B8

VDDQ P1

DQ0 P1

DQ1 P1

DQ2 P1

DQ3 P1

DQ4 P1

VSS

B9

VDD

D2

B10

B11

B12

B13

B14

B15

B16

B17

B18

CNTINTB P1

A2 P1

D3

D4

A7 P1

D5

A12 P1

A12 P4

A7 P4

D6

D7

D8

TRST

A2 P4

D9

NC

CNTINTB P4

VDD

D10

READYB P1

Document #: 38-06065 Rev. **

Page 3 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)

VSSPIN

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

E1

CY7C0451V18

A4 P1

VSSPIN

F3

CY7C0451V18

DQ11 P1

DQ12 P1

DQ13 P1

DQ14 P1

VSS

A9 P1

F4

A14 P1

A14 P4

A9 P4

F5

F6

F7

A4 P4

F8

TCK

READYB P4

NC

F9

TDO

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

G1

A1 P1

A6 P1

A11 P1

NC

VSS

DQ4 P4

DQ3 P4

DQ2 P4

DQ1 P4

DQ0 P4

VDDQ P4

VDDQ P1

DQ5 P1

DQ6 P1

DQ7 P1

DQ8 P1

DQ9 P1

VSS

NC

A11 P4

A6 P4

A1 P4

VSS

E2

VSS

E3

DQ 14 P4

DQ13 P4

DQ12 P4

DQ11 P4

DQ10 P4

VDDQ P4

VDDQ P1

DQ15 P1

DQ16 P1

DQ17 P1

DQ18 P1

DQ19 P1

VSS

E4

E5

E6

E7

E8

TMS

E9

TDI

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

A0 P4

G2

A5 P1

G3

A10 P1

A15 P1

A15 P4

A10 P4

A5 P4

G4

G5

G6

G7

G8

NC

A0 P1

G9

VSS

NC

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

VSS

DQ9 P4

DQ8 P4

DQ7 P4

DQ6 P4

DQ5 P4

VDDQ P4

VDDQ P1

DQ10 P1

VSS

F2

VSS

Document #: 38-06065 Rev. **

Page 4 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)

VSSPIN

G21

G22

G23

G24

G25

G26

H1

CY7C0451V18

DQ19 P4

DQ18 P4

DQ17 P4

DQ16 P4

DQ15 P4

VDDQ P4

VDD

VSSPIN

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

K1

CY7C0451V18

VSS

H2

VDD

VSS

H3

VDDC

C– P4

H4

ZQ P1

DOFFB P4

VDD

H5

OEB P1

C+ P1

H6

VDDQ P4

VDD

H7

VSS

H8

VSS

VDD

H9

VSS

VDD1 P1

DQ20 P1

DQ21 P1

DQ22 P1

DQ23 P1

DQ24 P1

VSS

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

J1

VREFA P1

VREFA P4

VSS

K2

K3

K4

K5

K6

K7

K8

VREFQ P1

VSS

K9

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

L1

VSS

C+ P4

VSS

OEB P4

ZQ P4

VSS

VDDC

VSS

VDD

VSS

VDD

VSS

VDD

VREFQ P4

VSS

J2

VDD

J3

VDDQ P1

VDD

DQ24 P4

DQ23 P4

DQ22 P4

DQ21 P4

DQ20 P4

VDDQ P4

VDDQ P1

DQ25 P1

DQ26 P1

DQ27 P1

J4

J5

DOFFB P1

C– P1

J6

J7

VSS

J8

VSS

J9

VSS

J10

J11

J12

VSS

L2

VSS

L3

VSS

L4

Document #: 38-06065 Rev. **

Page 5 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)

VSSPIN

L5

CY7C0451V18

DQ28 P1

DQ29 P1

VSS

VSSPIN

M23

M24

M25

M26

N1

CY7C0451V18

DQ32 P4

DQ31 P4

DQ30 P4

VDDQ P4

VDDQ P1

DQ35 P1

DQ36 P1

DQ37 P1

DQ38 P1

DQ39 P1

VSS

L6

L7

L8

VREFQ P1

VSS

L9

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

M1

VSS

N2

VSS

N3

VSS

N4

VSS

N5

VSS

N6

VSS

N7

VSS

N8

VREFQ P1

VSS

N9

VSS

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

P1

VSS

VREFQ P4

VSS

DQ29 P4

DQ28 P4

DQ27 P4

DQ26 P4

DQ25 P4

VDDQ P4

VDDQ P1

DQ30 P1

DQ31 P1

DQ32 P1

DQ33 P1

DQ34 P1

VSS

VREFQ P4

VSS

M2

M3

DQ39 P4

DQ38 P4

DQ37 P4

DQ36 P4

DQ35 P4

VDDQ P4

VDDQ P2

DQ35 P2

DQ36 P2

DQ37 P2

DQ38 P2

DQ39 P2

VSS

M4

M5

M6

M7

M8

VREFQ P1

VSS

M9

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

VSS

P2

VSS

P3

VSS

P4

VSS

P5

VSS

P6

VSS

P7

VSS

P8

VREFQ P2

VSS

P9

VSS

P10

P11

P12

P13

P14

VSS

VREFQ P4

VSS

DQ34 P4

DQ33 P4

VSS

Document #: 38-06065 Rev. **

Page 6 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)

VSSPIN

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

R1

CY7C0451V18

VSS

VSSPIN

T7

CY7C0451V18

VSSVSS

VREFQ P2

VSS

T8

VSS

T9

VSS

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

U1

VSS

VREFQ P3

VSS

DQ39 P3

DQ38 P3

DQ37 P3

DQ36 P3

DQ35 P3

VDDQ P3

VDDQ P2

DQ30 P2

DQ31 P2

DQ32 P2

DQ33 P2

DQ34 P2

VSS

VREFQ P3

VSS

R2

R3

DQ29 P3

DQ28 P3

DQ27 P3

DQ26 P3

DQ25 P3

VDDQ P3

VDDQ P2

DQ20 P2

DQ21 P2

DQ22 P2

DQ23 P2

DQ24 P2

VSS

R4

R5

R6

R7

R8

VREFQ P2

VSS

R9

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

T1

VSS

U2

VSS

U3

VSS

U4

VSS

U5

VSS

U6

VSS

U7

VSS

U8

VREFQ P2

VSS

U9

VSS

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

VSS

VREFQ P3

VSS

DQ34 P3

DQ33 P3

DQ32 P3

DQ31 P3

DQ30 P3

VDDQ P3

VDDQ P2

DQ25 P2

DQ26 P2

DQ27 P2

DQ28 P2

DQ29 P2

VSS

VREFQ P3

VSS

T2

T3

DQ24 P3

DQ23 P3

DQ22 P3

DQ21 P3

T4

T5

T6

Document #: 38-06065 Rev. **

Page 7 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)

VSSPIN

U25

U26

V1

CY7C0451V18

DQ20 P3

VDDQ P3

VDD

VSSPIN

W17

W18

W19

W20

W21

W22

W23

W24

W25

W26

Y1

CY7C0451V18

VREFA P3

VSS

V2

VDD

VSS

V3

VDDQ P2

VDD

C+ P3

V4

OEB P3

ZQ P3

VDDC

V5

DOFFB P2

C– P2

VSS

V6

V7

VDD

V8

VSS

VDD

V9

VSS

VDDQ P2

DQ15 P2

DQ16 P2

DQ17 P2

DQ18 P2

DQ19 P2

VSS

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

W1

VSS

Y2

VSS

Y3

VSS

Y4

VSS

Y5

VSS

Y6

VSS

Y7

VSS

Y8

MRSTB

VSS

Y9

VSS

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

VSS

C- P3

VSS

DOFFB P3

VDD

VSS

VDDQ P3

VDD

VSS

VDD

VSS

VDD

VSS

W2

VDD

VSS

W3

VDDC

ZQ P2

OEB P2

C+ P2

VSS

DQ19 P3

DQ18 P3

DQ17 P3

DQ16 P3

DQ15 P3

VDDQ P3

VDDQ P2

DQ10 P2

DQ11 P2

DQ12 P2

DQ13 P2

DQ14 P2

VSS

W4

W5

W6

W7

W8

VSS

W9

VSS

W10

W11

W12

W13

W14

W15

W16

VREFA P2

VREFA P3

NC

Document #: 38-06065 Rev. **

Page 8 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)

VSSPIN

AA9

CY7C0451V18

NC

VSSPIN

AC1

CY7C0451V18

VDDQ P2

DQ0 P2

DQ1 P2

DQ2 P2

DQ3 P2

DQ4 P2

VSS

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AB1

A1 P2

AC2

A6 P2

AC3

A11 P2

NC

AC4

AC5

NC

AC6

A11 P3

A6 P3

AC7

AC8

NC

A1 P3

AC9

NC

VSS

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

READYB P2

A4 P2

VSS

A9 P2

DQ 14 P3

DQ13 P3

DQ12 P3

DQ11 P3

DQ10 P3

VDDQ P3

VDDQ P2

DQ5 P2

DQ6 P2

DQ7 P2

DQ8 P2

DQ9 P2

VSS

A14 P2

A14 P3

A9 P3

A4 P3

READYB P3

NC

VSS

AB2

VSS

AB3

DQ4 P3

DQ3 P3

DQ2 P3

DQ1 P3

DQ0 P3

VDDQ P3

B0B P2

B1B P2

CE1 P2

CE0B P2

CNTRSTB P2

CNTLDB P2

CNTINCB P2

MKRDB P2

NC

AB4

AB5

AB6

AB7

AB8

NC

AB9

NC

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

A0 P2

AD2

A5 P2

AD3

A10 P2

A15 P2

A15 P3

A10 P3

A5 P3

AD4

AD5

AD6

AD7

AD8

A0 P3

AD9

VSS

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

INTB P2

A3 P2

VSS

A8 P2

DQ9 P3

DQ8 P3

DQ7 P3

DQ6 P3

DQ5 P3

VDDQ P3

A13 P2

A13 P3

A8 P3

A3 P3

INTB P3

NC

Document #: 38-06065 Rev. **

Page 9 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)

VSSPIN

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

CY7C0451V18

MKRDB P3

CNTINCB P3

CNTLDB P3

CNTRSTB P3

CE0B P3

CE1 P3

VSSPIN

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

CY7C0451V18

VDDA P2

VDDA P3

VDD

B1B P3

B0B P3

DIO P2

VDD

AE2

B2B P2

VDDA P3

VDDC

AE3

B3B P2

AE4

MKLDB P2

RETXB P2

CNTRDB P2

WRP0B P2

VDD

AE5

VDDC

AE6

RWB P3

AIO P3

AE7

AE8

VSS

AE9

VDD

Functional Description

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF1

CNTINTB P2

A2 P2

The CY7C0452V18/0451V18/0450V18/0431V18/0430V18 is

a family of synchronous true four-ported Datapath Switching

Element (DSE), up to 27 Gb/s and 5 Mb density. All four ports

may be clocked at independent frequencies from one another.

Writes and reads are permitted simultaneously from all four

ports to the switch array. Simultaneous reads are allowed for

accesses to the same address location; however, simulta-

neous reading and writing to the same location is not allowed.

A7 P2

A12 P2

A12 P3

A7 P3

A2 P3

The QuadPort DSE family can be clocked with synchronous,

pipelined accesses up to 167 MHz. Clock to data valid as low

as t_CD= 3.5 ns. Registers on control, address and data lines

allow for minimal set-up and hold time.

CNTINTB P3

VDD

The QuadPort DSE family supports a burst counter for block

transfers of data. The QuadPort DSE also supports features

such as: impedance matching, memory block retransmit capa-

bility, counter address readback, and mask address readback.

WRP0B P3

CNTRDB P3

RETXB P3

MKLDB P3

B3B P3

Burst Counter Operation

Each port contains a burst counter on the input address regis-

ter. After externally loading the counter with the initial address,

the counter will self-increment the address internally (more de-

tails to follow). The internal write pulse width is independent of

the duration of the R/W input signal. The internal write pulse is

self-timed to allow the shortest possible cycle times.

B2B P3

DIO P3

VSS

AF2

AIO P2

Counter enable inputs are provided to block the external ad-

dress input and utilize the internal address generated by the

internal counter for fast interleaved memory applications. A

port’s burst counter is loaded with an external address when

the port’s Counter Load pin (CNTLD) is asserted LOW. When

the port’s Counter Increment pin (CNTINC) is asserted, the

address counter will increment on each subsequent LOW-to-

HIGH transition of that port’s clock signal. This will read/write

one word from/into each successive address location until

CNTINC is deasserted. The counter can address the entire

memory array and will loop back to the start. Counter Reset

AF3

RWB P2

VDDC

AF4

AF5

VDDC

AF6

VDDA P2

VDD

AF7

AF8

AF9

VDD

AF10

VDDA P2

Document #: 38-06065 Rev. **

Page 10 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

(CNTRST) is used to reset the unmasked portion of burst

counter. A counter-mask register is used to control the counter

wrap. The counter and mask register operations are described

in more detail in the following sections.

traces on the PCB cause these effects. These mismatches

cause reflections on the board, which can dramatically impact

a system's ability to transmit data. One of the most common

ways used to solve this problem is to place terminating resis-

tors on each trace on the board. These resistor nets ensure

that the impedance of the device's I/O matches the traces on

the board. This approach, though, can have a huge impact on

the amount of board space required in a system. The Quad-

Port DSE solves both problems by allowing the designer to set

the impedance of the I/O driver to match the impedance of the

on board traces.

The counter or mask register values can be read back on the

bidirectional address lines by activating CNTRD or MKRD, re-

spectively.

Block Retransmit

Retransmit is a feature that allows the reread of a block of

memory more than once without the need to reload the initial

address. This eliminates the need for external logic to store

and route data. It also reduces the complexity of the system

design and saves board space. An internal “mirror register” is

used to store the initially loaded address counter value. When

the counter unmasked portion reaches its maximum value set

by the mask register, it will wrap back to the initial value stored

in this “mirror register”. If WRP = 0 the unmasked bits will wrap

to zero. The mirror register value will be loaded into the

counter when RETX is asserted LOW. When WRP = 1 the

unmasked bit can wrap to mirror register. If the counter is con-

tinuously configured in increment mode, it will increment again

to its maximum value and wraps back to the value initially

stored into the “mirror register,” thus allowing the access of the

same data repeatedly without the need for any external logic.

Each port of the QuadPort DSE has a Variable Impedance

Sense (VIS) circuit. The circuit sets the output impedance for

the DQ bus. The calibration circuit has one input called ZQ. A

calibrating resistor (RQ) is connected between ZQ and

ground. The value of RQ must be 5X the value of the intended

line impedance driven by the QuadPort DSE. The allowable

range of RQ to guarantee impedance matching with a toler-

ance of ±15% is between 175Ω and 500Ω. When MRST is

asserted LOW, the VIS control circuitry is reset and Ready is

deasserted. When MRST is released, the VIS circuit begins

the process of matching the DQ output impedance to 0.2*RQ.

Ready will be asserted within 1024 cycles of each port's re-

spective clock. Each port's DQ output impedance is guaran-

teed to be in the correct range when its Ready output is assert-

ed LOW. The output impedance is adjusted to account for

drifts in supply voltage and temperature every 1024 port clock

cycles thereafter. The user may also choose to disable vari-

Programmable I/Os

Each port will have two strapping pins that are used to select

the I/O standard used by data and address/control. S0 will set

the I/O standard for data and S1 will set the I/O standard for

address and control. Either LVTTL or SSTL2 Class 1 I/Os will

be selected as shown.

able impedance matching by connecting ZQ directly to V_DD

.

When VIS is disabled, The DQ output impedance will be

less-than equal 75Ω.

Variable Impedance Parameters

I/O Standard Strapping Codes

Parameter Minimum Maximum Units

Tolerance

±2%

Strapping Pin Value

I/O Standard Selected

LVTTL

RQ Value

175

35

500

100

Ω

0

1

Output

±15%

Impedance

SSTL2

Reset Time

NA

1024

cycles

NA

Variable Impedance Sense

Update

Time

Another problem that is often encountered in high-speed digi-

tal design is what is commonly known as transmission line

effects. Impedance mismatches between devices and the

Document #: 38-06065 Rev. **

Page 11 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Port 1 Operation-Control Logic Blocks^{[2, 3]}

READY

DOFF

B0

P1

Reset

Logic

MRST

B1

B2

P1

B3_P1

Port-1

Control

Logic

TMS

TCK

TDI

R/W

P1

JTAG

TDO

Controller

OE

P1

CE_0P1

CE

TRST

1P1

DIO

AIO

P1

C-

C+

P1

40

Port 1

I/O

Port 4 Logic Blocks^[4]

I/O -I/O

0P1

39P1

ZQ

P1

16

A

–A

15P1

0P1

Port 1

Port 4

QuadPort DSE

MKLD

Port 1

P1

CNTLD

Counter/

Mask Reg/

Address

P1

CNTINC

CNTRD

P1

Array

5/2/1 Meg

128/64/32Kx40

128/64Kx20

MKRD

P1

Decode

CNTRST

WRP

P1

RETX

INT

Port 2

Port 3

CNTINT

P1

Port 3 Logic Blocks^[4]

Port 2 Logic Blocks^[4]

Notes:

2. CY7C0431/0430V18 (x 20) has 20 I/O pins instead of 40.

3. CY7C0452/0431V18 (128K) have 17 address bits instead of 16. CY7C0451/0430V18 (64K) have 16 address bits. CY7C0450V18 (32K) has 15 address bits

instead of 16.

4. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.

Document #: 38-06065 Rev. **

Page 12 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Pin Definitions

Port 1

Port 2

Port 3

Port 4

Description

V_SS

V_DD

Ground supply for the core, address/control, data, or

clock.

Power supply for the core.

The user must ensure that V_DDramps simultaneously or

ahead of all other device power supplies.

V_{DDA P1}

V_{DDQ P1}

V_{DDA P2}

V_{DDQ P2}

V_{DDA P3}

V_{DDQ P3}

V_DDC

V_{DDA P4}

Power supply for address/control I/O on port x

Power supply for data I/O on port x

Power supply for clock I/O

V_{DDQ P4}

V_{REFA P1}

V_{REFA P2}

V_{REFA P3}

V_{REFA P4}

Pins must be connected to I/O reference voltage if us-

ing SSTL I/O on address/control on port x

V_{REFQ P1}

V_{REFQ P2}

V_{REFQ P3}

V_{REFQ P4}

Pins must be connected to I/O reference voltage if us-

ing SSTL I/O on data on port x

[3]

A_0P1–A_15P1

.

A_0P2–A_15P2

DQ_0P2

DQ_39P2

.

A_0P3–A_15P3

.

A_0P4–A_15P4

.

Address Input/Output

Data Bus Input/Output

DQ_0P1

–

DQ_0P3

–

DQ_0P4

–

[2]

DQ_39P1

DQ_39P3

DQ_39P4

C+_P1

C+_P2

C+_P3

C+_P4

Positive Clock Input. C+ is used to capture synchronous

inputs to the device. This input can be free running or

strobed. Maximum clock input rate is f_MAX

.

C–_P1

C–_P2

C–_P3

C–_P4

NegativeClockInput. C–is usedtocapturesynchronous

inputs to the device and must be equal to C frequency.

This input can be free running or strobed. Maximum clock

input rate is f_MAX

.

DIO_P1

DIO_P2

DIO_P3

DIO_P4

Data Pin I/O Standard Select Input. This pin will select

the I/O standard of the data pins. A HIGH signal will select

thepins toswitchatSSTL2levels. A LOWsignalwillselect

the pins to switch at LVTTL levels. The pins must be

strapped to either V_CCor VSS upon power-up.

AIO_P1

AIO_P2

AIO_P3

AIO_P4

Address/Control Pin I/O Standard Select Input. This

pin will select the I/O standard of the address and control

pins. A HIGH signal will select the pins to switch at SSTL2

levels. A LOW signal will select the pins to switch at LVTTL

levels. The pins must be strapped to either V_CCor VSS

upon power-up.

B0_P1

B1_P1

B0_P2

B0_P3

B1_P3

B0_P4

B1_P4

Byte 0 Select Input. Asserting this signal LOW enables

read and write operations to byte 0. For read operations

both the B0 and OE signals must be asserted to drive

output data on the lower byte of the data pins.

B1_P2

Byte 1 Select Input. Same function as B0, but to byte 1.

Byte 2 Select Input. Same function as B0, but to byte 2.

Byte 3 Select Input. Same function as B0, but to byte 3.

[5]

B2_P1

B2_P

B2_P3

B2_P4

2

[5]

B3_P1

B3_P2

B3_P3

B3_P4

CE_0P1,CE_1P1

CE_0P2,CE_1P2

CE_0P3,CE_1P3

CE_0P4,CE_1P4

Chip EnableInput. Toselect any port, bothCE₀AND CE₁

must be asserted to their active states (CE₀≤ V_ILand CE₁

≥ V_IH).

OE_P1

OE_P2

OE_P3

OE_P4

Output Enable Input. This signal must be asserted LOW

to enable the I/O data lines during read operations. OE is

asynchronous input.

R/W_P1

R/W_P2

R/W_P3

R/W_P4

Read/Write Enable Input. This signal is asserted LOW to

write to the QuadPort memory array. For read operations,

assert this pin HIGH.

Note:

5. Not available for CY7C0431/0430V18 (x 20)

Document #: 38-06065 Rev. **

Page 13 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Pin Definitions (continued)

Port 1

Port 2

Port 3

Port 4

Description

MRST

Master Reset Input. This is onesignal for all Ports. MRST

isanasynchronousinput. AssertingMRSTLOW performs

all of the reset functions as described in the text. A MRST

operation must be performed at power-up.

[6]

CNTRST_P1

CNTRST_P2

CNTRST_P3

CNTRST_P4

Counter Reset Input. Asserting this signal LOW resets

the unmasked portion of the burst address counter of its

respective port to zero. CNTRST is second to MRST in

priority with respect to counter and mask register opera-

tions.

[6]

MKLD_P1

MKLD_P2

MKLD_P3

MKLD_P4

Mask Register Load Input. Asserting this signal LOW

loads the mask register with the external address avail-

able on the address lines. MKLD operation has higher pri-

ority over CNTLD operation.

[6]

CNTLD_P1

CNTLD_P2

CNTLD_P3

CNTLD_P4

Counter Load Input. Asserting this signal LOW loads the

burst counter with the external address present on the

address pins.

[6]

CNTINC_P1

CNTINC_P2

CNTINC_P3

CNTINC_P4

Counter Increment Input. Asserting this signal LOW in-

crements the burst address counter of its respective port

on each rising edge of C.

[6]

CNTRD_P1

CNTRD_P2

CNTRD_P3

CNTRD_P4

Counter Readback Input. When asserted LOW, the in-

ternal address value of the counter will be read back on

the address lines. During CNTRD operation, both CNTLD

and CNTINC must be HIGH. Counter readback operation

has higher priority over mask register readback operation.

Counter readback operation is independent of port chip

enables. If address readback operation occurs with chip

enables active (CE₀= LOW, CE₁= HIGH), the data lines

(I/Os) will be three-stated.

[6]

MKRD_P1

MKRD_P2

MKRD_P3

MKRD_P4

Mask Register Readback Input. When asserted LOW,

the value of the mask register will be readback on address

lines. During mask register readback operation, all

counter and MKLD inputsmustbeHIGH(seeCounter and

Mask Register Operations truth table). Mask register read-

back operation is independent of port chip enables. DQ is

three-stated regardless of the chip enables. When the in-

ternal counter is driven to the address pins, the DQ pins

are three-stated.

[6]

CNTINT_P1

CNTINT_P2

INT_P2

CNTINT_P3

CNTINT_P4

INT_P4

Counter Interrupt Flag Output. Flag is assertedLOW for

one clock cycle when the counter reaches maximum

count.

INT_P1

INT_P3

Interrupt Flag Output. Interrupt permits communications

between all four ports. The upper four memory locations

can be used for message passing. Example of operation:

INT_P4is asserted LOW when another port writes to the

mailbox location of Port 4. Flag is cleared when Port 4

reads the contents of its mailbox. The same operation is

applicable to Ports 1, 2, and 3.

[6]

WRP_P1

WRP_P2

WRP_P3

WRP_P4

When the burst counter reaches the maximum count,

the unmasked bits will wrap to 0 if WRP is asserted LOW.

Otherwise, the counter will be loaded with the contents of

the mirror register.

[6]

RETX_P1

RETX_P2

RETX_P3

RETX_P4

When RETX is asserted LOW the burst counter is loaded

with the contents of the mirror register.

Note:

6. Not available on CY7C0452V18

Document #: 38-06065 Rev. **

Page 14 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Pin Definitions (continued)

Port 1

ZQ_P1

Port 2

ZQ_P2

Port 3

ZQ_P3

Port 4

ZQ_P4

Description

Output Impedance Matching Input. This input is used to

adjust the device data outputs impedance to match the

system data bus impedance. Output impedance is set to

0.2 x RQ, where RQ is a resistor connected between ZQ

and ground. The acceptable resistor values for RQ is

175Ω to 500Ω. Alternately, this pin can be connected di-

rectly to V_DD, which disables impedance matching. This

pin cannot be connected directly to V_SSor left floating.

READY_P1

DOFF_P1

READY_P2

DOFF_P2

READY_P3

DOFF_P3

READY_P4

DOFF_P4

Output pin indicates the port is ready for operation.

The DLL has been properly locked to the clock input sig-

nals.

The DLL requires 1024 cycles to lock following a master

reset operation.

DLL off input pin disables the integrated Delay Locked

Loop circuit for the port. DOFF can be toggled LOW then

HIGH to reset the DLL for the associated port. That port

will require 1024 cycles for the DLL to relock, but the other

3 ports are unaffected.

TRST

JTAG Port Reset

TCK

JTAG Test Clock Input. This can be CLK of any port or

an external clock connected to the JTAG TAP.

TDI

JTAG Test Data Input. This is the only data input. TDI

inputs will shift data serially in to the selected register.

TDO

JTAG Test Data Output. This is the only data output. TDO

transitions occur on the falling edgeof TCK. TDO normally

three-stated except when captured data is shifted out of

the JTAG TAP.

TMS

JTAG Test Mode Select Input. It controls the advance of

JTAG TAP state machine. State machine transitions occur

on the rising edge of TCK.

Document #: 38-06065 Rev. **

Page 15 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

DC Input Voltage for SSTL2 ..........................–0.3V to + 2.7V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage (HBM) ................................ >2200V

Static Discharge Voltage (CDM)..................................>750V

Latch-Up Current.....................................................>200 mA

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ................................ –40°C to + 125°C

Ambient Temperature with

Power Applied............................................–40°C to + 125°C

Supply Voltage to Ground Potential.............. –0.5V to + 1.9V

Operating Ranges

DC Voltage Applied to

Outputs in High Z State for LVTTL ................ –0.3V to + 3.9V

Ambient

Range

Commercial

Industrial

Temperature

0°C to +70°C

–40°C to +85°C

V_DD

DC Input Voltage........................................... –0.3V to + 3.9V

1.8V ± 5%

DC Voltage Applied to

Outputs in High Z State for SSTL2................ –0.3V to + 2.7V

Current Characteristics Over the Operating Range

CY7C0452V18/0451V18/0450V18/0431V18/0430V18

-167 -133 -100

Parameter

Description

Typ.

Max.

Typ.

Max.

Typ.

Max.

Unit

I_CC

Core Operating Current (V_DD= Max., I_OUT= 0 mA)

Outputs Disabled, CE = V_IL, f = f_max

900

1300

700

1100

500

900

mA

I_SB

Core Standby Current (4 Ports CMOS Level, 0 ac-

tive) CE_1-4≥ V_IH, f = 0

200

32

500

40

150

29

500

36

100

26

500

32

mA

I_CCQ

I_SBQ

I/O Operating Current per port

(V_DDQ= Max, no external load, f = f_max

)

I/O Standby Current per port

(V_DDQ= Max, (no external load, f = 0)

OR Outputs Disabled

12

20

12

20

12

20

I_CCA

I_SBA

I_CCC

I_SBC

Address/ Control Operating Current per port

(V_DDA= Max, no external load, f = f_max

24

12

8

30

15

10

22

12

8

27

15

10

20

12

8

24

15

10

mA

)

Address/Control Standby Current per port

(V_DDA= Max, no external load, f = 0)

Clock / JTAG Operating Current Total

(V_DDC= Max, f = f_max

)

Clock / JTAG Standby Current Total

(V_DDC= Max, CE_1-4≥ V_IH)

8

Document #: 38-06065 Rev. **

Page 16 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Electrical Characteristics

CY7C0452V18/0451V18/0450V18/0431V18/

0430V18

Parameter

V_DDQ/A

V_REF

V_TT

I/O Type

Description

Min.

2.3

Max.

2.7

Unit

V

SSTL2-Class 1 Supply Voltage

Reference Voltage

1.15

1.35

V

Termination Voltage

V_REF– 0.04

V_REF+ 0.18

–0.3

V_REF+ 0.04

V_DDQ+ 0.3

V_REF– 0.18

100

V

V_IH

Input High Voltage

V

V_IL

Input Low Voltage (V_DDQ= 2.3V–2.7V)

V

I_OZ

Output Leakage Current

–100

µA

mA

I_OH

Output Source Current (V_DDQ= 2.3V)

Output Sink Current (V_DDQ= 2.3V)

–7.6

I_OL

7.6

V_DDQ/A

V_IH

LVTTL

Supply Voltage

3.0

2.0

3.6

V_DD+ 0.3

0.8

V

Input High Voltage

V_IL

Input Low Voltage

–0.3

2.4

V

V_OH

V_OL

I_OZ

Output High Voltage (I_OH= –8 mA)

Output Low Voltage (I_OL= 8 mA)

Output Leakage Current

V

0.4

V

–100

100

µA

V_DDC

V_IH

LVPECL

(Clocks only)

Supply Voltage

3.0

3.6

V

Input High Voltage

Input Low Voltage

Input Differential Voltage

V_DD– 1.2

V_DD– 1.85

600

V_DD– 0.85

V_DD– 1.45

1000

V_IL

V

V_IDIF

mV

JTAG TAP Electrical Characteristics Over the Operating Range

Parameter

V_OH1

V_OL1

Description

Test Conditions

Min.

Max.

Unit

V

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

I_OH= –8.0 mA

2.4

I_OL= 8.0 mA

0.4

0.8

V

V_IH

2.0

V

V_IL

V

Capacitance

Parameter

Description

Test Conditions

Max.

Unit

pF

C_IN(ALL PINS)

C_OUT(ALL PINS)

C_IN(C PINS)

Input Capacitance

T_A= 25°C, f = 1 MHz,

V_CC= 3.3V

10

15

Output Capacitance

Input Capacitance

pF

Document #: 38-06065 Rev. **

Page 17 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

AC Test Load

Z

= 50Ω

R = 50Ω

0

OUTPUT

Z

= 50Ω

R = 50Ω

0

5 pF

OUTPUT

[7]

C

V

= 1.5V

= 3.3V

TH

Z = 50Ω

0

V

TH

= 1.5V

5 pF

(a) Normal Load (LVTTL)

V

TH

Z

= 50Ω

R = 50Ω

0

(b) Three-state Delay

OUTPUT

[7]

R

= 25Ω

S

C

V

TT

= 0.5 * V

DDQ

3.0V

GND

90%

10%

90%

10%

(a) Normal Load (SSTL2 Class 1)

t = 1.6 ns

f

r

1.5V

LVTTL INPUTS

50Ω

TDO

V

= VREF + 0.35V

IHmin(AC)

Z = 50Ω

V

0

SWING (MAX)

= 1.5V

VREF = 1.25V

V

C = 20 pF

= VREF – 0.35V

ILmax(AC)

deltaT

)/deltaT = 1.0 V/ns

ILMAX(AC)

GND

(c) TAP Load

SLEW = (V

IHMIN(AC)

– V

SSTL2 INPUTS

LVPECL Input Waveform

V_{DD_CLK}

V_IH(MAX)

V_IH(MIN)

90%

10%

V_IDIF

V_IL(MAX)

V_IL(MIN)

V_{SS_CLK}

10%

t_r/ t_f

t_r= Rise Time <= 0.6 ns

t_f= Fall Time <= 0.6 ns

All timing referenced to C+ and C- crossing

LVPECL INPUTS

Note:

7. Test Conditions: C = 10 pF.

Document #: 38-06065 Rev. **

Page 18 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Characteristics Over the Commercial/Industrial Operating Range

CY7C0452V18/0451V18/0450V18/0431V18/0430V18

-167 -133 -100

Parameter

qualifier

Description

Maximum Operating Frequency

Clock Cycle Time

Min.

Max.

Min.

Max.

Min.

Max.

Unit

f_MAX

t_CYC

t_CH

t_CL

t_R

167

133

100

6

7.5

3.4

10

4.0

ns

Clock HIGH Time

2.7

Clock LOW Time

Clock Rise Time

0.6

t_F

Clock Fall Time

t_SD

t_HD

Input Data Set-up Time

Input Data Hold Time

WRP0 Set-up Time

1.9

0.7

1.9

0.7

1.9

0.7

1.9

0.7

1.9

0.7

1.9

0.7

1.9

0.7

1.9

0.7

1.9

0.7

1.9

0.7

1.9

0.7

1.9

0.7

1.9

0.7

2.3

0.7

2.3

0.7

2.3

0.7

2.3

0.7

2.3

0.7

2.3

0.7

2.3

0.7

2.3

0.7

2.3

0.7

2.3

0.7

2.3

0.7

2.3

0.7

2.3

0.7

3.0

0.7

3.0

0.7

3.0

0.7

3.0

0.7

3.0

0.7

3.0

0.7

3.0

0.7

3.0

0.7

3.0

0.7

3.0

0.7

3.0

0.7

3.0

0.7

3.0

0.7

t_SWRP

t_HWRP

t_SRT

WRP0 Hold Time

RETX Set-up Time

t_HRT

t_SA

RETX Hold Time

Address Set-up Time

Address Hold Time

t_HA

t_SB

Byte Set-up Time

t_HB

Byte Hold Time

t_SC

Chip Enable Set-up Time

Chip Enable Hold Time

R/W Set-up Time

t_HC

t_SW

t_HW

R/W Hold Time

t_SCLD

t_HCLD

t_SCINC

t_HCINC

t_SCRD

t_HCRD

t_SRST

t_HRST

t_SMLD

t_HMLD

t_SMRD

t_HMRD

t_OE

CNTLD Set-up Time

CNTLD Hold Time

CNTINC Set-up Time

CNTINC Hold Time

CNTRD Set-up Time

CNTRD Hold Time

CNTRST Set-up Time

CNTRST Hold Time

MKLD Set-up Time

MKLD Hold Time

MKRD Set-up Time

MKRD Hold Time

Output Enable to Data Valid

Output Enable to Low Z

Output Enable to High Z

Clock to Counter Addr. Readback Valid

Address Output Hold After Clock HIGH

Clock High to Address Output High Z

5.5

6.5

8.5

t_OLZ

1.0

t_OHZ

t_CA

5.5

6.0

5.5

7.5

8.5

10

t_AC

1.0

t_CKHZA

6.0

7.5

10.0

Document #: 38-06065 Rev. **

Page 19 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Characteristics Over the Commercial/Industrial Operating Range (continued)

CY7C0452V18/0451V18/0450V18/0431V18/0430V18

-167 -133 -100

Parameter

qualifier

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

ns

t_CKLZA

Clock High to Address Output Low Z

1.0

t_CM

Clock to Master Register Readback

Valid

6.0

3.5

7.5

4.0

10

ns

t_CD

with DLL Clock to DQ Valid

4.5

ns

t_DC

with DLL DQ/A Output Hold After Clock HIGH

with DLL Clock High to DQ/A Output Low Z

with DLL Clock High to DQ/A Output High Z

1.0

0.5

1.0

t_CKLZ

t_CKHZ

t_CD2

t_DC2

3.5

4.7

4.0

6.0

4.5

7.0

no DLL

Clock to DQ Valid (DOFF=0)

DQ/A Output Hold After Clock HIGH

(DOFF=0)

1.0

5.0

1.0

6.5

1.0

9.0

t_CKHZ2

t_CKLZ2

no DLL

Clock HIGH to DQ/A Output High Z

(DOFF=0)

4.7

6.0

7.0

ns

Clock HIGH to DQ/A Output Low Z

(DOFF=0)

t_CCS

t_SCINT

t_RCINT

t_SINT

t_RINT

t_RS

Clock to Clock Set-up Time

Clock to CNTINT LOW

Clock to CNTINT HIGH

Clock to INT LOW

ns

4.7

7.5

6

9

7

10

Clock to INT HIGH

Master Reset Pulse Width

Master Reset Recovery Time

24

18

30

40

30

t_RSR

t_RSF

22.5

Master Reset to Outputs

Inactive/High Z

18

22.5

30

t_RDY

f_JTAG

t_TCYC

t_TH

Master Reset Release to Port Ready

JTAG TAP Controller Frequency

TCK Cycle Time

1024

10

1024

10

1024 Cycles

10

MHz

ns

100

40

10

100

40

10

100

40

10

TCK High Time

t_TL

TCK Low Time

t_TMSS

t_TMSH

t_TDIS

t_TDIH

t_TDOV

t_TDOX

t_TRS

TMS Set-Up to TCK Rise

TMS Hold to TCK Rise

TDI Set-Up to TCK Rise

TDI Hold to TCK Rise

TCK Low to TDO Valid

TCK Low to TDO Invalid

TRST Pulse Width

20.0

20

20.0

0

24

30

40

Document #: 38-06065 Rev. **

Page 20 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

JTAG Timing and Switching Waveforms

t

TH

TL

Test Clock

TCK

t

TCYC

t

TMSS

t

TMSH

Test Mode Select

TMS

t

TDIS

t

TDIH

Test Data-In

TDI

Test Data-Out

TDO

t

TDOX

t

TDOV

Document #: 38-06065 Rev. **

Page 21 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms

Master Reset^{[8, 9, 10]}

t

CYC

t

CH

CL

C+

t

CH

CHCH

CL

C–

t

RSR

RS

MRST

READY

t

RDY

RSF

[2]

DQ

39:0

[3]

A

16:0

CNTINT

INT

[9]

t

S

All Control Inputs

TRST

INACTIVE

ACTIVE

t

TRS

Notes:

8. A master reset cycle is required after power-up

9. The parameter t_Srepresents the set-up time required for each input

10. At power up, TRST must be asserted low for at least t_TRSto ensure the TAP controller is in the Test-Logic-Reset state.

Document #: 38-06065 Rev. **

Page 22 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Read Cycle^{[6, 7, 13]}

t

CYC

t

CL

CH

C+

t

CL

CHC

CHCH

CH

C–

t

HW

SW

R/W

t

HA

SA

[3]

16:0

A

n+5

n

n+1

n+2

n+3

n+4

t

CD

DC

[2]

DQ

Q

n+1

39:0

x-3

x-2

x-1

x

n

Write Cycle^{[11, 14]}

t

CYC

t

CL

CH

C+

t

CHCH

CH

CL

C–

t

HW

SW

R/W

t

SA

HA

HD

[3]

A

D

A

D

A

D

16:0

n

n+1

n+2

n+3

n+4

t

SD

[2]

DQ

D

39:0

n

n+1

n+3

n+4

Notes:

11. _nis the address for location n. D_nis data written to location n. Q_nis the data read from location n.

12. There are 3 cycles of latency for data to reach the DQ bus in response to a read instruction

A

13. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = V_IL, MRST = CE1 = CNTRST = MKLD = V_IH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X

14. CE0 = B3 = B2 = B1 = B0 = CNTLD = V_IL, MRST = CE1 = CNTRST = MKLD = V_IH, OE = CNTINC = RETX = WRP0 = CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 23 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Bank Select Read During Depth Expansion^{[11, 15, 16]}

t

CYC

t

CL

CH

C+

t

CHCH

CH

CL

C–

t

SA

HA

HC

[3]

16:0(B1)

A

n+6

n

n+1

n+2

n+3

n+4

n+5

t

SC

CE0

(B1)

t

CKLZ

CD

CKHZ

[2]

DQ

Q

n+2

39:0(B1)

n

t

SA

HA

[3]

A

n+6

16:0(B2)

n

n+1

n+2

n+3

n+4

n+5

t

SC

HC

CE1

(B2)

t

CKLZ

DC

CKHZ

CD

[2]

DQ

Q

n+1

39:0(B2)

x3

x-2

x-1

x

Notes:

15. B1 represents Bank #1 and B2 represents Bank #2. Each bank consists of one QuadPort DSE device. A_(B1)= A_(B2)

16. CE0_(B2)= OE = B3 = B2 = B1 = B0 = CNTLD = V_IL, MRST = CE1_(B1)= R/W = CNTRST = MKLD = V_IH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 24 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Bank Select Write During Depth Expansion^{[11, 15, 17]}

t

CYC

t

CL

CH

C+

t

CHCH

CH

CL

C–

t

SA

SC

SD

HA

HC

HD

[3]

A

16:0(B1)

n

n+1

n+2

n+3

n+4

n+5

n+6

t

CE0

(B1)

[2]

DQ

D

A

D

A

D

A

D

A

D

A

D

A

39:0(B1)

n

n+1

n+2

n+3

n+4

n+5

n+6

t

SA

SC

SD

HA

HC

HD

[3]

A

16:0(B2)

n

n+1

n+2

n+3

n+4

n+5

n+6

t

CE1

(B2)

[2]

DQ

D

39:0(B2)

n

n+1

n+2

n+3

n+4

n+5

n+6

Note:

17. CE0_(B2)= OE = B3 = B2 = B1 = B0 = R/W = CNTLD = V_IL, MRST = CE1_(B1)= CNTRST = MKLD = V_IH,CNTINC = RETX = WRP0 = CNTRD = MKRD= X

Document #: 38-06065 Rev. **

Page 25 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Read-to-Write (OE = V_IL)^{[11, 12, 18, 19, 20, 21]}

t

CYC

t

CL

CH

C+

t

CL

CHCH

CH

C–

t

HA

SA

HA

SA

[3]

A

D

A

D

16:0

x

n

n+1

n+2

t

HW

SW

HW

SW

R/W

t

HD

DC

CD

CKHZ

SD

[2]

39:0

DQ

Q

D

n

x-4

x-3

x-2

x-1

x

n+1

n+2

Read-to-Write (OE Controlled)^{[11, 12, 22, 23, 24]}

t

CYC

t

CL

CH

C+

t

CL

CHCH

CH

C–

t

HA

SA

HA

SA

[3]

A

n+4

16:0

x+2

x+3

x+4

n

n+1

n+2

n+3

t

HW

SW

HW

SW

R/W

OE

t

HD

DC

CD

OH

SD

[2]

39:0

DQ

Q

D

n+4

x-2

x-1

x

n

n+1

n+2

n+3

Notes:

18. When OE = V_IL, the last read operation is allowed to complete before the DQ bus is three-stated and the user is allowed to drive write data.

19. Four dummy writes should be issued to accomplish bus turnaround. The fifth write instruction is the first valid write.

20. The address should be held constant during the four dummy writes and first valid write instruction to avoid data corruption.

21. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = V_IL, MRST = CE1 = CNTRST = MKLD = V_IH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X

22. OE should be deasserted and t_OHZallowed to elapse before the first write operation is issued.

23. Any read scheduled to complete after OE is asserted will be preempted.

24. CE0 = B3 = B2 = B1 = B0 = CNTLD = V_IL, MRST = CE1 = CNTRST = MKLD = V_IH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 26 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Byte Enable Write^{[11, 25]}

t

CYC

t

CL

CH

C+

t

CL

CHCH

CH

C–

t

HW

SW

R/W

[3]

A

n

16:0

t

CD

SD

HD

[2,5]

[2]

DQ

0x000

0x3FF

0x155

0x2AA

0x155

0x3FF

0x2AA

0x000

39:30

29:20

19:10

0x000

[2]

9:0

t

HB

SB

[5]

B

3

[5]

B

2

1

0

B

Note:

25. CE0 = OE = CNTLD = V_IL, MRST = CE1 = CNTRST = MKLD = V_IH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 27 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Byte Enable Read^{[11, 26]}

t

CYC

t

CL

CH

C+

t

CL

CHCH

CH

C–

t

HW

SW

R/W

[3]

A

n

16:0

t

CKHZ

SD

HD

[2,5]

[2]

DQ

0x000

0x3FF

0x155

0x2AA

0x000

39:30

29:20

19:10

t

CKLZ

0x3FF

t

CD

0x155

0x2AA

[2]

9:0

t

HB

SB

[5]

B

3

[5]

B

2

1

0

B

Note:

26. CE0 = OE = CNTLD = V_IL, MRST = CE1 = CNTRST = MKLD = V_IH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 28 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Read with Address Counter Advance^{[6, 11, 27]}

t

CYC

t

CL

CH

C+

t

CHCH

CH

CL

C–

t

SA

HA

[3]

16:0

A

n

Internal address

CNTLD

A

n+3

n

n+1

n+2

t

HCLD

SCLD

t

HCINC

SCINC

CNTINC

[2]

t

DC

CD

DQ

Q

n+2

39:0

x-2

x-1

x

n

n+1

Note:

27. CE0 = OE = B3 = B2 = B1 = B0 = V_IL, MRST = CE1 = R/W = CNTRST = MKLD = RETX = V_IH, WRP0 = CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 29 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Write with Address Counter Advance^{[6, 11, 28]}

t

CYC

t

CL

CH

C+

t

CHCH

CH

CL

CHCH

C–

t

SA

HA

[3]

16:0

A

n

Internal address

A

n+3

n

n+1

n+2

t

HCLD

SCL

CNTLD

t

HCINC

SCINC

CNTINC

[2]

t

HD

SD

DQ

D

n+5

39:0

n

n+1

n+2

n+3

n+4

Note:

28. CE0 = B3 = B2 = B1 = B0 = R/W = V_IL, MRST = CE1 = CNTRST = MKLD = RETX = V_IH, OE = WRP0 = CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 30 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Counter Reset^{[6, 11, 29, 30, 31]}

t

CYC

t

CL

CH

C+

t

CHCH

CH

CL

C–

t

SA

HA

[3]

A

OX1755

16:0

Internal address

0X17550

0X17551

0X17000

0X17001

0X17002

t

SCLD

HCLD

CNTLD

t

HCINC

SCINC

CNTINC

CNTRST

t

HRST

SRST

t

HW

SW

R/W

t

DC

CD

[2]

39:0

DQ

Q

17000

17550

17551

Notes:

29. Only umasked bits of the burst counter are reset in response to a CNTRST operation. MASK = 0x00FFF.

30. CE0 = OE = B3 = B2 = B1 = B0 = V_IL, MRST = CE1 = CNTRST = MKLD = RETX = V_IH, R/W = WRP0 = CNTRD = MKRD = X

31. MASK = 0x00FFF.

Document #: 38-06065 Rev. **

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CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Counter Interrupt (WRP = V_IH)^{[6, 11, 31, 32, 31, 33, 34, 35, 36, 37, 38]}

t

CYC

t

CL

CH

C+

t

CHCH

CH

CL

C–

t

SA

HA

[3]

A

O 17FFC

X

16:0

Internal address

0 17FFC

0 17FFD

0 17FFE

0 17FFF

0 17FFC

X

t

HCLD

SCLD

CNTLD

CNTNC

CNTINT

R/W

t

HCINC

SCINC

t

RCINT

SCINT

t

HW

SW

t

DC

CD

[2]

39:0

DQ

Q

17FFE

17FFC

17FFD

Notes:

32. The internal burst counter reaches its maximum count when each bit is either masked or equal to 1.

33. Each port has a mirror register that loads the external address value in response to a CNTLD operation.

34. All bits of the mirror register are reset to 0 in response to a MRST operation.

35. Unmasked bits of the mirror register are reset to 0 in response to a CNTRST operation.

36. The value in the mirror register is unaffected by all other burst counter operations including CNTINC.

37. When WRP0 = V_IH, the internal burst counter is loaded with the contents of the mirror register on the cycle after COUNT = maximum count.

38. CE0 = OE = B3 = B2 = B1 = B0 = V_IL, MRST = CE1 = CNTRST = MKLD = RETX = V_IH, CNTRD = MKRD = X

Document #: 38-06065 Rev. **

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CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Counter Interrupt (WRP = V_IL)^{[6, 11, 31, 32, 39, 40]}

t

CYC

t

CL

CH

C+

t

CHCH

CH

CL

C–

t

HA

SA

[3]

16:0

A

O 17FFC

X

Internal address

0 17FFC

0 17FFD

0 17FFE

0 17FFF

0 17000

X

t

HCLD

SCLD

CNTLD

CNTNC

CNTINT

R/W

t

HCINC

SCINC

t

RCINT

SCINT

t

HW

SW

t

CD

[2]

DQ

Q

17FFE

39:0

17FFC

17FFD

t

DC

Notes:

39. When WRP0 = V_IL, the unmasked bits of the burst counter are reset to 0 on the cycle after COUNT = maximum count.

40. CE0 = OE = B3 = B2 = B1 = B0 = V_IL, MRST = CE1 = CNTRST = MKLD = RETX = V_IH, CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 33 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Forced Retransmit^{[6, 11, 31, 32, 33, 34, 35, 36, 41, 42]}

t

CYC

t

CL

CH

C+

t

CHCH

CH

CL

C–

t

SA

HA

[3]

16:0

A

n

Internal address

A

n+1

n

n+1

n+2

n

t

SCLD

HCLD

CNTLD

CNTINC

RETX

R/W

t

HCINC

SCINC

t

HRT

SRT

t

HW

SW

t

DC

CD

[2]

DQ

Q

n+2

39:0

n

n+1

Notes:

41. When RETX= V_IL, the value in the mirror register is loaded to the burst counter regardless of the counter’s current value.

42. CE0 = OE = B3 = B2 = B1 = B0 = V_IL, MRST = CE1 = CNTRST = MKLD = V_IH, WRP0 = CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 34 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Load and Read Address Counter^{[6, 11, 43]}

t

CY

t

CL

CH

C+

t

CHCH

CHC

CH

CL

C–

t

CKHZ

SA

HA

CKLZ

[3]

A

n+1

16:0

n

t

CA2

SCLD

HCLD

CNTLD

CNTINC

CNTRD

R/W

t

HCINC

SCIN

t

HCRD

SCR

t

CKLZ

CD

DC

CKHZ

[2]

39:0

DQ

Q

n+1

n

n+1

Note:

43. CE0 = OE = B3 = B2 = B1 = B0 = V_IL, MRST = CE1 = CNTRST = MKLD = RETX = V_IH, WRP0 = MKRD = X

Document #: 38-06065 Rev. **

Page 35 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Load and Read Mask Register^{[6, 11, 44]}

t

CY

t

CL

CH

C+

t

CL

CH

C–

t

CKHZ

SA

HA

CKLZ

[3]

0x17FF

A

0x17FFC

16:0

t

CA2

SMLD

HMLD

MKLD

MKRD

R/W

t

HM-

SM-

t

CKLZ

CKHZ

CKLZ

CKHZ

[2]

39:0

DQ

Note:

44. CE0 = OE = B3 = B2 = B1 = B0 = V_IL, MRST = CE1 = CNTRST = CNTLD = CNTINC = RETX = CNTRD = V_IH, WRP0 = X

Document #: 38-06065 Rev. **

Page 36 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Mailbox Interrupt^{[11, 45, 46, 47, 48]}

t

CYC

t

CL

CH

C+

(P1)

t

CHCH

CHC

CH

CL

C–

(P1)

t

HA

[3]

A

0x1FFF

16:0(P1)

R/W

(P1)

t

HD

SD

[2]

39:0(P1)

DQ

D

1FFFE

t

RINT

SINT

INT

(P2)

t

CL

CH

C+

t

CHCH

CHC

CH

CL

C–

(P2)

t

HA

SA

[3]

A

0x1FFFE

16:0(P2)

t

HW

SW

R/W

(P2)

t

CD

DC

[2]

39:0(P2)

DQ

Q

1FFFE

Notes:

45. Port 1 Mailbox Address = 0x1FFFF, Port 2 Mailbox Address = 0x1FFFE, Port 3 Mailbox Address = 0x1FFFD, Port Mailbox Address = 0x1FFFC

46. There is one cycle of latency between writing a mailbox location and the INT flag being asserted LOW.

47. There is one cycle of latency between reading a mailbox location and the INT flag being deasserted HIGH.

48. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = V_IL, MRST = CE1 = CNTRST = MKLD = V_IH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 37 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Switching Waveforms (continued)

Port 1 Write to Port 2 Read^{[11, 49, 50, 51]}

t

CYC

t

CL

CH

C+

(P1)

t

CHCH

CH

CL

C–

(P1)

t

SA

HA

[3]

A

16:0(P1)

n

t

SW

HW

HD

R/W

(P1)

t

SD

[2]

DQ

D

39:0(P1)

n

t

CCS

t

CL

CH

C+

(P2)

t

CHCH

CH

CL

C–

(P2)

t

HA

SA

[3]

A

n

16:0(P2)

t

HW

SW

R/W

(P2)

t

DC

CD

[2]

DQ

Q

n

39:0(P2)

Notes:

49. If t_CCSis not allowed to elapse between the write on Port 1 and the Read on Port 2, the data resulting from the read operation is indeterminate.

50. This waveform applies to write to read operations on any two ports.

51. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = V_IL, MRST = CE1 = CNTRST = MKLD = V_IH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X

Document #: 38-06065 Rev. **

Page 38 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 2. Read/Write and Enable Operation (Any Port)^{[52, 53, 54]}

Inputs

Outputs

I/O₀–I/O₃₉

High-Z

OE

C

CE₀

CE₁

R/W

Operation

X

H

X

Deselected

X

L

X

L

X

L

High-Z

D_IN

Deselected

Write

H

X

D_OUT

High-Z

Read

H

X

Outputs Disabled

Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)^{[6, 52, 55, 56]}

C

MRST

CNTRST

MKLD CNTLD

RETX

CNTINC

CNTRD

MKRD

Mode

Operation

X

L

X

Master Counter/Address Register Reset and

Reset Mask Register Set (resets entire chip as

per reset state table)

H

L

X

L

X

Reset Counter/Address Register Reset

H

Load Load of Address Lines into Mask Regis-

ter

H

L

X

L

X

L

X

L

X

L

Load Load of Address Lines into Counter/Ad-

dress Register

H

Re-

Load address from Mask Register

Transmit

H

Incre- Counter Increment

ment

H

Read- Readback Counter on Address Lines

back

H

Read- Readback Mask Register on Address

back

Lines

H

Hold

Counter Hold

Notes:

52. “X” = “Don’t Care,” “H” = V_IH, “L” = V_IL

.

53. OE is an asynchronous input signal.

54. When CE changes state, deselection and read happen after one cycle of latency.

55. CE₀= OE = V_IL; CE₁= R/W = V_IH

.

56. Counter operation and mask register operation are independent of Chip Enables.

Document #: 38-06065 Rev. **

Page 39 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Master Reset

READY Outputs

The QuadPort DSE has a global asynchronous master reset

input, MRST. A complete device reset can be initiated at any

time by asserting MRST LOW. A master reset cycle is required

at power-up. MRST must remain asserted for at least t_RS. Ad-

ditionally, MRST should not be released until all power sup-

plies are fully ramped and all port clocks are stable. Asserting

MRST will have the following effects:

The QuadPort DSE output circuitry includes some advanced

features that enhance the user's interface to the DQ bus. Each

port includes an on-board DLL that is used to reduce all output

timing parameters. Each port also has a VIS circuit that match-

es the DQ output driver impedance to one fifth of an external

calibration resistor (0.2 * RQ). The user can use the VIS circuit

to match the output driver impedance to the board trace im-

pedance, which eliminates the requirement for external series

match resistors. Both the DLL and VIS circuits require a cali-

bration period. Calibration cannot start before the supplies for

each port have ramped and the clock inputs are stable. Both

the DLL and VIS circuits are reset when MRST is asserted.

Calibration of both circuits starts when MRST is released.

1. Ready is deasserted (driven HIGH).

2. All DQ and address are three-stated. (No effect on

JTAG/TAP signals)

3. The internal burst counter for each port is reset to all 0s.

4. The internal mirror register for each port is reset to all 0s.

When either the DLL or VIS circuits are enabled, the device

will not be fully functional until the calibration period has

elapsed. This is indicated to the user by the READY output for

each port. When MRST is asserted (LOW), READY is deas-

serted (HIGH). READY will not be asserted until both the DLL

and VIS circuits have completed calibration. READY is guar-

anteed to be asserted within 1024 clock cycles after MRST is

released.

5. The internal mask register for each port is set to all 1s (fully

unmasked state).

6. All pipeline control registers will be set to an inactive state.

7. All mailbox and burst counter interrupts will be deasserted

(driven HIGH).

8. The control circuitry for the internal delay-locked-loops

(DLLs) and variable impedance sense (VIS) circuitry for all

ports will be reset.

Any operation that results in data being driven to the DQ bus

is prohibited before READY is asserted. All other operations

are allowed during the period between the release of MRST

and the assertion of READY.

The circuitry for each port includes a delay-lock-loop (DLL)

and variable impedance sense (VIS). The DLL and VIS circuits

require a fully ramped power supply and stable clock to oper-

ate correctly. Releasing MRST is a signal to QuadPort DSE

that all power supplies have fully ramped and all port clocks

are stable. At this time the DLL lock sequence and VIS match-

ing procedure will commence. Each port’s READY signal will

be asserted (LOW) when the DLL is locked and output imped-

ance matched to 0.2 * RQ. READY will be asserted within

1024 clock cycles of MRST’s release. Releasing MRST has

the following effects:

The DLL circuit can be disabled by asserting DOFF. The VIS

can be disabled by connection the ZQ input to V_DD. If both

circuits are disabled when MRST is asserted, READY will be

asserted within two clock cycles after MRST is released.

Interrupts

The upper four memory locations may be used for message

passing and permit communications between ports. Table 4

shows the interrupt operation for all ports. For the 2-Meg

QuadPort DSE, the highest memory location FFFF is the mail-

box for Port 1, FFFE is the mailbox for Port 2, FFFD is the

mailbox for Port 3, and FFFC is the mailbox for Port 4. Table

4 shows that in order to set Port 1 INT_P1flag, a write by any

other port to address FFFF will assert INT_P1LOW. A read of

FFFF location by Port 1 will reset INT_P1HIGH. When one port

writes to the other port’s mailbox, the Interrupt flag (INT) of the

port that the mailbox belongs to is asserted LOW. The Interrupt

is reset when the owner (port) of the mailbox reads the con-

tents of the mailbox.

1. DLL circuit starts lock procedure.

2. VIS circuit starts matching output impedance.

3. READY for each port is asserted within 1024 clock cycles

of the clock for the respective port. If both the DLL and VIS

circuitry for a port are disabled (DOFF = 0 and VIS = V_CC),

then the port’s READY is asserted within 2 clock cycles.

The following operation commences independent of the

READY output state.

4. Data and address outputs remain in three-state, but the

three-state control passes to the control pipeline.

Each port can read the other port’s mailbox without resetting

the interrupt. If an application does not require message pass-

ing, INT pins should be treated as no-connect and should be

left floating. When two ports or more write to the same mailbox

at the same time INT will be asserted but the contents of the

mailbox are not guaranteed to be valid.

5. The burst counter is released from reset.

6. The mirror register is released from reset.

7. The mask register is released from preset.

8. External control inputs are allowed to latch into the control

pipeline.

9. All mailbox and burst counter interrupts are released from

preset.

Document #: 38-06065 Rev. **

Page 40 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 4. Interrupt Operation Example^[57]

Port 1

Port 2

A_0P2–15P2

Port 3

A_0P3–15P3

Port 4

A_0P4–15P4

Function

A_0P1–15P1

X

INT_P1

INT_P2

INT_P3

INT_P4

Set Port 1 INT_P1Flag

Reset Port 1 INT_P1Flag

Set Port 2 INT_P2Flag

Reset Port 2 INT_P2Flag

Set Port 3 INT_P3Flag

Reset Port 3 INT_P3Flag

Set Port 4 INT_P4Flag

L

H

X

FFFF

X

L

FFFF

X

L

FFFF

X

L

FFFF

FFFE

X

FFFE

X

FFFE

X

FFFE

FFFD

X

H

X

FFFD

X

FFFD

X

FFFD

FFFC

X

H

X

FFFC

X

FFFC

X

Reset Port 4 INT_P4Flag

FFFC

H

Note:

57. During Master Reset the control signals will be set to a deselected read state: CE0i = B1i = B2i = B3i = B4i = R/Wi = MKLDi = MKRDi = CNTRDi = CNTRSTi =

CNTLDi = CNTINCi = VIH; CE1i = VIL. The “i” suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals.

Document #: 38-06065 Rev. **

Page 41 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Address Counter Control Operations^[6]

internal address value of the counter will be read back on the

address lines when the Counter Readback Signal (CNTRD) is

asserted. Figure 1 provides a block diagram of the readback

operation. Table 3 lists control signals required for counter op-

erations. The signals are listed based on their priority. For ex-

ample, Master Reset takes precedence over Counter Reset,

and Counter Load has lower priority than Mask Register Load

(described below). All counter operations are independent of

Chip Enables (CE₀and CE₁).The read back address can be

either of the burst counter or the mask register based on the

levels of Counter Read signal (CNTRD) and Mask Register

Read signal (MKRD). Both signals are synchronized to the

port's clock as shown in Table 3. Counter read has a higher

priority than mask read.

Counter enable inputs are provided to stall the operation of the

address input and utilize the internal address generated by the

internal counter for the fast interleaved memory applications.

A port’s burst counter is loaded with the port’s Counter Load

pin (CNTLD). When the port’s Counter Increment (CNTINC) is

asserted, the address counter will increment on each transi-

tion of that port’s clock signal. This will read/write one word

from/into each successive address location until CNTINC is

deasserted. Depending on the mask register state, the counter

can address the entire memory array and will loop back to

start. Counter Reset (CNTRST) is used to reset the Burst

Counter (the Mask Register value is unaffected, the unmasked

bits are reset). When using the counter in readback mode, the

Read back

Register

CNTRD

MKRD

Addr.

Read

Back

QuadPort

MKLD = 1

DSE

Array

Mask

Register

Bidirectional

Address Lines

Counter/

Address

Register

WRP = 1

RETX = 1

CNTINC = 1

CNTLD = 1

CNTRST = 1

CLK

Figure 1. Counter and Mask Register Read Back on Address Lines

Document #: 38-06065 Rev. **

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CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Counter-Mask Register

CNTINT

H

Example:

Load

Counter-Mask

0

0s

0

1

Register = 3F

2¹⁵2¹⁴

2⁶2⁵2⁴2³2²2¹2⁰

Counter Address

Mask

Register

bit-0

Blocked Address

Load

Address

Counter = 8

H

L

X

Xs

X

0

1

0

1

2¹⁵2¹⁴

2⁶2⁵2⁴2³2²2¹2⁰

Address

Counter

bit-0

Max

Address

Register

X

1

2¹⁵2¹⁴

2⁶2⁵2⁴2³2²2¹2⁰

Max + 1

Address

Register

X

0

2¹⁵2¹⁴

2⁶2⁵2⁴2³2²2¹2⁰

Figure 2. Programmable Counter-Mask Register Operation^[58]

The burst counter has a mask register that controls when and

where the counter wraps. An interrupt flag (CNTINT) is assert-

ed for one clock cycle when the unmasked portion of the

counter address reaches maximum count (all 1s). The exam-

ple in Figure 2 shows the counter mask register loaded with a

mask value of 003F unmasking the first 6 bits with bit “0” as

the LSB and bit “15” as the MSB. The maximum value the

mask register can be loaded with is FFFF. Setting the mask

register to this value allows the counter to access the entire

memory space. The address counter is then loaded with an

initial value of XXX8. The “blocked” addresses (in this case,

the 6th address through the 15th address) are loaded with an

address but do not increment once loaded. The counter ad-

dress will start at address XXX8. With CNTINC asserted LOW,

the counter will increment its internal address value till it reach-

es the mask register value of 3F and wraps around the mem-

ory block to location XXX0. Therefore, the counter uses the

mask-register to define wrap-around point. The mask register

of a port is loaded when MKLD (mask register load) for that

port is LOW. When MKRD is LOW, the value of the mask reg-

ister can be read out on the address lines in a manner similar

to the counter read back operation (see Table 3 for required

conditions).

If the loaded value for address counter bit 0 is “0,” the counter

will increment by two and the address values are even. If the

loaded value for address counter bit 0 is “1,” the counter will

increment by two and the address values are odd. This oper-

ation allows the user to achieve an 80-bit interface using any

two ports, where the counter of one port counts even address-

es and the counter of the other port counts odd addresses.

This even-odd address scheme stores one half of an 80-bit

word in even memory locations, and the other half in odd mem-

ory locations. CNTINT will be asserted when the unmasked

portion of the counter reaches its maximum count. Loading

mask register bit 0 with “1” allows the counter to increment the

address value sequentially.

Table 3 groups the operations of the mask register with the

operations of the address counter. Address counter and mask

register signals are all synchronized to the port's clock C+.

Master reset (MRST) is the only asynchronous signal listed on

Table 3. Signals are listed based on their priority going from

left column to right column with MRST being the highest. A

LOW on MRST will reset the counter register to all zeros and

the mask register to all ones. On the other hand, a LOW on

CNTRST will only clear the address counter register to zeros

and the mask register will remain unaffected.

When the burst counter is loaded with an address higher than

the mask register value, the higher addresses will form the

masked portion of the counter address and are called blocked

addresses. The blocked addresses will not be changed or af-

fected by the counter increment operation. The only exception

is mask register bit 0. It can be masked to allow the address

counter to increment by two. If the mask register bit 0 is loaded

with a logic value of “0,” then address counter bit 0 is masked

and can not be changed during counter increment operation.

There are four operations for the counter and mask register:

1. Load operation: When CNTLD or MKLD is LOW, the ad-

dress counter or the mask register is loaded with the ad-

dress value presented at the address lines. This value rang-

es from 0 to FFFF (64K). The mask register load operation

has a higher priority over the address counter load opera-

tion.

Note:

58. The “X” in this diagram represents the counter upper-bits.

Document #: 38-06065 Rev. **

Page 43 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

2. Increment: Once the address counter is loaded with an ex-

ternal address, the counter can internally increment the ad-

dress value by asserting CNTINC LOW. The counter can

address the entire memory array (depend on the value of

the mask register) and loop back to location 0. The incre-

ment operation is second in priority to the load operation.

Test Data Out (TDO)

The TDO output pin is used to serially clock data out from the

registers. The output is active depending upon the current

state of the TAP state machine (see TAP Controller State Dia-

gram (FSM)). The output changes on the falling edge of TCK.

TDO is connected to the least significant bit (LSB) of any reg-

ister.

3. Readback: The internal value of either the burst counter or

themaskregistercanbereadoutontheaddresslineswhen

CNTRD or MKRD is LOW. Counter readback has higher

priority over mask register readback. Counter and mask

register readback have the same latency as memory READ

operations, i.e., three (3) cycles. The address will be valid

after t_CA2(for counter readback) or t_CM2(for mask read-

back) from the port’s third following clock rising edge. Ad-

dress readback operation is independent of the port’s chip

enables (CE₀and CE₁). If address readback occurs while

the port is enabled (chip enables active), the data lines

(I/Os) will be three-stated, during the cycle the address is

driven from the part.

Test Reset (TRSTB)

This input provides for asynchronous initialization of the TAP

controller. According to IEEE 1149.1-2001 the TAP controller

shall be asynchronously reset to the TEST-Logic_reset con-

troller state when a 0 logic is applied to TRSTB. TAP initializa-

tion is independent of system initialization (MRSTB).

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the QuadPort DSE

test circuitry. Only one register can be selected at a time

through the instruction registers. Data is serially loaded into

the TDI pin on the rising edge of TCK. Data is output on the

TDO pin on the falling edge of TCK.

4. Hold operation: In order to hold the value of the address

counter at certain address, all signals in Table 3 have to be

HIGH. This operation has the least priority. This operation

is useful in many applications where wait states are needed

or when the address is available few cycles ahead of data.

Instruction Register

Four-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the

TDI and TDO pins as shown in the following JTAG/BIST Con-

troller diagram. Upon power-up, the instruction register is load-

ed with the IDCODE instruction. It is also loaded with the ID-

CODE instruction if the controller is placed in a reset state as

described in the Test Reset section. When the TAP controller

is in the CaptureIR state, the two least significant bits are load-

ed with a binary “01” pattern to allow for fault isolation of the

board level serial test path.

The counter and mask register operations are totally indepen-

dent of port chip enables.

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C0452/451/450/431/430V18 incorporates a serial

boundary scan test access port (TAP). This port operates in

accordance with IEEE Standard 1149.1-2001. Note that the

TAP controller functions in a manner that does not conflict with

the operation of other devices using 1149.1 fully compliant

TAPs. The TAP operates using JEDEC standard 3.3V I/O logic

levels. It is composed of four input connections and one output

connection required by the test logic defined by the standard.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain devices. The bypass

register is a single-bit register that can be placed between TDI

and TDO pins. This allows data to be shifted through the

QuadPort DSE with minimal delay. The bypass register is set

LOW (V_SS) when the BYPASS instruction is executed.

Disabling the JTAG Feature

It is possible to operate the QuadPort DSE without using the

JTAG feature, by setting TRST* to ground (V_SS)

.

Test Access Port (TAP) – Test Clock (TCK)

Boundary Scan Register

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

The boundary scan register is connected to all the input and

output pins on the QuadPort DSE. The boundary scan register

is loaded with the contents of the QP Input and Output ring

when the TAP controller is in the Capture-DR state and is then

placed between the TDI and TDO pins when the controller is

moved to the Shift-DR state. The EXTEST, and SAM-

PLE/PRELOAD instructions can be used to capture the con-

tents of the Input and Output ring.

Test Mode Select

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

Identification (ID) Register

Test Data-In (TDI)

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the QuadPort DSE and can be shifted out when the TAP

controller is in the Shift-DR state. The ID register has a vendor

code and other information described in the Identification Reg-

ister Definitions table.

The TDI pin is used to serially input information into the regis-

ters and can be connected to the input of any of the registers.

The register between TDI and TDO is chosen by the instruc-

tion that is loaded into the TAP instruction register. For infor-

mation on loading the instruction register, see the TAP Con-

troller State Diagram. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) on any register.

Document #: 38-06065 Rev. **

Page 44 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

TAP Instruction Set

SAMPLE/PRELOAD

Sixteen different instructions are possible with the 4-bit instruc-

tion register. All combinations are listed in Table 6, Instruction

Codes. Seven of these instructions (codes) are listed as RE-

SERVED and should not be used. The other nine instructions

are described in detail below. The TAP controller used in this

QuadPort DSE is fully compliant to the 1149.1 convention. The

TAP controller can be used to load address, data or control

signals into the QuadPort DSE and can preload the Input or

output buffers. The QuadPort DSE implements all of the

1149.1 instructions except INTEST. Table 6 lists all instruc-

tions. Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP control-

ler needs to be moved into the Update-IR state.

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the in-

struction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is cap-

tured in the boundary scan register. The user must be aware

that the TAP controller clock can only operate at a frequency

up to 10 MHz, while the QuadPort DSE clock operates more

than an order of magnitude faster. Because there is a large

difference in the clock frequencies, it is possible that during the

Capture-DR state, an input or output will undergo a transition.

The TAP may then try to capture a signal while in transition

(metastable state). This will not harm the device, but there is

no guarantee as to the value that will be captured. Repeatable

results may not be possible. To guarantee that the boundary

scan register will capture the correct value of a signal, the

QuadPort DSE signal must be stabilized long enough to meet

the TAP controller’s capture set-up plus hold times. Once the

data is captured, it is possible to shift out the data by putting

the TAP into the Shift-DR state. This places the boundary scan

register between the TDI and TDO pins. If the TAP controller

goes into the Update-DR state, the sampled data will be up-

dated.

EXTEST

EXTEST is a mandatory 1149.1 instruction that is to be exe-

cuted whenever the instruction register is loaded with all 0s.

EXTEST allows circuitry external to the QuadPort DSE pack-

age to be tested. Boundary-scan register cells at output pins

are used to apply test stimuli, while those at input pins capture

test results.

BYPASS

When the BYPASS instruction is loaded in the instruction reg-

ister and the TAP is placed in a Shift-DR state, the bypass

register is placed between the TDI and TDO pins. The advan-

tage of the BYPASS instruction is that it shortens the boundary

scan path when multiple devices are connected together on a

board.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the identification register. It also places the

identification register between the TDI and TDO pins and al-

lows the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

is loaded into the instruction register upon power-up or

when-ever the TAP controller is given a test logic reset state.

CLAMP

The optional CLAMP instruction allows the state of the signals

driven from QuadPort DSE pins to be determined from the

boundary-scan register while the BYPASS register is selected

as the serial path between TDI and TDO. CLAMP controls

boundary cells to 1 or 0.

High-Z

The High-Z instruction causes the bypass register to be con-

nected between the TDI and TDO pins when the TAP control-

ler is in a Shift-DR state. It also places all QuadPort DSE out-

puts into a High-Z state.

Document #: 38-06065 Rev. **

Page 45 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Tap Controller State Diagram (FSM)^[59]

TEST-LOGIC

1

RESET

1

RUN_TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

CAPTURE-IR

0

SHIFT-DR

0

SHIFT-IR

0

1

EXIT1-DR

0

1

EXIT1-IR

0

1

0

PAUSE-DR

1

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-DR

UPDATE-IR

1

0

Note:

59. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 38-06065 Rev. **

Page 46 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

0

Bypass Register (BYR)

3

2

1

0

Instruction Register (IR)

0

31 30 29

Identification Register (IDR)

Selection

TDO

Circuitry

TDI

39 38 37

0

EID Register

(MUX)

63 62 61

0

VIS Register

557

0

Boundary Scan Register (BSR)

TAP

CONTROLLER

TCK

TMS

TRST

Document #: 38-06065 Rev. **

Page 47 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Table 5. Scan Registers Sizes

Register Name

Bit Size

Bypass (BYR)

Instruction (IR)

1

4

Identification (IDR)

32

40

64

558

Electrical Identification Register (EID)

Variable Impedance Register (VIS)

Boundary Scan (BSR)

Table 6. Instruction Identification Codes

Instruction

Bypass

Code

Description

1111

Places the bypass register (BYR) between TDI and TDO.

Sample/Preload

Extest^[60]

1000

Captures the Input/Output ring contents. Places the boundary scan register (BSR)

between TDI and TDO.

0000

1011

Captures the Input/Output ring contents. Places the boundary scan register (BSR)

between the TDI and TDO.

Idcode

Loads the ID register (IDR) with the vendor ID code and places the register be-

tween TDI and TDO.

Clamp^[60]

Highz^[60]

0100

0111

Controls boundary to 1/0. Uses BYR.

Places the BYR between TDI and TDO. Forces all QuadPort DSE output drivers

to a High-Z state.

Intest^[60]

0001

Allows testing of the on-chip system logic while the component is assembled on

the board. The test stimuli are shifted in one at a time and applied to the on-chip

system logic.

Eidcode

VIS

1001

1010

Loads the Electrical Identification Register (EID) with the vendor Electrical ID code

and places the register between TDI and TDO.

Loads the Variable Impedance Register (VIS) with the vendor VIS ID code and

places the register between TDI and TDO.

Note:

60. Instruction that requires a master reset after completion before using the chip in normal mode

Document #: 38-06065 Rev. **

Page 48 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Ordering Information

128K x 40 1.8V Synchronous QuadPort DSE

Speed

Package

Name

Operating

(MHz)

Ordering Code

CY7C0452V18-167BBI

CY7C0452V18-167BBC

CY7C0452V18-133BBI

CY7C0452V18-133BBC

CY7C0452V18-100BBC

Package Type

Range

167

BB676

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Industrial

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Industrial

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial

133

100

64K x 40 1.8V Synchronous QuadPort DSE

Speed

Package

Name

Operating

(MHz)

Ordering Code

CY7C0451V18-167BBI

CY7C0451V18-167BBC

CY7C0451V18-133BBI

CY7C0451V18-133BBC

CY7C0451V18-100BBC

Package Type

Range

167

BB676

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Industrial

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Industrial

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial

133

100

32K x 40 1.8V Synchronous QuadPort DSE

Speed

(MHz)

167

Package

Name

Operating

Ordering Code

CY7C0450V18-167BBC

CY7C0450V18-133BBC

CY7C0450V18-100BBC

Package Type

Range

BB676

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial

133

100

128K x 20 1.8V Synchronous QuadPort DSE

Speed

Package

Name

Operating

(MHz)

Ordering Code

CY7C0431V18-167BBI

CY7C0431V18-167BBC

CY7C0431V18-133BBC

CY7C0431V18-100BBC

Package Type

Range

167

BB676

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Industrial

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial

133

100

64K x 20 1.8V Synchronous QuadPort DSE

Speed

Package

Name

Operating

(MHz)

Ordering Code

CY7C0430V18-167BBC

CY7C0430V18-133BBC

CY7C0430V18-100BBC

Package Type

Range

167

BB676

Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch Commercial

133

100

Document #: 38-06065 Rev. **

Page 49 of 51

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Package Diagram

676-Ball FBGA (27 x 27 x 1.6 mm) BB676

51-85125-*B

QuadPort is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document

may be the trademarks of their respective holders.

Document #: 38-06065 Rev. **

Page 50 of 51

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C0452V18/0451V18/0450V18

PRELIMINARY

CY7C0431V18/0430V18

Document Title: CY7C0452V18/0451V18/0450V18/0431V18/0430V18 QuadPort™ Datapath Switching Element (DSE)

Family

Document Number: 38-06065

Issue

Date

Orig. of

Change

REV.

ECN NO.

Description of Change

**

117356

08/02/02

OOR

New Data Sheet

Document #: 38-06065 Rev. **

Page 51 of 51


型号：	CY7C0431V18-167BBI
厂家：	CYPRESS
描述：	Multi-Port SRAM, 128KX20, 3.5ns, CMOS, PBGA676 时钟静态存储器内存集成电路
文件：	总51页 (文件大小：962K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C0431V18-167BBI [CYPRESS]

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