CY7C027-20AXCT [CYPRESS]
Multi-Port SRAM, 32KX16, 20ns, CMOS, PQFP100, ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100;
| 型号： | CY7C027-20AXCT |
| 厂家： | 
CYPRESS |
| 描述： | Multi-Port SRAM, 32KX16, 20ns, CMOS, PQFP100, ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C027/028
CY7C037/03832K/64K
x 16/18 Dual-Port Static RAM
CY7C027/028
CY7C037/038
32K/64K x 16/18 Dual-Port Static RAM
■
■
Automatic power down
Features
Expandable data bus to 32 and 36 bits or more using
Master/Slave chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flags for port-to-port communication
Separate upper-byte and lower-byte control
Dual chip enables
■
True dual-ported memory cells which allow simultaneous
access of the same memory location
32K x 16 organization (CY7C027)
64K x 16 organization (CY7C028)
32K x 18 organization (CY7C037)
64K x 18 organization (CY7C038)
0.35 micron CMOS for optimum speed and power
High speed access: 12[1], 15, and 20 ns
Low operating power
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Pin select for Master or Slave
Commercial and industrial temperature ranges
Available in 100-pin TQFP
Active: ICC = 180 mA (typical)
Standby: ISB3 = 0.05 mA (typical)
Fully asynchronous operation
Pb-free packages available
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE0R
CE1L
CE1R
CEL
CER
LBL
LBR
OEL
OER
8/9
[2]
8/9
[2]
I/O8/9L–I/O15/17L
I/O8/9L–I/O15/17R
8/9
8/9
I/O
Control
I/O
Control
[3]
[3]
I/O0L–I/O7/8L
I/O0L–I/O7/8R
15/16
15/16
Address
Decode
Address
Decode
True Dual-Ported
RAM Array
[4]
[4]
A0L–A14/15L
A0R–A14/15R
15/16
15/16
[4]
[4]
A0L–A14/15L
A0R–A14/15R
CEL
CER
OER
Interrupt
Semaphore
Arbitration
OEL
R/WL
SEML
R/WR
SEMR
[5]
[5]
BUSYL
BUSYR
INTL
UBL
LBL
INTR
UBR
LBR
M/S
Notes
1. See page 6 for Load Conditions.
2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
8
15
9
17
3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
0
7
0
8
4. A –A for 32K; A –A for 64K devices.
0
14
0
15
5. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06042 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 10, 2008
[+] Feedback
CY7C027/028
CY7C037/038
Each port has independent control pins: dual chip enables (CE0
and CE1), read or write enable (R/W), and output enable (OE).
Two flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore)
at any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power down feature is controlled
independently on each port by the chip enable pins.
Functional Description
The CY7C027/028 and CY7C037/038 are low power CMOS
32K, 64K x 16/18 dual-port static RAMs. Various arbitration
schemes are included on the devices to handle situations when
multiple processors access the same piece of data. Two ports
are provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can be
used as standalone 16 and 18-bit dual-port static RAMs or
multiple devices can be combined to function as a 32/36-bit or
wider master/slave dual-port static RAM. An M/S pin is provided
for implementing 32/36-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor and
multiprocessor designs, communications status buffering, and
dual-port video/graphics memory.
The CY7C027/028 and CY7C037/038 are available in 100-pin
Thin Quad Plastic Flatpack (TQFP) packages.
Pin Configurations
Figure 1. 100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
A14L
A15L
NC
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A9R
2
A10R
A11R
A12R
A13R
A14R
A15R
NC
3
4
5
6
[6]
[6]
7
8
NC
9
NC
LBL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
LBR
UBL
UBR
CE0R
CE1R
CE0L
CE1L
CY7C028 (64K x 16)
CY7C027 (32K x 16)
SEML
VCC
SEMR
GND
R/WL
OEL
R/WR
OER
GND
GND
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O11L
I/O10L
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note
6. This pin is NC for CY7C027.
Document #: 38-06042 Rev. *D
Page 2 of 19
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CY7C027/028
CY7C037/038
Pin Configurations (continued)
Figure 2. 100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
A14L
A15L
LBL
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A8R
2
A9R
3
A10R
A11R
A12R
A13R
A14R
4
5
6
[7]
7
[7]
8
A15R
LBR
UBL
9
CE0L
CE1L
SEML
R/WL
OEL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
UBR
CE0R
CE1R
CY7C038 (64K x 18)
CY7C037 (32K x 18)
SEMR
R/WR
GND
VCC
GND
OER
I/O17L
I/O16L
GND
GND
I/O17R
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O11L
I/O10L
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C027/028 CY7C027/028 CY7C027/028
CY7C037/038 CY7C037/038 CY7C037/038
Parameter
Unit
-12[1]
12
-15
-20
Maximum Access Time
15
20
ns
Typical Operating Current
195
55
190
50
180
45
mA
mA
mA
Typical Standby Current for ISB1 (Both ports TTL level)
Typical Standby Current for ISB3 (Both ports CMOS level)
0.05
0.05
0.05
Note
7. This pin is NC for CY7C037.
Document #: 38-06042 Rev. *D
Page 3 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Pin Definitions
Left Port
CE0L, CE1L
R/WL
Right Port
CE0R, CE1R
Description
Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH)
Read/Write Enable
R/WR
OEL
OER
Output Enable
A0L–A15L
I/O0L–I/O17L
SEML
A0R–A15R
I/O0R–I/O17R
SEMR
UBR
Address (A0–A14 for 32K; A0–A15 for 64K devices)
Data Bus Input/Output (I/O0–I/O15 for x16 devices; I/O0–I/O17 for x18)
Semaphore Enable
UBL
Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices)
LBL
LBR
Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices)
INTL
INTR
Interrupt Flag
Busy Flag
BUSYL
M/S
BUSYR
Master or Slave Select
Power
VCC
GND
Ground
NC
No Connect
Document #: 38-06042 Rev. *D
Page 4 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Input Voltage[9] ...............................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >1100V
Latch-Up Current.................................................... >200 mA
Maximum Ratings[8]
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature .................................–65
°
C to +150
°C
Ambient Temperature with
Power Applied ............................................–55
Operating Range
°
C to +125
°C
Ambient
Supply Voltage to Ground Potential................–0.3V to +7.0V
Range
Commercial
Industrial[10]
Temperature
VCC
DC Voltage Applied to Outputs
in High Z State.............................................–0.5V to +7.0DC
0
°
C to +70
°
C
5V ± 10%
5V ± 10%
–40 C to +85°C
°
Electrical Characteristics Over the Operating Range
CY7C027/028
CY7C037/038
Symbol
Parameter
Unit
-12[1]
Typ
-15
-20
Min
Max
Min
Typ
Max
Min
Typ
Max
VOH
Output HIGH Voltage (VCC = Min, IOH
–4.0 mA)
=
2.4
2.4
2.4
V
V
VOL
Output LOW Voltage (VCC = Min, IOH
+4.0 mA)
=
0.4
0.4
0.4
VIH
VIL
IOZ
ICC
Input HIGH Voltage
Input LOW Voltage
2.2
2.2
2.2
V
0.8
10
0.8
10
0.8
10
V
Output Leakage Current
–10
–10
–10
μA
mA
mA
Operating Current (VCC=Max,
OUT=0 mA)
Com’l.
Ind.[10]
195
55
325
190
50
280
180
305
265
290
I
Outputs Disabled
ISB1
Standby Current (Both Ports
TTL Level) CEL & CER ≥ VIH, f
= fMAX
Com’l.
Ind.[10]
75
70
45
60
65
80
mA
mA
ISB2
ISB3
Standby Current (One Port TTL Com’l.
125
205
0.5
120
180
0.5
110
125
0.05
0.05
160
175
0.5
0.5
mA
mA
mA
mA
Level) CEL | CER ≥ VIH, f = fMAX
Ind.[10]
Com’l.
Ind.[10]
Standby Current (Both Ports
CMOS Level) CEL & CER ≥ VCC
– 0.2V, f = 0
0.05
0.05
ISB4
Standby Current (One Port
Com’l.
Ind.[10]
115
185
110
160
100
115
140
155
mA
mA
CMOS Level) CEL | CER ≥ VIH,
[11]
f = fMAX
Notes
8. The voltage on any input or I/O pin cannot exceed the power pin during power up.
9. Pulse width < 20 ns.
10. Industrial parts are available in CY7C028 and CY7C038 only.
11. f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS
MAX
RC RC
level standby I
SB3.
Document #: 38-06042 Rev. *D
Page 5 of 19
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CY7C027/028
CY7C037/038
Capacitance[12]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
C, f = 1 MHz,
CC = 5.0V
Max
10
Unit
pF
CIN
TA = 25°
V
COUT
10
pF
Figure 3. AC Test Loads and Waveforms
5V
5V
R
TH
= 250Ω
R1 = 893Ω
R2 = 347Ω
OUTPUT
C = 30 pF
OUTPUT
R1 = 893Ω
OUTPUT
C = 5 pF
C = 30 pF
R2 = 347Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
(b) Thévenin Equivalent (Load 1)
ALL INPUTPULSES
3.0V
GND
90%
90%
10%
3 ns
10%
3 ns
≤
≤
AC Test Loads (Applicable to -12 only)[13]
1.00
0.90
Z0 = 50Ω
R = 50Ω
OUTPUT
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
C
V
TH
= 1.4V
(a) Load 1 (-12 only)
0
5
10
15
20
25
30
(pF)
Capacitance
(b) Load Derating Curve
Notes
12. Tested initially and after any design or process changes that may affect these parameters.
13. Test conditions: C = 0 pF.
Document #: 38-06042 Rev. *D
Page 6 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Switching Characteristics Over the Operating Range[14]
CY7C027/028
CY7C037/038
Parameter
Description
Unit
-20
-12[1]
Max
-15
Min
12
3
Min
15
3
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
20
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
12
15
20
tOHA
[15]
tACE
tDOE
tLZOE
12
8
15
10
20
12
[16, 17, 18]
[16, 17, 18]
3
3
0
3
3
0
3
3
0
tHZOE
OE HIGH to High Z
10
10
10
10
12
12
[16, 17, 18]
tLZCE
CE LOW to Low Z
[16, 17, 18]
tHZCE
CE HIGH to High Z
[18]
tPU
tPD
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable Access Time
[18]
12
12
15
15
20
20
[15]
tABE
Write Cycle
tWC
Write Cycle Time
12
10
10
0
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[15]
tSCE
tAW
tHA
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Setup to Write Start
Write Pulse Width
[15]
tSA
tPWE
tSD
0
0
0
10
10
0
12
10
0
15
15
0
Data Setup to Write End
Data Hold From Write End
R/W LOW to High Z
tHD
[17, 18]
tHZWE
10
10
12
[17, 18]
tLZWE
R/W HIGH to Low Z
3
3
3
[19]
tWDD
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
25
20
30
25
45
30
[19]
tDDD
Busy Timing[20]
tBLA
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Setup for Priority
12
12
12
12
15
15
15
15
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
ns
tBHA
tBLC
tBHC
tPS
5
0
5
0
5
0
tWB
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
tWH
11
13
15
[21]
tBDD
12
15
20
Notes
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I /I
OI OH
and 30 pF load capacitance.
15. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
time.
SCE
16. At any given temperature and voltage condition for any given device, t
17. Test conditions used are Load 2.
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
18. This parameter is guaranteed by design, but it is not production tested.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11.
20. Test conditions used are Load 1.
Document #: 38-06042 Rev. *D
Page 7 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Switching Characteristics Over the Operating Range[14] (continued)
CY7C027/028
CY7C037/038
Parameter
Description
Unit
-20
-12[1]
Max
-15
Min
Min
Max
Min
Max
INTERRUPT TIMING[20]
tINS
INT Set Time
12
12
15
15
20
20
ns
ns
tINR
INT Reset Time
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
10
5
10
5
ns
ns
ns
ns
5
5
5
tSAA
12
15
20
Timing
Data Retention Mode
Data Retention Mode
4.5V
The CY7C027/028 and CY7C037/038 are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
V
CC
4.5V
V
CC
> 2.0V
t
RC
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
V
CC
to V – 0.2V
CC
V
IH
CE
2. CE must be kept between VCC – 0.2V and 70% of VCC during
the power up and power down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5V).
Parameter
Test Conditions[22]
Max
1.5
Unit
ICCDR1
At VCCDR = 2V
mA
Notes
21. t
is a calculated parameter and is the greater of t
–t
(actual) or t
–t (actual).
BDD
WDD PWE
DDD SD
22. CE = V , V = GND to V , T = 25°C. This parameter is guaranteed but not tested.
CC
in
CC
A
Document #: 38-06042 Rev. *D
Page 8 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access)[23 ,24, 25]
t
RC
ADDRESS
DATA OUT
t
AA
t
t
OHA
OHA
PREVIOUS DATAVALID
DATA VALID
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)[23, 26, 27]
t
ACE
CE and
LB or UB
t
HZCE
t
DOE
OE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
Figure 6. Read Cycle No. 3 (Either Port)[23, 25, 26, 27]
t
RC
ADDRESS
UB or LB
t
AA
t
OHA
t
t
HZCE
t
t
LZCE
LZCE
t
ABE
CE
HZCE
t
ACE
DATA OUT
Notes
23. R/W is HIGH for read cycles.
24. Device is continuously selected CE = V and UB or LB = V . This waveform cannot be used for semaphore reads.
IL
IL
25. OE = V .
IL
26. Address valid prior to or coincident with CE transition LOW.
27. To access RAM, CE = V , UB or LB = V , SEM = V . To access semaphore, CE = V , SEM = V .
IL
IL
IH
IH
IL
Document #: 38-06042 Rev. *D
Page 9 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1: R/W Controlled Timing[28, 29, 30, 31]
t
WC
ADDRESS
OE
[34]
t
HZOE
t
AW
[32,33]
CE
[31]
PWE
t
t
t
HA
SA
R/W
DATAOUT
DATA IN
[34]
HZWE
t
t
LZWE
NOTE 35
NOTE 35
t
t
HD
SD
Figure 8. Write Cycle No. 2: CE Controlled Timing[28, 29, 30, 34, 35]
t
WC
ADDRESS
t
AW
[32,33]
CE
t
t
t
HA
SA
SCE
R/W
t
t
HD
SD
DATA IN
Notes
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (t or t ) of a LOW CE or SEM and a LOW UB or LB.
SCE
PWE
30. t is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data
PWE
HZWE SD
to be placed on the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
SD
as short as the specified t
.
PWE
32. To access RAM, CE = V , SEM = V
.
IH
IL
33. To access upper byte, CE = V , UB = V , SEM = V .
IL
IL
IL
IL
IH
IH
To access lower byte, CE = V , LB = V , SEM = V .
34. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document #: 38-06042 Rev. *D
Page 10 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Switching Waveforms (continued)
Figure 9. Semaphore Read After Write Timing, Either Side[37]
t
t
OHA
SAA
A –A
0
VALID ADRESS
VALID ADRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Figure 10. Timing Diagram of Semaphore Contention[38, 39, 40]
A
0L
–A
2L
MATCH
R/W
L
SEM
–A
L
t
SPS
A
MATCH
0R
2R
R/W
R
SEM
R
Notes
37. CE = HIGH for the duration of the above timing (both write and read cycle).
38. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
39. Semaphores are reset (available to both ports) at cycle start.
40. If t is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
SPS
Document #: 38-06042 Rev. *D
Page 11 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Switching Waveforms (continued)
Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH)[41]
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Figure 12. Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note
41. CE = CE = LOW.
L
R
Document #: 38-06042 Rev. *D
Page 12 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Switching Waveforms (continued)
Figure 13. Busy Timing Diagram No.1 (CE Arbitration)[42]
CELValid First:
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER ValidFirst:
ADDRESS
L,R
ADDRESS MATCH
CE
R
t
PS
CE
L
L
t
t
BHC
BLC
BUSY
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)[42]
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right AddressValid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note
42. If t is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
PS
Document #: 38-06042 Rev. *D
Page 13 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Switching Waveforms (continued)
Figure 15. Interrupt Timing Diagrams
Left Side Sets INTR:
t
WC
ADDRESS
WRITE 7FFF (FFFF for CY7C028/38)
[43]
L
t
HA
CE
L
R/W
INT
L
R
[44]
t
INS
Right Side Clears INTR:
t
RC
READ 7FFF
(FFFF for CY7C028/38)
ADDRESS
R
CE
R
[44]
t
INR
R/W
R
OE
R
INT
R
:
Right Side Sets INTL
t
WC
ADDRESS
R
WRITE 7FFE (FFFE for CY7C028/38)
[43]
t
HA
CE
R
R
R/W
INT
L
[44]
INS
t
Left SideClears INTL:
t
RC
READ 7FFE
(FFFE for CY7C028/38)
ADDRESS
CE
R
L
[44]
t
INR
R/W
OE
L
L
L
INT
Notes
43. t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
44. t
or t
depends on which enable pin (CE or R/W ) is asserted last.
INS
INR L L
Document #: 38-06042 Rev. *D
Page 14 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Busy
Architecture
The CY7C027/028 and CY7C037/038 provide on-chip
arbitration to resolve simultaneous memory location access
(contention). If both ports’ CEs are asserted and an address
match occurs within tPS of each other, the busy logic determines
which port has access. If tPS is violated, one port definitely gains
permission to the location, but it is not predictable which port gets
that permission. BUSY is asserted tBLA after an address match
or tBLC after CE is taken LOW.
The CY7C027/028 and CY7C037/038 consist of an array of 32K
and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O
and address lines, and control signals (CE, OE, R/W). These
control pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes/reads to the
same location, a BUSY pin is provided on each port. Two
interrupt (INT) pins can be used for port-to-port communication.
Two semaphore (SEM) control pins are used for allocating
shared resources. With the M/S pin, the devices can function as
a master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power down feature
controlled by CE. Each port is provided with its own output
enable control (OE), which allows data to be read from the
device.
Master/Slave
A M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (tBLC or tBLA), otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see Figure 7) or the CE pin (see Figure 8).
Required inputs for non-contention operations are summarized
in Table 1.
Semaphore Operation
The CY7C027/028 and CY7C037/038 provide eight semaphore
latches, which are separate from the dual-port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports.The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for tSOP before attempting to read the semaphore.
The semaphore value is available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore. When the right side has relin-
quished control of the semaphore (by writing a one), the left side
succeeds in gaining control of the semaphore. If the left side no
longer requires the semaphore, a one is written to cancel its
request.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port tDDD after
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the
CY7C027/37, FFFF for the CY7C028/38) is the mailbox for the
right port and the second-highest memory location (7FFE for the
CY7C027/37, FFFE for the CY7C028/38) is the mailbox for the
left port. When one port writes to the other port’s mailbox, an
interrupt is generated to the owner. The interrupt is reset when
the owner reads the contents of the mailbox. The message is
user defined.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Table 3 shows sample semaphore opera-
tions.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy is
summarized in Table 2.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
Document #: 38-06042 Rev. *D
Page 15 of 19
[+] Feedback
CY7C027/028
CY7C037/038
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within tSPS of each other, the semaphore is
definitely obtained by one side or the other, but there is no
guarantee which side controls the semaphore.
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
X
L
R/W
X
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
H
H
H
H
H
H
X
I/O9–I/O17
High Z
I/O0–I/O8
High Z
Operation
Deselected: Power Down
Deselected: Power Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
High Z
High Z
L
Data In
High Z
High Z
L
L
H
L
Data In
Data In
High Z
L
L
L
Data In
Data Out
High Z
L
H
H
H
X
L
H
L
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
Data Out
Data Out
High Z
L
L
L
Data Out
High Z
X
H
X
H
H
L
X
X
H
X
X
X
H
X
Outputs Disabled
H
H
L
Data Out
Data Out
Data In
Data Out
Data Out
Data In
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
L
L
X
L
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
L
L
X
X
X
X
L
X
L
L
L
Not Allowed
Not Allowed
X
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[23]
Left Port
Right Port
Function
R/WL CEL
OEL
X
A0L–14L
7FFF
X
INTL R/WR CER
OER
X
A0R–14R
X
INTR
L[25]
H[24]
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
X
L
X
L
L
X
X
X
L
7FFF
7FFE
X
X
X
L[24]
H[25]
X
L
7FFE
X
X
X
Table 3. Semaphore Operation Example
Function I/O0–I/O17 Left I/O0–I/O17 Right
Status
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Left port writes 1 to semaphore
Notes
23. A
and A
, FFFF/FFFE for the CY7C028/038.
0R–15R
0L–15L
24. If BUSY = L, then no change.
R
25. If BUSY = L, then no change.
L
Document #: 38-06042 Rev. *D
Page 16 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Ordering Information
32K x16 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
12[1]
15
Ordering Code
Package Type
100-Pin Thin Quad Flat Pack
CY7C027-12AC
A100
A100
A100
A100
A100
Commercial
Commercial
Industrial
CY7C027-15AC
CY7C027-15AXI
CY7C027-20AC
CY7C027-20AXC
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
Commercial
Commercial
100-Pin Pb-Free Thin Quad Flat Pack
64K x16 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
100-Pin Thin Quad Flat Pack
12[1]
CY7C028-12AC
A100
A100
A100
A100
A100
A100
A100
A100
Commercial
Commercial
Commercial
Commercial
Industrial
CY7C028-12AXC
CY7C028-15AC
CY7C028-15AXC
CY7C028-15AI
CY7C028-15AXI
CY7C028-20AC
CY7C028-20AI
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
15
20
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
Commercial
Industrial
100-Pin Thin Quad Flat Pack
32K x18 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
12[1]
15
Ordering Code
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
CY7C037-12AC
A100
A100
A100
Commercial
Commercial
Commercial
CY7C037-15AC
CY7C037-20AC
20
64K x18 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
12[1]
15
Ordering Code
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
CY7C038-12AC
A100
A100
A100
A100
Commercial
Commercial
Commercial
Industrial
CY7C038-15AC
CY7C038-20AC
CY7C038-20AI
20
Document #: 38-06042 Rev. *D
Page 17 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Package Diagram
Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*C
Document #: 38-06042 Rev. *D
Page 18 of 19
[+] Feedback
CY7C027/028
CY7C037/038
Document History Page
Document Title: CY7C027/028, CY7C037/038 32K/64K x 16/18 Dual-Port Static RAM
Document Number: 38-06042
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
110190
122292
236765
377454
SZV
RBI
09/29/01
12/27/02
6/23/04
Change from Spec number: 38-00666 to 38-06042
*A
*B
*C
Power up requirements added to Maximum Ratings Information
Removed cross information from features section
YDT
PCX
See ECN Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C027-20AXC, CY7C028-12AXC, CY7C028-15AXC, CY7C028-15AI,
CY7C028-15AXI
*D
2623540 VKN/PYRS
12/17/08
Added CY7C027-15AXI in the Ordering information table
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Document #: 38-06042 Rev. *D
Revised December 10, 2008
Page 19 of 19
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