CY7C027AV-25AXI [CYPRESS]
3.3V 32K/64K x 16/18 Dual-Port Static RAM; 3.3V 32K / 64K X 16/18双端口静态RAM
| 型号： | CY7C027AV-25AXI |
| 厂家： | 
CYPRESS |
| 描述： | 3.3V 32K/64K x 16/18 Dual-Port Static RAM |
| 文件： | 总18页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
3.3V 32K/64K x 16/18 Dual-Port Static
RAM
■
■
■
Fully asynchronous operation
Automatic power down
Features
■
True Dual-Ported memory cells which allow
Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
simultaneous access of the same memory location
■
■
■
■
■
■
■
■
■
32K x 16 organization (CY7C027V/027VN/027AV [1]
)
■
■
On-chip arbitration logic
64K x 16 organization (CY7C028V)
Semaphores included to permit software handshaking
between ports
32K x 18 organization (CY7C037V/037AV[2]
64K x 18 organization (CY7C038V)
)
■
■
■
■
■
■
INT flag for port-to-port communication
Separate upper-byte and lower-byte control
Dual chip enables
0.35 micron CMOS for optimum speed and power
High speed access: 15, 20, and 25 ns
Low operating power
Pin select for Master or Slave
Active: ICC = 115 mA (typical)
Commercial and Industrial temperature ranges
100-pin Pb-free TQFP and 100-pin TQFP
Standby: ISB3 = 10 μA (typical)
Logic Block Diagram
R/W
R/W
UB
L
R
R
UB
L
CE
CE
CE
CE
0L
1L
0R
1R
CE
CE
R
L
LB
LB
R
L
L
OE
OE
R
8/9
8/9
[3]
15/17L
[4]
I/O
–I/O
I/O
–I/O[3]
8/9L
8/9L
15/17R
[4]
8/9
8/9
I/O
Control
I/O
Control
I/O –I/O
I/O –I/O
0L
7/8L
0L
7/8R
15/16
15/16
[5]
A
A
–A[5]
A
A
–A
Address
Decode
Address
Decode
True Dual-Ported
0L
14/15L
0R
14/15R
14/15R
RAM Array
15/16
15/16
–A[5]
[5]
–A
0L
14/15L
0R
CE
CE
R
Interrupt
Semaphore
Arbitration
L
OE
OE
R
L
R/W
SEM
R/W
SEM
L
R
R
L
[6]
[6]
BUSY
INT
BUSY
INT
UB
L
R
R
R
R
L
UB
L
LB
M/S
LB
L
Notes
1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical.
2. CY7C037V and CY7C037AV are functionally identical.
3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
8
15
9
17
4. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
0
7
0
8
5. A –A for 32K; A –A for 64K devices.
0
14
0
15
6. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06078 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 09, 2008
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Pin Configurations
Figure 1. 100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
A14L
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A9R
2
A10R
A11R
A12R
A13R
A14R
A15R [1]
NC
3
4
5
6
[1]
A15L
NC
7
8
NC
9
NC
LBL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
LBR
UBL
UBR
CE0L
CE1L
SEML
VCC
CE0R
CE1R
SEMR
GND
CY7C028V (64K x 16)
CY7C027V/027VN/027AV (32K x 16)
R/WL
OEL
R/WR
OER
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
GND
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O11L
I/O10L
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note
1. This pin is NC for CY7C027V/027VN/027AV.
Document #: 38-06078 Rev. *B
Page 2 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Pin Configurations (continued)
Figure 2. 100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
1
2
3
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
LBR
A12L
A13L
4
5
A14L
6
[2] A15L
LBL
7
[2]
8
UBL
9
CE0L
CE1L
SEML
R/WL
OEL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
UBR
CE0R
CE1R
SEMR
R/WR
GND
OER
GND
CY7C038V (64K x 18)
CY7C037V/037AV (32K x 18)
VCC
GND
I/O17L
I/O16L
GND
I/O17R
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O11L
I/O10L
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
Parameter
-15
15
-20
20
-25
Unit
ns
Maximum Access Time
25
Typical Operating Current
125
35
120
35
115
30
mA
mA
μA
Typical Standby Current for ISB1 (Both ports TTL level)
Typical Standby Current for ISB3 (Both ports CMOS level)
10 μA
10 μA
10 μA
Note
2. This pin is NC for CY7C037V/037AV.
Document #: 38-06078 Rev. *B
Page 3 of 18
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Pin Definitions
Left Port
CE0L, CE1L
R/WL
Right Port
CE0R, CE1R
Description
Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH)
R/WR
Read/Write Enable
OEL
OER
Output Enable
A
0L–A15L
A0R–A15R
I/O0R–I/O17R
SEMR
UBR
Address (A0–A14 for 32K; A0–A15 for 64K devices)
I/O0L–I/O17L
SEML
UBL
Data Bus Input/Output (I/O0–I/O15 for x16 devices; I/O0–I/O17 for x18)
Semaphore Enable
Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices)
LBL
LBR
Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices)
INTL
INTR
Interrupt Flag
Busy Flag
BUSYL
M/S
BUSYR
Master or Slave Select
Power
VCC
GND
NC
Ground
No Connect
systems by means of a mail box. The semaphores are used to pass a
flag, or token, from one port to the other to indicate that a shared
Architecture
resource is in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at any time.
Control of a semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on each port
by a chip select (CE) pin.
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V consist of an array of 32K and 64K words
of 16 and 18 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be utilized for
port-to-port communication. Two semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the devices can
function as a master (BUSY pins are outputs) or as a slave (BUSY pins
are inputs). The devices also have an automatic power down feature
controlled by CE. Each port is provided with its own output enable
control (OE), which allows data to be read from the device.
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V are available in 100-pin Thin Quad Plas-
tic Flatpacks (TQFP).
Write Operation
Data must be set up for a duration of tSD before the rising edge of
R/W to guarantee a valid write. A write operation is controlled by either
the R/W pin (see Figure 7) or the CE pin (see Figure 8). Required inputs
for non-contention operations are summarized in Table 1.
Functional Description
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port tDDD after
the data is presented on the other port.
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V are low power CMOS 32K, 64K x 16/18
dual-port static RAMs. Various arbitration schemes are included
on the devices to handle situations when multiple processors
access the same piece of data. Two ports are provided, permit-
ting independent, asynchronous access for reads and writes to
any location in memory. The devices can be utilized as
stand-alone 16/18-bit dual-port static RAMs or multiple devices
can be combined to function as a 32/36-bit or wider master/slave
dual-port static RAM. An M/S pin is provided for implementing
32/36-bit or wider memory applications without the need for sep-
arate master and slave devices or additional discrete logic. Ap-
plication areas include interprocessor/multiprocessor designs,
communications status buffering, and dual-port video/graphics
memory.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is asserted. If
the user wishes to access a semaphore flag, then the SEM pin must be
asserted instead of the CE pin, and OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the
CY7C027V/027VN/027AV/37V, FFFF for the CY7C028V/38V) is
the mailbox for the right port and the second-highest memory
location (7FFE for the CY7C027V/027VN/027AV/037V/037AV,
FFFE for the CY7C028V/38V) is the mailbox for the left port.
When one port writes to the other port’s mailbox, an interrupt is
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags are provided
on each port (BUSY and INT). BUSY signals that the port is trying to
access the same location currently being accessed by the other port.
The interrupt flag (INT) permits communication between ports or
Document #: 38-06078 Rev. *B
Page 4 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore. The
semaphore value is available tSWRD + tDOE after the rising edge of the
semaphore write. If the left port was successful (reads a zero), it
assumes control of the shared resource, otherwise (reads a one) it
assumes the right port has control and continues to poll the semaphore.
When the right side has relinquished control of the semaphore (by
writing a one), the left side succeeds in gaining control of the
semaphore. If the left side no longer requires the semaphore, a one is
written to cancel its request.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2.
Busy
Semaphores are accessed by asserting SEM LOW. The SEM pin
functions as a chip select for the semaphore latches (CE must remain
HIGH during SEM LOW). A0–2 represents the semaphore address. OE
and R/W are used in the same manner as a normal memory access.
When writing or reading a semaphore, the other address pins have no
effect.
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEs are assertedandanaddress matchoccurs withintPS of eachother,
the busy logic determines which port has access. If tPS is violated, one
port definitely gains permission to the location, but it is not predictable
which port gets that permission. BUSY is asserted tBLA after an address
match or tBLC after CE is taken LOW.
When writing to the semaphore, only I/O0 is used. If a zero is written
to the left port of an available semaphore, a one appears at the same
semaphore address on the right port. That semaphore can now only be
modified by the side showing zero (the left port in this case). If the left
port now relinquishes control by writing a one to the semaphore, the
semaphore is set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port had control,
the right port would immediately own the semaphore as soon as the left
port released it. Table 3 shows sample semaphore operations.
Master/Slave
A M/S pin is provided to expand the word width by configuring the
device as either a master or a slave. The BUSY output of the master is
connected to the BUSY input of the slave. This allows the device to
interface to a master device with no external components. Writing to
slave devices must be delayed until after the BUSY input has settled
(tBLC or tBLA), otherwise, the slave chip may begin a write cycle during
a contention situation. When tied HIGH, the M/S pin allows the device
tobeusedasa master and, therefore, theBUSYline is anoutput. BUSY
can then be used to send the arbitration outcome to a slave.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within tSPS of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which side
controls the semaphore.
Semaphore Operation
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V provide eight semaphore latches, which
are separate from the dual-port memory locations. Semaphores
Document #: 38-06078 Rev. *B
Page 5 of 18
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
DC Input Voltage[2] .................................. –0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 1100V
Latch-up Current.................................................... > 200 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature .................................–65
°
C to +150
°C
Ambient Temperature with
Power Applied ............................................–55
Operating Range
°
C to +125
°C
Ambient
Supply Voltage to Ground Potential................–0.5V to +4.6V
Range
Commercial
Industrial[3]
Temperature
VCC
DC Voltage Applied to
Outputs in High-Z State ...........................–0.5V to VCC+0.5V
0
°
C to +70
°
C
3.3V ± 300 mV
3.3V ± 300 mV
–40 C to +85°C
°
Electrical Characteristics Over the Operating Range
CY7C027V/027VN/027AV/028V/CY7C037V/037AV/038V
-15 -20 -25
Min Typ Max Min Typ Max Min Typ Max
Parameter
Description
Unit
VOH
Output HIGH Voltage
(VCC=Min., IOH= –4.0 mA)
2.4
2.4
2.4
V
VOL
VIH
VIL
IIX
Output LOW Voltage (VCC=Min., IOH= +4.0 mA)
Input HIGH Voltage
0.4
0.4
0.4
V
2.2
2.2
2.2
V
Input LOW Voltage
0.8
5
0.8
5
0.8
V
Input Leakage Current
−5
−5
−5
5
10
μA
μA
mA
mA
mA
mA
mA
mA
μA
μA
mA
mA
IOZ
ICC
Output Leakage Current
–10
10 –10
125 185
10
–10
Operating Current (VCC=Max. IOUT=0 Com’l.
mA) Outputs Disabled
Ind.[3]
120 175
140 195
115 165
ISB1
ISB2
ISB3
ISB4
Standby Current (Both Ports TTL
Level) CEL & CER ≥ VIH, f=fMAX
Com’l.
Ind.[3]
35
50
35
45
75
85
10
10
70
80
45
55
30
65
10
60
40
95
Standby Current (One Port TTL Level) Com’l.
80 120
10 250
75 105
110
120
250
250
95
CEL | CER ≥ VIH, f=fMAX
Ind.[3]
Com’l.
Ind.[3]
Standby Current (Both Ports CMOS
Level) CEL & CER ≥ VCC−0.2V, f=0
250
80
Standby Current (One Port CMOS Lev- Com’l.
[4]
el) CEL | CER ≥ VIH, f=fMAX
Ind.[3]
105
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
Unit
CIN
TA = 25
V
°C, f = 1 MHz,
10
10
pF
pF
CC = 3.3V
COUT
Notes
2. Pulse width < 20 ns.
3. Industrial parts are available in CY7C028V and CY7C038V only.
4.
f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I
.
MAX
RC
RC
SB3
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06078 Rev. *B
Page 6 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Figure 3. AC Test Loads and Waveforms
3.3V
3.3V
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
C = 30 pF
OUTPUT
C = 30 pF
R1 = 590Ω
OUTPUT
C = 5 pF
R2 = 435Ω
R2 = 435Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(b) Thévenin Equivalent (Load 1)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
ALL INPUTPULSES
3.0V
GND
90%
90%
10%
3 ns
10%
3 ns
≤
≤
Switching Characteristics Over the Operating Range[6]
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V
Parameter
Description
Unit
-15
-20
-25
Min
15
3
Max
Min
20
3
Max
Min
25
3
Max
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
15
20
25
tOHA
[7]
tACE
tDOE
tLZOE
15
10
20
12
25
13
[8, 9, 10]
[8, 9, 10]
3
3
0
3
3
0
3
3
0
tHZOE
OE HIGH to High Z
10
10
12
12
15
15
[8, 9, 10]
tLZCE
CE LOW to Low Z
[8, 9, 10]
tHZCE
CE HIGH to High Z
[10]
[10]
[7]
tPU
tPD
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable Access Time
15
15
20
20
25
25
tABE
Write Cycle
tWC
Write Cycle Time
15
12
12
0
20
16
16
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
[7]
tSCE
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Setup to Write Start
Write Pulse Width
tAW
tHA
[7]
tSA
0
0
0
tPWE
12
10
17
12
22
15
tSD
Data Setup to Write End
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I /I
OI OH
and 30 pF load capacitance.
7. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
time.
SCE
8. At any given temperature and voltage condition for any given device, t
9. Test conditions used are Load 2.
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
10. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Figure 11.
Document #: 38-06078 Rev. *B
Page 7 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Characteristics Over the Operating Range[6](continued)
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V
Unit
Parameter
Description
-15
-20
-25
Min
Max
Min
Max
Min
Max
tHD
tHZWE
Data Hold From Write End
R/W LOW to High Z
0
0
0
ns
ns
ns
ns
ns
[9, 10]
[9 ,10]
10
12
15
tLZWE
R/W HIGH to Low Z
3
3
3
[36]
tWDD
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
30
25
40
30
50
35
[36]
tDDD
Busy Timing[11]
tBLA
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Setup for Priority
15
15
15
15
20
20
20
16
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
ns
tBHA
tBLC
tBHC
tPS
5
0
5
0
5
0
tWB
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
tWH
13
15
17
[13]
tBDD
Interrupt Timing[11]
15
20
25
tINS
INT Set Time
15
15
20
20
20
20
ns
ns
tINR
INT Reset Time
Semaphore Timing
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
10
5
12
5
ns
ns
ns
ns
5
5
5
tSAA
15
20
25
Data Retention Mode
Timing
The
CY7C027V/027VN/027AV/028V
and
Data Retention Mode
3.0V
CY7037V/037AV/038V are designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules ensure data retention:
V
CC
3.0V
V
CC
> 2.0V
t
RC
1. Chip enable (CE) must be held HIGH during data retention, within
VCC to VCC – 0.2V.
V
CC
to V – 0.2V
CC
V
IH
CE
2. CE must be kept between VCC – 0.2V and 70% of VCC during
the power up and power down transitions.
3. The RAM can begin operation >tRC after VCC reaches the mini-
mum operating voltage (3.0 volts).
Parameter
ICCDR1
Test Conditions[14]
Max
50
Unit
At VCCDR = 2V
μA
Notes
11. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 waveform.
12. Test conditions used are Load 1.
13. t
is a calculated parameter and is the greater of t
–t
(actual) or t
–t (actual).
BDD
WDD PWE
DDD SD
14. CE = V , V = GND to V , T = 25° C. This parameter is guaranteed but not tested.
CC
in
CC
A
Document #: 38-06078 Rev. *B
Page 8 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access)[15, 16, 17]
t
RC
ADDRESS
DATA OUT
t
AA
t
t
OHA
OHA
PREVIOUS DATAVALID
DATA VALID
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)[15, 18, 19]
t
ACE
CE and
LB or UB
t
HZCE
t
DOE
OE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
Figure 6. Read Cycle No. 3 (Either Port)[15, 17, 18, 19]
t
RC
ADDRESS
UB or LB
t
AA
t
OHA
t
t
HZCE
t
t
LZCE
LZCE
t
ABE
CE
HZCE
t
ACE
DATA OUT
Notes
15. R/W is HIGH for read cycles.
16. Device is continuously selected CE = V and UB or LB = V . This waveform cannot be used for semaphore reads.
IL
IL
17. OE = V .
IL
18. Address valid prior to or coincident with CE transition LOW.
19. To access RAM, CE = V , UB or LB = V , SEM = V . To access semaphore, CE = V , SEM = V .
IL
IL
IH
IH
IL
Document #: 38-06078 Rev. *B
Page 9 of 18
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 7. Write Cycle No. 1: R/W Controlled Timing[20, 21, 22, 23]
t
WC
ADDRESS
OE
[26]
t
HZOE
t
AW
[24,25]
CE
[23]
PWE
t
t
t
HA
SA
R/W
DATAOUT
DATA IN
[26]
HZWE
t
t
LZWE
NOTE 27
NOTE 27
t
t
HD
SD
Figure 8. Write Cycle No. 2: CE Controlled Timing[20, 21, 22, 28]
t
WC
ADDRESS
t
AW
[24,25]
CE
t
t
t
HA
SA
SCE
R/W
t
t
HD
SD
DATA IN
Notes
20. R/W must be HIGH during all address transitions.
21. A write occurs during the overlap (t
or t
) of a LOW CE or SEM and a LOW UB or LB.
SCE
PWE
22. t is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data to be placed on
PWE
HZWE SD
the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
.
SD
PWE
24. To access RAM, CE = V , SEM = V
.
IL
IH
25. To access upper byte, CE = V , UB = V , SEM = V .
IL
IL
IH
To access lower byte, CE = V , LB = V , SEM = V .
IL
IL
IH
26. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
27. During this period, the I/O pins are in the output state, and input signals must not be applied.
28. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document #: 38-06078 Rev. *B
Page 10 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 9. Semaphore Read After Write Timing, Either Side[29]
t
t
OHA
SAA
A0–A
VALID ADRESS
VALID ADRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Figure 10. Timing Diagram of Semaphore Contention[30, 31, 32]
A
0L
–A
2L
MATCH
R/W
L
SEM
–A
L
t
SPS
A
MATCH
0R
2R
R/W
R
SEM
R
Notes
29. CE = HIGH for the duration of the above timing (both write and read cycle).
30. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
31. Semaphores are reset (available to both ports) at cycle start.
32. If t is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
SPS
Document #: 38-06078 Rev. *B
Page 11 of 18
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH)[33]
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Figure 12. Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note
33. CE = CE = LOW.
L
R
Document #: 38-06078 Rev. *B
Page 12 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)[34]
CELValid First:
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER ValidFirst:
ADDRESS
L,R
ADDRESS MATCH
CE
R
t
PS
CE
L
L
t
t
BHC
BLC
BUSY
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)[34]
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right AddressValid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note
34. If t is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
PS
Document #: 38-06078 Rev. *B
Page 13 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 15. Interrupt Timing Diagrams
Left Side Sets INT :
R
t
WC
ADDRESS
L
WRITE 7FFF (FFFF for CY7C028V/38V)
[35]
t
HA
CE
L
R/W
INT
L
R
[36]
t
INS
Right Side Clears INT :
R
t
RC
READ 7FFF
(FFFF for CY7C028V/38V)
ADDRESS
R
CE
R
[36]
t
INR
R/W
R
OE
R
INT
R
:
Right Side Sets INTL
t
WC
ADDRESS
R
WRITE 7FFE (FFFE for CY7C028V/38V)
[35]
t
HA
CE
R
R
R/W
INT
L
[36]
INS
t
Left SideClears INT :
L
t
RC
READ 7FFE
(FFFF for CY7C028V/38V)
ADDRESS
CE
R
L
[36]
t
INR
R/W
OE
L
L
L
INT
Notes
35. t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
36. t or t depends on which enable pin (CE or R/W ) is asserted last.
INS
INR
L
L
Document #: 38-06078 Rev. *B
Page 14 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
X
L
R/W
X
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
H
H
H
H
H
H
X
I/O9–I/O17
High Z
I/O0–I/O8
High Z
Operation
Deselected: Power Down
Deselected: Power Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
High Z
High Z
L
Data In
High Z
High Z
L
L
H
L
Data In
Data In
High Z
L
L
L
Data In
Data Out
High Z
L
H
H
H
X
L
H
L
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
Data Out
Data Out
High Z
L
L
L
Data Out
High Z
X
H
X
H
H
L
X
X
H
X
X
X
H
X
Outputs Disabled
H
H
L
Data Out
Data Out
Data In
Data Out
Data Out
Data In
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
L
L
X
L
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
L
L
X
X
X
X
L
X
L
L
L
Not Allowed
Not Allowed
X
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[37]
Left Port
Right Port
Function
R/WL CEL
OEL
X
A0L–14L
7FFF
X
INTL R/WR CER
OER
X
A0R–14R
X
INTR
L[39]
H[38]
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
X
L
X
L
L
X
X
X
L
7FFF
7FFE
X
X
X
L[38]
H[39]
X
L
7FFE
X
X
X
Table 3. Semaphore Operation Example
Function I/O0–I/O17 Left I/O0–I/O17 Right
Status
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Left port writes 1 to semaphore
Notes
37. A
and A
,FFFF/FFFE for the CY7C028V/038V.
0L–15L
0R–15R
38. If BUSY =L, then no change.
R
39. If BUSY =L, then no change.
L
Document #: 38-06078 Rev. *B
Page 15 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Ordering Information
32K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Ordering Code
CY7C027V-15AC
Name
A100
A100
A100
A100
A100
A100
A100
A100
Package Type
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
15
100-Pin Thin Quad Flat Pack
CY7C027V-15AXC
CY7C027VN-15AXC
CY7C027V-20AC
CY7C027V-20AXC
CY7C027V-25AC
CY7C027V-25AXC
CY7C027AV-25AXI
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
25
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
64K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C028V-15AC
Name
A100
A100
A100
A100
A100
A100
A100
A100
Package Type
100-Pin Thin Quad Flat Pack
15
Commercial
Commercial
Commercial
Commercial
Industrial
CY7C028V-15AXC
CY7C028V-20AC
CY7C028V-20AXC
CY7C028V-20AI
CY7C028V-20AXI
CY7C028V-25AC
CY7C028V-25AXC
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
25
Commercial
Commercial
100-Pin Pb-Free Thin Quad Flat Pack
32K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C037V-15AC
Name
A100
A100
A100
A100
A100
A100
Package Type
100-Pin Thin Quad Flat Pack
15
20
25
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
CY7C037V-15AXC
CY7C037V-20AC
CY7C037AV-20AXC
CY7C037V-25AC
CY7C037V-25AXC
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
64K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C038V-15AC
Name
A100
A100
A100
A100
A100
A100
A100
A100
Package Type
100-Pin Thin Quad Flat Pack
15
Commercial
Commercial
Commercial
Commercial
Industrial
CY7C038V-15AXC
CY7C038V-20AC
CY7C038V-20AXC
CY7C038V-20AI
CY7C038V-20AXI
CY7C038V-25AC
CY7C038V-25AXC
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
25
Commercial
Commercial
100-Pin Pb-Free Thin Quad Flat Pack
Document #: 38-06078 Rev. *B
Page 16 of 18
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Package Diagram
Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*C
Document #: 38-06078 Rev. *B
Page 17 of 18
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document History Page
Document Title: CY7C027V/027VN/027AV/CY7C028V/037V/037AV/038V 3.3V 32K/64K x 16/18 Dual Port Static RAM
Document Number: 38-06078
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
237626
YDT
6/30/04
Converted data sheet from old spec 38-00670 to conform with new data
sheet. Removed cross information from features section
*A
*B
259110
JHX
See ECN Added Pb-Free packaging information.
2623540
VKN/PYRS
12/17/08
Added CY7C027VN, CY7C027AV and CY7C037AV parts
Updated Ordering information table
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© Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06078 Rev. *B
Revised December 09, 2008
Page 18 of 18
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相关型号：
CY7C027V-15AXIT
Multi-Port SRAM, 32KX16, 15ns, CMOS, PQFP100, ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
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