CY7C026AV-25AXI [CYPRESS]
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM; 3.3V 4K / 8K / 16K X 16/18双端口静态RAM
| 型号： | CY7C026AV-25AXI |
| 厂家： | 
CYPRESS |
| 描述： | 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM |
| 文件： | 总19页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
• Automatic power-down
Features
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• True dual-ported memory cells which allow
simultaneous access of the same memory location
• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)
• 4/8K × 18 organization (CY7C0241AV/0251AV)
• 16K × 18 organization (CY7C036AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20 and 25 ns
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Low operating power
• Commercial and industrial temperature ranges
• Available in 100-pin Lead (Pb)-free TQFP and 100-pin
TQFP
— Active: ICC = 115 mA (typical)
—Standby: ISB3 = 10 μA (typical)
• Fully asynchronous operation
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CEL
CER
LBL
LBR
OEL
OER
[1]
8/9
[1]
8/9
I/O8/9L–I/O15/17L
I/O8/9L–I/O15/17R
[2]
8/9
8/9
I/O
Control
I/O
Control
[2]
I/O0L–I/O7/8L
I/O0L–I/O7/8R
12/13/14
12/13/14
[3]
[3]
Address
Decode
Address
Decode
True Dual-Ported
A0L–A11/1213L
A0R–A11/12/13R
RAM Array
[3]
[3]
12/13/14
12/13/14
A0L–A11/12/13L
A0R–A11/12/13R
CER
CEL
Interrupt
Semaphore
Arbitration
OEL
R/WL
OER
R/WR
SEML
[4]
SEMR
[4]
BUSYL
INTL
UBL
BUSYR
INTR
UBR
LBL
M/S
LBR
Notes:
1. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
8
15
9
17
2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
0
7
0
8
3. A –A for 4K devices; A –A for 8K devices; A –A for 16K devices.
0
11
0
12
0
13
4. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06052 Rev. *H
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised June 15, 2005
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations
100-Pin TQFP
Top View
100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
NC
NC
NC
NC
1
NC
NC
NC
2
3
4
72
71
70
69
NC
A
5L
I/O
10L
5
6
7
8
A
4L
I/O
I/O
11L
12L
A
3L
A
2L
68
I/O
13L
A
1L
67
66
GND
9
A
0L
I/O
I/O
10
11
12
13
14L
15L
INT
BUSY
GND
M/S
L
65
64
63
62
L
V
CC
CY7C024AV (4K × 16)
CY7C025AV (8K × 16)
GND
I/O
0R
I/O
1R
14
BUSY
INT
61
60
59
58
R
15
16
17
R
I/O
2R
A
0R
V
CC
A
1R
I/O
3R
18
19
20
21
A
2R
57
56
55
54
53
I/O
4R
I/O
5R
I/O
6R
A
3R
A
4R
NC
NC
NC
NC
NC
22
23
NC
NC
52
51
24
25
NC
26 27 28 29 30 31 32 3334 35 36 37 38 39 40 41 42 43 44 45 46 4748 49 50
Notes:
5.
6.
A
A
on the CY7C025AV.
on the CY7C025AV.
12L
12R
Document #: 38-06052 Rev. *H
Page 2 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations (continued)
Top View
100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
NC
NC
NC
NC
1
NC
NC
2
3
4
I/O
8L
17L
11L
72
71
70
69
I/O
I/O
A
5L
5
6
7
8
A
4L
I/O
12L
I/O
13L
A
A
A
3L
2L
1L
0L
68
I/O
14L
67
66
GND
9
A
I/O
I/O
10
11
12
13
15L
16L
INT
BUSY
GND
M/S
L
65
64
63
62
L
V
CC
CY7C0241AV (4K × 18)
CY7C0251AV (8K × 18)
GND
I/O
0R
I/O
1R
14
BUSY
INT
61
60
59
58
R
15
16
17
18
19
20
21
R
I/O
2R
A
A
A
0R
1R
V
CC
I/O
3R
57
56
55
54
53
2R
3R
I/O
4R
I/O
5R
I/O
6R
I/O
8R
A
A
4R
NC
NC
NC
22
23
I/O
17R
52
51
NC
NC
24
25
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
NC
1
NC
NC
NC
NC
I/O10L
I/O11L
I/O12L
I/O13L
GND
2
3
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
NC
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
I/O14L
I/O15L
VCC
GND
CY7C026AV (16K × 16)
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
NC
24
25
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes:
7.
8.
A
A
on the CY7C0251AV.
on the CY7C0251AVC.
12L
12R
Document #: 38-06052 Rev. *H
Page 3 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations (continued)
100-Pin TQFP
Top View
100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
NC
NC
NC
1
NC
NC
2
3
4
73
72
71
70
69
I/O
8L
A
13L
I/O
17L
A
5L
I/O
11L
5
6
7
8
A
4L
I/O
12L
A
3L
I/O
13L
A
68
67
66
2L
I/O
14L
A
1L
GND
9
A
0L
I/O
15L
10
11
12
13
INT
BUSY
GND
M/S
L
65
64
63
62
I/O
16L
L
V
CC
CY7C036AV (16K × 18)
GND
I/O
0R
I/O
1R
14
15
16
17
BUSY
INT
61
60
59
58
R
R
I/O
2R
A
0R
V
CC
A
1R
I/O
3R
18
19
20
21
A
2R
57
56
55
54
53
I/O
A
3R
4R
I/O
A
4R
5R
I/O
A
13R
6R
I/O
8R
22
23
NC
NC
NC
I/O
17R
52
51
NC
NC
24
25
26 27 28 29 30 31 32 3334 35 36 37 38 39 40 41 42 43 44 45 46 4748 49 50
Selection Guide
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-25
Unit
ns
Maximum Access Time
20
120
35
25
115
30
Typical Operating Current
mA
mA
Typical Standby Current for ISB1
(Both ports TTL Level)
Typical Standby Current for ISB3
(Both ports CMOS Level)
10
10
μA
Document #: 38-06052 Rev. *H
Page 4 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Definitions
Left Port
CEL
Right Port
Description
CER
Chip Enable.
R/WL
R/WR
OER
Read/Write Enable.
Output Enable.
OEL
A0L–A13L
I/O0L–I/O17L
SEML
UBL
A0R–A13R
I/O0R–I/O17R
SEMR
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K).
Data Bus Input/Output.
Semaphore Enable.
UBR
Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices).
LBL
LBR
Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices).
INTL
INTR
Interrupt Flag.
Busy Flag.
BUSYL
M/S
BUSYR
Master or Slave Select.
Power.
VCC
GND
Ground.
NC
No Connect.
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
Architecture
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV consist of an array of 4K, 8K, and 16K words of 16 and
18 bits each of dual-port RAM cells, I/O and address lines, and
control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in
memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. Two Interrupt
(INT) pins can be utilized for port-to-port communication. Two
Semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power-down
feature controlled by CE. Each port is provided with its own
output enable control (OE), which allows data to be read from
the device.
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Select (CE) pin.
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV are available in 100-pin Lead (Pb)-free Thin Quad Flat
Pack (TQFP) and 100-pin TQFP.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in Table 1.
Functional Description
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV
/036AV are low-power CMOS 4K, 8K, and 16K ×16/18
dual-port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can
be utilized as standalone 16/18-bit dual-port static RAMs or
multiple devices can be combined in order to function as a
32/36-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 32/36-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C024AV/41AV, 1FFF for the CY7C025AV/51AV, 3FFF for
Document #: 38-06052 Rev. *H
Page 5 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
the CY7C026AV/36AV) is the mailbox for the right port and the
second-highest memory location (FFE for the CY7C024AV/
41AV, 1FFE for the CY7C025AV/51AV, 3FFE for the
CY7C026AV/36AV) is the mailbox for the left port. When one
port writes to the other port’s mailbox, an interrupt is generated
to the owner. The interrupt is reset when the owner reads the
contents of the mailbox. The message is user defined.
Semaphore Operation
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV provide eight semaphore latches, which are separate
from the dual-port memory locations. Semaphores are used to
reserve resources that are shared between the two ports. The
state of the semaphore indicates that a resource is in use. For
example, if the left port wants to request a given resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore.
The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was
successful (reads a zero), it assumes control of the shared
resource, otherwise (reads a one) it assumes the right port has
control and continues to poll the semaphore. When the right
side has relinquished control of the semaphore (by writing a
one), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore,
a one is written to cancel its request.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV provide on-chip arbitration to resolve simultaneous
memory location access (contention). If both ports’ CEs are
asserted and an address match occurs within tPS of each
other, the busy logic will determine which port has access. If
tPS is violated, one port will definitely gain permission to the
location, but it is not predictable which port will get that
permission. BUSY will be asserted tBLA after an address
match or tBLC after CE is taken LOW.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to
access the semaphore within tSPS of each other, the
semaphore will definitely be obtained by one side or the other,
but there is no guarantee which side will control the
semaphore.
Document #: 38-06052 Rev. *H
Page 6 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
X
L
R/W
X
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
H
H
H
H
H
H
X
I/O9–I/O17
High Z
I/O0–I/O8
High Z
Operation
Deselected: Power-Down
Deselected: Power-Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
High Z
High Z
L
Data In
High Z
High Z
L
L
H
L
Data In
Data In
High Z
L
L
L
Data In
Data Out
High Z
L
H
H
H
X
L
H
L
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
Data Out
Data Out
High Z
L
L
L
Data Out
High Z
X
H
X
H
H
L
X
X
H
X
X
X
H
X
Outputs Disabled
H
H
L
Data Out
Data Out
Data In
Data Out
Data Out
Data In
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
L
L
X
L
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
L
L
X
X
X
X
L
X
L
L
L
Not Allowed
Not Allowed
X
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[9]
Left Port
Right Port
Function
R/WL CEL
OEL
X
A0L–13L
FFF[12]
X
INTL R/WR CER
OER
X
A0R–13R
INTR
L[11]
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
X
L
X
L
L
X
X
X
X
L
FFF (or 1/3FFF) H[10]
X
X
L[10]
H[11]
X
1FFE (or 1/3FFE)
X
X
X
L
1FFE[12]
X
X
Table 3. Semaphore Operation Example
Function I/O0–I/O17 Left I/O0–I/O17 Right
Status
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore-free
Left Port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore-free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore-free
Left port writes 1 to semaphore
Notes:
9. See Functional Description for specific highest memory locations by device.
10. If BUSY =L, then no change.
R
11. If BUSY =L, then no change.
L
12. See Functional Description for specific addresses by device.
Document #: 38-06052 Rev. *H
Page 7 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
DC Input Voltage[14]............................... –0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
Latch-up Current.................................................... > 200 mA
Maximum Ratings[13]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Range
Commercial
Industrial[15]
Ambient Temperature
0°C to +70°C
VCC
Supply Voltage to Ground Potential............... –0.5V to +4.6V
3.3V ± 300 mV
3.3V ± 300 mV
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to VCC + 0.5V
–40°C to +85°C
Electrical Characteristics Over the Operating Range
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
-25
Parameter
VOH
Description
Output HIGH Voltage (VCC=3.3V)
Output LOW Voltage
Min.
Typ. Max. Min. Typ. Max. Unit
2.4
2.4
2.0
V
VOL
VIH
VIL
IOZ
IIX
0.4
0.4
V
Input HIGH Voltage
2.0
–0.3[16]
–10
V
Input LOW Voltage
0.8
10
0.8
10
V
Output Leakage Current
Input Leakage Current
–10
–10
μA
μA
mA
mA
mA
mA
mA
mA
μA
μA
mA
mA
–10
10
10
ICC
Operating Current (VCC = Max.,
Com’l.
120
35
75
175
115
135
30
40
65
75
10
10
60
70
165
185
40
IOUT = 0 mA) Outputs Disabled
Ind.[15]
Com’l.
Ind.[15]
Com’l.
Ind.[15]
ISB1
ISB2
ISB3
ISB4
Standby Current (Both Ports TTL Level)
CEL & CER ≥ VIH, f = fMAX
45
110
500
95
50
Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
95
105
500
500
80
Standby Current (Both Ports CMOS Level) Com’l.
CEL & CER ≥ VCC−0.2V, f = 0
10
Ind.[15]
Standby Current (One Port CMOS Level)
Com’l.
Ind.[15]
70
[17]
CEL | CER ≥ VIH, f = fMAX
90
Capacitance[18]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 3.3V
Max.
10
Unit
CIN
pF
pF
V
COUT
10
Notes:
13. The Voltage on any input or I/O pin can not exceed the power pin during power-up.
14. Pulse width < 20 ns.
15. Industrial parts are available in CY7C026AV and CY7C036AV only.
16. VIL > –1.5V for pulse width less than 10ns.
17.
f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
MAX RC RC
standby I
.
SB3
18. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06052 Rev. *H
Page 8 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
AC Test Loads and Waveforms
3.3V
3.3V
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
C = 30pF
OUTPUT
R1 = 590Ω
OUTPUT
C = 30 pF
R2 = 435Ω
C = 5 pF
R2 = 435Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, and tLZWE
(b) Thévenin Equivalent (Load 1)
ALL INPUTPULSES
including scope and jig)
3.0V
GND
90%
90%
10%
3 ns
10%
3 ns
≤
≤
Switching Characteristics Over the Operating Range [19]
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
-25
Parameter
Description
Min.
20
Max.
Min.
25
3
Max.
Unit
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
20
25
tOHA
3
[20]
tACE
tDOE
tLZOE
20
12
25
13
[21, 22, 23]
[21, 22, 23]
3
3
0
3
3
0
tHZOE
OE HIGH to High Z
12
12
15
15
[21, 22, 23]
tLZCE
CE LOW to Low Z
[21, 22, 23]
tHZCE
CE HIGH to High Z
[23]
tPU
tPD
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
[23]
20
20
25
25
[20]
tABE
Write Cycle
tWC
Write Cycle Time
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
[20]
tSCE
tAW
tHA
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-up to Write Start
Write Pulse Width
[20]
tSA
0
0
tPWE
15
20
Notes:
19. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
/I and 30-pF load capacitance.
I
OI OH
20. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
time.
SCE
21. At any given temperature and voltage condition for any given device, t
22. Test conditions used are Load 3.
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
23. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing
with Busy waveform.
Document #: 38-06052 Rev. *H
Page 9 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Characteristics Over the Operating Range (continued)[19]
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
-25
Parameter
Description
Data Set-up to Write End
Min.
15
Max.
Min.
15
0
Max.
Unit
ns
tSD
tHD
tHZWE
Data Hold From Write End
R/W LOW to High Z
0
ns
[22, 23]
12
15
ns
[22, 23]
tLZWE
R/W HIGH to Low Z
3
0
ns
[24]
tWDD
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
45
30
50
35
ns
[24]
tDDD
ns
Busy Timing[25]
tBLA
tBHA
tBLC
tBHC
tPS
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
20
20
20
17
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
ns
BUSY HIGH from CE HIGH
Port Set-up for Priority
5
0
5
0
tWB
tWH
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
15
17
[26]
tBDD
20
25
Interrupt Timing[25]
tINS
INT Set Time
20
20
20
20
ns
ns
tINR
INT Reset Time
Semaphore Timing
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
12
5
ns
ns
ns
ns
5
5
tSAA
20
25
Data Retention Mode
Timing
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV are designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
Data Retention Mode
3.0V
V
CC
3.0V
V
CC
> 2.0V
t
RC
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
V
CC
to V – 0.2V
CC
V
IH
CE
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0V).
Parameter
Test Conditions[27]
Max.
Unit
ICCDR1
@ VCCDR = 2V
50
μA
Notes:
24. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
25. Test conditions used are Load 2.
26.
t
is a calculated parameter and is the greater of t
– t
(actual) or t
– t (actual).
BDD
WDD
PWE
DDD SD
27. CE = V , V = GND to V , T = 25°C. This parameter is guaranteed but not tested.
CC
in
CC
A
Document #: 38-06052 Rev. *H
Page 10 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[28, 29, 30]
t
RC
ADDRESS
DATA OUT
t
AA
t
t
OHA
OHA
PREVIOUS DATAVALID
DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[28, 31, 32]
t
ACE
CE and
LB or UB
t
HZCE
t
DOE
OE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
Read Cycle No. 3 (Either Port)[28, 30, 31, 32]
t
RC
ADDRESS
t
AA
t
OHA
UB or LB
t
t
HZCE
t
t
LZCE
LZCE
t
ABE
CE
HZCE
t
ACE
DATA OUT
Notes:
28. R/W is HIGH for read cycles.
29. Device is continuously selected CE = V and UB or LB = V . This waveform cannot be used for semaphore reads.
IL
IL
30. OE = V .
IL
31. Address valid prior to or coincident with CE transition LOW.
32. To access RAM, CE = V , UB or LB = V , SEM = V . To access semaphore, CE = V , SEM = V .
IL
IL
IH
IH
IL
Document #: 38-06052 Rev. *H
Page 11 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[33, 34, 35, 36]
t
WC
ADDRESS
OE
[39]
t
HZOE
t
AW
[37, 38]
CE
[36]
PWE
t
t
t
HA
SA
R/W
DATAOUT
DATA IN
[39]
HZWE
t
t
LZWE
NOTE 40
NOTE 40
t
t
HD
SD
Write Cycle No. 2: CE Controlled Timing[33, 34, 35, 41]
t
WC
ADDRESS
t
AW
[37, 38]
CE
t
t
t
HA
SA
SCE
R/W
t
t
HD
SD
DATA IN
Notes:
33. R/W must be HIGH during all address transitions.
34. A write occurs during the overlap (t or t ) of a LOW CE or SEM and a LOW UB or LB.
SCE
PWE
35.
t
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
36. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data
SD
PWE
HZWE
to be placed on the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
SD
as short as the specified t
.
PWE
37. To access RAM, CE = V , SEM = V
.
IH
IL
38. To access upper byte, CE = V , UB = V , SEM = V .
IL
IL
IH
To access lower byte, CE = V , LB = V , SEM = V .
IL
IL
IH
39. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
40. During this period, the I/O pins are in the output state, and input signals must not be applied.
41. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06052 Rev. *H
Page 12 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[42]
t
t
OHA
SAA
A –A
0
VALID ADRESS
VALID ADRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[43, 44, 45]
A
0L
–A
2L
MATCH
R/W
L
SEM
–A
L
t
SPS
A
MATCH
0R
2R
R/W
R
SEM
R
Notes:
42. CE = HIGH for the duration of the above timing (both write and read cycle).
43. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
44. Semaphores are reset (available to both ports) at cycle start.
45. If t is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
SPS
Document #: 38-06052 Rev. *H
Page 13 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[46]
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note:
46. CE = CE = LOW.
L
R
Document #: 38-06052 Rev. *H
Page 14 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[47]
CELValid First:
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER ValidFirst:
ADDRESS
ADDRESS MATCH
L,R
CE
R
t
PS
CE
L
L
t
t
BHC
BLC
BUSY
Busy Timing Diagram No.2 (Address Arbitration)[47]
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right AddressValid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note:
47. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
PS
Document #: 38-06052 Rev. *H
Page 15 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR :
t
WC
ADDRESS
WRITE 1FFF (OR 1/3FFF)
L
[48]
t
HA
CE
L
R/W
INT
L
R
[49]
t
INS
Right Side Clears INTR:
t
RC
READ 7FFF
(OR 1/3FFF)
ADDRESS
R
CE
R
[49]
t
INR
R/W
R
OE
R
INT
R
:
Right Side Sets INTL
t
WC
ADDRESS
WRITE 1FFE (OR 1/3FFE)
R
[48]
HA
t
CE
R
R
R/W
INT
L
[49]
INS
t
Left Side Clears INTL:
t
RC
READ 7FFE
OR 1/3FFE)
ADDRESS
R
CE
L
[49]
t
INR
R/W
L
OE
INT
L
L
Notes:
48.
49.
t
depends on which enable pin (CE or R/W ) is deasserted first.
HA L L
t
or t
depends on which enable pin (CE or R/W ) is asserted last.
L L
INS
INR
Document #: 38-06052 Rev. *H
Page 16 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Ordering Information
4K x16 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
CY7C024AV-15AI
Package Type
100-Pin Thin Quad Flat Pack
Range
15
A100
A100
A100
A100
A100
A100
A100
A100
A100
A100
Industrial
CY7C024AV-15AXI
CY7C024AV-20AC
CY7C024AV-20AXC
CY7C024AV-20AI
CY7C024AV-20AXI
CY7C024AV-25AC
CY7C024AV-25AXC
CY7C024AV-25AI
CY7C024AV-25AXI
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
25
Commercial
Industrial
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Commercial
Industrial
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Lead-free Thin Quad Flat Pack
8K x16 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C025AV-20AC
CY7C025AV-20AXC
CY7C025AV-20AXI
CY7C025AV-25AC
CY7C025AV-25AXC
CY7C025AV-25AI
Package Type
100-Pin Thin Quad Flat Pack
20
A100
A100
A100
A100
A100
A100
A100
Commercial
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
25
Commercial
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
CY7C025AV-25AXI
100-Pin Lead-free Thin Quad Flat Pack
16K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C026AV-20AC
CY7C026AV-20AXC
CY7C026AV-20AXI
CY7C026AV-25AC
CY7C026AV-25AXC
CY7C026AV-25AI
Name
A100
A100
A100
A100
A100
A100
A100
Package Type
100-Pin Thin Quad Flat Pack
20
25
Commercial
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
Commercial
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
CY7C026AV-25AXI
100-Pin Lead-free Thin Quad Flat Pack
4K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
20
Package
Name
Operating
Range
Ordering Code
CY7C0241AV-20AC
CY7C0241AV-25AC
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
A100
A100
Commercial
Commercial
25
8K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
20
Package
Name
Operating
Range
Ordering Code
CY7C0251AV-20AC
CY7C0251AV-25AC
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
A100
A100
Commercial
Commercial
25
Document #: 38-06052 Rev. *H
Page 17 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
16K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Ordering Code
CY7C036AV-20AC
CY7C036AV-25AC
CY7C036AV-25AXC
CY7C036AV-25AI
Name
A100
A100
A100
A100
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Lead-free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Range
Commercial
Commercial
20
25
Industrial
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
100-Pin Lead (Pb)-free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06052 Rev. *H
Page 18 of 19
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document History Page
Document Title: CY7C024AV/CY7C025AV/CY7C026AV/CY7C0241AV/CY7C0251AV/CY7C036AV 3.3V 4K/8K/16K x 16/18
Dual Port Static RAM
Document Number: 38-06052
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Change from Spec number: 38-00838 to 38-06052
Power-up requirements added to Maximum Ratings Information
Added CY7C025AV-25AI to Ordering Information
Removed cross information from features section
Added CY7C024AV-25AI to Ordering Information
Corrected x18 for 026AV to x16
110204
122302
128958
237622
241968
276451
279452
11/11/01
12/27/02
9/03/03
SZV
RBI
*A
*B
JFU
*C
*D
*E
See ECN
See ECN
See ECN
See ECN
YDT
WWZ
SPN
RUY
*F
Added lead (Pb)-free packaging information
Corrected pin A113L to A13L on CY7C026AV pin list
Added minimum VIL of 0.3V and note 16
*G
*H
373580
380476
See ECN
See ECN
RUY
PCX
Corrected CY7C024AC-25AXC to CY7C024AV-25AXC in Ordering Infor-
mation
Added to Part Ordering information:
CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI,
CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI
Document #: 38-06052 Rev. *H
Page 19 of 19
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