CY7C026A_05 [CYPRESS]
16K x 16/18 Dual-Port Static RAM; 16K X 16/18双端口静态RAM
| 型号： | CY7C026A_05 |
| 厂家： | 
CYPRESS |
| 描述： | 16K x 16/18 Dual-Port Static RAM |
| 文件： | 总18页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C026A
CY7C036A16K
x 16/18 Dual-Port Static RAM
CY7C026A
CY7C036A
16K x 16/18 Dual-Port Static RAM
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
Features
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• On-chip arbitration logic
• 16K x 16 organization (CY7C026A)
• 16K x 18 organization (CY7C036A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12[1]/15/20 ns
• Low operating power
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
— Active: ICC = 180 mA (typical)
— Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-Pin TQFP
• Pb-Free packages available
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CEL
CER
LBL
LBR
OEL
OER
8/9
[2]
8/9
8/9
[2]
I/O8/9L–I/O15/17L
I/O8/9L–I/O
15/17R
[3]
8/9
I/O
I/O
Control
[3]
I/O0L–I/O7/8L
Control
I/O0L–I/O
7/8R
14
14
Address
Decode
Address
Decode
True Dual-Ported
A0L–A13L
A0R–A13R
RAM Array
14
14
A
0L–A13L
A0R–A13R
CER
CEL
Interrupt
Semaphore
Arbitration
OEL
OER
R/WL
SEML
R/WR
SEMR
[4]
[4]
BUSYL
INTL
UBL
BUSYR
INTR
UBR
LBL
M/S
LBR
Notes:
1. See page 6 for Load Conditions.
2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
8
15
9
17
3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
0
7
0
8
4. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06046 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 6, 2005
CY7C026A
CY7C036A
Pin Configurations
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
NC
NC
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
2
3
A
4
6L
I/O
I/O
I/O
I/O
5
A
A
A
A
A
A
10L
11L
12L
13L
5L
4L
3L
2L
1L
0L
6
7
8
GND
9
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
14L
15L
I/O
INT
L
VCC
GND
BUSY
GND
M/S
L
CY7C026A (16K x 16)
I/O
I/O
I/O
0R
1R
2R
BUSY
R
INT
R
VCC
A
A
A
A
A
A
0R
I/O
3R
1R
2R
3R
4R
5R
I/O
4R
I/O
5R
I/O
6R
NC
NC
NC
NC
NC
NC
NC
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Document #: 38-06046 Rev. *C
Page 2 of 18
CY7C026A
CY7C036A
Pin Configurations (continued)
100-Pin TQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
NC
NC
NC
1
NC
NC
2
3
4
I/O
8L
17L
11L
A
13L
72
71
I/O
I/O
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
5
70
69
I/O
I/O
12L
13L
6
7
68
I/O
14L
8
67
66
GND
9
I/O
10
11
12
13
15L
16L
INT
L
65
64
I/O
BUSY
GND
M/S
L
V
CC
63
62
CY7C036A (16K x 18)
GND
I/O
0R
14
BUSY
61
60
59
R
I/O
1R
INT
R
15
16
17
I/O
V
2R
A
0R
CC
A
58
1R
I/O
3R
18
19
20
21
A
57
56
55
54
53
2R
I/O
I/O
I/O
I/O
A
4R
5R
3R
A
4R
A
6R
8R
13R
22
23
NC
NC
I/O
17R
52
51
NC
NC
24
25
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C026A
CY7C036A
-12[1]
CY7C026A
CY7C036A
-15
CY7C026A
CY7C036A
-20
Unit
ns
Maximum Access Time
12
195
55
15
190
50
20
180
45
Typical Operating Current
mA
mA
mA
Typical Standby Current for ISB1 (Both Ports TTL Level)
Typical Standby Current for ISB3 (Both Ports CMOS Level)
0.05
0.05
0.05
Document #: 38-06046 Rev. *C
Page 3 of 18
CY7C026A
CY7C036A
Pin Definitions
Left Port
CEL
Right Port
Description
CER
Chip Enable
R/WL
R/WR
OER
Read/Write Enable
Output Enable
OEL
A0L–A13L
I/O0L–I/O17L
SEML
UBL
A0R–A13R
I/O0R–I/O17R
SEMR
Address
Data Bus Input/Output
Semaphore Enable
UBR
Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices)
LBL
LBR
Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices)
INTL
INTR
Interrupt Flag
Busy Flag
BUSYL
M/S
BUSYR
Master or Slave Select
Power
VCC
GND
Ground
NC
No Connect
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
Architecture
The CY7C026A and CY7C036A consist of an array of 16K
words of 16 and 18 bits each of dual-port RAM cells, I/O and
address lines, and control signals (CE, OE, R/W). These
control pins permit independent access for reads or writes to
any location in memory. To handle simultaneous writes/reads
to the same location, a BUSY pin is provided on each port. Two
Interrupt (INT) pins can be utilized for port-to-port communi-
cation. Two Semaphore (SEM) control pins are used for
allocating shared resources. With the M/S pin, the devices can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The devices also have an automatic
power-down feature controlled by CE. Each port is provided
with its own Output Enable control (OE), which allows data to
be read from the device.
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by the chip
enable pin.
The CY7C026A and CY7C036A are available in 100-pin Thin
Quad Plastic Flatpack (TQFP) packages.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in Table 1.
Functional Description
The CY7C026A and CY7C036A are low-power CMOS 16K x
16/18 dual-port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can
be utilized as standalone 16/18-bit dual-port static RAMs or
multiple devices can be combined in order to function as a
32/36-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 32/36-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
The upper two memory locations may be used for message
passing. The highest memory location (3FFF) is the mailbox
for the right port and the second-highest memory location
(3FFE) is the mailbox for the left port. When one port writes to
the other port’s mailbox, an interrupt is generated to the owner.
Document #: 38-06046 Rev. *C
Page 4 of 18
CY7C026A
CY7C036A
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
shared between the two ports. The state of the semaphore
indicates that a resource is in use. For example, if the left port
wants to request a given resource, it sets a latch by writing a
zero to a semaphore location. The left port then verifies its
success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value will
be available tSWRD + tDOE after the rising edge of the
semaphore write. If the left port was successful (reads a zero),
it assumes control of the shared resource, otherwise (reads a
one) it assumes the right port has control and continues to poll
the semaphore. When the right side has relinquished control
of the semaphore (by writing a one), the left side will succeed
in gaining control of the semaphore. If the left side no longer
requires the semaphore, a one is written to cancel its request.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C026A and CY7C036A provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ CEs are asserted and an address match occurs
within tPS of each other, the busy logic will determine which
port has access. If tPS is violated, one port will definitely gain
permission to the location, but it is not predictable which port
will get that permission. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to
access the semaphore within tSPS of each other, the
semaphore will definitely be obtained by one side or the other,
but there is no guarantee which side will control the
semaphore.
Semaphore Operation
The CY7C026A and CY7C036A provide eight semaphore
latches, which are separate from the dual-port memory
locations. Semaphores are used to reserve resources that are
Document #: 38-06046 Rev. *C
Page 5 of 18
CY7C026A
CY7C036A
DC Input Voltage[6] ........................................–0.5V to + 7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
Latch-Up Current.................................................... >200 mA
Maximum Ratings[5]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential............... –0.3V to +7.0V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
5V ± 10%
5V ± 10%
Electrical Characteristics Over the Operating Range
CY7C026A
CY7C036A
-12[1]
-15
-20
Parameter
Description
Output HIGH Voltage
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH
2.4
2.4
2.4
V
(VCC = Min., IOH = –4.0 mA)
VOL
Output LOW Voltage
(VCC = Min., IOH = +4.0 mA)
0.4
0.4
0.4
V
VIH
VIL
IOZ
ICC
Input HIGH Voltage
2.2
2.2
2.2
V
Input LOW Voltage
0.8
10
0.8
10
0.8
10
V
Output Leakage Current
–10
–10
–10
µA
mA
mA
mA
mA
Operating Current (VCC = Max., Com’l.
195
55
325
190
215
50
285
305
70
180
45
275
IOUT = 0 mA) Outputs Disabled
Indust.
Com’l.
Indust.
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports TTL Level)
CEL & CER ≥ VIH, f = fMAX
75
205
0.5
65
160
0.5
65
95
Standby Current
(One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
Com’l.
Indust.
125
0.05
115
120
135
180
205
110
0.05
100
mA
mA
Standby Current
(Both Ports CMOS Level)
CEL & CER ≥ VCC–0.2V, f = 0
Com’l.
Indust.
0.05
0.05
0.5
0.5
mA
mA
Standby Current
(One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
Com’l.
Indust.
185
110
125
160
175
140
mA
mA
[7]
Capacitance[8]
Parameter
Description
Test Conditions
Max.
10
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
pF
pF
COUT
10
Notes:
5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
6. Pulse width < 20 ns.
7. f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
MAX
RC RC
standby I
.
SB3
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06046 Rev. *C
Page 6 of 18
CY7C026A
CY7C036A
AC Test Loads and Waveforms
5V
5V
RTH = 250Ω
R1 = 893Ω
OUTPUT
C = 30 pF
R1 = 893Ω
OUTPUT
OUTPUT
C = 5 pF
C = 30 pF
R2 = 347Ω
R2 = 347Ω
VTH = 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
(b) Thévenin Equivalent (Load 1)
AC Test Loads (Applicable to -12 only)[9]
ALL INPUT PULSES
90%
Z0 = 50Ω
R = 50Ω
OUTPUT
3.0V
GND
90%
10%
C
10%
3 ns
3 ns
≤
≤
VTH = 1.4V
(a) Load 1 (-12 only)
1 .00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.1 0
0.00
1 0
1 5
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Note:
9. Test Conditions: C = 10 pF.
Document #: 38-06046 Rev. *C
Page 7 of 18
CY7C026A
CY7C036A
Switching Characteristics Over the Operating Range[10]
CY7C026A
CY7C036A
-12[1]
Max.
-15
-20
Parameter
Description
Min.
12
Min.
Max.
Min.
20
3
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
12
15
20
tOHA
3
[11]
tACE
tDOE
tLZOE
12
8
15
10
20
12
[12, 13, 14]
[12, 13, 14]
3
3
0
3
3
0
3
3
0
tHZOE
OE HIGH to High Z
10
10
10
10
12
12
[12, 13, 14]
tLZCE
CE LOW to Low Z
[12, 13, 14]
tHZCE
CE HIGH to High Z
[14]
tPU
tPD
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
[14]
12
12
15
15
20
20
[11]
tABE
WRITE CYCLE
tWC
Write Cycle Time
12
10
10
0
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[11]
tSCE
tAW
tHA
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
[11]
tSA
tPWE
tSD
0
0
0
10
10
0
12
10
0
15
15
0
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
[16]
tHD
[13, 14]
tHZWE
10
10
12
[13, 14]
tLZWE
R/W HIGH to Low Z
3
3
3
[15]
tWDD
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
25
20
30
25
45
30
[15]
tDDD
Notes:
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
/I and 30-pF load capacitance.
I
OI OH
11. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
time.
SCE
12. At any given temperature and voltage condition for any given device, t
13. Test conditions used are Load 3.
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
14. This parameter is guaranteed but not tested.
15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
16. For 15 ns industrial parts t Min. is 0.5 ns.
HD
Document #: 38-06046 Rev. *C
Page 8 of 18
CY7C026A
CY7C036A
Switching Characteristics Over the Operating Range[10] (continued)
CY7C026A
CY7C036A
-12[1]
-15
-20
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING[17]
tBLA
tBHA
tBLC
tBHC
tPS
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
12
12
12
12
15
15
15
15
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
ns
BUSY HIGH from CE HIGH
Port Set-Up for Priority
5
0
5
0
5
0
tWB
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
tWH
11
13
15
[18]
tBDD
12
15
20
INTERRUPT TIMING[17]
tINS
INT Set Time
12
12
15
15
20
20
ns
ns
tINR
INT Reset Time
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
10
5
10
5
ns
ns
ns
ns
5
5
5
tSAA
12
15
20
Data Retention Mode
Timing
The CY7C026A and CY7C036A are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
Data Retention Mode
4.5V
V
CC
4.5V
V
CC
> 2.0V
t
RC
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
V
to V – 0.2V
CC
CC
V
IH
CE
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 volts).
Parameter
Test Conditions[19]
Max.
Unit
ICCDR1
@ VCCDR = 2V
1.5
mA
Notes:
17. Test conditions used are Load 2.
18. t
is a calculated parameter and is the greater of t
–t
(actual) or t
–t (actual).
DDD SD
BDD
WDD PWE
19. CE = V , V = GND to V , T = 25°C. This parameter is guaranteed but not tested.
CC
in
CC
A
Document #: 38-06046 Rev. *C
Page 9 of 18
CY7C026A
CY7C036A
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[20, 21, 22]
t
RC
ADDRESS
DATA OUT
t
AA
t
t
OHA
OHA
PREVIOUS DATAVALID
DATA VALID
Read Cycle No.2 (Either Port CE/OE Access)[20, 23, 24]
t
ACE
CE and
LB or UB
t
HZCE
t
DOE
OE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
Read Cycle No. 3 (Either Port)[20, 22, 23, 24]
t
RC
ADDRESS
t
AA
t
OHA
UB or LB
t
t
HZCE
t
t
LZCE
LZCE
t
ABE
CE
HZCE
t
ACE
DATA OUT
Notes:
20. R/W is HIGH for read cycles.
21. Device is continuously selected CE = V and UB or LB = V . This waveform cannot be used for semaphore reads.
IL
IL
22. OE = V
.
IL
23. Address valid prior to or coincident with CE transition LOW.
24. To access RAM, CE = V , UB or LB = V , SEM = V . To access semaphore, CE = V , SEM = V .
IL
IL
IH
IH
IL
Document #: 38-06046 Rev. *C
Page 10 of 18
CY7C026A
CY7C036A
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[25, 26, 27, 28]
t
WC
ADDRESS
OE
[31]
t
HZOE
t
AW
[29,30]
CE
[28]
PWE
t
t
t
HA
SA
R/W
DATA OUT
DATA IN
[31]
HZWE
t
t
LZWE
NOTE 32
NOTE 32
t
t
HD
SD
Write Cycle No. 2: CE Controlled Timing[25, 26, 27, 33]
t
WC
ADDRESS
t
AW
[29,30]
CE
t
t
t
HA
SA
SCE
R/W
t
t
HD
SD
DATA IN
Notes:
25. R/W must be HIGH during all address transitions.
26. A write occurs during the overlap (t or t ) of a LOW CE or SEM and a LOW UB or LB.
SCE
PWE
27. t is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
28. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data
HZWE SD
PWE
to be placed on the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
SD
as short as the specified t
.
PWE
29. To access RAM, CE = V , SEM = V
.
IH
IL
30. To access upper byte, CE = V , UB = V , SEM = V .
IL
IL
IL
IL
IH
IH
To access lower byte, CE = V , LB = V , SEM = V .
31. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
32. During this period, the I/O pins are in the output state, and input signals must not be applied.
33. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06046 Rev. *C
Page 11 of 18
CY7C026A
CY7C036A
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[34]
t
t
OHA
SAA
A0–A2
VALID ADRESS
VALID ADRESS
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[35, 36, 37]
A0L–A2L
MATCH
R/WL
SEML
t
SPS
A0R–A2R
MATCH
R/WR
SEMR
Notes:
34. CE = HIGH for the duration of the above timing (both write and read cycle).
35. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
36. Semaphores are reset (available to both ports) at cycle start.
37. If t is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
SPS
Document #: 38-06046 Rev. *C
Page 12 of 18
CY7C026A
CY7C036A
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S = HIGH)[38]
t
WC
ADDRESSR
R/WR
MATCH
t
PWE
t
t
HD
SD
DATA INR
VALID
t
PS
ADDRESSL
MATCH
t
BLA
t
BHA
BUSYL
t
BDD
t
DDD
DATAOUTL
VALID
t
WDD
Write Timing with Busy Input (M/S = LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note:
38. CE = CE = LOW.
L
R
Document #: 38-06046 Rev. *C
Page 13 of 18
CY7C026A
CY7C036A
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[39]
CEL Valid First:
ADDRESSL,R
CEL
ADDRESS MATCH
t
PS
CER
t
t
BHC
BLC
BUSYR
CER Valid First:
ADDRESSL,R
ADDRESS MATCH
CER
CEL
t
PS
t
t
BHC
BLC
BUSYL
Busy Timing Diagram No. 2 (Address Arbitration)[39]
Left Address Valid First:
t
or t
WC
RC
ADDRESSL
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESSR
BUSYR
t
t
BHA
BLA
Right Address Valid First:
t
or t
WC
RC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESSL
BUSYL
t
t
BHA
BLA
Note:
39. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
PS
Document #: 38-06046 Rev. *C
Page 14 of 18
CY7C026A
CY7C036A
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
t
WC
ADDRESSL
CEL
WRITE 3FFF
[40]
t
HA
R/WL
INTR
[41]
t
INS
Right Side Clears INTR:
t
RC
ADDRESSR
CER
READ 3FFF
[41]
t
INR
R/WR
OER
INTR
Right Side Sets INTL:
t
WC
ADDRESSR
CER
WRITE 3FFE
[40]
HA
t
R/WR
INTL
[41]
INS
t
Left Side Clears INTL:
t
RC
READ 3FFE
ADDRESSR
CEL
[41]
t
INR
R/WL
OEL
INTL
Notes:
40. t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
41. t
or t
depends on which enable pin (CE or R/W ) is asserted last.
INS
INR L L
Document #: 38-06046 Rev. *C
Page 15 of 18
CY7C026A
CY7C036A
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
X
L
R/W
X
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
H
H
H
H
H
H
X
I/O9–I/O17
High Z
I/O0–I/O8
High Z
Operation
Deselected: Power-Down
Deselected: Power-Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
High Z
High Z
L
Data In
High Z
High Z
L
L
H
L
Data In
Data In
High Z
L
L
L
Data In
Data Out
High Z
L
H
H
H
X
L
H
L
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
Data Out
Data Out
High Z
L
L
L
Data Out
High Z
X
H
X
H
H
L
X
X
H
X
X
X
H
X
Outputs Disabled
H
H
L
Data Out
Data Out
Data In
Data Out
Data Out
Data In
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
L
L
X
L
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
L
L
X
X
X
X
L
X
L
L
L
Not Allowed
Not Allowed
X
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)
Left Port
Right Port
Function
R/WL CEL
OEL
X
A0L–13L
3FFF
X
INTL R/WR CER
OER
X
A0R–13R
X
INTR
L[43]
H[42]
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
X
L
X
L
L
X
X
X
L
3FFF
3FFE
X
X
X
L[42]
H[43]
X
L
3FFE
X
X
X
Table 3. Semaphore Operation Example
Function I/O0–I/O17 Left I/O0–I/O17 Right
Status
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Left port writes 1 to semaphore
Notes:
42. If BUSY =L, then no change.
L
43. If BUSY =L, then no change.
R
Document #: 38-06046 Rev. *C
Page 16 of 18
CY7C026A
CY7C036A
Ordering Information
16K x16 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
12[1]
15
Ordering Code
CY7C026A-12AC
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
A100
A100
A100
A100
A100
A100
Commercial
Commercial
CY7C026A-15AC
CY7C026A-15AXC
CY7C026A-15AI
CY7C026A-20AC
CY7C026A-20AXC
Industrial
20
Commercial
Speed
(ns)
12[1]
Package
Name
Operating
Range
Ordering Code
CY7C036A-12AC
CY7C036A-15AC
CY7C036A-15AI
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
A100
A100
A100
A100
Commercial
Commercial
Industrial
15
20
CY7C036A-20AC
Commercial
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06046 Rev. *C
Page 17 of 18
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C026A
CY7C036A
Document History Page
Document Title: CY7C026A/CY7C036A 16K X 16/18 Dual-Port Static RAM
Document Number: 38-06046
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
110198
122296
237621
393454
Description of Change
09/29/01
12/27/02
SEE ECN
See ECN
SZV
RBI
Change from Spec number: 38-00832 to 38-06046
*A
Power up requirements added to Maximum Ratings Information
Removed cross information from features section
Added Pb-Free Logo
*B
YDT
YIM
*C
Added Pb-Free parts to ordering information:
CY7C026A-15AXC, CY7C026A-20AXC
Document #: 38-06046 Rev. *C
Page 18 of 18
相关型号：
©2020 ICPDF网 联系我们和版权申明