CY62157DV30LL-55ZSXI [CYPRESS]
8-Mbit (512K x 16) MoBL Static RAM; 8兆位（ 512K ×16 ）的MoBL静态RAM
| 型号： | CY62157DV30LL-55ZSXI |
| 厂家： | 
CYPRESS |
| 描述： | 8-Mbit (512K x 16) MoBL Static RAM |
| 文件： | 总12页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157DV30
MoBL®
8-Mbit (512K x 16) MoBL Static RAM
Features
Functional Description[1]
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C (Preliminary)
• Very high speed: 45 ns, 55 ns and 70 ns
• Wide voltage range: 2.20V – 3.60V
The CY62157DV30 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL®) in
portable applications such as cellular telephones.The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can also be put into
• Pin-compatible with CY62157CV25, CY62157CV30, and
standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A18). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table for a complete description
of read and write modes.
CY62157CV33
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 12 mA @ f = fmax
• Ultra-low standby power
• Easy memory expansion with CE1, CE2, and OE
features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered: 48-ball BGA, 48-pin TSOPI, and
44-pin TSOPII
Logic Block Diagram
DATA-IN DRIVERS
A
A
A
A
A
A
A
10
9
8
7
512K × 16
RAM Array
6
5
I/O0 – I/O7
4
3
2
I/O8 – I/O15
A
A
A
A
1
0
COLUMN DECODER
BHE
WE
CE
1
2
CE
OE
BLE
Power-down
Circuit
Notes:
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05392 Rev. *E
Revised August 24, 2004
CY62157DV30
MoBL®
Product Portfolio
Power Dissipation
Operating ICC, (mA)
f = 1MHz f = fmax
Standby ISB2
,
VCC Range (V)
(µA)
Speed
(ns)
Product
Range
Min. Typ.[2] Max.
Typ.[2] Max. Typ.[2] Max. Typ.[2] Max.
CY62157DV30L Industrial
CY62157DV30LL Industrial
CY62157DV30L Automotive[3]
2.2
2.2
2.2
3.0
3.0
3.0
3.6 45, 55, 70
3.6 45, 55, 70
1.5
1.5
1.5
3
3
3
12
12
12
20
15
20
2
2
2
20
8
50
3.6
FBGA
55
Pin Configuration[4, 5, 6, 7]
op
e
1
2
4
3
5
6
A
0
A
A
2
CE2
CE1 I/O
OE
BLE
1
A
A
A
3
I/O BHE
B
C
4
0
8
A
5
A
6
I/O
I/O
I/O
2
I/O
9
10
1
Vcc
A
V
I/O
I/O
3
A17
D
E
F
SS
7
11
Vss
I/O
DNU
A
16
V
CC
I/O
I/O
12
4
A
A
15
I/O
I/O
I/O
14
13
5
14
6
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
A
A
9
A
A
8
A18
NC
10
11
48TSOPI
44 TSOP II
Top View
Top View
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
A
A
5
4
A
A
6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
A
2
A
7
OE
A
1
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
BHE
BLE
A
0
CE
A8
I/O
I/O
15
0
NC
DNU 10
I/O
I/O
I/O
1
14
13
12
WE
11
12
I/O
2
CE2
DNU 13
BHE 14
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
I/O
V
I/O
3
V
BLE
A18
A17
A7
15
16
17
18
19
20
21
22
23
24
SS
CC
V
V
SS
CC
I/O
I/O
I/O
4
5
6
7
11
10
9
8
A6
I/O
I/O
I/O
A5
A4
I/O
I/O
A3
Vss
A2
CE1
A0
A
8
A1
WE 17
18
A
9
A
18
17
19
20
21
22
26
25
24
23
A
A
10
A
A
16
11
A
12
A
15
A
A
13
14
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
CC
, T = 25°C.
A
CC(typ.)
3. Automotive data is PRELIMINARY. Shaded areas of the datasheet contain PRELIMINARY information.
4. NC pins are not internally connected on the die.
5. DNU pins have to be left floating.
6. The BYTE pin in the 48-TSOPI package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOPI package can also be used as a 1M × 8
SRAM by tying the BYTE signal LOW. For 1M × 8 Functionality, please refer to the CY62158DV30 datasheet. In the 1M × 8 configuration, Pin 45 is A19.
7. The 44-TSOPII package device has only one chip enable pin (CE).
Document #: 38-05392 Rev. *E
Page 2 of 12
CY62157DV30
MoBL®
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current......................................................>200 mA
Storage Temperature ................................–65°C to + 150°C
Operating Range
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Ambient
[10]
Supply Voltage to Ground
Device
Range
Industrial
Temperature (TA) VCC
Potential.........................................–0.3V to + VCC(max) + 0.3V
CY62157DV30L
CY62157DV30LL
CY62157DV30L
–40°C to +85°C 2.20V
DC Voltage Applied to Outputs
to
in High-Z State[8, 9]............................–0.3V to VCC(max) + 0.3V
3.60V
Automotive –40°C to +125°C
(Preliminary)
DC Input Voltage[8, 9] ........................–0.3V to VCC(max) + 0.3V
Electrical Characteristics Over the Operating Range
CY62157DV30
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
Min. Typ.[2]
2.0
2.4
Max.
Unit
V
V
V
V
V
V
V
V
µA
µA
µA
µA
mA
mA
IOH = –0.1 mA
OH = –1.0 mA
IOL = 0.1 mA
VCC = 2.20V
VCC = 2.70V
VCC = 2.20V
VCC = 2.70V
I
VOL
VIH
VIL
IIX
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
0.4
0.4
VCC + 0.3V
VCC + 0.3V
IOL = 2.1mA
VCC = 2.2V to 2.7V
1.8
2.2
–0.3
–0.3
–1
-4
–1
V
CC= 2.7V to 3.6V
VCC = 2.2V to 2.7V
CC= 2.7V to 3.6V
GND < VI < VCC
0.6
0.8
+1
+4
+1
+4
20
15
V
Industrial
Automotive
Industrial
Automotive
VCC = VCCmax
IOUT = 0 mA
CMOS levels
IOZ
ICC
Output Leakage Current GND < VO < VCC, Output
Disabled
-4
VCC Operating Supply
Current
f = fMAX = 1/tRC
L
LL
12
f = 1 MHz
L
LL
L
LL
L
1.5
3
3
20
8
mA
mA
µA
ISB1
Automatic CE
Power-Down
Current — CMOS
Inputs
CE1 > VCC−0.2V, CE2< 0.2V Industrial
VIN>VCC–0.2V, VIN<0.2V)
2
2
f = fMAX (Address and Data
Automotive
50
Only),
f = 0 (OE, WE, BHE and
BLE), VCC=3.60V
ISB2
Automatic CE
Power-Down
Current — CMOS
Inputs
CE1 > VCC – 0.2V or CE2 < Industrial
L
LL
L
2
2
20
8
50
µA
0.2V,
VIN > VCC – 0.2V or VIN
0.2V,
<
Automotive
f = 0, VCC = 3.60V
Notes:
8. V
9. V
= –2.0V for pulse durations less than 20 ns.
CC
IL(min.)
IH(max)
= V +0.75V for pulse duration less than 20 ns.
10. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
cc
cc
Document #: 38-05392 Rev. *E
Page 3 of 12
CY62157DV30
MoBL®
Capacitance[11, 12]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = VCC(typ)
Max.
10
10
Unit
pF
pF
CIN
COUT
V
Thermal Resistance[11]
Parameter
Description
Test Conditions
BGA
TSOP II
TSOP I
Unit
ΘJA
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch,
72
75.13
74.88
°C/W
(Junction to Ambient)
four-layer printed circuit board
ΘJC
Thermal Resistance
(Junction to Case)
8.86
8.95
8.6
°C/W
AC Test Loads and Waveforms[13]
R1
ALL INPUT PULSES
VCC
VCC
GND
Rise Time = 1 V/ns
90%
90%
OUTPUT
10%
10%
R2
30 pF / 50 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.50V
16667
15385
8000
3.0V
1103
1554
645
Unit
Ω
R1
R2
RTH
VTH
Ω
Ω
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.[2] Max. Unit
VDR
VCC for Data Retention
1.5
V
ICCDR
Data Retention Current
VCC= 1.5V
CE1 > VCC – 0.2V, CE2 < 0.2V,
IN > VCC – 0.2V or VIN < 0.2V
Industrial (L)
Industrial (LL)
Automotive (L)
10
4
25
µA
V
[11]
tCDR
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
ns
ns
[14]
tR
tRC
Notes:
11. Tested initially and after any design or process changes that may affect these parameters.
12. The input capacitance on the CE pin of the FBGA and 48TSOPI packages and on the BHE pin of the 44TSOPII package is 15 pF.
2
13. Test condition for the 45 ns part is a load capacitance of 30 pF.
14. Full device operation requires linear V ramp from V to V
> 100 us or stable at V
> 100 us.
CC(min.)
CC
DR
CC(min.)
Document #: 38-05392 Rev. *E
Page 4 of 12
CY62157DV30
MoBL®
Data Retention Waveform[15]
DATA RETENTION MODE
VCC, min.
tR
> 1.5 V
VDR
VCC, min.
tCDR
VCC
CE or
1
BHE.BLE
or
CE2
Switching Characteristics Over the Operating Range [16]
45 ns [13]
55 ns
Max.
70 ns
Parameter
Read Cycle
tRC
tAA
tOHA
Description
Min.
Max.
Min.
55
Min.
Max.
Unit
Read Cycle Time
Address to Data Valid
45
10
70
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
55
70
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
10
tACE
tDOE
45
25
55
25
70
35
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle[19]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
OE LOW to LOW Z[17]
5
10
0
5
10
0
5
10
0
OE HIGH to High Z[17, 18]
15
20
20
20
25
25
CE1 LOW and CE2 HIGH to Low Z[17]
CE1 HIGH and CE2 LOW to High Z[17, 18]
CE1 LOW and CE2 HIGH to Power-Up
CE1 HIGH and CE2 LOW to Power-Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z[17]
45
45
55
55
70
70
10
10
10
BLE / BHE HIGH to HIGH Z[17, 18]
15
20
25
Write Cycle Time
45
40
40
0
55
40
40
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW and CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[17, 18]
WE HIGH to Low-Z[17]
0
0
0
35
40
25
0
40
40
25
0
45
60
30
0
tHZWE
tLZWE
15
20
25
10
10
10
Notes:
15. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
16. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
OL OH
CC(typ.)
17. At any given temperature and voltage condition, t
given device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
18. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedence state.
HZOE HZCE HZBE
HZWE
19. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the write.
Document #: 38-05392 Rev. *E
Page 5 of 12
CY62157DV30
MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[20, 21]
tRC
ADDRESS
t
AA
t
OHA
PREVIOUS DATA VALID
DATA OUT
DATA VALID
Read Cycle 2 (OE Controlled)[21, 22]
ADDRESS
t
RC
CE
1
t
PD
t
HZCE
CE
2
t
ACE
BHE/BLE
t
DBE
t
HZBE
t
LZBE
OE
t
HZOE
t
DOE
LZOE
HIGH IMPEDANCE
t
HIGH
IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
ICC
ISB
t
PU
50%
50%
SUPPLY
CURRENT
Notes:
20. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V .
IH
1
IL
IL
2
21. WE is HIGH for read cycle.
22. Address valid prior to or coincident with CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05392 Rev. *E
Page 6 of 12
CY62157DV30
MoBL®
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[19, 23, 24, 25]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
t
PWE
SA
WE
t
BW
BHE/BLE
OE
t
t
SD
VALID DATA
HD
DATA I/O
See note 24
t
HZOE
[19, 23, 24, 25]
Write Cycle 2 (CE1 or CE2 Controlled)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
VALID DATA
HD
DATA I/O
See note 24
t
HZOE
Notes:
23. Data I/O is high impedance if OE = V
.
IH
24. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high-impedance state.
1
2
IH
25. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05392 Rev. *E
Page 7 of 12
CY62157DV30
MoBL®
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[24, 25]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
BW
BHE/BLE
WE
t
t
HA
AW
t
t
PWE
SA
t
t
HD
SD
See note 24
DATA
I/O
VALID DATA
t
LZWE
t
HZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[24, 25]
t
WC
ADDRESS
CE1
CE
2
t
SCE
AW
t
t
HA
tBW
BHE/BLE
WE
t
SA
tPWE
t
t
HD
SD
VALID DATA
See note 24
DATA I/O
Document #: 38-05392 Rev. *E
Page 8 of 12
CY62157DV30
MoBL®
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Power
Standby (ISB
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
)
X
L
X
X
X
X
High Z
High Z
)
X
X
X
X
H
H
)
L
H
H
L
L
L
Data Out (I/O0 – I/O15) Read (Upper byte and Lower Byte)
)
L
H
H
L
H
L
Data Out (I/O0 – I/O7); Read (Lower Byte only)
High Z (I/O8 – I/O15)
)
L
H
H
L
L
H
High Z (I/O0 – I/O7);
Read (Upper Byte only)
Active (ICC)
Data Out (I/O8 – I/O15)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
Data In (I/O0 – I/O15) Write(Upper byte and Lower Byte)
)
L
H
Data In (I/O0 – I/O7);
High Z (I/O8 – I/O15)
Write (Lower Byte only)
)
L
H
L
X
L
H
High Z (I/O0 – I/O7);
Data In (I/O8 – I/O15)
Write (Upper Byte only)
Active (ICC)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
45
Ordering Code
CY62157DV30L-45BVI
Package Type
BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm)
Industrial
Industrial
Industrial
Industrial
Industrial
CY62157DV30LL-45BVI
CY62157DV30L-45ZXI
CY62157DV30LL-45ZXI
CY62157DV30L-45ZSXI
CY62157DV30LL-45ZSXI
CY62157DV30L-55BVI
CY62157DV30LL-55BVI
CY62157DV30L-55BVXI
CY62157DV30LL-55BVXI
CY62157DV30L-55BVE
CY62157DV30L-55ZXI
CY62157DV30LL-55ZXI
CY62157DV30L-55ZXE
CY62157DV30L-55ZSXI
CY62157DV30LL-55ZSXI
CY62157DV30L-55ZSXE
CY62157DV30L-55ZSI
CY62157DV30LL-55ZSI
CY62157DV30L-70BVI
CY62157DV30LL-70BVI
CY62157DV30L-70BVXI
CY62157DV30LL-70BVXI
CY62157DV30L-70ZXI
CY62157DV30LL-70ZXI
45
45
55
55
Z-48
48-pin TSOP I (Pb-free)
44-pin TSOP II (Pb-free)
ZS-44
BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm)
BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm) (Pb-free)
BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm)
55
55
Automotive
Industrial
Z-48
48-pin TSOP I (Pb-free)
55
55
Z-48
ZS-44
48-pin TSOP I (Pb-free)
44-pin TSOP II (Pb-free)
Automotive
Industrial
55
55
ZS-44
ZS-44
44-pin TSOP II (Pb-free)
44-pin TSOP II
Automotive
Industrial
70
70
70
BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm)
Industrial
Industrial
Industrial
BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm) (Pb-free)
Z-48
48-pin TSOP I (Pb-free)
Document #: 38-05392 Rev. *E
Page 9 of 12
CY62157DV30
MoBL®
Ordering Information (continued)
Speed
Package
Name
ZS-44
Operating
Range
Industrial
(ns)
Ordering Code
Package Type
44-pin TSOP II (Pb-free)
70
CY62157DV30L-70ZSXI
CY62157DV30LL-70ZSXI
CY62157DV30L-70ZSI
CY62157DV30LL-70ZSI
70
ZS-44
44-pin TSOP II
Industrial
Package Diagrams
48-ball (6.0 mm × 8.0 mm × 1.0 mm) Fine Pitch BGA BV48A
51-85150-*B
Document #: 38-05392 Rev. *E
Page 10 of 12
CY62157DV30
MoBL®
Package Diagrams (continued)
48-Lead TSOP I (12 mm x 18.4 mm x 1.0 mm) Z48A
DIMENSIONS IN INCHES[MM] MIN.
MAX.
JEDEC # MO-142
0.037[0.95]
0.041[1.05]
N
1
0.020[0.50]
TYP.
0.472[12.00]
0.007[0.17]
0.011[0.27]
0.002[0.05]
0.006[0.15]
0.724 [18.40]
0.047[1.20]
MAX.
0.787[20.00]
0.004[0.10]
0.008[0.21]
0.010[0.25]
GAUGE PLANE
0.020[0.50]
0.028[0.70]
0°-5°
51-85183-*A
44-Pin TSOP II ZS44
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05392 Rev. *E
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62157DV30
MoBL®
Document History Page
Document Title:CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL Static RAM
Document Number: 38-05392
Orig. of
REV.
**
*A
*B
*C
ECN NO. Issue Date Change
Description of Change
New Data Sheet
126316
131013
133115
211601
05/22/03
HRT
11/19/03 CBD/LDZ Change from Advance to Preliminary
01/24/04
See ECN
CBD
AJU
Minor Change: Change MPN and upload.
Change from Preliminary to Final
Changed Marketing part number from CY62157DV to CY62157DV30 in the
title and in the Ordering Information table
Added footnotes 4, 5 and 11
Modified footnote 8 to include ramp time and wait time
Removed MAX value for VDR on Data Retention Characteristics table
Changed ordering code for Pb-free parts
Modified voltage limits in Maximum Ratings section
*D
*E
236628
257349
See ECN SYT/AJU Added 45-ns and 70-ns Speed Bins
Added Automotive product information
See ECN
PCI
Added test condition for 45 ns part (footnote #13 on page 4)
Document #: 38-05392 Rev. *E
Page 12 of 12
相关型号：
CY62157DV30LL-70BVIT
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CYPRESS
CY62157DV30LL-70BVXIT
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, FBGA-48
CYPRESS
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