CY62157DV30LL-55BVXA [CYPRESS]
8-Mbit (512K x 16) MoBL㈢ Static RAM; 8兆位（ 512K ×16 ） MoBL㈢静态RAM
| 型号： | CY62157DV30LL-55BVXA |
| 厂家： | 
CYPRESS |
| 描述： | 8-Mbit (512K x 16) MoBL㈢ Static RAM |
| 文件： | 总12页 (文件大小：578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157DV30 MoBL®
8-Mbit (512K x 16) MoBL® Static RAM
Features
Functional Description[1]
• Temperature Ranges
The CY62157DV30 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones.The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH and WE LOW).
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62157CV25, CY62157CV30, and
CY62157CV33
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 12 mA @ f = fmax
• Ultra-low standby power
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A18). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
• Easy memory expansion with CE1, CE2, and OE
features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball FBGA,
44-pin TSOPII, and Pb-free 48-pin TSOPI
Reading from the device is accomplished by taking Chip
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table for a complete description
of read and write modes.
Logic Block Diagram
DATA-IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
512K × 16
RAM Array
I/O0–I/O7
I/O8–I/O15
A2
A1
A0
COLUMN DECODER
BHE
WE
CE2
CE
1
OE
BLE
Power-down
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05392 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 8, 2006
CY62157DV30 MoBL®
Product Portfolio
Power Dissipation
Operating ICC, (mA)
f = 1MHz f = fmax
Typ.[2] Max. Typ.[2] Max. Typ.[2] Max.
Standby ISB2
,
VCC Range (V)
Min. Typ.[2] Max.
(µA)
Speed
(ns)
Product
Range
CY62157DV30L Industrial
CY62157DV30LL Industrial
CY62157DV30LL Automotive-A
CY62157DV30L Automotive-E
2.2
2.2
2.2
2.2
3.0
3.0
3.0
3.0
3.6 45, 55, 70
3.6 45, 55, 70
1.5
1.5
1.5
1.5
3
3
3
3
12
12
12
12
20
15
15
20
2
2
2
2
20
8
3.6
3.6
55
55
8
50
Pin Configuration[4, 5, 6]
48-Pin TSOP I Pinout
Top View
A15
A14
A13
A12
A11
A10
A9
A8
NC
DNU 10
WE
CE2
DNU 13
BHE 14
BLE
A18
A17
A7
A6
A5
A4
A3
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
2
3
4
5
6
7
8
9
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
11
12
15
16
17
18
19
20
21
22
23
24
Vss
CE1
A0
A2
A1
48-Ball FBGA Pinout
Top View
44-pin TSOP II Pinout
Top View
1
2
4
3
5
6
44
43
42
41
40
39
38
1
2
3
4
5
6
A
A
5
4
A
A
3
6
A
A
A
2
CE2
OE
BLE
0
1
A
B
C
A
A
7
OE
BHE
BLE
I/O
15
2
A
1
A
A
I/O BHE
8
CE1 I/O
A
4
3
0
0
CE
I/O
7
0
A
A
6
I/O I/O
I/O
I/O
2
5
9
10
1
37
36
35
34
33
I/O
8
I/O
I/O
1
2
14
13
12
I/O
9
Vcc
A
V
I/O
I/O
3
A17
D
E
F
SS
7
11
10
11
12
13
I/O
3
CC
V
SS
I/O
4
I/O
V
V
SS
Vss
I/O
DNU
A
V
V
I/O
I/O
CC
CC
16
12
4
32
31
30
29
28
27
I/O
I/O
11
10
I/O
14
15
16
5
A
A
15
I/O
I/O
5
I/O
14
13
14
6
I/O
I/O
6
9
8
I/O
I/O
7
A
8
WE 17
18
A
A
G
H
I/O
NC
WE I/O
7
13
12
15
A
A
18
9
19
20
21
22
26
25
A
A
10
17
A
A
9
A
11
A
A18
NC
10
8
A
A
12
16
11
A
A
24
23
15
A
A
13
14
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ.)
3. NC pins are not internally connected on the die.
4. DNU pins have to be left floating.
5. The BYTE pin in the 48-TSOPI package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOPI package can also be used as a 1M × 8
SRAM by tying the BYTE signal LOW. For 1M × 8 Functionality, please refer to the CY62158DV30 datasheet. In the 1M × 8 configuration, Pin 45 is A19, while
BHE, BLE and I/O8 to I/O14 pins are not used.
6. The 44-TSOPII package device has only one chip enable pin (CE).
Document #: 38-05392 Rev. *H
Page 2 of 12
CY62157DV30 MoBL®
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current......................................................>200 mA
Operating Range
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Ambient
Temperature
[10]
Device
Range
(TA)
VCC
Supply Voltage to Ground
Potential............................................–0.3V to VCC(max) + 0.3V
CY62157DV30L
CY62157DV30LL
Industrial
–40°C to +85°C 2.20V
to
3.60V
DC Voltage Applied to Outputs
in High-Z State[8, 9]............................–0.3V to VCC(max) + 0.3V
CY62157DV30LL Automotive-A –40°C to +85°C
CY62157DV30L Automotive-E –40°C to +125°C
DC Input Voltage[8, 9] ........................–0.3V to VCC(max) + 0.3V
Output Current into Outputs (LOW) .............................20 mA
Electrical Characteristics Over the Operating Range
-45, -55, -70
Parameter
Description
Test Conditions
Min. Typ.[2] Max.
Unit
V
VOH
Output HIGH
Voltage
IOH = –0.1 mA
VCC = 2.20V
VCC = 2.70V
VCC = 2.20V
VCC = 2.70V
2.0
2.4
0.4
0.4
IOH = –1.0 mA
V
VOL
VIH
VIL
IIX
Output LOW
Voltage
IOL = 0.1 mA
V
IOL = 2.1 mA
V
Input HIGH
Voltage
VCC = 2.2V to 2.7V
VCC= 2.7V to 3.6V
VCC = 2.2V to 2.7V
VCC= 2.7V to 3.6V
GND < VI < VCC
1.8
2.2
VCC + 0.3
VCC + 0.3
0.6
V
V
Input LOW
Voltage
–0.3
–0.3
–1
V
0.8
V
Input Leakage
Current
+1
µA
Ind’l/Auto-A[7]
Auto-E[7]
–4
–1
–4
+4
+1
+4
µA
µA
µA
IOZ
Output Leakage GND < VO < VCC, Output Disabled
Current
Ind’l/Auto-A[7]
Auto-E[7]
ICC
VCC Operating
Supply Current
f = fMAX = 1/tRC
VCC = VCCmax
IOUT = 0 mA
CMOS levels
L
12
12
1.5
1.5
2
20
15
3
mA
mA
mA
mA
µA
LL
L
f = 1 MHz
LL
L
3
ISB1
Automatic CE
Power-Down
Current — CMOS
Inputs
20
8
CE1 > VCC − 0.2V, CE2 < 0.2V
Ind’l
VIN > VCC – 0.2V, VIN < 0.2V)
LL
2
Ind’l/Auto-A[7]
Auto-E[7]
f = fMAX (Address and Data Only),
(OE, WE, BHE and BLE), VCC = 3.60V
f = 0
L
L
50
20
ISB2
Automatic CE
Power-Down
Current -CMOS
Inputs
2
2
µA
Ind’l[7]
CE1 > VCC– 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
LL
L
8
Ind’l/Auto-A[7]
Auto-E[7]
50
Capacitance[11, 12]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max.
Unit
CIN
10
10
pF
pF
COUT
Notes:
7. Automotive-A and Automotive-E available only in -55.
8. V
9. V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
= V +0.75V for pulse duration less than 20 ns.
IH(max)
CC
10. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
CC
CC
11. Tested initially and after any design or process changes that may affect these parameters.
12. The input capacitance on the CE pin of the FBGA and 48TSOPI packages and on the BHE pin of the 44TSOPII package is 15 pF.
2
Document #: 38-05392 Rev. *H
Page 3 of 12
CY62157DV30 MoBL®
Thermal Resistance[11]
Parameter
Description
Test Conditions
FBGA
TSOP II
TSOP I
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
39.3
35.62
36.9
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
9.69
9.13
10.05
°C/W
AC Test Loads and Waveforms[13]
R1
ALL INPUT PULSES
VCC
OUTPUT
VCC
GND
Rise Time = 1 V/ns
90%
10%
90%
10%
R2
30 pF / 50 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.50V
16667
15385
8000
3.0V
1103
1554
645
Unit
Ω
R1
R2
Ω
RTH
VTH
Ω
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
Conditions
Min. Typ.[2] Max.
Unit
V
VCC for Data Retention
Data Retention Current
1.5
10
4
ICCDR
VCC= 1.5V
CE1 > VCC – 0.2V, CE2 < 0.2V,
IN > VCC – 0.2V or VIN < 0.2V
Ind’l (L)
Ind’l/Auto-A (LL)
Auto-E (L)
µA
V
25
[11]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[14]
tR
Operation Recovery Time
tRC
Data Retention Waveform[15]
DATA RETENTION MODE
> 1.5 V
VCC, min.
tR
VCC, min.
tCDR
VDR
VCC
CE or
1
BHE.BLE
or
CE2
Notes:
13. Test condition for the 45 ns part is a load capacitance of 30 pF.
14. Full device operation requires linear V ramp from V to V
> 100 µs or stable at V > 100 µs.
CC(min.)
CC
DR
CC(min.)
Document #: 38-05392 Rev. *H
Page 4 of 12
CY62157DV30 MoBL®
Switching Characteristics Over the Operating Range [16]
45 ns[13]
55 ns
70 ns
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
45
10
55
70
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
45
55
70
tOHA
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z[17]
OE HIGH to High Z[17, 18]
CE1 LOW and CE2 HIGH to Low Z[17]
CE1 HIGH and CE2 LOW to High Z[17, 18]
CE1 LOW and CE2 HIGH to Power-Up
CE1 HIGH and CE2 LOW to Power-Down
BLE/BHE LOW to Data Valid
10
tACE
45
25
55
25
70
35
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
5
10
0
5
10
0
15
20
20
20
25
25
tPD
45
45
55
55
70
70
tDBE
tLZBE
tHZBE
Write Cycle[19]
tWC
BLE/BHE LOW to Low Z[17]
BLE/BHE HIGH to HIGH Z[17, 18]
10
10
10
15
20
25
Write Cycle Time
45
40
40
0
55
40
40
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
0
0
tPWE
35
40
25
0
40
40
25
0
45
60
30
0
tBW
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[17, 18]
WE HIGH to Low-Z[17]
tSD
tHD
tHZWE
15
20
25
tLZWE
10
10
10
Notes:
15. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse
CC(typ)
levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
CC(typ.)
OL OH
17. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
given device.
18. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
19. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the write.
Document #: 38-05392 Rev. *H
Page 5 of 12
CY62157DV30 MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[20, 21]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle 2 (OE Controlled)[21, 22]
ADDRESS
t
RC
CE
t
PD
t
HZCE
CE
t
ACE
BHE/BLE
t
DBE
t
HZBE
t
LZBE
OE
t
HZOE
t
DOE
LZOE
HIGH IMPEDANCE
t
HIGH
IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
ICC
ISB
t
PU
50%
50%
SUPPLY
CURRENT
Notes:
20. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V .
1
IL
IL
2
IH
21. WE is HIGH for read cycle.
22. Address valid prior to or coincident with CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05392 Rev. *H
Page 6 of 12
CY62157DV30 MoBL®
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[19, 23, 24, 25]
t
WC
ADDRESS
CE1
t
SCE
CE2
t
t
HA
AW
t
t
PWE
SA
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID DATA
DATA I/O
See note 25
t
HZOE
Write Cycle 2 (CE1 or CE2 Controlled)[19, 23, 24, 25]
t
WC
ADDRESS
CE1
t
SCE
CE2
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID DATA
DATA I/O
See note 25
t
HZOE
Notes:
23. Data I/O is high-impedance if OE = V
.
IH
24. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high-impedance state.
1
2
IH
25. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05392 Rev. *H
Page 7 of 12
CY62157DV30 MoBL®
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[24, 25]
t
WC
ADDRESS
CE1
t
SCE
CE2
t
BW
BHE/BLE
t
t
HA
AW
t
t
PWE
SA
WE
t
t
HD
SD
See note 25
DATA I/O
VALID DATA
t
LZWE
t
HZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[24, 25]
t
WC
ADDRESS
CE1
CE2
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
t
t
HD
SD
See note 25
DATA I/O
VALID DATA
Document #: 38-05392 Rev. *H
Page 8 of 12
CY62157DV30 MoBL®
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Power
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Read (Upper byte and Lower Byte)
Read (Lower Byte only)
Standby (ISB
Standby (ISB
Standby (ISB
)
)
)
X
L
X
X
X
X
High Z
X
X
X
X
H
H
High Z
L
H
H
L
L
L
Data Out (I/O0–I/O15
)
Active (ICC
)
)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15
Active (ICC
)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15
Read (Upper Byte only)
Active (ICC
)
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
High Z
High Z
Output Disabled
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
Output Disabled
Output Disabled
L
Data In (I/O0–I/O15
Data In (I/O0–I/O7);
High Z (I/O8–I/O15
)
Write (Upper byte and Lower Byte)
Write (Lower Byte only)
L
H
)
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15
Write (Upper Byte only)
Active (ICC
)
)
Document #: 38-05392 Rev. *H
Page 9 of 12
CY62157DV30 MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62157DV30L-45BVI
CY62157DV30LL-45ZSXI
CY62157DV30LL-55BVI
CY62157DV30L-55BVXI
CY62157DV30LL-55BVXI
CY62157DV30L-55ZXI
CY62157DV30LL-55ZSI
CY62157DV30L-55ZSXI
CY62157DV30LL-55ZSXI
CY62157DV30LL-55BVXA
CY62157DV30L-55BVXE
CY62157DV30L-55ZSXE
CY62157DV30LL-70BVI
CY62157DV30LL-70BVXI
51-85150 48-ball (6 x 8 x 1 mm) FBGA
51-85087 44-pin TSOP II (Pb-free)
51-85150 48-ball (6 x 8 x 1 mm) FBGA
48-ball (6 x 8 x 1 mm) FBGA (Pb-free)
Industrial
55
Industrial
51-85183 44-pin TSOP I (Pb-free)
51-85087 44-pin TSOP II
44-pin TSOP II (Pb-free)
51-85150 48-ball (6 x 8 x 1 mm) FBGA (Pb-free)
51-85150 48-ball (6 x 8 x 1 mm) FBGA (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
Automotive-A
Automotive-E
70
51-85150 48-ball (6 x 8 x 1 mm) FBGA
48-ball (6 x 8 x 1 mm) FBGA (Pb-free)
Industrial
Package Diagrams
48-ball FBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05ꢀ(48X
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
51-85150-*D
SEATING PLANE
C
Document #: 38-05392 Rev. *H
Page 10 of 12
CY62157DV30 MoBL®
Package Diagrams (continued)
48-pin TSOP I (12 mm x 18.4 mm x 1.0 mm) (51-85183)
DIMENSIONS IN INCHES[MM] MIN.
MA8.
JEDEC # MO-1(2
0.037[0.95]
0.0(1[1.05]
N
1
0.020[0.50]
TYP.
0.(72[12.00]
0.007[0.17]
0.011[0.27]
0.002[0.05]
0.006[0.15]
0.72( [14.(0]
0.747[20.00]
0.0(7[1.20]
MA8.
0.00([0.10]
0.004[0.21]
0.010[0.25]
GAUGE PLANE
0.020[0.50]
0.024[0.70]
0°-5°
51-85183-*A
44-pin TSOP II (51-85087)
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05392 Rev. *H
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62157DV30 MoBL®
Document History Page
Document Title: CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL® Static RAM
Document Number: 38-05392
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
126316
131013
133115
211601
05/22/03
HRT
New Data Sheet
*A
11/19/03 CBD/LDZ Change from Advance to Preliminary
*B
01/24/04
See ECN
CBD
AJU
Minor Change: Change MPN and upload.
*C
Change from Preliminary to Final
Changed Marketing part number from CY62157DV to CY62157DV30 in the
title and in the Ordering Information table
Added footnotes 4, 5 and 11
Modified footnote 8 to include ramp time and wait time
Removed MAX value for VDR on Data Retention Characteristics table
Changed ordering code for Pb-free parts
Modified voltage limits in Maximum Ratings section
*D
236628
See ECN SYT/AJU Added 45-ns and 70-ns Speed Bins
Added Automotive product information
*E
*F
257349
372074
See ECN
See ECN
PCI
Added test condition for 45 ns part (footnote #13 on page 4)
SYT
Added Pb-Free Automotive Part in the Ordering Information
Removed ‘Preliminary’ tag from Automotive Information
*G
433838
See ECN
See ECN
ZSD
VKN
Changed the address of Cypress Semiconductor Corporation on Page #1
from “3901 North First Street” to “198 Champion Court”
Updated the thermal resistance table
Updated the ordering information table and changed the package name
column to package diagram
*H
488954
Added Automotive-A product
Updated ordering Information table
Document #: 38-05392 Rev. *H
Page 12 of 12
相关型号：
CY62157DV30LL-70BVIT
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CYPRESS
CY62157DV30LL-70BVXIT
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, FBGA-48
CYPRESS
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