CY25C16-SXI [CYPRESS]
EEPROM, 16KX8, Serial, CMOS, PDSO8, LEAD FREE, SOIC-8;
| 型号： | CY25C16-SXI |
| 厂家： | 
CYPRESS |
| 描述： | EEPROM, 16KX8, Serial, CMOS, PDSO8, LEAD FREE, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总17页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25C01/02/04/08/16
1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, and 16 Kbit (x8)
SPI Serial EEPROM
Features
Functional Description
■ Continuous voltage operation
❐ VCC = 1.8V to 5.5V
The CY25C01/02/04/08/16 provides 1024, 2048, 4096, 8192,
and 16384 bits of serial Electrically Erasable and Programmable
Read Only Memory (EEPROM) organized as 128, 256, 512,
1024, or 2048 words of eight bits each. The device is optimized
for use in many industrial applications where low power and low
voltage operations are essential. The CY25C01/02/04/08/16 is
available in space saving 8-Pin SOIC, and 8-Pin TSSOP
packages.
■ Internally organized as 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K), or 2048 x 8 (16K)
■ Serial peripheral interface compatible
■ Supports SPI modes 0 (0,0) and 3 (1,1)
The CY25C01/02/04/08/16 is enabled through the Chip Select
pin (CS) and accessed via a three-wire interface consisting of
Serial Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK). All programming cycles are completely self timed and no
separate erase cycle is required before write.
■ Block write protection
❐ Protect 1/4,1/2, or entire array
■ Fast clock rate
❐ 20 MHz clock rate (VCC = 4.5V to 5.5V)
❐ 10 MHz clock rate (VCC = 1.8V to 5.5V)
Block write protection is enabled by programming the status
register with one of four blocks of write protection. Separate
program enable and program disable instructions are provided
for additional data protection. Hardware data protection is
provided through the WP pin to protect against inadvertent write
attempts to the status register. The HOLD pin can be used to
suspend any serial communication without resetting the serial
sequence.
■ Write protect (WP) pin and write disable instructions for both
hardware and software data protection
■ 32-byte page write mode
■ Self timed write cycle (5 ms max)
■ High reliability
❐ Endurance: 1 million write cycles
❐ Data retention: 100 years
■ Industrial temperature range
■ 8-Pin SOIC and 8-Pin TSSOP packages
■ Pb-free and RoHS compliant
Logic Block Diagram
VCC
CS
HOLD
SI
CY25C01/02/04/08/16
SO
WP
SCK
VSS
Cypress Semiconductor Corporation
Document #: 001-15633 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 05, 2009
[+] Feedback
CY25C01/02/04/08/16
Pin Configuration
Figure 1. Pin Diagram - 8-Pin SOIC/TSSOP
CS
SO
1
2
VCC
8
7
6
5
HOLD
Top View
(not to scale)
WP
SCK
SI
3
4
GND
Table 1. Pin Definitions - 8 Pin SOIC/TSSOP
8-SOIC/PDIP/TSSOP
Pin Name
I/O Type
Description
Pin Number
CS
SO
1
2
3
4
5
6
7
8
Input
Output
Input
Input
Input
Input
Input
Input
Chip Select
Serial Data Output
Write Protect
WP
GND
SI
Ground
Serial Data Input
Serial Data Clock
Suspends Serial Input
Power Supply
SCK
HOLD
VCC
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CY25C01/02/04/08/16
operations are inhibited. WP going low while CS is still low inter-
rupts a write to the CY25C01/02/04/08/16. If the internal write
cycle is already initiated, WP going low has no effect on the write
operation.
Serial Interface Description
Master
The device that generates the serial clock.
SPI Modes
Slave
The CY25C01/02/04/08/16 always operates as a slave because
the Serial Clock pin (SCK) is always an input.
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the following modes:
■ CPOL=0, CPHA=0
■ CPOL=1, CPHA=1
Transmitter or Receiver
The CY25C01/02/04/08/16 has separate pins designated for
data transmission (SO) and reception (SI).
For these two modes, input data is latched in on the rising edge
of Serial Clock (SCK) and output data is available from the falling
edge of Serial Clock (SCK).
MSB
The Most Significant Bit (MSB) is the first bit transmitted and
received.
The difference between the two modes, shown in Figure 2 and
Figure 3, is the clock polarity when the bus master is in standby
mode and not transferring data:
Serial Op-Code
■ SCK remains at 0 for (CPOL=0, CPHA=0)
■ SCK remains at 1 for (CPOL=1, CPHA=1)
Figure 2. SPI Mode 0
After the device is selected with CS going low, the first byte is
received. This byte contains the op-code that defines the opera-
tions to be performed.
Invalid Op-Code
If an invalid op-code is received, no data is shifted to the
CY25C01/02/04/08/16. The serial output pin (SO) remains in a
high impedance state until the falling edge of CS is detected
again. This reinitializes the serial communication.
CS
0
1
2
3
4
5
6
7
SCK
SO
Chip Select
The CY25C01/02/04/08/16 is selected when the CS pin is low.
When the device is not selected, data is not accepted through
the SI pin and the serial output pin (SO) remains in a high
impedance state.
7
6
5
4
3
2
1
0
MSB
LSB
Hold
Figure 3. SPI Mode 3
The HOLD pin is used in conjunction with the CS pin to select
the CY25C01/02/04/08/16. When the device is selected and a
serial sequence is underway, HOLD can be used to pause the
serial communication with the master device without resetting
the serial sequence. To pause, the HOLD pin must be brought
low when the SCK pin is low. To resume serial communication,
the HOLD pin is brought high when the SCK pin is low (SCK may
still toggle during HOLD). The HOLD signal behaves as a level
sensitive signal. This means, if the HOLD signal is asserted
when SCK is high, its value is latched and when SCK becomes
low, the latched value is considered to halt the transmission.
Inputs to the SI pin are ignored when the SO pin is in the high
impedance state.
CS
0
1
2
3
4
5
6
7
SCK
SO
7
6
5
4
3
2
1
0
MSB
LSB
Write Protect
The write protect pin (WP) enables normal read or write opera-
tions when held high. When the WP pin is brought low, all write
Document #: 001-15633 Rev. *C
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CY25C01/02/04/08/16
defined). When VCC passes over the POR threshold, the device
is reset and is in the following state:
Operating Features
Power Up
■ Standby power mode
When the power supply is turned on, VCC rises from VSS to VCC
.
■ Deselected (after power up, a falling edge is required on Chip
Select (S) before any instructions are started)
During this time, the Chip Select ( ) must be allowed to follow
CS
the VCC voltage. It must not be allowed to float, but must be
connected to VCC through a suitable pull up resistor. As a built in
■ Not in the hold condition
safety feature, Chip Select ( ) is edge sensitive and level
CS
Status register state:
sensitive. After power up, the device is not selected until a falling
edge is first detected on Chip Select ( ). This ensures that the
CS
■ The Write Enable (WEN) bit is reset to 0
Chip Select ( ) was high, before going low to start the first
CS
■ (RDY) is set to 1
operation.
Device Internal Reset
The WPEN[1], BP1 and BP0 bits of the status register are
unchanged from the previous power down (they are non volatile
bits). Before selecting and issuing instructions to the memory, a
valid and stable VCC voltage must be applied. This voltage must
remain stable and valid until the end of the transmission of the
instruction and for a write instruction, until the completion of the
internal write cycle (tWR).
To prevent inadvertent write operations during power up, a
Power On Reset (POR) circuit is included. During power up
(continuous rise up of VCC), the device does not respond to any
instruction until the VCC reaches the POR threshold voltage (this
threshold is lower than the minimum VCC operating voltage
During power down (continuous decay of VCC), as soon as VCC
drops from the normal operating voltage, below the POR
threshold voltage, the device stops responding to any instruction
sent to it.
Table 2. Instruction Set
Instruction Instruction
Operation
Name
WREN
WRDI
Format
0000 X110
0000 X100
0000 X101
0000 X001
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Power Down
During power down, the device must be deselected and in
standby power mode (no internal write cycle in progress). Chip
RDSR
WRSR
READ
WRITE
Select (CS) must be allowed to follow the voltage applied on VCC
.
0000 X011 Read Data From Memory Array
0000 X010 Write Data To Memory Array
Active Power and Standby Power Modes
When Chip Select (CS) is low, the device is selected in the active
power mode. The device consumes ICC, as specified in
DC Electrical Characteristics on page 9. When Chip Select (CS)
is high, the device is deselected. If an erase or write cycle is
currently not in progress, the device goes into the standby power
Write Enable (WREN)
The device powers up in the write disable state when VCC is
applied. All programming instructions must therefore be
preceded by a Write Enable instruction.
mode, and the device consumption drops to ISB1
.
Write Disable (WRDI)
Functional Description
To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI
instruction is independent of the status of the WP pin.
The CY25C01/02/04/08/16 supports the SPI bus data trans-
mission protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CY25C01/02/04/08/16 to interface directly with
many of the popular microcontrollers.
Read Status Register (RDSR)
The CY25C01/02/04/08/16 uses an 8-bit instruction register. The
list of instructions and their operation codes are contained in
Table 2. All instructions, addresses, and data are transferred with
the MSB, and it starts with a high to low (CS) transition.
The Read Status Register instruction provides access to the
status register. The READY/BUSY and Write Enable status of
the device is determined by the RDSR instruction. Similarly, the
block write protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruction.
Note
1. WPEN bit is applicable only for 8K and 16K devices.
Document #: 001-15633 Rev. *C
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CY25C01/02/04/08/16
Table 3. Status Register Format for CY25C01/02/04
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
BP1
BP0
WEN
RDY
Table 4. Status Register Format for CY25C08/16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 5. Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bit 0 = ‘0’ (RDY) indicates the device is READY. Bit 0 = ‘1’ indicates the write cycle is in progress.
Bit 1= ‘0’ indicates the device is not WRITE ENABLED. Bit 1 = ‘1’ indicates the device is write enabled.
See Table 6.
See Table 6.
Bits 4–6 are ‘0’s when device is not in an internal write cycle.
Bit 7 (X / WPEN) When the device is not in an internal write cycle, this bit is 0 in CY25C01/02/04 and WPEN (See
Table 7 on page 5) in CY25C08/16
Bits 0–7 are ‘1’s during an internal write cycle.
The WRSR instruction in CY25C08/16 also allows the user to
Write Status Register (WRSR)
enable or disable the write protect (WP) pin using the Write
Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is ‘1’. Hardware write
protection is disabled when the WP pin is high or when the
WPEN bit is ‘0’ (See Table 7).
The WRSR instruction enables the user to select one of four
levels of protection. The CY25C01/02/04/08/16 is divided into
four array segments. One quarter, one half, or all of the memory
segments can be protected. Any of the data within any selected
segment is therefore read only. The block write protection levels
and corresponding status register control bits are shown in
Table 6.
The three bits BP0, BP1, and WPEN[1] are nonvolatile cells that
have the same properties and functions as the regular memory
cells (for example, WREN, tWC, RDSR).
When the device is hardware write protected, writes to the status
register, including the block protect bits and the WPEN[1] bit, and
the block protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory that are not
block protected.
Table 6. Block Write Protect Bits
Status Register Bits
Level
Array Addresses Protected
BP1
BP0
CY25C01
None
CY25C02
None
CY25C04
CY25C08
CY25C16
0
0
0
1
1
0
1
0
1
None
None
None
1 (1/4)
2 (1/2)
3 (All)
60 - 7F
40 - 7F
00 - 7F
C0 - FF
80 - FF
00 - FF
180 - 1FF 0300 - 03FF 0600 - 07FF
100 - 1FF 0200 - 03FF 0400 - 07FF
000 - 1FF 0000 - 03FF 0000 - 07FF
Table 7. WPEN Operation
WPEN
WP
X
WEN
Protected Blocks
Unprotected Blocks
Protected
Status Register
Protected
Writable
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
X
Writable
Low
Low
High
High
Protected
Protected
Protected
Protected
Writable
Writable
Protected
Writable
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CY25C01/02/04/08/16
internal write cycle, all commands are ignored except the RDSR
instruction.
Read Sequence (READ)
Reading the CY25C01/02/04/08/16 through the Serial Output
(SO) pin requires the following sequence. After the CS line is
pulled low to select a device, the read op-code (including A8) is
transmitted through the SI line followed by the byte address to
be read (A7–A0). When completed, any data on the SI line is
ignored. The data (D7–D0) at the specified address is shifted out
onto the SO line. If only one byte is to be read, the CS line must
be driven high after the data comes out. The read sequence can
be continued since the byte address is automatically incre-
mented and data continues to be shifted out. When the highest
address is reached, the address counter rolls over to the lowest
address allowing the entire memory to be read in one continuous
read cycle.
The sequence for a write instruction is as follows. After the CS
line is pulled low to select the device, the WRITE op-code is
transmitted throuh the SI line followed by the byte address
(A7–A0) and the data (D7–D0) to be programmed. Programming
starts after the CS pin is brought high. The low to high transition
of the CS pin must occur during the SCK low time immediately
after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device is determined by initi-
ating a read status register (RDSR) instruction. If Bit 0 = ‘1’, the
write cycle is still in progress. If Bit 0 = ‘0’, the write cycle has
ended. Only the RDSR instruction is enabled during the write
programming cycle.
Write Sequence (WRITE)[2]
The CY25C01/02/04/08/16 is capable of a 32-byte page write
operation. After each byte of data is received, the five low order
address bits are internally incremented by one; the high order
bits of the address remain constant. If more than 16 bytes of data
are transmitted, the address counter rolls over and the previously
written data is overwritten. The CY25C01/02/04/08/16 is
automatically returned to the write disable state at the completion
of a write cycle. WEN bit is reset after every write instruction
regardless of it belonging to a protected array.
To program the CY25C01/02/04/08/16, two separate instructions
must be executed. First, the device must be write enabled
through the WREN instruction. Then a write (WRITE) instruction
can be executed. Also, the address of the memory locations to
be programmed must be outside the protected address field
location selected by the block write protection level. During an
Figure 4. Write Enable (WREN) Instruction Timing
CS
SCK
SI
SO
Note
2. If the device is not write enabled (WREN), the device ignores the write instruction and return to the standby state, when CS is brought HIGH. A new CS falling edge is
required to re initiate the serial communication.
Document #: 001-15633 Rev. *C
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CY25C01/02/04/08/16
Figure 5. Write Disable (WRDI) Instruction Timing
CS
SCK
SI
Figure 6. Read Status Register (RDSR) Instruction Timing
CS
SCK
SI
SO
Figure 7. Write Status Register (WRSR) Instruction Timing
CS
SCK
HOLD
SO
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CY25C01/02/04/08/16
Figure 8. Read Instruction Timing
CS
SCK
SI
SO
Figure 9. Write Instruction Timing
Document #: 001-15633 Rev. *C
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CY25C01/02/04/08/16
Package power dissipation
capability (TA = 25°C).................................................... 1.0W
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Surface mount lead soldering
temperature (3 Seconds)...................+260°C for 10 seconds
Output short circuit current[3]....................................... 50 mA
Storage temperature .................................. –65°C to +150°C
Ambient temperature with
power applied............................................. –40°C to +125°C
Static discharge voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Supply voltage on VCC relative to GND..........–0.6V to +6.0V
Latch up current .................................................... > 200 mA
DC voltage applied to outputs
in high-Z state........................................ –0.5V to VCC + 1.0V
Operating Range
Range
Ambient Temperature
VCC
Input voltage.......................................... –0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
1.8V to 5.5V
Transient voltage (<20 ns) on
any pin to ground potential.................... –1.0V to VCC + 2.0V
DC Electrical Characteristics
Over the Operating Range (VCC = 1.8V to 5.5V)
Parameter
VCC
Description
Supply Voltage
Test Conditions
VCC = 1.8V, CS = VCC
Min
Max
5.5
1
Unit
V
1.8
ISB1
ISB2
ISB3
ICC1
Standby Current
Standby Current
Standby Current
Supply Current (Read)
μA
μA
μA
mA
mA
mA
μA
μA
VCC = 2.7V, CS = VCC
VCC = 5.5V, CS = VCC
1.1
1.2
5
VCC = 1.8V - 5.5V at 10 MHz
VCC = 4.5V - 5.5V at 20 MHz
VCC = 5.5V
10
5
ICC2
ILI
Supply Current (Write)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
VIN = VCC or VSS
1
ILO
VIL
VIN = VCC or VSS
1
1.8V < VCC < 2.7V
–0.6 [4]
–0.6 [4]
0.7 VCC
0.3 VCC
0.8
VCC + 0.5 [4]
V
2.7V < VCC < 5.5V
VIH
Input HIGH Voltage
Output LOW Voltage
1.8V < VCC < 5.5V
V
V
VOL
IOL = 3 mA, 3.6 < VCC < 5.5V
0.4
I
OL = 0.15 mA, 1.8 < VCC < 3.6V
IOH = -0.1 mA, 1.8 < VCC < 3.6V
OH = -1.6 mA, 3.6 < VCC < 5.5V
0.2
VOH
Output HIGH Voltage
VCC – 0.2
VCC – 0.8
V
I
Note
3. Outputs shorted for only one second. Only one output shorted at a time.
4. This parameter is characterized but not tested.
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CY25C01/02/04/08/16
Capacitance
In the following table, the capacitance parameters are listed. [5]
Parameter
Description
Input Capacitance
Output Pin Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 5.5V
Max
6
Unit
pF
CIN
V
COUT
8
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[5]
Parameter
Description
Test Conditions
8-SOIC
8-TSSOP
Unit
ΘJA
Thermal Resistance
(Junction to Ambient) dures for measuring thermal impedance, per EIA /
Test conditions follow standard test methods and proce- 120.83
119.31
°C/W
JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
90.31
82.77
°C/W
Reliability Characteristics
In the following table, the reliability characteristics parameters are listed.[5]
Parameter
Description
Endurance
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
Min
1 Million
100
Unit
NEND
TDR
Cycles
Years
mA
Data Rentention
Latch Up
ILTH
100 + ICC
Figure 10. AC Test Loads and Waveforms
R1
VCC
OUTPUT
R2
C
L
Parameters
Frequency
1.8V - 2.7V
2.7V - 5.5V
1.8K
Unit
R1
R2
CL
20/10 MHz
20/10 MHz
20 MHz
1.8K
1.3K
-
Ω
Ω
1.3K
30
pF
10 MHz
30
Figure 11. AC Input/Output Reference Waveforms
VIHT
VILT
VHT
VLT
VHT
VLT
OUTPUT
REFERENCE POINTS
INPUT
AC test inputs are driven at VIHT (0.9VCC) for a logic “1” and VILT (0.1VCC) for a logic “0”. Measurement reference points for inputs
and outputs are VLT (VCC/2 - 0.1V) and VHT (VCC/2 + 0.1V). Input rise and fall times (10%–90%) are <20 ns
Note
5. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Document #: 001-15633 Rev. *C
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CY25C01/02/04/08/16
AC Switching Characteristics
Cypress
Alt
20 MHz
(4.5V to 5.5V)
10 MHz
Unit
Description
Parameter Parameter
(1.8V to 5.5V)
Min
Max
Min
Max
fSCK
tCL
fSCK
tLOWH
tWL
tCS
tCSS
tCSH
tSU
tH
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
CS High Time
20
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
20
20
30
25
25
5
40
40
50
50
50
10
10
10
10
tCH
tCE
tCES
tCEH
tSD
CS Setup Time
CS Hold Time
Data In Setup Time
Data In Hold Time
HOLD Hold Time
HOLD Setup Time
Output Valid
tHD
5
tH.HLD
tS.HLD
tCO
tHZ
tHD
tCD
tV
5
5
20
40
25
40
80
50
tHZ
tLZ
HOLD to Output High Z
HOLD to Output Low Z
Output Hold Time
Output Disable Time
Write Cycle Time
Rise Time
tLZ
tOH
tHZCE
tWC
tr
tHO
tDIS
tWC
tr
0
0
40
5
80
5
4.8
4.8
10
10
tf
tf
Fall Time
Figure 12. Synchronous Data Timing (Mode 0)
tCE
CS
tCEH
tCES
tCL
tCH
SCK
SI
tSD
tHD
tOH
tCO
tHZC
SO
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CY25C01/02/04/08/16
Figure 13.
Timing
HOLD
CS
tS.HLD
tS.HLD
SCK
tH.HLD
tH.HLD
HOLD
SO
tHZ
tLZ
Part Numbering Nomenclature
CY25 C 01 - SX
I T
Option:
T = Tape & Reel
Blank = Std.
Temperature:
I = Industrial (–40 to 85°C)
X = Pb-Free
Package:
S = SOIC
Z = TSSOP
Density:
01 = 1 Kb
02 = 2 Kb
04 = 4 Kb
08 = 8 Kb
16 = 16 Kb
Voltage:
C = 1.8V - 5.5V
25 = SPI Interface
Cypress
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CY25C01/02/04/08/16
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
1 Kbit
CY25C01-SXI
CY25C01-SXIT
CY25C01-ZXI
CY25C01-ZXIT
CY25C02-SXI
CY25C02-SXIT
CY25C02-ZXI
CY25C02-ZXIT
CY25C04-SXI
CY25C04-SXIT
CY25C04-ZXI
CY25C04-ZXIT
CY25C08-SXI
CY25C08-SXIT
CY25C08-ZXI
CY25C08-ZXIT
CY25C16-SXI
CY25C16-SXIT
CY25C16-ZXI
CY25C16-ZXIT
51-85066 8-Pin SOIC
Industrial
Industrial
Industrial
Industrial
Industrial
8-Pin SOIC (Tape & Reel)
51-85093 8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
51-85066 8-Pin SOIC
8-Pin SOIC (Tape & Reel)
51-85093 8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
51-85066 8-Pin SOIC
8-Pin SOIC (Tape & Reel)
51-85093 8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
51-85066 8-Pin SOIC
8-Pin SOIC (Tape & Reel)
51-85093 8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
51-85066 8-Pin SOIC
8-Pin SOIC (Tape & Reel)
51-85093 8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
2 Kbit
4 Kbit
8 Kbit
16 Kbit
This table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-15633 Rev. *C
Page 13 of 17
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CY25C01/02/04/08/16
Package Diagrams
Figure 14. 8-Pin (150-Mil) SOIC, 51-85066
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
0.150[3.810]
0.157[3.987]
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document #: 001-15633 Rev. *C
Page 14 of 17
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CY25C01/02/04/08/16
Package Diagrams (continued)
Figure 15. 8-Pin (4.4 mm) TSSOP, 51-85093
51-85093-*A
Document #: 001-15633 Rev. *C
Page 15 of 17
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CY25C01/02/04/08/16
Document History Page
Document Title: CY25C01/02/04/08/16, 1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, and 16 Kbit (x8) SPI Serial EEPROM
Document Number: 001-15633
Rev. ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
1069220
2522135
UHA
See ECN New Data Sheet
*A
GVCH/
PYRS
06/27/08 32 byte Page Mode in Features
Added Pb-Free and RoHS compliant information in “Features”
Removed PDIP package
Removed Automotive Temperature range
Updated Status Register Bit Definition Table 3.
Added description on write status Register(WRSR)
Added WPEN Operation Table 5.
Changed Supply voltage on VCC relative to GND max value from 5.0V to 6.0V
Corrected Typo of Vcc max value from 5.0V to 5.5V
Table 10: Added Thermal Resistance values for 8-TSSOP package
Table 12: Changed tr and tf values from 9.75 ns to 10 ns
Added AC test load values for different parameters
Updated Part Numbering Nomenclature and Ordering Information
*B
*C
2611873
VKN/
PYRS
11/24/08 Changed Part # from CY25D01/02/04 to CY25C01/02/04
Added 8 Kbit and 16 Kbit parts and their related information
Added footnote 1 related to WPEN
Added 20 MHz clock rate specifications
Updated part numbering nomenclature
Updated ordering information table
2656511 VKN/PYRS
02/09/09 Converted from preliminary to final
Added figures 2 and 3
Included VIL spec of 0.8V for the VCC range between 2.7V to 5.5V
Updated VIH test conditions
Added footnote #4
Updated VOL and VOH test conditions
On page 10, specified VCC range for AC test load conditions
Changed CL from 100pF to 30pF for 10MHz
On page 10, corrected AC measurement reference points from VIT and VOT to VLT
and VHT respectively
Changed VLT level from 0.3VCC to VCC/2 - 0.1V
Changed VHT level from 0.7VCC to VCC/2 + 0.1V
Document #: 001-15633 Rev. *C
Page 16 of 17
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CY25C01/02/04/08/16
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15633 Rev. *C
Revised February 05, 2009
Page 17 of 17
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