CY25702FXC [CYPRESS]
Clock Generator, 125MHz, CMOS, PDSO4, 5 X 2.80 MM, LEAD FREE, PLASTIC, SMD, 4 PIN;
| 型号： | CY25702FXC |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 125MHz, CMOS, PDSO4, 5 X 2.80 MM, LEAD FREE, PLASTIC, SMD, 4 PIN 振荡器 晶体振荡器 石英晶振 |
| 文件： | 总6页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25702
Programmable High-Frequency Crystal Oscillator (XO)
Features
Benefits
• Programmable High-frequency Crystal Oscillator (XO)
• Wide operating output clock frequency range of 1–166 MHz
• Integrated phase-locked loop (PLL)
• Internal PLL to generate up to 166 MHz output
• Suitable for most PC, consumer, and networking
applications
• Application compatibility in standard and low-power
systems
• 85 ps typical cycle-to-cycle Jitter with CLK = 133 MHz
• 3.3V operation
• CY25701 can be used as a direct replacement without any
PCBmodificationifspreadspectrumclock(SSC)isrequired
for EMI reduction.
• Output Enable and Power-down functions
• Package available in 4-Pin Ceramic LCC SMD
• Pb-free package
• In-house programming of samples and prototype quantities
is available using CY3672 programming kit and CY3724
socket adapters. Production quantities are available
through Cypress’s value-added distribution partners or by
usingthird-partyprogrammersfromBPMicrosystems, HiLo
Systems, and others.
• Industrial Temperature from –40°C to 85°C
• For SSCG functionality refer to CY25701 data sheet
Pin Configuration
Logic Block Diagram
CY25702
RFB
4-pin Ceramic SMD
PLL
4
3
VDD
CLK
CXIN
OUTPUT
DIVIDERS
and
PROGRAMMABLE
CONFIGURATION
OE/PD#
1
VSS
2
3
CLK
MUX
CXOUT
1
OE/PD#
4
2
VDD
VSS
Cypress Semiconductor Corporation
Document #: 38-07721 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 07, 2006
CY25702
Pin Definition
Pin
Name
Description
1
OE/PD#
Output Enable pin: Active HIGH. If OE = 1, CLK is enabled.
Power Down pin: Active LOW. If PD# = 0, Power Down is enabled.
2
3
4
VSS
CLK
VDD
Power supply ground.
Clock output.
3.3V power supply.
Table 1. Programming Data Requirement
Pin Function
Pin Name
Pin#
Output Frequency
Output Enable/Power Down
CLK
OE/PD#
3
1
Units
MHz
N/A
Program Value
ENTER DATA
ENTER DATA
Output Frequency, CLK Output (CLK, pin 3)
Functional Description
The frequency at the CLK output is produced by synthesizing
the embedded crystal oscillator frequency input. The range of
the synthesized clock is from 1 MHz to 166 MHz.
The CY25702 is a programmable high-frequency Crystal
Oscillator (XO) that uses a Cypress proprietary PLL to
synthesize the frequency of the embedded input crystal.
Output Enable or Power Down (OE/PD#, pin 1)
The CY25702 uses a programmable configuration memory
array to synthesize output frequency. The frequency CLK
output can be programmed from 1 MHz to 166 MHz.
Pin 1 can be programmed as either output enable (OE) or
Power Down (PD#).
The CY25702 is available in a 4-pin ceramic SMD package
with an operating temperature range of –40 to 85°C.
Absolute Maximum Rating
Supply Voltage (VDD)......................................–0.5V to +7.0V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Storage Temperature (Non-condensing) ...... –55°C to 100°C
Junction Temperature.................................. –40°C to 125°C
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Programming Description
Field/Factory-Programmable CY25702
Field/Factory programming is available for samples and
manufacturing by Cypress and its distributors. All requests
must be submitted to the local Cypress Field Application
Engineer (FAE) or sales representative. Once the request has
been processed, you will receive a new part number, samples,
and data sheet with the programmed values. This part number
will be used for additional sample requests and production
orders.
Additional information on the CY25702 can be obtained from
the Cypress web site at www.cypress.com.
Operating Conditions
Parameter
Description
Min.
3.00
–20
–40
–
Typ.
Max. Unit
V
Supply Voltage
3.30
3.60
70
V
DD
T
Ambient Temperature (Commercial)
Ambient Temperature (Industrial)
Max. Load Capacitance @ pin 3
–
–
–
–
–
°C
°C
pF
A
T
85
A
C
15
LOAD
CLK
PU
F
T
CLK output frequency, C
= 15 pF
1
166 MHz
500 ms
LOAD
Power-up time for VDD to reach minimum specified voltage (power ramp must be 0.05
monotonic)
Document #: 38-07721 Rev. *C
Page 2 of 6
CY25702
DC Electrical Characteristics
Parameter
Description
Output High Current (pin 3)
Output Low Current (pin 3)
Input High Voltage (pin 1)
Input Low Voltage (pin 1)
Input High Current (pin 1)
Input Low Current (pin 1)
Output Leakage Current (pin 3)
Input Capacitance (pin 1)
Supply Current
Condition
= V – 0.5, V = 3.3V (source)
Min.
10
Typ.
12
12
–
Max. Unit
I
I
V
V
–
–
mA
mA
V
OH
OL
OH
OL
DD
DD
= 0.5, V = 3.3V (sink)
10
DD
V
V
I
CMOS levels, 70% of V
CMOS levels, 30% of V
V = V
0.7V
V
DD
IH
DD
DD
DD
–
–
–
0.3V
DD
V
IL
–
10
10
10
7
μA
μA
μA
pF
mA
IH
in
DD
SS
I
I
V = V
–
–
IL
OZ
in
Three-state output, OE = 0
Pin 1, or OE
–10
–
–
[1]
C
5
IN
I
V
C
= 3.3V, CLK = 1 to 166 MHz,
DD
–
–
50
VDD
= 0, OE = V
DD
LOAD
Δf/f
Initial Accuracy at Room Temp.
T = 25°C, 3.3V
–25
–25
–12
–5
–
–
–
–
25
25
12
5
ppm
ppm
ppm
ppm
A
Freq. Stability over Temp. Range T = –20°C to 70°C, 3.3V
A
Freq. Stability over Voltage Range 3.0 to 3.6V
Aging
T = 25°C, First year
A
AC Electrical Characteristics[1]
Parameter
Description
Output Duty Cycle
Condition
CLK, Measured at V /2
Min.
45
–
Typ.
50
–
Max. Unit
DC
55
%
ns
ns
ps
ps
ps
ns
DD
t
t
Output Rise Time
20%–80% of V
20%–80% of V
C =15 pF
2.7
R
F
DD,
DD,
L
Output Fall Time
C =15 pF
–
–
2.7
L
[2]
T
Cycle-to-Cycle Jitter CLK (Pin 3)
CLK > 133 MHz, Measured at V /2
–
85
215
–
200
400
500
350
CCJ1
DD
25 MHz < CLK < 133 MHz, Measured at V /2
–
DD
CLK < 25 MHz, Measured at V /2
–
DD
T
T
T
Output Disable Time (pin1 = OE)
Output Enable Time (pin1 = OE)
PLL Lock Time
Time from falling edge on OE to stopped
outputs (Asynchronous)
–
150
OE1
Time from rising edge on OE to outputs at a
valid frequency (Asynchronous)
–
–
150
–
350
10
ns
OE2
Time for CLK to reach valid frequency
ms
LOCK
Note
1. Guaranteed by characterization, not 100% tested.
2. Jitter is configuration dependent. Actual jitter is dependent on output frequencies, spread percentage, temperature, and output load. For more information, refer
to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html, or contact your
local Cypress Field Application Engineer.
Document #: 38-07721 Rev. *C
Page 3 of 6
CY25702
Application Circuit
Figure 1. Application Circuit Diagram
0.1 µ F
P ow er
3
4
C LK
V D D
C Y 25702
V S S
2
O E /P D #
1
V D D
Switching Waveforms
Figure 2. Duty Cycle Waveform
Cycle Timing (DC = t1A/t1B
)
t
1B
t
1A
CLK
Figure 3. Output Rise/Fall Time Waveform
VDD
0V
CLK
Tr
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Figure 4. Output Enable/Disable Timing Waveforms
VDD
VIH
OUTPUT
TOE2
ENABLE
VIL
0V
High Impedance
CLK
(Asynchronous)
TOE1
Document #: 38-07721 Rev. *C
Page 4 of 6
CY25702
Ordering Information
Part Number
Lead-free (Pb-free)
CY25702FLXCT[3]
CY25702FLXIT[3]
CY25702LXCZZZT[4]
CY25702LXIZZZT[4]
Package Description
Product Flow
4-Lead Ceramic LCC SMD -Tape and Reel
4-Lead Ceramic LCC SMD -Tape and Reel
4-Lead Ceramic LCC SMD -Tape and Reel
4-Lead Ceramic LCC SMD -Tape and Reel
Commercial, –20° to 70°C
Industrial, –40° to 85°C
Commercial, –20° to 70°C
Industrial, –40° to 85°C
Actual Marking[5]
CY25702FLX*
CY25702LX*
F=Field
Programmable
Marketing Part Number (CY25702)
Marketing Part Number (CY25702)
L = LCC
C Y
2
z
5
z
7
z
0 2 L
Y W W
C Y 2 5 7 0 2 F
X
*
X
*
Y W W
L
zzz = Programmable Dash Code YWW = Date Code (Year & WW)
Temp
YWW = Date Code (Year & WW)
Pin 1 mark
X = Pb free
Temp
Pin 1 mark
L = LCC X = Pb free
Package Drawings and Dimensions
Figure 5. 4-Lead (5.0x3.2 mm) Ceramic LCC LZ04A
Dimensions in MM
General Tolerance: 0.15MM
Kyocera dwg ref KD-VA5G08
Package Weight ~ 0.12 grams
SIDE VIEW
5.0
1.20
0.80
#3
#2
#4
#1
2.50
TOP VIEW
BOTTOM VIEW
001-02743-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Notes
3. “FLX” suffix is used for products programmed in field by Cypress Distributors.
4. “ZZZ” denotes the assigned product dash number. This number will be assigned by factory after the output frequency programming data is received from the
customer.
5. Temp can be C (Commercial) or I (Industrial).
Document #: 38-07721 Rev. *C
Page 5 of 6
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY25702
Document History Page
Document Title: CY25702 Programmable High-Frequency Crystal Oscillator (XO)
Document Number: 38-07721
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
296081
333298
See ECN
See ECN
RGL
New data sheet
*A
RGL
Added Jitter Specifications
Corrected the Ordering Information table to match the DevMaster
Removed CY25702FXC and CY25702XCZZZ
Complete data sheet rewrite
*B
*C
390406
595857
See ECN
See ECN
RGL
RGL
Document #: 38-07721 Rev. *C
Page 6 of 6
相关型号：
CY25702FXCT
Clock Generator, 125MHz, CMOS, PDSO4, 5 X 2.80 MM, LEAD FREE, PLASTIC, SMD, 4 PIN
CYPRESS
CY25702XCZZZT
Clock Generator, 125MHz, CMOS, PDSO4, 5 X 2.80 MM, LEAD FREE, PLASTIC, SMD, 4 PIN
CYPRESS
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