CY25702FXT [CYPRESS]
Programmable High-Frequency Crystal Oscillator (XO); 可编程高频晶体振荡器（ XO ）
| 型号： | CY25702FXT |
| 厂家： | 
CYPRESS |
| 描述： | Programmable High-Frequency Crystal Oscillator (XO) |
| 文件： | 总7页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25702
Programmable High-Frequency Crystal Oscillator (XO)
Features
Benefits
• Programmable High-frequency Crystal Oscillator (XO)
• Wide output (CLK) range from:
— 1.0 to 125 MHz (VDD = 5.0V)
— 1.0 to 90 MHz (VDD = 3.3V)
• Integrated phase-locked loop (PLL)
• Low cycle-to-cycle Jitter
• 3.3/5.0V operation
• Output Enable function
• Power-down function
• Refer to CY25701 for SSCG function
• Lead-free package
• Eliminates the need for external crystal oscillator.
• Internal PLL to generate up to 125-MHz output.
• Suitable for most PC, consumer and networking
applications.
• Application compatibility in standard and low-power
systems.
• CY25701 can be used as a direct replacement in 3.3V
applications if Spread Spectrum Clock (SSC) is
required for EMI reduction without any PCB
modification.
• In-house programming of samples and prototype
quantities is available using the CY3672 programming
kit and CY36xx socket adapter. Sample and production
quantitiesareavailablethroughCypress’svalue-added
distribution partners.
Pin Configuration
Logic Block Diagram
CY25702
4-pin Plastic SMD
RFB
PLL
1
2
OE/PD#
VSS
VDD
CLK
4
3
CXIN
OUTPUT
DIVIDERS
and
PROGRAMMABLE
CONFIGURATION
3
CLK
MUX
CXOUT
1
OE/PD#
4
2
VDD
VSS
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07721 Rev. **
Revised December 09, 2004
CY25702
Pin Definition
Pin
Name
Description
1
OE/PD#
Output Enable pin: Active HIGH. If OE = 1, CLK is enabled.
Power Down pin: Active LOW. If PD# = 0, Power Down is enabled.
Power supply ground.
2
3
4
VSS
CLK
VDD
Clock output.
3.3V or 5.0V power supply.
The CY25702 uses a programmable configuration memory
array to synthesize output frequency.
Functional Description
The CY25702 is a Crystal Oscillator (XO).
The frequency CLK output can be programmed from 10–125
The device uses a Cypress proprietary PLL to synthesize the
MHz.
frequency of the embedded input crystal.
The CY25702 is available in a 4-pin plastic SMD packages
with operating temperature range of –20 to 70°C.
Table 1. Programming Data Requirement
Pin Function
Pin Name
Pin#
Output Frequency
Output Enable/Power Down
Power Supply
CLK
3
OE/PD#
VDD
4
1
Units
MHz
N/A
V
Program Value
ENTER DATA
ENTER DATA
ENTER DATA
synthesized clock is from 1–125MHz when VDD= 5V and
1–90MHz when VDD = 3.3V.
Programming Description
Field/Factory-Programmable CY25702
Output Enable or Power Down (OE/PD#, pin 1)
Field/Factory programming is available for samples and
manufacturing by Cypress and its distributors. All requests
must be submitted to the local Cypress Field Application
Engineer (FAE) or sales representative. Once the request has
been processed, you will receive a new part number, samples,
and data sheet with the programmed values. This part number
will be used for additional sample requests and production
orders.
Pin 1 can be programmed as either output enable (OE) or
Power Down (PD#).
Absolute Maximum Rating
Supply Voltage (VDD).....................................–0.5V to +7.0V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Storage Temperature (Non-condensing) .... –55°C to +100°C
Junction Temperature................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Additional information on the CY25702 can be obtained from
the Cypress web site at www.cypress.com.
Output Frequency, CLK Output (CLK, pin 3)
The frequency at the CLK output is produced by synthesizing
the embedded crystal oscillator frequency input. The range of
Operating Conditions
Parameter
VDD1
Description
Supply Voltage Range
Supply Voltage Range
Ambient Temperature
Max. Load Capacitance @ pin 3
CLK output frequency, CLOAD = 15 pF, VDD = 5.0V
CLK output frequency, CLOAD = 15 pF, , VDD = 3.3V
Min.
3.00
4.50
–20
–
1.0
1.0
0.05
Typ.
3.30
5.00
–
–
–
Max.
3.60
5.50
70
15
125
90
Unit
V
V
°C
pF
MHz
MHz
ms
VDD2
TA
CLOAD
FCLK1
FCLK2
TPU
–
–
Power-up time for VDD to reach minimum specified
500
voltage (power ramp must be monotonic)
DC Electrical Characteristics
Parameter
VOH1
VOL1
Description
High Output Voltage
Low Output Voltage
Condition
VDD = 5.0V, IOH = –16mA
VDD= 5.0V , IOL= 16mA
Min.
VDD-0.4
Typ.
–
–
Max. Unit
–
V
–
0.4
V
Document #: 38-07721 Rev. **
Page 2 of 7
CY25702
DC Electrical Characteristics
Parameter
VOH2
VOL2
VIH1
VIL1
VIH2
VIL2
IIH
IIL
IOZ
CIN
IVDD1
Description
High Output Voltage
Low Output Voltage
Condition
VDD = 3.3V , IOH = –8mA
Min.
VDD-0.4
–
2.0
Typ.
–
–
–
–
–
–
–
–
Max. Unit
–
0.4
–
V
V
V
VDD= 3.3V , IOL = 8mA
VDD = 5.0V
VDD = 5.0V
VDD = 3.3V
VDD = 3.3V
Vin = VDD
Input High Voltage (pin 1)
Input Low Voltage (pin 1)
Input High Voltage (pin 1)
Input Low Voltage (pin 1)
Input High Current (pin 1)
Input Low Current (pin 1)
Output Leakage Current (pin 3) Three-state output, OE = 0
Input Capacitance (pin 1)
Supply Current
–
0.8
–
V
V
0.7VDD
–
–
–
–10
–
–
0.2VDD
10
10
10
7
V
µA
µA
µA
pF
mA
Vin = VSS
–
5
–
Pin 1, OE or PD#
VDD = 3.3V, CLK = 1 to 90 MHz,
28
CLOAD = 0, OE = VDD
IVDD2
IVDD3
IVDD4
Supply Current
Supply Current
Supply Current
VDD = 3.3V, CLK = 1 to 90 MHz,
CLOAD = 0, OE = GND
–
–
–
–
–
–
16
45
30
mA
mA
mA
VDD = 5.0V, CLK = 1 to 125 MHz,
CLOAD = 0, OE = VDD
VDD = 5.0V, CLK = 1 to 125 MHz,
CLOAD = 0, OE = GND
IPD#
FS
AG
SR
Power Down Current
Frequency Stability
Aging
PD# = GND
–20 to +70°C
Ta = 25°C, First Year
Three drops on a hard board from 750 mm or
excitation test with 29.400m/s2 x 0.3ms x 1/2
sinewave in three directions
–
–50
–5
–
–
–
–
50
50
5
µA
ppm
ppm
ppm
Shock Resistance
–20
20
AC Electrical Characteristics
Parameter
DC
tR
tF
Description
Output Duty Cycle
Output Rise Time
Output Fall Time
Condition
CLK, Measured at VDD/2
20%–80% of VDD, CL = 15 pF
20%–80% of VDD, CL = 15 pF
Min.
40
–
–
–
Typ. Max. Unit
50
60
4.0
4.0
350
%
ns
ns
ns
–
–
TOE1
Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped
150
outputs (Asynchronous)
TOE2
Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a
valid frequency (Asynchronous)
–
150
350
ns
TLOCK
TSU
TPDD
PLL Lock Time
Start-up time out of Power Down PD# pin Low to High
Power Down Delay Time PD# pin Low to CLK Low (Asynchronous)
Time for CLK to reach valid frequency
–
–
–
–
–
–
10
5
25
ms
ms
ns
Application Circuit
Power
4
3
VDD
OE/PD#
VDD
CLK
1
2
(GND if PD#)
0.1uF
CY25702
VSS
Document #: 38-07721 Rev. **
Page 3 of 7
CY25702
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B
)
t
1B
t
1A
CLK
Output Rise/Fall Time
VDD
0V
CLK
Tr
Tf
Output Rise time (Tr) = 20 to 80% of V
DD
Output Fall time (Tf) = 80 to 20% of V
DD
Output Enable/Disable Timing
VDD
VIH
OUTPUT
ENABLE
TOE2
VIL
0V
High Impedance
CLK
TOE1
Document #: 38-07721 Rev. **
Page 4 of 7
CY25702
Ordering Information
Part Number[1,2]
CY25702JXCZZZZ
CY25702JXCZZZZT
CY25702FJXC
CY25702FJXCT
CY25702XZZZ
CY25702XZZZT
CY25702FX
CY25702FXT
Package description
4-Lead Plastic JE04A SMD – Lead-free
4-Lead Plastic JE04A SMD, Tape and Reel – Lead-free
4-Lead Plastic JE04A SMD – Lead-free
4-Lead Plastic JE04A SMD, Tape and Reel – Lead-free
4-Lead Plastic JE04B SMD – Lead-free
4-Lead Plastic JE04B SMD, Tape and Reel – Lead-free
4-Lead Plastic JE04B SMD – Lead-free
Product Flow
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
4-Lead Plastic JE04B SMD, Tape and Reel – Lead-free
Package Drawings and Dimensions
4-Lead JEC JE04A
10.2 0.ꢀ
(10.5 MAX)
4
1.0 0.2
(1.0)
ꢀ.6
5.0
5.6 0.2
(5.8 MAX)
1.0 0.2
(1.0)
1
1.ꢀ
2.1
+0.2
-0.1
2.5
2.4
(2.7 MAX)
4.6
0.1
0.15 0.1
0.51
(0.05 MIN)
5.08 0.1
DIMENSIONS IN MILLIMETERS
REFERENCE JEDEC: N/A
PKG. WEIGHT: 0.24 gms
5.08
RECOMMENDED SOLDERING PATTERN
51-85204-*A
Notes:
1. “ZZZZ” or “ZZZ” denotes the assigned product dash number. This number will be assigned by factory after the output frequency and spread percent programming
data is received from the customer.
2. “FJXC” or “FX” suffix is used for products programmed in field by Cypress distributors.
Document #: 38-07721 Rev. **
Page 5 of 7
CY25702
Package Drawings and Dimensions (continued)
4-Lead JE (5.0 x 2.8 MM) JE04B
5.0 0.ꢀ
4
0.35 MIN.
ꢀ.5 0.ꢀ
ꢀ.8
3.ꢀ 0.ꢀ
0.35 MIN.
ꢁ
0.5
ꢁ.0
ꢁ.6
ꢁ.ꢁ 0.ꢁ
ꢁ.ꢀ MAX.
ꢁ.5
0.ꢁ
0.05 0.05
(0 MIN.)
ꢀ.54 0.ꢁ
ꢀ.ꢀ
DIMENSIONS IN MILLIMETERS
REFERENCE JEDEC: N/A
PKG. WEIGHT: 0.034 gms
ꢀ.54
RECOMMENDED SOLDERING PATTERN
51-85212-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07721 Rev. **
Page 6 of 7
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY25702
Document History Page
Document Title: CY25702 Programmable High-Frequency Crystal Oscillator (XO)
Document Number: 38-07721
Orig. of
REV.
ECN NO. Issue Date Change
Description of Change
**
296081
See ECN
RGL
New data sheet
Document #: 38-07721 Rev. **
Page 7 of 7
相关型号：
CY25702XCZZZT
Clock Generator, 125MHz, CMOS, PDSO4, 5 X 2.80 MM, LEAD FREE, PLASTIC, SMD, 4 PIN
CYPRESS
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