CY22E016L-SZ25I [CYPRESS]
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| 型号： | CY22E016L-SZ25I |
| 厂家： | 
CYPRESS |
| 描述： | 暂无描述 存储 内存集成电路 静态存储器 光电二极管 |
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CY22E016L
16 Kbit (2K x 8) nvSRAM
Features
Functional Description
■ 25 ns, 35 ns and 45 ns access times
The Cypress CY22E016L is a fast static RAM with a
non-volatile element incorporated in each static memory cell.
The SRAM is read and written an infinite number of times,
while independent, non-volatile data resides in non-volatile
elements. Data transfers from the SRAM to the non-volatile
elements (the STORE operation) takes place automatically on
power down. A 68 μF or larger capacitor tied from VCAP to
ground guarantees the STORE operation, regardless of power
down slew rate or loss of power from “hot swapping.” Transfers
from the non-volatile elements to the SRAM (the RECALL
operation) take place automatically on restoration of power. A
hardware STORE is initiated with the HSB pin.
■ Hands off automatic STORE on power down with external
68 μF capacitor
■ STORE to QuantumTrap™ non-volatile elements is initiated
by hardware or AutoStore on power down
■ RECALL to SRAM is initiated on power up
■ Infinite READ, WRITE, and RECALL cycles
■ 10 mA typical ICC at 200 ns cycle time
■ 1,000,000 STORE cycles to QuantumTrap
■ 100 year data retention to QuantumTrap
■ Single 5V operation +10%
■ Commercial and industrial temperature
■ SOIC package
■ RoHS compliance
Logic Block Diagram
V
V
CC
CAP
Quantum Trap
32 X 512
POWER
A5
STORE
CONTROL
A6
RECALL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
32 X 512
A7
A8
HSB
A9
DQ0
COLUMN I/O
DQ1
DQ2
DQ3
COLUMN DEC
DQ4
DQ5
DQ6
DQ7
A0
A4
A10
A1
A3
A2
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06727 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 1, 2007
[+] Feedback
CY22E016L
Pin Configurations
1
28
VCC
WE
VCAP
2
3
NC
A7
A6
27
26
HSB
A8
4
5
25
24
A5
A4
A3
A9
6
7
NC
23
22
21
20
19
18
17
16
28-SOIC
OE
A10
Top View
A2
8
(Not To Scale)
A1
A0
9
CE
10
11
12
13
DQ7
DQ6
DQ5
DQ4
DQ0
DQ1
DQ2
VSS
14
15
DQ3
Pin Definitions
Pin Name
IO Type
Description
A0–A10
Input
Address Inputs. Used to select one of the 2,048 bytes of the nvSRAM.
DQ0-DQ7 Input/Output Bidirectional Data IO lines. Used as input or output lines depending on operation.
Input
Write Enable Input, Active LOW. When selected LOW, this writes data on the IO pins to the address
location latched by the falling edge of CE.
WE
Input
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS
VCC
Ground
Ground for the Device. Is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Input/Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a non-volatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional).
HSB
VCAP
NC
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
non-volatile elements.
No Connect No Connects. This pin is not connected to the die.
Document Number: 001-06727 Rev. *D
Page 2 of 14
[+] Feedback
CY22E016L
on the stored system charge as power goes down. The user
must, however, guarantee that VCC does not drop below 3.6V
during the 10 ms STORE cycle..
Device Operation
The CY22E016L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a non-volatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the non-volatile cell (the STORE
operation) or from the non-volatile cell to SRAM (the RECALL
operation). This unique architecture enables storage and recall
of all cells in parallel. During the STORE and RECALL opera-
tions, SRAM READ and WRITE operations are inhibited. The
CY22E016L supports infinite reads and writes similar to a typical
SRAM. In addition, it provides infinite RECALL operations from
the non-volatile cells and up to one million STORE operations.
Figure 1. AutoStore Mode
1
28
27
26
SRAM Read
The CY22E016L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A0–10 determines which of the 2,048 data bytes are
accessed. When the READ is initiated by an address transition,
the outputs are valid after a delay of tAA (READ cycle 1). If the
READ is initiated by CE or OE, the outputs are valid at tACE or at
tDOE, whichever is later (READ cycle 2). The data outputs
repeatedly respond to address changes within the tAA access
time without the need for transitions on any control input pins,
and remains valid until another address change or until CE or OE
is brought HIGH, or WE or HSB is brought LOW.
14
15
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs are stable prior to entering the
WRITE cycle and must remain stable until either CE or WE goes
HIGH at the end of the cycle. The data on the common IO pins
IO0–7 is written into the memory if it is valid tSD, before the end
of a WE controlled WRITE or before the end of an CE controlled
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
Figure 2. System Power Mode
1
28
27
26
AutoStore Operation
During normal AutoStore operation, the CY22E016L draws
current from VCC to charge a capacitor connected to the VCAP
pin. This stored charge is used by the chip to perform a single
STORE operation. After power up, when the voltage on the VCAP
pin drops below VSWITCH, the part automatically disconnects the
VCAP pin from VCC and initiates a STORE operation.
Figure 1 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. A charge storage capacitor,
having a capacity of between 68 μF and 220 μF (±20%) rated at
6V, is provided. In system power mode, both VCC and VCAP are
connected to the +5V power supply without the 68 μF capacitor.
In this mode, the AutoStore function of the CY22E016L operates
14
15
Document Number: 001-06727 Rev. *D
Page 3 of 14
[+] Feedback
CY22E016L
If an automatic STORE on power loss is not required, then VCC
is tied to ground and +5V is applied to VCAP. This is the AutoStore
Inhibit mode where the AutoStore function is disabled. If the
CY22E016L is operated in this configuration, references to VCC
are changed to VCAP throughout this datasheet. In this mode,
STORE operations are triggered with the HSB pin. It is not
permissible to change between these three options at will.
pin is connected together to the HSB pins from the other
CY22E016L. An external pull up resistor to +5V is required, since
HSB acts as an open drain pull down. The VCAP pins from the
other CY22E016L parts are tied together and share a single
capacitor. The capacitor size is scaled by the number of devices
connected to it. When any one of the CY22E016L detects a
power loss and asserts HSB, the common HSB pin causes all
parts to request a STORE cycle. (A STORE takes place in those
CY22E016L that are written since the last non-volatile cycle.)
To prevent unneeded STORE operations, automatic STOREs
and those initiated by externally driving HSB LOW are ignored,
unless at least one WRITE operation takes place since the most
recent STORE or RECALL cycle. An optional pull up resistor is
shown connected to HSB. This is used to signal the system that
the AutoStore cycle is in progress.
During any STORE operation, regardless of how it is initiated,
the CY22E016L continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the CY22E016L remains disabled until the
HSB pin returns HIGH.
Figure 3. AutoStore Inhibit Mode
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC
<
VSWITCH), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
1
28
27
26
Data Protection
The CY22E016L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC is less than VSWITCH. If the CY22E016L is in a WRITE
mode (both CE and WE are LOW) at power up after a RECALL
or after a STORE, the WRITE is inhibited until a negative
transition on CE or WE is detected. This protects against
inadvertent writes during power up or brown out conditions.
Noise Considerations
The CY22E016L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduces circuit noise.
14
15
Hardware STORE (HSB) Operation
The CY22E016L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
low, the CY22E016L conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle begins if a WRITE to the
SRAM took place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is internally driven
low to indicate a busy condition, while the STORE (initiated by
any means) is in progress.
Low Average Active Power
CMOS technology provides the CY22E016L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 4 shows the relationship between ICC and
READ/WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY22E016L depends on the
following items:
SRAM READ and WRITE operations that are in progress when
HSB is driven low by any means are given time to complete
before the STORE operation is initiated. After HSB goes low, the
CY22E016L continues SRAM operations for tDELAY. During
1. The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. CMOS vs. TTL input levels
5. The operating temperature
6. The VCC level
t
DELAY, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it is allowed a time,
DELAY, to complete. However, any SRAM WRITE cycles
t
requested after HSB goes LOW are inhibited until HSB returns
HIGH.
The HSB pin is used to synchronize multiple CY22E016L while
using a single larger capacitor. To operate in this mode, the HSB
7. IO loading
Document Number: 001-06727 Rev. *D
Page 4 of 14
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CY22E016L
Preventing STOREs
The STORE function is disabled by holding HSB HIGH with a
driver capable of sourcing 30 mA at a VOH of at least 2.2V,
because it has to overpower the internal pull down device. The
device drives HSB low for 20 ns at the onset of a STORE. When
the CY22E016L is connected for AutoStore operation (system
V
CC connected to VCC and a 68 μF capacitor on VCAP) and VCC
crosses VSWITCH on the way down, the CY22E016L attempts to
pull HSB LOW; if HSB does not actually get below VIL, the part
stops trying to pull HSB low and abort the STORE attempt.
Table 1. Hardware Mode Selection
CE
H
L
WE
X
HSB
H
A10–A0
Mode
IO
Power
Standby
Active
Active
ICC2
X
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
H
H
L
L
H
X
X
L
Non-volatile
STORE
Output High Z
Figure 5. Current versus Cycle Time (WRITE)
Figure 4. Current versus Cycle Time (READ)
Document Number: 001-06727 Rev. *D
Page 5 of 14
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CY22E016L
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Surface Mount Lead Soldering
Temperature (3 Seconds).......................................... +260°C
Output Short Circuit Current [1].................................... 15 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V
Latch up Current.................................................... > 200 mA
Voltage Applied to Outputs
in High Z State.......................................–0.5V to VCC + 0.5V
Operating Range
Input Voltage.............................................–0.5V to Vcc+0.5V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Transient Voltage (greater than 20 ns) on
Any Pin to Ground Potential ..................–0.5V to VCC + 2.0V
4.5V to 5.5V
-40°C to +85°C
DC Electrical Characteristics
Over the Operating Range (VCC = 4.5V to 5.5V) [2]
Parameter
Description
Test Conditions
Min
Max
Unit
ICC1
Average VCC Current tRC = 25 ns
Commercial
85
75
65
mA
mA
mA
t
RC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads. IOUT = 0mA.
Industrial
75
mA
ICC2
ICC3
Average VCC Current All Inputs Do Not Care, VCC = Max
during STORE Average current for duration tSTORE
3
mA
Average VCC Current at WE > (VCC – 0.2). All other inputs cycling.
AVAV =200ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained
Typical without output loads.
10
mA
t
ICC4
ISB
Average VCAP Current All Inputs Do Not Care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
2
mA
mA
VCC Standby Current
CE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V). Standby
current level after non-volatile cycle is complete.
Inputs are static. f = 0 MHz.
2.5
IILK
Input Leakage Current VCC = Max, VSS < VIN < VCC
-1
-5
+1
+5
μA
μA
IOLK
Off State Output
Leakage Current
VCC = Max, VSS < VIN < VCC, CE or OE > VIH
VIH
VIL
Input HIGH Voltage
2.2
VSS – 0.5
2.4
VCC + 0.5
0.8
V
V
V
V
V
Input LOW Voltage
VOH
VOL
VBL
Output HIGH Voltage IOUT = –4 mA except HSB
Output LOW Voltage
Logic’0’ on HSB
IOUT = 8 mA except HSB
IOUT = 3 mA
0.4
0.4
Notes
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
2. Typical conditions for the Active Current shown on the front page of the datasheet are average values at 25°C (room temperature) and V = 5V. Not 100% tested.
CC
Document Number: 001-06727 Rev. *D
Page 6 of 14
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CY22E016L
Capacitance
These parameters are guaranteed but not tested.
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
8
Unit
pF
TA = 25°C, f = 1 MHz,
CC = 0 to 3.0 V
V
7
pF
Thermal Resistance
These parameters are guaranteed but not tested.
Parameter
Description
Test Conditions
28-SOIC
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and proce-
dures for measuring thermal impedance, per EIA / JESD51.
TBD
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
TBD
°C/W
AC Test Loads
For Tri-state
Specifications
R1 963Ω
R1 963
Ω
5.0V
5.0V
Output
Output
R2
R2
30 pF
5 pF
512Ω
512Ω
AC Test Conditions
Input Pulse Levels.................................................... 0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <5 ns
Input and Output Timing Reference Levels.....................1.5V
Document Number: 001-06727 Rev. *D
Page 7 of 14
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CY22E016L
AC Switching Characteristics
Parameter
25 ns Part
35 ns Part
45 ns Part
Description
Unit
Cypress
Alt.
Min
Max
Min
Max
Min
Max
Parameter Parameter
SRAM Read Cycle
tACE
tACS
tRC
tAA
Chip Enable Access Time
Read Cycle Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[4]
tRC
25
35
45
[5]
tAA
tDOE
Address Access Time
25
10
35
15
45
20
tOE
tOH
tLZ
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
[5]
tOHA
5
5
5
5
5
5
[6]
[6]
[6]
[6]
tLZCE
tHZCE
tLZOE
tHZOE
tHZ
10
10
25
13
13
35
15
15
45
tOLZ
tOHZ
tPA
0
0
0
0
0
0
[3]
tPU
[ 3]
tPD
tPS
SRAM Write Cycle
tWC
tWC
tWP
tCW
tDW
tDH
tAW
tAS
Write Cycle Time
25
20
20
10
0
35
25
25
12
0
45
30
30
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPWE
tSCE
tSD
Write Pulse Width
Chip Enable to End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
tHD
tAW
20
0
25
0
30
0
tSA
tHA
tWR
tWZ
tOW
0
0
0
[6,7]
[6]
tHZWE
tLZWE
10
13
14
5
5
5
AutoStore Power Up RECALL
CY22E016L
Parameter
Description
Unit
Min
Max
[8]
tHRECALL
Power up RECALL Duration
550
10
μs
ms
μs
V
[9]
tSTORE
STORE Cycle Duration
tDELAY
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
Low Voltage Reset Level
1
VSWITCH
VRESET
4.0
4.5
3.6
V
Notes
3. These parameters are guaranteed but not tested.
4. IWE must be HIGH during SRAM Read Cycles.
5. Device is continuously selected with CE and OE both Low.
6. Measured ±200 mV from steady state output voltage.
7. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
8.
t
starts from the time V rises above V
HRECALL CC SWITCH.
9. If an SRAM Write has not taken place since the last non-volatile cycle, no STORE will take place
Document Number: 001-06727 Rev. *D
Page 8 of 14
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CY22E016L
Hardware STORE Cycle
CY22E016L
Parameter
Description
Unit
Min
Max
[6]
tSTORE
STORE Cycle Duration
10
ms
ms
ns
[10]
tDELAY
tRESTORE
tHLHX
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
1
[11]
700
300
15
ns
tHLBL
Hardware STORE Low to STORE Busy
ns
Switching Waveforms
Figure 6. SRAM Read Cycle Number 1: Address Controlled [3, 5, 12]
tRC
ADDRESS
tAA
tOH
DQ (DATA OUT)
DATA VALID
Figure 7. SRAM Read Cycle Number 2: CE Controlled [3,12]
tRC
ADDRESS
CE
tACE
tPD
tHZCE
tLZCE
OE
tHZOE
tDOE
tLZOE
DQ (DATA OUT)
DATA VALID
ACTIVE
tPU
STANDBY
ICC
Notes
10. Read and Write cycles in progress before HSB are given this amount of time to complete.
11. t is only applicable after t is complete.
RESTORE
STORE
12. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-06727 Rev. *D
Page 9 of 14
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CY22E016L
Switching Waveforms (continued)
Figure 9. SRAM Write Cycle Number 1: WE Controlled [12,13]
tWC
ADDRESS
CE
tHA
tSCE
tAW
tSA
tPWE
WE
tHD
tSD
DATA VALID
DATA IN
tHZWE
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
Figure 8. SRAM Write Cycle Number 2: CE Controlled
tWC
ADDRESS
tHA
tSCE
tSA
CE
tAW
tPWE
WE
tSD
tHD
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Note
13.
CE or WE is less thanV during address transitions.
IH
Document Number: 001-06727 Rev. *D
Page 10 of 14
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CY22E016L
Switching Waveforms (continued)
Figure 10. AutoStore or Power Up RECALL
V
CC
V
SWITCH
V
RESET
AutoStore
POWER-UP RECALL
HSB
tRESTORE
tVSBL
tSTORE
tDELAY
DQ (DATA OUT)
BROWN OUT
AutoStoreTM
POWER UP
RECALL
BROWN OUT
NO STROKE
BROWN OUT
AutoStoreTM
(NO SRAM WRITES)
NO RECALL
NO RECALL
RECALL WHEN
(VCC DID NOT GO
(VCC DID NOT GO
V
CC RETURNS
BELOW VRESET
)
BELOW VRESET)
ABOVE VSWITCH
Figure 11. Hardware STORE Cycle
tHLHX
HSB (IN)
tSTORE
tHLBL
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
tDELAY
DATA VALID
DATA VALID
DQ (DATA OUT)
Document Number: 001-06727 Rev. *D
Page 11 of 14
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CY22E016L
Part Numbering Nomenclature
CY 22 E 016 L- SZ 25 X C T
Option:
T-Tape and Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (-40°C to 85°C)
Speed:
Pb-Free
25 - 25 ns
35 - 35 ns
45 - 45 ns
Package:
SZ - 28-SOIC
Data Bus:
L - x8
Density:
016 - 16 Kb
Voltage:
E - 5.0V
nvSRAM
22 - AutoStore + Hardware Store
Cypress
Document Number: 001-06727 Rev. *D
Page 12 of 14
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CY22E016L
Ordering Information
All the parts below are Pb-Free.
Speed
Package
Name
Operating
Range
Package Type
(ns)
Ordering Code
CY22E016L-SZ25XCT
CY22E016L-SZ25XC
CY22E016L-SZ25XIT
CY22E016L-SZ25XI
CY22E016L-SZ35XCT
CY22E016L-SZ35XC
CY22E016L-SZ35XIT
CY22E016L-SZ35XI
CY22E016L-SZ45XCT
CY22E016L-SZ45XC
CY22E016L-SZ45XIT
CY22E016L-SZ45XI
25
51-85026 28-pin SOIC
51-85026 28-pin SOIC
51-85026 28-pin SOIC
51-85026 28-pin SOIC
51-85026 28-pin SOIC
51-85026 28-pin SOIC
51-85026 28-pin SOIC
51-85026 28-pin SOIC
51-85026 28-pin SOIC
51-85026 28-pin SOIC
51-85026 28-pin SOIC
51-85026 28-pin SOIC
Commercial
25
35
35
45
45
Industrial
Commercial
Industrial
Commercial
Industrial
Package Diagrams
28-Pin(300 Mil) Molded SOIC
NOTE :
PIN 1 ID
1. JEDEC STD REF MO-119
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE
14
1
MIN.
3. DIMENSIONS IN INCHES
MAX.
0.291[7.39]
0.300[7.62]
4. PACKAGE WEIGHT 0.85gms
*
0.394[10.01]
0.419[10.64]
PART #
15
28
0.026[0.66]
0.032[0.81]
S28.3 STANDARD PKG.
SZ28.3 LEAD FREE PKG.
SEATING PLANE
0.697[17.70]
0.713[18.11]
0.092[2.33]
0.105[2.67]
*
0.004[0.10]
0.0091[0.23]
0.0125[3.17]
0.015[0.38]
0.050[1.27]
0.013[0.33]
0.019[0.48]
*
0.004[0.10]
0.050[1.27]
TYP.
0.0118[0.30]
51-85026-*D
Document Number: 001-06727 Rev. *D
Page 13 of 14
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CY22E016L
Document History Page
Document Title: CY22E016L 16 Kbit (2K x 8) nvSRAM
Document Number: 001-06727
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
427789
437321
472053
503290
See ECN
See ECN
See ECN
See ECN
TUP
TUP
TUP
PCI
New datasheet
Show datasheet on external Web
*A
*B
*C
Updated Part Numbering Nomenclature and Ordering Information
Converted from Advance to Preliminary
Changed the term “Unlimited” to “Infinite”
Removed Industrial Grade mention
Corrected VIL min specification from (VCC - 0.5) to (VSS - 0.5)
Updated Part Nomenclature Table and Ordering Information Table
*D
1349963
See ECN UHA/SFV Changed from Preliminary to Final. Updated AC Test Conditions.
Updated Ordering Information Table
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06727 Rev. *D
Revised August 1, 2007
Page 14 of 14
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
2
trademarks referenced herein are property of the respective corporations. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
2
2
2
Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. AutoStore and QuantumTrap are
registered trademarks of Simtek Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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