CY22E016L-SZ25IT [CYPRESS]
Non-Volatile SRAM, 2KX8, 25ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-28;
| 型号： | CY22E016L-SZ25IT |
| 厂家： | 
CYPRESS |
| 描述： | Non-Volatile SRAM, 2KX8, 25ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：557K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE
INFORMATION
CY22E016L
16-Kbit (2K x 8) nvSRAM
• SOIC Package
Features
• RoHS Compliance
• 25 ns, 35 ns and 45 ns Access Times
Functional Description
• “Hands-off” Automatic STORE on Power Down with
only a small capacitor
The Cypress CY22E016L is a fast static RAM with a nonvol-
atile element incorporated in each static memory cell. The
SRAM can be read and written an unlimited number of times,
while independent, nonvolatile data resides in Nonvolatile
Elements. Data transfers from the SRAM to the Nonvolatile
Elements (the STORE operation) can take place automatically
on power down. A 68-µF or larger capacitor tied from VCAP to
ground guarantees the STORE operation, regardless of
power-down slew rate or loss of power from “hot swapping”.
Transfers from the Nonvolatile Elements to the SRAM (the
RECALL operation) take place automatically on restoration of
power. A hardware STORE may be initiated with the HSB pin.
• STORE to QuantumTrap® Nonvolatile Elements is
initiated by Hardware or Autostore®on Power-down
• RECALL to SRAM Initiated on Power-up
• Unlimited READ, WRITE and RECALL Cycles
• 10 mA Typical ICC at 200 ns Cycle Time
• 1,000,000 STORE Cycles to QuantumTrap
• 100-Year Data Retention to QuantumTrap
• Single 5V Operation +10%
• Industrial Temperature
Logic Block Diagram
OE
CE
WE
Cypress Semiconductor Corporation
Document #: 001-06727 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 22, 2006
ADVANCE
INFORMATION
CY22E016L
Pin Configurations
V
V
CC
1
2
CAP
NC
WE
A
A
6
3
4
5
6
7
8
HSB
A
8
7
A
5
A
9
A
NC
OE
A
10
4
A
28-SOIC
Top View
(not to scale)
3
A
2
A
1
9
10
CE
DQ7
A
0
11
12
13
14
DQ0
DQ1
DQ2
DQ6
DQ5
DQ4
DQ3
V
SS
Pin Definitions
Pin Name
I/O Type
Description
Address Inputs used to select one of the 131,072 bytes of the nvSRAM.
A0–A10
Input
DQ0-DQ7 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation.
WE
Input
Write Enable Input, active LOW. When selected LOW, enables data on the I/O pins to be written to
the address location latched by the falling edge of CE.
CE
OE
Input
Input
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tri-state.
VSS
VCC
HSB
Ground
Ground for the device. Should be connected to ground of the system.
Power Supply Power Supply inputs to the device.
Input/Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled
low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor
keeps this pin high if not connected. (Connection Optional)
VCAP
NC
Power Supply Autostore® Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No Connect No Connects. This pin is not connected to the die
Device Operation
SRAM Read
The CY22E016L nvSRAM is made up of two functional
components paired in the same physical cell. These are a
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell to SRAM
(the RECALL operation). This unique architecture allows all
cells to be stored and recalled in parallel. During the STORE
and RECALL operations SRAM READ and WRITE operations
are inhibited. The CY22E016L supports unlimited reads and
writes just like a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and up to
1 million STORE operations.
The CY22E016L performs a READ cycle whenever CE and
OE are low while WE and HSB are high. The address specified
on pins A0–10 determines which of the 2048 data bytes will be
accessed. When the READ is initiated by an address
transition, the outputs will be valid after a delay of tAA (READ
cycle #1). If the READ is initiated by CE or OE, the outputs will
be valid at tACE or at tDOE, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address changes
within the tAA access time without the need for transitions on
any control input pins, and will remain valid until another
address change or until CE or OE is brought high, or WE or
HSB is brought low.
Document #: 001-06727 Rev. *A
Page 2 of 14
ADVANCE
INFORMATION
CY22E016L
SRAM Write
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until either
CE or WE goes high at the end of the cycle. The data on the
common I/O pins I/O0–7 will be written into the memory if it is
valid tSD before the end of a WE controlled WRITE or before
the end of an CE controlled WRITE. It is recommended that
OE be kept high during the entire WRITE cycle to avoid data
bus contention on common I/O lines. If OE is left low, internal
circuitry will turn off the output buffers tHZWE after WE goes
low.
AutoStore Operation
During normal AutoStore operation, the CY22E016L will draw
current from VCC to charge a capacitor connected to the VCAP
pin. This stored charge will be used by the chip to perform a
single STORE operation. After power up, when the voltage on
the VCAP pin drops below VSWITCH, the part will automatically
disconnect the VCAP pin from VCC and initiate a STORE
operation.
Figure 2. System Power Mode
Figure 1 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. A charge storage
capacitor having a capacity of between 68 µF and 220 µF
(±20%) rated at 6V should be provided.In system power mode
both VCC and VCAP are connected to the +5V power supply
without the 68-µF capacitor. In this mode the AutoStore
function of the CY22E016L will operate on the stored system
charge as power goes down. The user must, however,
guarantee that VCC does not drop below 3.6V during the
10-ms STORE cycles.
Figure 3. AutoStore Inhibit Mode
In order to prevent unneeded STORE operations, automatic
STOREs as well as those initiated by externally driving HSB
low will be ignored unless at least one WRITE operation has
taken place since the most recent STORE or RECALL cycle.
An optional pull-up resistor is shown connected to HSB. This
can be used to signal the system that the AutoStore cycle is in
progress.
Hardware STORE (HSB) Operation
The CY22E016L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin can be
used to request a hardware STORE cycle. When the HSB pin
is driven low, the CY22E016L will conditionally initiate a
STORE operation after tDELAY. An actual STORE cycle will
only begin if a WRITE to the SRAM took place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a busy
condition while the STORE (initiated by any means) is in
progress.
Figure 1. AutoStore® Mode
If an automatic STOREon power loss is not required, then VCC
can be tied to ground and +5V applied to VCAP. This is the
AutoStore Inhibit mode, in which the AutoStore function is
disabled. If the STK22C48 is operated in this configuration,
references to VCC should be changed to VCAP throughout this
data sheet. In this mode, STORE operations may be triggered
with the HSB pin. It is not permissible to change between these
three options “on the fly”.
SRAM READ and WRITE operations that are in progress
when HSB is driven low by any means are given time to
Document #: 001-06727 Rev. *A
Page 3 of 14
ADVANCE
INFORMATION
CY22E016L
complete before the STORE operation is initiated. After HSB
goes low, the CY22E016L will continue SRAM operations for
a negative transition on CE or WE is detected. This protects
against inadvertent writes during power-up or brown-out
conditions.
t
DELAY. During tDELAY, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is pulled low
it will be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low will be
inhibited until HSB returns high.
Noise Considerations
The CY22E016L is a high-speed memory and so must have a
high-frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high-speed CMOS ICs,
careful routing of power, ground, and signals will reduce circuit
noise.
The HSB pin can be used to synchronize multiple
CY22E016Ls while using a single larger capacitor. To operate
in this mode the HSB pin should be connected together to the
HSB pins from the other CY22E016Ls. An external pull-up
resistor to +5V is required since HSB acts as an open-drain
pull-down. The VCAP pins from the other CY22E016L parts can
be tied together and share a single capacitor. The capacitor
size must be scaled by the number of devices connected to it.
When any one of the CY22E016Ls detects a power loss and
asserts HSB, the common HSB pin will cause all parts to
request a STORE cycle (a STORE will take place in those
CY22E016Ls that have been written since the last nonvolatile
cycle).
Low Average Active Power
CMOS technology provides the CY22E016L the benefit of
drawing significantly less current when it is cycled at times
longer than 50 ns. Figure 4 shows the relationship between
ICC and READ/WRITE cycle time. Only standby current is
drawn when the chip is disabled. The overall average current
drawn by the CY22E016L depends on the following items:
During any STORE operation, regardless of how it was
initiated, the CY22E016L will continue to drive the HSB pin
low, releasing it only when the STORE is complete. Upon
completion of the STORE operation the CY22E016L will
remain disabled until the HSB pin returns high.
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. CMOS vs. TTL Input Levels.
5. The operating temperature.
6. The VCC level.
If HSB is not used, it should be left unconnected.
Hardware RECALL (Power-up)
7. I/O loading.
During power-up, or after any low-power condition (VCC
<
V
SWITCH), an internal RECALL request will be latched. When
Preventing STOREs
VCC once again exceeds the sense voltage of VSWITCH, a
RECALL cycle will automatically be initiated and will take
The STOREfunction can be disabled on the fly by holding HSB
high with a driver capable of sourcing 30 mA at a VOH of at
least 2.2V, as it will have to overpower the internal pull-down
device that drives HSB low for 20 ns at the onset of a STORE.
When the CY22E016L is connected for AutoStore operation
t
HRECALL to complete.
Data Protection
The CY22E016L protects data from corruption during
low-voltage conditions by inhibiting all externally initiated
STORE and WRITE operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY22E016L is in a
WRITE mode (both CE and WE low) at power-up, after a
RECALL, or after a STORE, the WRITE will be inhibited until
(system VCC connected to VCC and a 68 µF capacitor on VCAP
)
and VCC crosses VSWITCH on the way down, the CY22E016L
will attempt to pull HSB low; if HSB doesn’t actually get below
VIL, the part will stop trying to pull HSB low and abort the
STORE attempt.
Table 1. Hardware Mode Selection
CE
H
L
WE
X
HSB
H
A10–A0
Mode
I/O
Power
Standby
Active
Active
ICC2
X
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High-Z
Output Data
Input Data
H
H
L
L
H
X
X
L
Non-Volatile
STORE
Output High-Z
Document #: 001-06727 Rev. *A
Page 4 of 14
ADVANCE
INFORMATION
CY22E016L
Figure 5. Current vs. Cycle Time (WRITE)
Figure 4. Current vs. Cycle Time (READ)
Document #: 001-06727 Rev. *A
Page 5 of 14
ADVANCE
INFORMATION
CY22E016L
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Surface Mount Lead Soldering
Temperature (3 Seconds).......................................... +240°C
Output Short Circuit Current[1]..................................... 15 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND.......... –0.5V to 7.0V
Latch-up Current.................................................... > 200 mA
Voltage Applied to Outputs
in High-Z State .......................................–0.5V to VCC + 0.5V
Operating Range
Input Voltage............................................ –0.5V to Vcc+0.5V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Transient Voltage (<20 ns) on
Any Pin to Ground Potential...................–0.5V to VCC + 2.0V
2.7V to 3.6V
2.7V to 3.6V
–40°C to +85°C
Shaded area contains Advance Information
DC Electrical Characteristics Over the Operating Range (VCC = 4.5V to 5.5V)[2]
Parameter
Description
Test Conditions
Min.
Max. Unit
ICC1
Average VCC Current tRC = 25 ns
Commercial
Industrial
85
75
65
mA
mA
mA
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads. IOUT = 0mA.
90
75
65
mA
mA
mA
ICC2
ICC3
Average VCC Current All Inputs Don’t Care, VCC = Max.
during STORE Average current for duration tSTORE
3
mA
mA
Average VCC Current at WE > (VCC – 0.2). All other inputs cycling.
tAVAV =200ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained
typical without output loads.
10
ICC4
ISB
Average VCAP Current All Inputs Don’t Care, VCC = Max.
during AutoStore Cycle Average current for duration tSTORE
2
mA
mA
VCC Standby Current
CE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0MHz.
2.5
IILK
Input Leakage Current VCC = Max., VSS < VIN < VCC
-1
-5
+1
+5
µA
µA
IOLK
Off-State Output
Leakage Current
VCC = Max., VSS < VIN < VCC
CE or OE > VIH
,
VIH
Input HIGH Voltage
Input LOW Voltage
2.2
VCC – 0.5
2.4
VCC + 0.5
0.8
V
V
VIL
VOH
VOL
VBL
VCAP
Output HIGH Voltage IOUT = –4 mA except HSB
V
Output LOW Voltage
Logic “0” on HSB
Storage Capacitor
IOUT = 8 mA except HSB
IOUT = 3 mA
0.4
0.4
120
V
V
Between VCAP pin and Vss, 5V Rated
17
µF
Capacitance[3]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 0 to 3.0V
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
8
7
V
COUT
pF
Notes:
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
2. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C (room temperature), and V = 5V. Not 100% tested.
CC
3. These parameters are guaranteed but not tested.
Document #: 001-06727 Rev. *A
Page 6 of 14
ADVANCE
INFORMATION
CY22E016L
Table 2. Thermal Resistance[3]
Parameter
Description
Test Conditions
28-SOIC
Unit
ΘJA
Thermal Resistance
Test conditions follow standard test methods and proce-
TBD
°C/W
(Junction to Ambient) dures for measuring thermal impedance, per EIA / JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
TBD
°C/W
AC Test Loads
R1 480Ω
5.0V
OUTPUT
R2
255Ω
30 pF
AC Test Conditions
Input Pulse Levels ..........................................0V to 3V
Input Rise and Fall Times (10% - 90%) ............... <5ns
Input and Output Timing Reference Levels .......... 1.5V
Document #: 001-06727 Rev. *A
Page 7 of 14
ADVANCE
INFORMATION
CY22E016L
AC Switching Characteristics
Parameters
CY22E016L-25 CY22E016L-35 CY22E016L-45
Cypress
Alt.
Parameter Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
SRAM Read Cycle
tACE
tACS
tRC
tAA
Chip Enable Access Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[4]
tRC
Read Cycle Time
25
35
45
[5]
tAA
Address Access Time
25
10
35
15
45
20
tDOE
tOE
tOH
tLZ
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
[5]
tOHA
5
5
5
5
5
5
[6]
[6]
tLZCE
tHZCE
tHZ
10
10
25
13
13
35
15
15
45
[6]
tLZOE
tOLZ
tOHZ
tPA
0
0
0
0
0
0
[6]
tHZOE
[3]
tPU
[3]
tPD
tPS
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tWC
tWP
tCW
tDW
tDH
tAW
tAS
Write Cycle Time
25
20
20
10
0
35
25
25
12
0
45
30
30
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Chip Enable To End of Write
Data Set-Up to End of Write
Data Hold After End of Write
Address Set-Up to End of Write
Address Set-Up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
tHD
tAW
20
0
25
0
30
0
tSA
tHA
tWR
tWZ
tOW
0
0
0
[6,7]
tHZWE
10
13
14
[6]
tLZWE
5
5
5
AutoStore/Power-Up RECALL
CY22E016L
550
Parameters
Description
Power-Up RECALL Duration
STORE Cycle Duration
Unit
[8]
tHRECALL
µs
ms
µs
V
[9]
tSTORE
10
tDELAY
Time allowed to complete SRAM Cycle
Low Voltage Trigger Level
1
VSWITCH
4.0
4.5
3.6
VRESET
Low Voltage Reset Level
V
Notes:
4. WE must be HIGH during SRAM Read Cycles.
5. Device is continuously selected with CE and OE both Low.
6. Measured ±200 mV from steady state output voltage.
7. If WE is Low when CE goes Low, the outputs remain in the high-impedance state.
8. t
starts from the time V rises above V
HRECALL
CC SWITCH.
9. If an SRAM Write has not taken place since the last non-volatile cycle, no STORE will take place.
Document #: 001-06727 Rev. *A
Page 8 of 14
ADVANCE
INFORMATION
CY22E016L
Hardware STORE Cycle
CY22E016L
Parameters
Description
Min
Max
Unit
ms
µs
[6]
tSTORE
STORE Cycle Duration
10
[12]
tDELAY
tRESTORE
tHLHX
Time allowed to complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
1
[13]
700
300
ns
15
ns
tHLBL
Hardware STORE Low to STORE Busy
ns
Switching Waveforms
tRC
tAA
tOH
Figure 6. SRAM Read Cycle #1: Address Controlled[4, 5, 14]
t
t
ACE
PU
CE
OE
t
LZCE
t
HZCE
t
t
HZOE
DOE
t
LZOE
t
PU
Figure 7. SRAM Read Cycle #2: CE and OE Controlled[4,14]
Notes:
10. The software sequence is clocked with CE controlled or OE controlled READs.
11. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
12. Read and Write cycles in progress before HSB are given this amount of time to complete.
13. t
is only applicable after t
is complete.
RESTORE
STORE
14. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-06727 Rev. *A
Page 9 of 14
ADVANCE
INFORMATION
CY22E016L
Switching Waveforms (continued)
tHA
tSCE
CE
tSA
tPWE
WE
tSD
tHD
tHZWE
tLZWE
Figure 8. SRAM Write Cycle #1: WE Controlled[14,15]
tSA
tHA
tSCE
CE
tPWE
WE
tSD
tHD
Figure 9. SRAM Write Cycle #2: CE Controlled
Note:
15. CE or WE must be > V during address transitions.
IH
Document #: 001-06727 Rev. *A
Page 10 of 14
ADVANCE
INFORMATION
CY22E016L
Switching Waveforms (continued)
Figure 10. AutoStore/Power-Up RECALL
tRESTORE
Figure 11. Hardware STORE Cycle
Document #: 001-06727 Rev. *A
Page 11 of 14
ADVANCE
INFORMATION
CY22E016L
PART NUMBERING NOMENCLATURE
CY 22 E 016 L- SZ 25 C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
A - Automotive (–40 to 125°C)
Speed:
25 - 25 ns
35 - 35 ns
45 - 45 ns
55 - 55 ns
Package:
SZ - 28 SOIC
PZ - 28 PDIP
Data Bus:
K - x8 + RTC
L - x8
Density:
016 - 16 Kb
064 - 64 Kb
256 - 256 Kb
101 - 1 Mb
102 - 2 Mb
104 - 4 Mb
Voltage:
A - 1.8V
B - 3.0V
C - 3.3V
D - 3.0/3.3V
E - 5.0V
NVSRAM
14 - AutoStore + software store + hardware store
11 - Software store
15 - AutoStore + software store
16 - AutoStorePlus+ hardware store
10 - Hardware store
22 - AutoStore + Hardware Store
25 - AutoStore
Cypress
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
25
CY22E016L-SZ25IT
CY22E016L-SZ25I
CY22E016L-SZ25CT
CY22E016L-SZ35IT
CY22E016L-SZ35I
CY22E016L-SZ35CT
51-85026 28-Lead SOIC Pb-Free
51-85026 28-Lead SOIC Pb-Free
51-85026 28-Lead SOIC Pb-Free
51-85026 28-Lead SOIC Pb-Free
51-85026 28-Lead SOIC Pb-Free
51-85026 28-Lead SOIC Pb-Free
Industrial
Commercial
Industrial
35
Commercial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-06727 Rev. *A
Page 12 of 14
ADVANCE
INFORMATION
CY22E016L
Package Diagrams
28-Lead (300-Mil) Molded SOIC (51-85026)
NOTE :
PIN 1 ID
1. JEDEC STD REF MO-119
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE
14
1
MIN.
3. DIMENSIONS IN INCHES
MAX.
0.291[7.39]
0.300[7.62]
4. PACKAGE WEIGHT 0.85gms
*
0.394[10.01]
0.419[10.64]
PART #
15
28
0.026[0.66]
0.032[0.81]
S28.3 STANDARD PKG.
SZ28.3 LEAD FREE PKG.
SEATING PLANE
0.697[17.70]
0.713[18.11]
0.092[2.33]
0.105[2.67]
*
0.004[0.10]
0.0091[0.23]
0.0125[3.17]
0.015[0.38]
0.050[1.27]
0.013[0.33]
0.019[0.48]
*
0.004[0.10]
0.050[1.27]
TYP.
0.0118[0.30]
51-85026-*D
28-Lead (350-Mil) SOIC (TBD)
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation.All products and company names mentioned in
this document are the trademarks of their respective holders.
Document #: 001-06727 Rev. *A
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© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
ADVANCE
INFORMATION
CY22E016L
Document History Page
Document Title: CY22E016L 16-Kbit (2K x 8) nvSRAM
Document Number: 001-06727
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
427789
437321
Description of Change
See ECN
See ECN
TUP
TUP
New Data Sheet
Show Data Sheet on external Web
*A
Document #: 001-06727 Rev. *A
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相关型号：
CY22E016L-SZ35I
Non-Volatile SRAM, 2KX8, 35ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-28
CYPRESS
CY22E016L-SZ35IT
Non-Volatile SRAM, 2KX8, 35ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-28
CYPRESS
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