CY2277APVC-12_技术文档

7A

CY2277A

Pentium^®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/

Mobile PCs with Intel^®82430TX and 2 DIMMs or 3 SO-DIMMs

The CY2277A has power-down, CPU stop and PCI stop pins

for power management control. The CPU stop and PCI stop

are controlled by the MODE pin. They are multiplexed with

Features

• Mixed 2.5V and 3.3V operation

• Complete clock solution to meet requirements of Pen-

SDRAM clock outputs, and are selected when the MODE pin

is driven LOW. Additionally, these inputs are synchronized

on-chip, enabling glitch-free transitions. When the

CPU_STOP input is asserted, the CPU outputs are driven

LOW. When the PCI_STOP input is asserted, the PCI outputs

(except the free-running PCI clock) are driven LOW. Finally,

when the PWR_DWN pin is asserted, the reference oscillator

and PLLs are shut down, and all outputs are driven LOW.

tium^®, Pentium^®II, 6x86, or K6 motherboards

— Four CPU clocks at 2.5V or 3.3V

— Up to eight 3.3V SDRAM clocks

— Seven 3.3V synchronous PCI clocks, one free

running

— Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable

by serial interface

— One 2.5V IOAPIC clock at 14.318 MHz

— Two 3.3V Ref. clocks at 14.318 MHz

• Factory-EPROM programmable CPU, PCI, and USB/IO

clock frequencies for custom configuration

The CY2277A outputs are designed for low EMI emission.

Controlled rise and fall times, unique output driver circuits and

factory-EPROM programmable output drive and slew-rate en-

able optimal configurations for EMI control.

• Factory-EPROM programmable output drive and slew

rate for EMI customization

CY2277A Selector Guide

-12/

• MODE Enable pin for CPU_STOP and PCI_STOP

• SMBus serial configuration interface

• Available in space-saving 48-pin SSOP and TSSOP

packages.

-12M/

Clock Outputs

CPU (60, 66.6 MHz)

CPU (33.3, 66.6 MHz)

-1/-1M

-3

--

4

-7M

4

-12I

4

--

4

--

Functional Description

CPU (SMBus select-

able)

--

The CY2277A is a Clock Synthesizer/Driver for Pentium, Pen-

tium II, 6X86, and K6 portable PCs designed with the Intel^®

82430TX or similar chipsets. There are three available options

as shown in the selector guide

PCI (CPU/2)

7^[1]

6/8

2

7^[1]

6/8

2

7^[1]

6/8

2

7^[1]

6/8

2

SDRAM

The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up

to nine selectable frequencies. There are up to eight 3.3V

SDRAM clocks and seven PCI clocks, running at one half the

CPU clock frequency. One of the PCI clocks is free-running.

Additionally, the part outputs two 3.3V USB/IO clocks at 48

MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and

two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,

USB, and IO clock frequencies are factory-EPROM program-

mable for easy customization with fast turnaround times.

USB/IO (48 or 24 MHz)

IOAPIC (14.318 MHz)

Ref (14.318 MHz)

CPU-PCI delay

1

2

1–6 ns 1–6 ns <1 ns 1–4 ns

Note:

1. One free-running PCI clock.

Pin Configuration

SSOP

Logic Block Diagram

IOAPIC (14.318 MHz)

Top View

V

DDQ2

REF1

REF0

AV

1

2

3

4

48

47

46

45

44

43

42

41

DD

REF [0–1]

(14.318)

PWR_SEL

XTALIN

14.318

MHz

OSC.

V

SS

DDQ2

XTALIN

XTALOUT

MODE

XTALOUT

IOAPIC

PWR_DWN

STOP

CPU

PLL

CPUCLK[0–3]

5

6

LOGIC

V

SS

V

CPUCLK0

CPUCLK1

7

8

9

10

11

DDQ3

V

DDCPU

PCICLK_F

PCICLK0

SDRAM[0–5]

V

SEL

40

39

38

37

36

35

34

33

32

31

EPROM

DDCPU

V

SS

CPUCLK2

CPUCLK3

PCICLK1

PCICLK2

MODE

SDRAM6/CPU_STOP

12

13

V

SYS

PLL

SS

PCICLK3

PCICLK4

SDRAM0

SDRAM1

14

15

16

17

18

19

20

21

22

23

24

SDRAM7/PCI_STOP

V

DDQ3

V

DDQ3

/2

PCICLK5

SDRAM2

SDRAM3

V

SS

Delay

SEL

V

PWR_DWN

STOP

LOGIC

SS

PCI[0–5]

SDATA

SCLK

30

29

28

27

26

25

SDRAM4

SDRAM5

PCICLK_F

SERIAL

SCLK

V

DDQ3

Divide and

Mux Logic

INTERFACE

CONTROL

LOGIC

USBCLK/IOCLK[0:1]

USBCLK/IOCLK

SDRAM6/CPU_STOP

SDRAM7/PCI_STOP

SDATA

V

AV

DD

SS

Cypress Semiconductor Corporation

Document #: 38-07332 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised December 7, 2002

CY2277A

Pin Summary

Name

V_DDQ3

V_DDQ2

V_DDCPU

AV_DD

Pins

Description

7, 15, 21, 28, 34

3.3V Digital voltage supply

IOAPIC Digital voltage supply, 2.5V

CPU Digital voltage supply, 2.5V or 3.3V

3.3V Analog voltage supply

46

40

25, 48

V_SS

3, 10, 17, 24, 31, 37, 43 Ground

XTALIN^[2]

XTALOUT^[2]

MODE

SEL

4

Reference crystal input

5

Reference crystal feedback

6

Mode select input, enables power management features

18

Select input to enable 66.66 MHz or 60 MHz CPU clock (See Function

tables.)

SDATA

19

20

44

47

SMBus serial data input for serial configuration port

SCLK

SMBus serial clock input for serial configuration port

PWR_DWN

PWR_SEL

Active low control input to put osc., PLLs, and outputs in power down state

Power select input, indicates whether V_DDCPUis at 2.5V or 3.3V

HIGH = 3.3V, LOW=2.5V (internal pull-up to V_DD

)

SDRAM7/PCI_STOP 26

SDRAM6/CPU_STOP 27

SDRAM clock output. Also, active LOW control input to stop PCI clocks,

enabled when MODE is LOW

SDRAM clock output. Also, active LOW control input to stop CPU clocks,

enabled when MODE is LOW

SDRAM[0:5]

CPUCLK[0:3]

PCICLK[0:5]

PCICLK_F

IOAPIC

36, 35, 33, 32, 30, 29

SDRAM clock outputs, have same frequency as CPU clocks

CPU clock outputs

42, 41, 39, 38

9, 11, 12, 13, 14, 16

PCI clock outputs

8

PCI clock output, free-running

45

IOAPIC clock output

REF[0:1]

1, 2

22, 23

Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load

USB or IO clock outputs, frequency selected by serial word

USBCLK/IOCLK

Note:

2. For best accuracy, use a parallel-resonant crystal, C_LOAD= 18 pF.

Document #: 38-07332 Rev. *A

Page 2 of 19

CY2277A

Function Table (-1, -1M, -7M, -12, -12M, -12I)

CPUCLK[0:3]

SDRAM[0:7]

PCICLK[0:5]

PCICLK_F

REF[0:1]

IOAPIC

SEL

XTALIN

14.318 MHz

USBCLK / IOCLK^[3]

0

1

60.0 MHz

66.67 MHz

30.0 MHz

33.33 MHz

14.318 MHz

48.0 MHz / 24.0 MHz

Function Table (-3)

CPUCLK[0:3]

SDRAM[0:7]

PCICLK[0:5]

PCICLK_F

REF[0:1]

IOAPIC

SEL

XTALIN

14.318 MHz

USBCLK / IOCLK^[3]

48.0 MHz / 24.0 MHz

0

1

33.33 MHz

66.67 MHz

16.67 MHz

33.33 MHz

14.318 MHz

CPU and PCI Clock Driver Strengths

Actual Clock Frequency Values (-1, -1M, -3, -7M,

-12, -12M, -12I)

• Matched impedances on both rising and falling edges on

the output drivers

• Output impedance: 25Ω (typical) measured at 1.5V

Target

Frequency

(MHz)

Actual

Frequency

(MHz)

Clock Output

PPM

–195

CPUCLK,

SDRAM

66.67

66.654

CPUCLK,

SDRAM

60.0

0

USBCLK^[4]

48.0

24.0

48.008

24.004

167

IOCLK

Notes:

3. On power-up, the default frequency on these outputs is 48 MHz.

4. Meets Intel USB clock requirements.

Document #: 38-07332 Rev. *A

Page 3 of 19

CY2277A

Power Management Logic

CPU_STOP PCI_STOP PWR_DWN

CPUCLK

LOW

PCICLK

LOW

PCICLK_F Other Clocks

Osc.

Off

PLLs

Off

X

0

1

X

0

1

0

1

0

1

Stopped

Running

Stopped

Running

LOW

Running Running

33/30 MHz Running

Running

66/60 MHz 33/30 MHz Running

66/60 MHz LOW

Serial Configuration Map

Byte 0: Functional and Frequency Select Clock

Register (1 = Enable, 0 = Disable)

• TheSerialbitswillbereadbytheclockdriverinthefollowing

order:

Bit Pin #

Bit 7 --

Description

(Reserved) drive to ‘0’

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Bit 6 --

(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,

-12M, -12I

.

Bit 5 --

Bit 4 --

Bit 3 23

Bit 2 22

(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,

-12M, -12I

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

• Reserved and unused bits should be programmed to “0”.

• SMBus Address for the CY2277A is:

(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,

-12M, -12I

48/24 MHz (Frequency Select) 1 = 48 MHz

(default), 0 = 24 MHz

A6

A5

A4

A3

A2

A1

A0

R/W

48/24 MHz (Frequency Select) 1 = 48 MHz

(default), 0 = 24 MHz

1

0

1

0

1

----

Bit 1 --

Bit 0

Bit 1 Bit 0

1

0

1 - Three-State (see table below)

0 - N/A

1 - Test Mode (see table below)

0 - Normal Operation

Select Functions

Outputs

Ref

Functional Description

CPU

PCI, PCI_F

Hi-Z

TCLK/4

SDRAM

Hi-Z

TCLK/2

IOAPIC

Hi-Z

IOCLK

Hi-Z

TCLK/4

USBCLK

Hi-Z

Three-State

Hi-Z

Test Mode

TCLK/2^[5]

TCLK

TCLK/2

Note:

5. TCLK supplied on the XTALIN, PIN 4.

Document #: 38-07332 Rev. *A

Page 4 of 19

CY2277A

Byte 1: CPU, 24/48 MHz Active/Inactive

Register (1 = Active, 0 = Inactive), Default = Active

Byte 2: PCI Active/Inactive

Register (1 = Active, 0 = Inactive), Default = Active

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

23

Description

48/24 MHz (Active/Inactive)

(Reserved) drive to ‘0’

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

Description

(Reserved) drive to ‘0’

--

8

22

--

PCICLK_F (Active/Inactive)

PCICLK5 (Active/Inactive)

PCICLK4 (Active/Inactive)

PCICLK3 (Active/Inactive)

PCICLK2 (Active/Inactive)

PCICLK1 (Active/Inactive)

PCICLK0 (Active/Inactive)

16

14

13

12

11

9

N/A

38

39

41

42

Not Used, drive 0

CPUCLK3 (Active/Inactive)

CPUCLK2 (Active/Inactive)

CPUCLK1 (Active/Inactive)

CPUCLK0 (Active/Inactive)

Byte 3: SDRAM Active/Inactive

Register (1 = Active, 0 = Inactive), Default = Active

Byte 4: SDRAM Active/Inactive

Register (1 = Active, 0 = Inactive), Default = Active

Bit Pin #

Bit 7 26

Bit 6 27

Bit 5 29

Bit 4 30

Bit 3 32

Bit 2 33

Bit 1 35

Bit 0 36

Description

SDRAM7 (Active/Inactive)

SDRAM6 (Active/Inactive)

SDRAM5 (Active/Inactive)

SDRAM4 (Active/Inactive)

SDRAM3 (Active/Inactive)

SDRAM2 (Active/Inactive)

SDRAM1 (Active/Inactive)

SDRAM0 (Active/Inactive)

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

N/A

Description

Not used, drive to ‘0’

N/A

Not used, drive to ‘0’

Byte 5: Peripheral Active/Inactive

Register (1 = Active, 0 = Inactive), Default = Active

Byte 6: Reserved, for future use

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

--

Description

(Reserved) drive to ‘0’

IOAPIC (Active/Inactive)

(Reserved) drive to ‘0’

REF1 (Active/Inactive)

REF0 (Active/Inactive)

--

45

--

1

2

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Junction Temperature............................................... +150°C

Supply Voltage..................................................–0.5 to +7.0V

Input Voltage............................................ –0.5V to V_DD+ 0.5

Storage Temperature (Non-Condensing)....–65°C to +150°C

Package Power Dissipation.............................................. 1W

Static Discharge Voltage............................................ >2000V

(per MIL-STD-883, Method 3015, like V_DDpins tied together)

Document #: 38-07332 Rev. *A

Page 5 of 19

CY2277A

Operating Conditions^[6]

Parameter

Description

Min.

Max.

Unit

AV_DD, V_DDQ3

V_DDCPU

Analog and Digital Supply Voltage

3.135

3.465

V

2.5V CPU Supply Voltage (-1,-1M, -3, -7M)

2.5V CPU Supply Voltage (-12, -12M, -12I)

3.3V CPU Supply Voltage

2.375

3.135

2.9

2.625

3.465

V_DDQ2

2.5V IOAPIC Supply Voltage (-1,-1M, -3, -7M)

2.5V IOAPIC Supply Voltage (-12, -12M, -12I)

3.3V IOAPIC Supply Voltage

2.375

3.135

2.9

2.625

3.465

V

T_A

C_L

Operating Temperature, Commercial

Operating Temperature, Industrial

0

70

85

°C

pF

–40

Max. Capacitive Load on

CPUCLK, USBCLK/IOCLK, REF1, IOAPIC

PCICLK, SDRAM

10

30, 20

20

30

45

REF0

f_(REF)

t_PU

Reference Frequency, Oscillator Nominal Value

14.318

MHz

ms

Power-up time for all VDD's to reach minimum specified voltage (power

ramps must be monotonic)

0.05

50

Electrical Characteristics (-1, -3, -12)

Parameter

V_IH

Description

Test Conditions

Min. Max. Unit

High-level Input Voltage

Low-level Input Voltage

High-level Output Voltage^[7]V_DDQ2= V_DDCPU= 2.375V

Low-level Output Voltage^[7]V_DDQ2= V_DDCPU= 2.375V

High-level Output Voltage^[7]V_DDQ3, AV_DD, V_DDCPU= 3.135V

Except Crystal Inputs

SMBus inputs only

2.0

V

V_IL

0.8

0.7

V_ILiic

V_OH

I_OH= 18 mA CPUCLK 2.0

_OH= 18 mA IOAPIC

I

V_OL

V_OH

I_OL= 29 mA CPUCLK

I_OL= 29 mA IOAPIC

I_OH= 32 mA CPUCLK 2.4

I_OH= 36 mA SDRAM

I_OH= 32 mA PCICLK

I_OH= 26 mA USBCLK

I_OH= 26 mA IOCLK

I_OH= 36 mA REF0

0.4

V

I_OH= 26 mA REF1

V_OL

Low-level Output Voltage^[7]V_DDQ3, AV_DD, V_DDCPU= 3.135V

I_OL= 24 mA CPUCLK

I_OL= 29 mA SDRAM

I_OL= 26 mA PCICLK

I_OL= 21 mA USBCLK

I_OL= 21 mA IOCLK

I_OL= 29 mA REF0

0.4V

V

I_OL= 21 mA REF1

I_IH

Input High Current

Input Low Current

Output Leakage Current

Power Supply Current^{[7, 8]}V_DD= 3.465V, V_IN= 0 or V_DD, Loaded Outputs, CPU = 66.67 MHz

Power Supply Current^{[7, 8]}V_DD= 3.465V, V_IN= 0 or V_DD, Unloaded Outputs

V_IH= V_DD

–10 +10 µA

10 µA

I_IL

V_IL= 0V, except PWR_SEL

V_IL= 0V, PWR_SEL only

Three-state

I_IL

100 µA

–10 +10 µA

250 mA

I_OZ

I_DD

I_DDS

120 mA

Power-down Current

Current draw in power-down state, PWR_SEL = V_DD

150 µA

Document #: 38-07332 Rev. *A

Page 6 of 19

CY2277A

Electrical Characteristics (-1, -3, -12)

Parameter

Description

Test Conditions

Min. Max. Unit

Notes:

6. Electrical parameters are guaranteed with these operating conditions.

7. Guaranteed by design and characterization. Not 100% tested in production.

8. Power supply current will vary with number of outputs which are running.

Electrical Characteristics (-1M, -7M, -12M)

Parameter

V_IH

Description

Min. Max. Unit

High-level Input Voltage

Low-level Input Voltage

High-level Output Voltage^[7]V_DDQ2= V_DDCPU= 2.375V

Low-level Output Voltage^[7]V_DDQ2= V_DDCPU= 2.375V

High-level Output Voltage^[7]V_DDQ3, AV_DD, V_DDCPU= 3.135V

Except Crystal Inputs

SMBus inputs only

2.0

V

V_IL

0.8

0.7

V_ILiic

V_OH

I_OH= 12.6 mA CPUCLK 1.75

I

_OH= 16.7mA IOAPIC

I_OL= 18.2 mA CPUCLK

_OL= 23.1 mA IOAPIC

I_OH= 32.2 mA SDRAM

_OH= 32.2 mA PCICLK

I_OH= 32.2 mA USBCLK

_OH= 32.2 mA IOCLK

I_OH= 32.2 mA REF0

_OH= 32.2 mA REF1

I_OL= 23.8 mA SDRAM

_OL= 23.8 mA PCICLK

I_OL= 23.8 mA USBCLK

_OL= 23.8 mA IOCLK

I_OL= 23.8 mA REF0

_OL= 23.8 mA REF1

V_OL

V_OH

0.4

V

I

2.4

I

V_OL

Low-level Output Voltage^[7]V_DDQ3, AV_DD, V_DDCPU= 3.135V

0.8V

V

I

I_IH

Input High Current

Input Low Current

Output Leakage Current

Power Supply Current^{[7, 8]}V_DD= 3.465V, V_IN= 0 or V_DD, Loaded Outputs, CPU = 66.67 MHz

Power Supply Current^{[7, 8]}V_DD= 3.465V, V_IN= 0 or V_DD, Unloaded Outputs

V_IH= V_DD

–10 +10 µA

10 µA

I_IL

V_IL= 0V, except PWR_SEL

V_IL= 0V, PWR_SEL only

Three-state

I_IL

100 µA

–10 +10 µA

250 mA

I_OZ

I_DD

I_DDS

120 mA

Power-down Current

Current draw in power-down state, PWR_SEL = V_DD

150 µA

Document #: 38-07332 Rev. *A

Page 7 of 19

CY2277A

Electrical Characteristics (-12I)

Parameter

V_IH

Description

Test Conditions

Min. Max. Unit

High-level Input Voltage

Low-level Input Voltage

High-level Output Voltage^[7]V_DDQ2= V_DDCPU= 2.375V

Low-level Output Voltage^[7]V_DDQ2= V_DDCPU= 2.375V

High-level Output Voltage^[7]V_DDQ3, AV_DD, V_DDCPU= 3.135V

Except Crystal Inputs

SMBus inputs only

2.0

V

V_IL

0.8

0.7

V_ILiic

V_OH

I_OH= 18 mA

_OH= 18 mA

I_OL= 29 mA

_OL= 29 mA

I_OH= 32 mA

_OH= 36 mA

I_OH= 32 mA

_OH= 26 mA

I_OH= 26 mA

_OH= 36 mA

CPUCLK 1.75

IOAPIC

I

V_OL

V_OH

CPUCLK

IOAPIC

0.4

V

I

CPUCLK 2.4

SDRAM

PCICLK

USBCLK

IOCLK

I

REF0

I_OH= 26 mA

I_OH= 24mA

I_OH= 29 mA

REF1

V_OL

Low-level Output Voltage^[7]V_DDQ3, AV_DD, V_DDCPU= 3.135V

CPUCLK

SDRAM

PCICLK

USBCLK

IOCLK

0.8V

V

I

_OH= 26 mA

I_OL= 21 mA

_OH= 21 mA

I_OL= 29mA

_OH= 21 mA

I

REF0

I

REF1

I_IH

Input High Current

Input Low Current

Output Leakage Current

Power Supply Current^{[7, 8]}V_DD= 3.465V, V_IN= 0 or V_DD, Loaded Outputs, CPU = 66.67 MHz

Power Supply Current^{[7, 8]}V_DD= 3.465V, V_IN= 0 or V_DD, Unloaded Outputs

V_IH= V_DD

–20 +20 µA

10 µA

I_IL

V_IL= 0V, except PWR_SEL

V_IL= 0V, PWR_SEL only

Three-state

I_IL

100 µA

–10 +10 µA

250 mA

I_OZ

I_DD

I_DDS

120 mA

Power-down Current

Current draw in power-down state, PWR_SEL = V_DD

150 µA

Document #: 38-07332 Rev. *A

Page 8 of 19

CY2277A

Switching Characteristics (-1, -3)^{[9, 10, 11]}

Parameter

Output

Description

Output Duty Cycle^[12]

Test Conditions

t₁= t_1A÷ t_1B

Min. Typ. Max.

Unit

t₁

CPUCLK

SDRAM

USBCLK

IOCLK

45

50

55

%

REF [0,1]

IOAPIC

t₁

t₂

PCI

Output Duty Cycle^[12]

t₁= t_1A÷ t_1B

40

50

55

%

CPUCLK, CPU and IOAPIC Clock

IOAPIC

Between 0.4V and 2.0V, V_DDCPU= 2.5V 0.75

4.0

V/ns

Rising and Falling Edge Between 0.4V and 2.4V, V_DDCPU= 3.3V 0.75

Rate

CPU clocks at 66.66 MHz

t₂

PCI

PCI Clock Rising and

Falling Edge Rate

Between 0.4V and 2.4V, V_DDCPU= 3.3V 0.75

4.0

V/ns

USBCLK, USB, I/O, REF0 Clock

IOCLK,

Between 0.4V and 2.4V

0.8

Rising and Falling Edge

REF0

Rate

t₂

t₃

t₄

SDRAM

REF1

SDRAM Rising and Fall- Between 0.4V and 2.4V

ing Edge Rate SDRAM clocks at 66.66 MHz

1.0

0.5

4.0

2.0

V/ns

ns

REF1 Rising and Falling Between 0.4V and 2.4V

Edge Rate

CPUCLK

CPU Clock Rise Time

Between 0.4V and 2.0V, V_DDCPU= 2.5V 0.4

Between 0.4V and 2.4V, V_DDCPU= 3.3V 0.5

2.13

2.0

USBCLK, USB Clock and I/O Clock Between 0.4V and 2.4V

IOCLK

2.5

ns

Rise Time

CPUCLK

CPU Clock Fall Time

Between 2.0V and 0.4V, V_DDCPU= 2.5V 0.4

Between 2.4V and 0.4V, V_DDCPU= 3.3V 0.5

2.13

2.0

ns

USBCLK, USB Clock and I/O Clock Between 2.4V and 0.4V

IOCLK

2.5

ns

Fall Time

t₅

t₆

CPUCLK

CPU-CPU Clock Skew

Measured at 1.25V, V_DDCPU= 2.5V

100

2.0

400

6.0

ps

ns

CPUCLK, CPU-PCI Clock Skew

PCICLK (-1, -3)

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

1.0

t₇

t₈

CPUCLK, CPU-SDRAM Clock

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks, V_DDCPU= 2.5V

775

450

ps

SDRAM

Skew

CPUCLK

Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks and

at 1.5V for 3.3V clocks

t₈

SDRAM

PCICLK

Cycle-Cycle Clock Jitter Measured at 1.5V for 3.3V clocks

Cycle-Cycle Clock Jitter Measured at 1.5V

650

500

1.3

ps

ns

USBCLK, Cycle-Cycle Clock Jitter Measured at 1.5V

IOCLK

t₉

CPUCLK, Power-up Time

PCICLK,

CPU, PCI, and SDRAM clock stabiliza-

tion from power-up

3

ms

SDRAM

t₁₀

CPU, PCI, Frequency Slew Rate

SDRAM

Rate of change of frequency

2

MHz/

ms

Notes:

9. All parameters specified with loaded outputs.

10. Over the operating range unless otherwise specified.

11. Parameters specified with: V_DDCPU= 2.5V, V_DDQ2= 2.5V, V_DDQ3= 3.3V.

12. Duty cycle is measured at 1.5V when V_DD= 3.3V. When V_DDCPU= 2.5V, CPUCLK duty cycle is measured at 1.25V.

Document #: 38-07332 Rev. *A

Page 9 of 19

CY2277A

Switching Characteristics (-1M, -7M, -12M)^{[9, 10, 11]}

Parameter

Output

Description

Output Duty Cycle^[12]

Test Conditions

t₁= t_1A÷ t_1B

Min. Typ. Max.

Unit

t₁

CPUCLK

SDRAM

USBCLK

REF [0,1]

IOAPIC

45

50

55

%

t₁

t₂

PCI

Output Duty Cycle^[12]

t₁= t_1A÷ t_1B

45

50

55

%

CPUCLK, CPU and IOAPIC Clock

IOAPIC

Between 0.4V and 2.0V, V_DDCPU= 2.5V 0.60

4.0

V/ns

Rising and Falling Edge CPU clocks at 66.66 MHz

Rate

t₂

PCI

PCI Clock Rising and

Falling Edge Rate

Between 0.4V and 2.0V, V_DDCPU= 2.5V 0.65

4.0

2.0

V/ns

USBCLK, USB, REF0 Clock Rising Between 0.4V and 2.4V

REF0

0.65

0.70

0.5

and Falling Edge Rate

SDRAM

SDRAM Rising and Fall- Between 0.4V and 2.4V

ing Edge Rate

SDRAM clocks at 66.66 MHz

REF1

REF1 Rising and Falling Between 0.4V and 2.4V

Edge Rate

t₃

t₄

t₅

CPUCLK

USBCLK

CPUCLK

USBCLK

CPUCLK

PCICLK

SDRAM

CPU Clock Rise Time

USB Clock Rise Time

CPU Clock Fall Time

USB Clock Fall Time

CPU-CPU Clock Skew

PCI-PCI Clock Skew

Between 0.4V and 2.0V, V_DDCPU= 2.5V 0.4

Between 0.4V and 2.0V

2.4

2.5

ns

ps

Between 2.0V and 0.4V, V_DDCPU= 2.5V 0.4

Between 2.0V and 0.4V

2.4

2.5

Measured at 1.25V, V_DDCPU= 2.5V

Measured at 1.5V

100

2.0

250

400

300

SDRAM-SDRAM Clock

Skew

Measured at 1.5V

t₆

t₇

CPUCLK, CPU-PCI Clock Skew

PCICLK -1M, -12M

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

1.0

6.0

750

600

ns

ps

CPUCLK, CPU-PCI Clock Skew

PCICLK -7M

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

CPUCLK, CPU-SDRAM Clock

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks, V_DDCPU= 2.5V

SDRAM

CPUCLK

SDRAM

PCICLK

Skew

t₈

Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks

Cycle-Cycle Clock Jitter Measured at 1.5V

525

600

400

900

ps

Cycle-Cycle Clock Jitter Measured at 1.5V

USBCLK, Cycle-Cycle Clock Jitter Measured at 1.5V

IOCLK

t₉

CPUCLK, Power-up Time

PCICLK,

CPU, PCI, and SDRAM clock stabiliza-

tion from power-up

3

ms

SDRAM

t₁₀

CPU, PCI, Frequency Slew Rate

SDRAM

Rate of change of frequency

2

MHz/

ms

Document #: 38-07332 Rev. *A

Page 10 of 19

CY2277A

Switching Characteristics (-12)^{[9, 10, 11]}

Parameter

Output

Description

Test Conditions

t₁= t_1A÷ t_1B

Between 0.6V and 1.8V, V_DDCPU= 2.5V 1.0

Min. Typ. Max.

Unit

%

t₁

t₂

All Clocks Output Duty Cycle^[12]

45

50

55

CPUCLK, CPU and IOAPIC Clock

4.0

V/ns

IOAPIC

PCI

Rising and Falling Edge Between 0.4V and 2.4V, V_DDCPU= 3.3V 1.0

Rate

CPU clocks at 66.6 MHz

t₂

PCI Clock Rising and

Falling Edge Rate

Between 0.4V and 2.4V, V_DDCPU= 3.3V 1.0

4.0

2.0

V/ns

REF0

SDRAM

REF0 Clock Rising and

Falling Edge Rate

Between 0.8V and 2.4V, V_DDCPU= 3.3V 1.0

SDRAM Rising and Fall- Between 0.5V and 2.0V

ing Edge Rate SDRAM clocks at 66.6 MHz

1.5

0.5

REF1

USBCLK

REF1,USBandIORising Between 0.4V and 2.4V

and Falling Edge Rate

IOCLK

t₃

t₄

CPUCLK

CPU Clock Rise Time

Between 0.4V and 2.0V, V_DDCPU= 2.5V 0.4

Between 0.4V and 2.4V, V_DDCPU= 3.3V 0.4

2.0

ns

USBCLK, USB Clock and I/O Clock Between 0.4V and 2.4V

IOCLK

1.0

4.0

Rise Time

CPUCLK

CPU Clock Fall Time

Between 2.0V and 0.4V, V_DDCPU= 2.5V 0.4

Between 2.4V and 0.4V, V_DDCPU= 3.3V 0.4

2.0

USBCLK, USB Clock and I/O Clock Between 2.4V and 0.4V

IOCLK

1.0

4.0

Fall Time

t₅

t₆

CPUCLK

CPU-CPU Clock Skew

Measured at 1.25V, V_DDCPU= 2.5V

100

250

4.0

ps

ns

CPUCLK, CPU-PCI Clock Skew

PCICLK (-12)

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

1.0

t₇

t₈

CPUCLK, CPU-SDRAM Clock

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks, V_DDCPU= 2.5V

500

250

ps

SDRAM

Skew

CPUCLK

Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks and

at 1.5V for 3.3V clocks

t₈

t₉

PCICLK

Cycle-Cycle Clock Jitter Measured at 1.5V

500

3

ps

CPUCLK, Power-up Time

PCICLK,

CPU, PCI, and SDRAM clock stabiliza-

tion from power-up

ms

SDRAM

t₁₀

CPU, PCI, Frequency Slew Rate

SDRAM

Rate of change of frequency

2

MHz/

ms

Document #: 38-07332 Rev. *A

Page 11 of 19

CY2277A

Switching Characteristics (-12I)^{[9, 10, 11]}

Parameter

Output

Description

Test Conditions

t₁= t_1A÷ t_1B

Between 0.6V and 1.8V, V_DDCPU= 2.5V 1.0

Min. Typ. Max.

Unit

%

t₁

t₂

All Clocks Output Duty Cycle^[12]

45

50

55

CPUCLK, CPU and IOAPIC Clock

4.0

V/ns

IOAPIC

PCI

Rising and Falling Edge Between 0.4V and 2.4V, V_DDCPU= 3.3V

.8

Rate

CPU clocks at 66.6 MHz

t₂

PCI Clock Rising and

Falling Edge Rate

Between 0.4V and 2.4V, V_DDCPU= 3.3V

.9

4.0

2.0

V/ns

REF0

SDRAM

REF0 Clock Rising and

Falling Edge Rate

Between 0.8V and 2.4V, V_DDCPU= 3.3V 1.0

SDRAM Rising and Fall- Between 0.5V and 2.0V

ing Edge Rate SDRAM clocks at 66.6 MHz

1

REF1

USBCLK

IOCLK

REF1,USBandIORising Between 0.4V and 2.4V

and Falling Edge Rate

0.5

t₃

t₄

CPUCLK

CPU Clock Rise Time

Between 0.4V and 2.0V, V_DDCPU= 2.5V 0.4

Between 0.4V and 2.4V, V_DDCPU= 3.3V 0.4

3.0

2.0

ns

USBCLK, USB Clock and I/O Clock Between 0.4V and 2.4V

IOCLK

1.0

4.0

Rise Time

CPUCLK

CPU Clock Fall Time

Between 2.0V and 0.4V, V_DDCPU= 2.5V 0.4

Between 2.4V and 0.4V, V_DDCPU= 3.3V 0.4

3.0

2.0

USBCLK, USB Clock and I/O Clock Between 2.4V and 0.4V

IOCLK

1.0

4.0

Fall Time

t₅

t₆

CPUCLK

CPU-CPU Clock Skew

Measured at 1.25V, V_DDCPU= 2.5V

100

250

4.0

ps

ns

CPUCLK, CPU-PCI Clock Skew

PCICLK (-12)

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

1.0

t₇

t₈

CPUCLK, CPU-SDRAM Clock

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks, V_DDCPU= 2.5V

625

350

ps

SDRAM

Skew

CPUCLK

Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks and

at 1.5V for 3.3V clocks, V_DDCPU=2.5V

t₈

t₉

PCICLK

Cycle-Cycle Clock Jitter Measured at 1.5V

500

3

ps

CPUCLK, Power-up Time

PCICLK,

CPU, PCI, and SDRAM clock stabiliza-

tion from power-up

ms

SDRAM

t₁₀

CPU, PCI, Frequency Slew Rate

SDRAM

Rate of change of frequency

2

MHz/

ms

Document #: 38-07332 Rev. *A

Page 12 of 19

CY2277A

Timing Requirement for the SMBus

Parameter

Description

Min.

0

Max.

Unit

kHz

µs

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

SCLK Clock Frequency

100

Time the bus must be free before a new transmission can start

Hold time start condition. After this period the first clock pulse is generated.

The LOW period of the clock.

4.7

4

µs

4.7

4

µs

The HIGH period of the clock.

µs

Setup time for start condition. (Only relevant for a repeated start condition.)

4.7

µs

Hold time DATA

µs

for CBUS compatible masters.

for SMBus devices

5

0

t₁₇

t₁₈

t₁₉

t₂₀

DATA input set-up time

250

ns

µs

ns

µs

Rise time of both SDATA and SCLK inputs

Fall time of both SDATA and SCLK inputs

Set-up time for stop condition

1

300

4.0

Switching Waveforms

Duty Cycle Timing

t

1B

t

1A

CPUCLK Outputs HIGH/LOW Time

t

1C

V

DD

OUTPUT

0V

t

1D

All Outputs Rise/Fall Time

V

DD

OUTPUT

0V

t

2

t

3

t

2

t

4

Document #: 38-07332 Rev. *A

Page 13 of 19

CY2277A

Switching Waveforms (continued)

CPU-CPU Clock Skew

CLK

t

5

CPU-SDRAM Clock Skew

CPUCLK

SDRAM

t

7

CPU-PCI Clock Skew

CPUCLK

PCICLK

t

6

CPU_STOP ^{[13, 14]}

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK

(Free-Running)

CPU_STOP

CPUCLK

(External)

Notes:

13. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.

14. CPU_STOP may be applied asynchronously. It is synchronized internally.

Document #: 38-07332 Rev. *A

Page 14 of 19

CY2277A

Switching Waveforms (continued)

PCI_STOP ^{[15, 16]}

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK

(Free-Running)

PCI_STOP

PCICLK

(External)

PWR_DOWN

CPUCLK

(Internal)

PCICLK

(Internal)

PWR_DWN#

CPUCLK

(External)

PCICLK

(External)

VCO

Crystal

Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.

Timing Requirements for the SMBus

SDA

t

19

t

11

18

12

SCL

t

12

t

15

20

t

17

t

13

14

16

Notes:

15. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK.

16. PCI_STOP may be applied asynchronously. It is synchronized internally.

Document #: 38-07332 Rev. *A

Page 15 of 19

CY2277A

Application Information

Clock traces must be terminated with either series or parallel termination, as is normally done.

Application Circuit

Summary

• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C_LOADof

this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different

C_LOADis used. Footprints can be laid out for flexibility.

• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.

In some cases, smaller value capacitors may be required.

• Thevalueofthe series terminatingresistorsatisfiesthefollowingequation, where R_traceistheloadedcharacteristicimpedance

ofthetrace,R_outistheoutputimpedanceoftheclockgenerator(specifiedinthedatasheet), andR_seriesistheseriesterminating

resistor.

R_series> R_trace– R_out

• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor

as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.

• A Ferrite Bead may be used to isolate the Board V_DDfrom the clock generator V_DDisland. Ensure that the Ferrite Bead offers

greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout

and Termination Techniques for Cypress Clock Generators” for more details.

• If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor

prevents power supply droop during current surges.

Document #: 38-07332 Rev. *A

Page 16 of 19

CY2277A

Test Circuit

V_DDQ3

48

3

0.1 µF

46

V_DDQ2

7

0.1 µF

43

40

10

V_DDCPU

0.1 µF

37

34

15

0.1 µF

17

21

31

28

0.1 µF

25

24

OUTPUTS

C_LOAD

Note:All capacitorsshould be placed as close to each pin as possible.

Ordering Information

Package

Name

Operating

Range

Ordering Code

CY2277APVC-1

Package Type

48-Pin SSOP

O48

Z48

O48

Z48

O48

Z48

O48

Commercial

Industrial

CY2277APAC-1M

CY2277APVC-3

48-Pin TSSOP

48-Pin SSOP

48-Pin TSSOP

48-Pin SSOP

48-Pin TSSOP

48-Pin SSOP

CY2277APAC-7M

CY2277APVC-12

CY2277APAC-12M

CY2277APVI-12

Intel and Pentium are registered trademarks of Intel Corporation. All product or company names mentioned in this document are

the trademarks of their respective holders.

Document #: 38-07332 Rev. *A

Page 17 of 19

CY2277A

Package Diagrams

48-Lead Shrunk Small Outline Package O48

51-85061-C

48-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48

51-85059-B

Document #: 38-07332 Rev. *A

Page 18 of 19

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY2277A

Document Title: CY2277A Pentium^®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/Mobile PCs with Intel^®82430TX

and 2 DIMMs or 3 SO-DIMMs

Document Number: 38-07332

Issue

Date

Orig. of

Change

REV.

**

ECN NO.

111731

Description of Change

12/15/01

12/14/02

DSG

RBI

Change from Spec number: 38-00612 to 38-07332

Power up requirements added to Operating Conditions Information

*A

121855

Document #: 38-07332 Rev. *A

Page 19 of 19


型号：	CY2277APVC-12
厂家：	CYPRESS
描述：	6x86, K6 Clock Synthesizer/Driver for Desktop Mobile PCs with Intel 82430TX and 2 DIMMs or 3 SO-DIMMs 6X86 ， K6时钟合成器/驱动器，用于移动台式电脑采用英特尔82430TX和2个DIMM或3 SO- DIMM内存模块晶体驱动器时钟发生器微控制器和处理器外围集成电路光电二极管电脑 PC
文件：	总19页 (文件大小：209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY2277APVC-12 [CYPRESS]

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