CY2277APVC-3 [SPECTRALINEAR]
Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel㈢ 82430TX and 2 DIMMs or 3 SO-DIMMs; Pentium㈢ / II ， 6X86 ， K6时钟合成器/驱动器，用于桌面/移动PC与Intel㈢ 82430TX和2个DIMM或3 SO- DIMM内存模块
| 型号： | CY2277APVC-3 |
| 厂家： | 
SPECTRALINEAR INC |
| 描述： | Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel㈢ 82430TX and 2 DIMMs or 3 SO-DIMMs |
| 文件： | 总18页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Y2277A
CY2277A
Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/
Mobile PCs with Intel® 82430TX and 2 DIMMs or 3 SO-DIMMs
82430TX or similar chipsets. There are three available options
as shown in the selector guide
Features
• Mixed 2.5V and 3.3V operation
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up
to nine selectable frequencies. There are up to eight 3.3V
SDRAM clocks and seven PCI clocks, running at one half the
• Complete clock solution to meet requirements of
Pentium®, Pentium® II, 6x86, or K6 motherboards
— Four CPU clocks at 2.5V or 3.3V
— Up to eight 3.3V SDRAM clocks
CPU clock frequency. One of the PCI clocks is free-running.
Additionally, the part outputs two 3.3V USB/IO clocks at 48
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,
USB, and IO clock frequencies are factory-EPROM program-
mable for easy customization with fast turnaround times.
— Seven 3.3V synchronous PCI clocks, one free
running
— Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable
by serial interface
— One 2.5V IOAPIC clock at 14.318 MHz
— Two 3.3V Ref. clocks at 14.318 MHz
The CY2277A has power-down, CPU stop and PCI stop pins
for power management control. The CPU stop and PCI stop
are controlled by the MODE pin. They are multiplexed with
SDRAM clock outputs, and are selected when the MODE pin
is driven LOW. Additionally, these inputs are synchronized
on-chip, enabling glitch-free transitions. When the
CPU_STOP input is asserted, the CPU outputs are driven
LOW. When the PCI_STOP input is asserted, the PCI outputs
(except the free-running PCI clock) are driven LOW. Finally,
when the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.
• Factory-EPROM programmable CPU, PCI, and USB/IO
clock frequencies for custom configuration
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• MODE Enable pin for CPU_STOP and PCI_STOP
• SMBus serial configuration interface
• Available in space-saving 48-pin SSOP and TSSOP
packages.
The CY2277A outputs are designed for low EMI emission.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate
enable optimal configurations for EMI control.
Functional Description
The CY2277A is a Clock Synthesizer/Driver for Pentium,
Pentium II, 6X86, and K6 portable PCs designed with the Intel®
.
Pin Configuration
Top View
Logic Block Diagram
IOAPIC (14.318 MHz)
VDDQ2
REF1
REF0
AV
1
48
47
46
45
44
43
42
41
DD
2
PWR_SEL
REF [0–1]
(14.318)
XTALIN
3
14.318
MHz
OSC.
V
V
SS
DDQ2
XTALIN
XTALOUT
MODE
4
IOAPIC
XTALOUT
5
PWR_DWN
STOP
LOGIC
CPU
PLL
CPUCLK[0–3]
6
V
SS
V
CPUCLK0
CPUCLK1
7
DDQ3
PCICLK_F
PCICLK0
8
VDDCPU
9
V
40
39
38
37
36
35
34
33
32
31
DDCPU
V
SS
10
11
SDRAM[0–5]
CPUCLK2
CPUCLK3
SEL
EPROM
PCICLK1
PCICLK2
12
13
V
SS
SDRAM0
SDRAM1
MODE
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
PCICLK3
PCICLK4
SYS
PLL
14
15
16
17
18
19
20
21
22
23
24
V
V
DDQ3
DDQ3
PCICLK5
V
SDRAM2
SDRAM3
/2
SS
SEL
V
SS
Delay
SDATA
SCLK
30
29
28
27
26
25
SDRAM4
SDRAM5
PWR_DWN
STOP
LOGIC
PCI[0–5]
V
V
DDQ3
DDQ3
PCICLK_F
USBCLK/IOCLK
USBCLK/IOCLK
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
SERIAL
INTERFACE
CONTROL
LOGIC
SCLK
Divide and
Mux Logic
USBCLK/IOCLK[0:1]
V
AV
DD
SS
SDATA
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 18
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com
CY2277A
Pin Summary
Name
VDDQ3
VDDQ2
VDDCPU
AVDD
Pins
Description
7, 15, 21, 28, 34
3.3V Digital voltage supply
IOAPIC Digital voltage supply, 2.5V
CPU Digital voltage supply, 2.5V or 3.3V
3.3V Analog voltage supply
46
40
25, 48
VSS
3, 10, 17, 24, 31, 37, 43 Ground
XTALIN[1]
XTALOUT[1]
MODE
SEL
4
Reference crystal input
5
Reference crystal feedback
6
Mode select input, enables power management features
18
Select input to enable 66.66 MHz or 60 MHz CPU clock (See Function
tables.)
SDATA
19
20
44
47
SMBus serial data input for serial configuration port
SCLK
SMBus serial clock input for serial configuration port
PWR_DWN
PWR_SEL
Active low control input to put osc., PLLs, and outputs in power down state
Power select input, indicates whether VDDCPU is at 2.5V or 3.3V
HIGH = 3.3V, LOW=2.5V (internal pull-up to VDD
)
SDRAM7/PCI_STOP 26
SDRAM6/CPU_STOP 27
SDRAM clock output. Also, active LOW control input to stop PCI clocks,
enabled when MODE is LOW
SDRAM clock output. Also, active LOW control input to stop CPU clocks,
enabled when MODE is LOW
SDRAM[0:5]
CPUCLK[0:3]
PCICLK[0:5]
PCICLK_F
IOAPIC
36, 35, 33, 32, 30, 29
SDRAM clock outputs, have same frequency as CPU clocks
CPU clock outputs
42, 41, 39, 38
9, 11, 12, 13, 14, 16
PCI clock outputs
8
PCI clock output, free-running
45
IOAPIC clock output
REF[0:1]
1, 2
22, 23
Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load
USB or IO clock outputs, frequency selected by serial word
USBCLK/IOCLK
Note:
1. For best accuracy, use a parallel-resonant crystal, C
= 18 pF.
LOAD
Table 1. CY2277A Selector Guide
Clock Outputs
-1/-1M
-3
-7M
4
-12/-12M/-12I
CPU (60, 66.6 MHz)
CPU (33.3, 66.6 MHz)
CPU (SMBus selectable)
PCI (CPU/2)
4
--
4
--
--
4
--
--
--
--
--
7[2]
6/8
2
7[2]
6/8
2
7[2]
6/8
2
7[2]
6/8
2
SDRAM
USB/IO (48 or 24 MHz)
IOAPIC (14.318 MHz)
Ref (14.318 MHz)
1
1
1
1
2
2
2
2
CPU-PCI delay
1–6 ns
1–6 ns
<1 ns
1–4 ns
Note:
2. One free-running PCI clock
Rev 1.0,November 25, 2006
Page 2 of 18
CY2277A
Function Table (-3)
CPUCLK[0:3]
SDRAM[0:7]
PCICLK[0:5]
PCICLK_F
REF[0:1]
IOAPIC
SEL
XTALIN
14.318 MHz
14.318 MHz
USBCLK / IOCLK[3]
0
1
33.33 MHz
66.67 MHz
16.67 MHz
33.33 MHz
14.318 MHz
14.318 MHz
48.0 MHz / 24.0 MHz
48.0 MHz / 24.0 MHz
Function Table (-1, -1M, -7M, -12, -12M, -12I)
CPUCLK[0:3]
SDRAM[0:7]
PCICLK[0:5]
PCICLK_F
REF[0:1]
IOAPIC
SEL
XTALIN
14.318 MHz
14.318 MHz
USBCLK / IOCLK[3]
48.0 MHz / 24.0 MHz
48.0 MHz / 24.0 MHz
0
1
60.0 MHz
66.67 MHz
30.0 MHz
33.33 MHz
14.318 MHz
14.318 MHz
Actual Clock Frequency Values (-1, -1M, -3, -7M, -12, -12M, -12I)
Target
Frequency (MHz)
Actual
Frequency (MHz)
Clock Output
CPUCLK, SDRAM
CPUCLK, SDRAM
USBCLK[4]
PPM
66.67
66.654
–195
0
60.0
48.0
24.0
60.0
48.008
24.004
167
167
IOCLK
• Output impedance: 25:ꢀ(typical) measured at 1.5V
CPU and PCI Clock Driver Strengths
• Matched impedances on both rising and falling edges on
the output drivers
Power Management Logic
CPU_STOP PCI_STOP PWR_DWN
CPUCLK
LOW
PCICLK
LOW
LOW
PCICLK_F Other Clocks
Osc.
Off
PLLs
Off
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Stopped
Running
Stopped
Running
Running
Running
Running
LOW
LOW
Running Running
Running Running
Running Running
Running Running
33/30 MHz Running
Running
66/60 MHz LOW
66/60 MHz 33/30 MHz Running
Select Functions
Outputs
Functional Description
Three-State
CPU
PCI, PCI_F
Hi-Z
TCLK/4
SDRAM
Hi-Z
TCLK/2
Ref
Hi-Z
TCLK
IOAPIC
Hi-Z
IOCLK
USBCLK
Hi-Z
Hi-Z
TCLK/2[5]
Hi-Z
Test Mode
TCLK
TCLK/4
TCLK/2
Notes:
3. On power-up, the default frequency on these outputs is 48 MHz.
4. Meets Intel USB clock requirements.
5. TCLK supplied on the XTALIN, PIN 4.
Rev 1.0,November 25, 2006
Page 3 of 18
CY2277A
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• SMBus Address for the CY2277A is:
Table 2.
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
----
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit 3 23
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
Bit Pin #
Bit 7 --
Description
(Reserved) drive to ‘0’
Bit 2 22
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
Bit 6 --
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M,
-12, -12M, -12I
Bit 1 --
Bit 0
Bit 1 Bit 0
1
1
0
0
1 - Three-State (see table below)
0 - N/A
1 - Test Mode (see table below)
0 - Normal Operation
Bit 5 --
Bit 4 --
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M,
-12, -12M, -12I
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M,
-12, -12M, -12I
Rev 1.0,November 25, 2006
Page 4 of 18
CY2277A
Byte 1: CPU, 24/48 MHz Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Byte 2: PCI Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
23
Description
48/24 MHz (Active/Inactive)
48/24 MHz (Active/Inactive)
(Reserved) drive to ‘0’
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Description
(Reserved) drive to ‘0’
--
8
22
--
PCICLK_F (Active/Inactive)
PCICLK5 (Active/Inactive)
PCICLK4 (Active/Inactive)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
PCICLK1 (Active/Inactive)
PCICLK0 (Active/Inactive)
16
14
13
12
11
9
N/A
38
39
41
42
Not Used, drive 0
CPUCLK3 (Active/Inactive)
CPUCLK2 (Active/Inactive)
CPUCLK1 (Active/Inactive)
CPUCLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Byte 4: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit Pin #
Bit 7 26
Bit 6 27
Bit 5 29
Bit 4 30
Bit 3 32
Bit 2 33
Bit 1 35
Bit 0 36
Description
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
N/A
Description
Not used, drive to ‘0’
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Byte 5: Peripheral Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Byte 6: Reserved, for future use
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Description
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
IOAPIC (Active/Inactive)
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
REF1 (Active/Inactive)
REF0 (Active/Inactive)
--
--
--
45
--
--
1
2
Rev 1.0,November 25, 2006
Page 5 of 18
CY2277A
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Junction Temperature............................................... +150qC
Supply Voltage..................................................–0.5 to +7.0V
Input Voltage............................................ –0.5V to VDD + 0.5
Storage Temperature (Non-Condensing)....–65qC to +150qC
Operating Conditions[6]
Package Power Dissipation.............................................. 1W
Static Discharge Voltage............................................ >2000V
(per MIL-STD-883, Method 3015, like VDD pins tied together)
Parameter
AVDD, VDDQ3
VDDCPU
Description
Analog and Digital Supply Voltage
Min.
Max.
Unit
V
3.135
3.465
2.5V CPU Supply Voltage (-1,-1M, -3, -7M)
2.5V CPU Supply Voltage (-12, -12M, -12I)
3.3V CPU Supply Voltage
2.375
2.375
3.135
2.9
2.625
3.465
V
VDDQ2
2.5V IOAPIC Supply Voltage (-1,-1M, -3, -7M)
2.5V IOAPIC Supply Voltage (-12, -12M, -12I)
3.3V IOAPIC Supply Voltage
2.375
2.375
3.135
2.9
2.625
3.465
V
TA
TA
CL
Operating Temperature, Commercial
Operating Temperature, Industrial
0
70
85
qC
qC
pF
–40
Max. Capacitive Load on
CPUCLK, USBCLK/IOCLK, REF1, IOAPIC
PCICLK, SDRAM
10
30, 20
20
20
30
45
REF0
f(REF)
tPU
Reference Frequency, Oscillator Nominal Value
14.318
14.318
MHz
ms
Power-up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
0.05
50
Electrical Characteristics (-1, -3, -12)
Parameter
VIH
Description
Test Conditions
Min. Max. Unit
High-level Input Voltage
Low-level Input Voltage
Low-level Input Voltage
High-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V
Low-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V
High-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V
Except Crystal Inputs
Except Crystal Inputs
SMBus inputs only
2.0
V
V
V
V
VIL
0.8
0.7
VILiic
VOH
IOH = 18 mA CPUCLK 2.0
OH = 18 mA IOAPIC
I
VOL
IOL = 29 mA CPUCLK
IOL = 29 mA IOAPIC
0.4
V
V
VOH
IOH = 32 mA CPUCLK 2.4
I
OH = 36 mA SDRAM
IOH = 32 mA PCICLK
I
I
OH = 26 mA USBCLK
OH = 26 mA IOCLK
IOH = 36 mA REF0
OH = 26 mA REF1
I
VOL
Low-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V
IOL = 24 mA CPUCLK
IOL = 29 mA SDRAM
0.4V
V
I
I
I
OL = 26 mA PCICLK
OL = 21 mA USBCLK
OL = 21 mA IOCLK
IOL = 29 mA REF0
OL = 21 mA REF1
I
Rev 1.0,November 25, 2006
Page 6 of 18
CY2277A
Electrical Characteristics (-1, -3, -12) (continued)
Parameter
Description
Input High Current
Input Low Current
Test Conditions
Min. Max. Unit
IIH
VIH = VDD
–10 +10 PA
IIL
VIL = 0V, except PWR_SEL
VIL = 0V, PWR_SEL only
Three-state
10
PA
IIL
Input Low Current
100 PA
–10 +10 PA
250 mA
IOZ
IDD
IDD
IDDS
Output Leakage Current
Power Supply Current[7, 8] VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz
Power Supply Current[7, 8] VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs
120 mA
Power-down Current
Current draw in power-down state, PWR_SEL = VDD
150 PA
Electrical Characteristics (-1M, -7M, -12M)
Parameter
VIH
Description
Test Conditions
Min. Max. Unit
High-level Input Voltage
Low-level Input Voltage
Low-level Input Voltage
High-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V
Low-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V
High-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V
Except Crystal Inputs
Except Crystal Inputs
SMBus inputs only
2.0
V
V
V
V
VIL
0.8
0.7
VILiic
VOH
IOH = 12.6 mA CPUCLK 1.75
IOH = 16.7mA IOAPIC
VOL
IOL = 18.2 mA CPUCLK
IOL = 23.1 mA IOAPIC
0.4
V
V
VOH
IOH = 32.2 mA SDRAM
IOH = 32.2 mA PCICLK
IOH = 32.2 mA USBCLK
IOH = 32.2 mA IOCLK
IOH = 32.2 mA REF0
IOH = 32.2 mA REF1
IOL = 23.8 mA SDRAM
IOL = 23.8 mA PCICLK
IOL = 23.8 mA USBCLK
IOL = 23.8 mA IOCLK
IOL = 23.8 mA REF0
IOL = 23.8 mA REF1
2.4
VOL
Low-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V
0.8V
V
IIH
Input High Current
Input Low Current
Input Low Current
Output Leakage Current
Power Supply Current[7, 8] VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz
Power Supply Current[7, 8] VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs
VIH = VDD
–10 +10 PA
10 PA
IIL
VIL = 0V, except PWR_SEL
VIL = 0V, PWR_SEL only
Three-state
IIL
100 PA
–10 +10 PA
250 mA
IOZ
IDD
IDD
IDDS
120 mA
Power-down Current
Current draw in power-down state, PWR_SEL = VDD
150 PA
Notes:
6. Electrical parameters are guaranteed with these operating conditions.
7. Guaranteed by design and characterization. Not 100% tested in production.
8. Power supply current will vary with number of outputs which are running.
Rev 1.0,November 25, 2006
Page 7 of 18
CY2277A
Electrical Characteristics (-12I)
Parameter
VIH
Description
Test Conditions
Min. Max. Unit
High-level Input Voltage
Low-level Input Voltage
Low-level Input Voltage
High-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V
Low-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V
High-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V
Except Crystal Inputs
Except Crystal Inputs
SMBus inputs only
2.0
V
V
V
V
VIL
0.8
0.7
VILiic
VOH
IOH = 18 mA
IOH = 18 mA
IOL = 29 mA
IOL = 29 mA
IOH = 32 mA
IOH = 36 mA
IOH = 32 mA
IOH = 26 mA
IOH = 26 mA
CPUCLK 1.75
IOAPIC
VOL
CPUCLK
IOAPIC
0.4
V
V
VOH
CPUCLK 2.4
SDRAM
PCICLK
USBCLK
IOCLK
I
OH = 36 mA
REF0
IOH = 26 mA
IOH = 24mA
IOH = 29 mA
IOH = 26 mA
IOL = 21 mA
IOH = 21 mA
IOL = 29mA
IOH = 21 mA
REF1
VOL
Low-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V
CPUCLK
SDRAM
PCICLK
USBCLK
IOCLK
0.8V
V
REF0
REF1
IIH
Input High Current
Input Low Current
Input Low Current
Output Leakage Current
Power Supply Current[7, 8] VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz
Power Supply Current[7, 8] VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs
VIH = VDD
–20 +20 PA
10 PA
IIL
VIL = 0V, except PWR_SEL
VIL = 0V, PWR_SEL only
Three-state
IIL
100 PA
–10 +10 PA
250 mA
IOZ
IDD
IDD
IDDS
120 mA
Power-down Current
Current draw in power-down state, PWR_SEL = VDD
150 PA
Rev 1.0,November 25, 2006
Page 8 of 18
CY2277A
Switching Characteristics (-1, -3)[9, 10, 11]
Parameter
Output
Description
Output Duty Cycle[12]
Test Conditions
t1 = t1A y t1B
Min. Typ. Max.
Unit
t1
CPUCLK
SDRAM
USBCLK
IOCLK
45
50
55
%
REF [0,1]
IOAPIC
t1
t2
PCI
Output Duty Cycle[12]
t1 = t1A y t1B
40
50
55
%
CPUCLK, CPU and IOAPIC Clock
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.75
Rising and Falling Edge Between 0.4V and 2.4V, VDDCPU = 3.3V 0.75
Rate
4.0
4.0
V/ns
IOAPIC
PCI
CPU clocks at 66.66 MHz
t2
t2
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V, VDDCPU = 3.3V 0.75
4.0
4.0
V/ns
V/ns
USBCLK, USB, I/O, REF0 Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.4V
0.8
IOCLK,
REF0
t2
t2
t3
t3
t4
t4
SDRAM
SDRAM Rising and
Falling Edge Rate
Between 0.4V and 2.4V
SDRAM clocks at 66.66 MHz
1.0
0.5
4.0
2.0
V/ns
V/ns
ns
REF1
REF1 Rising and Falling Between 0.4V and 2.4V
Edge Rate
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.4
Between 0.4V and 2.4V, VDDCPU = 3.3V 0.5
2.13
2.0
USBCLK, USB Clock and I/O Clock Between 0.4V and 2.4V
Rise Time
2.5
ns
IOCLK
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V 0.4
Between 2.4V and 0.4V, VDDCPU = 3.3V 0.5
2.13
2.0
ns
USBCLK, USB Clock and I/O Clock Between 2.4V and 0.4V
Fall Time
2.5
ns
IOCLK
t5
t6
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
100
2.0
400
6.0
ps
ns
CPUCLK, CPU-PCI Clock Skew
PCICLK (-1, -3)
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1.0
t7
t8
CPUCLK, CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
775
450
ps
ps
SDRAM
CPUCLK
Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks
t8
t8
t8
SDRAM
PCICLK
Cycle-Cycle Clock Jitter Measured at 1.5V for 3.3V clocks
Cycle-Cycle Clock Jitter Measured at 1.5V
650
500
1.3
ps
ps
ns
USBCLK, Cycle-Cycle Clock Jitter Measured at 1.5V
IOCLK
t9
CPUCLK, Power-up Time
PCICLK,
SDRAM
CPU, PCI, and SDRAM clock stabili-
zation from power-up
3
ms
t10
CPU, PCI, Frequency Slew Rate
SDRAM
Rate of change of frequency
2
MHz/
ms
Notes:
9. All parameters specified with loaded outputs.
10. Over the operating range unless otherwise specified.
11. Parameters specified with: V
12. Duty cycle is measured at 1.5V when V = 3.3V. When V
DD
= 2.5V, V
= 2.5V, V
= 3.3V.
= 2.5V, CPUCLK duty cycle is measured at 1.25V.
DDCPU
DDQ2
DDQ3
DDCPU
Rev 1.0,November 25, 2006
Page 9 of 18
CY2277A
Switching Characteristics (-1M, -7M, -12M)[9, 10, 11]
Parameter
Output
Description
Output Duty Cycle[12]
Test Conditions
t1 = t1A y t1B
Min. Typ. Max.
Unit
t1
CPUCLK
SDRAM
USBCLK
REF [0,1]
IOAPIC
45
50
55
%
t1
t2
PCI
Output Duty Cycle[12]
t1 = t1A y t1B
45
50
55
%
CPUCLK, CPU and IOAPIC Clock
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.60
4.0
V/ns
IOAPIC
PCI
Rising and Falling Edge CPU clocks at 66.66 MHz
Rate
t2
t2
t2
t2
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.65
4.0
4.0
4.0
2.0
V/ns
V/ns
V/ns
V/ns
USBCLK, USB, REF0 Clock Rising Between 0.4V and 2.4V
and Falling Edge Rate
0.65
0.70
0.5
REF0
SDRAM
SDRAM Rising and
Falling Edge Rate
Between 0.4V and 2.4V
SDRAM clocks at 66.66 MHz
REF1
REF1 Rising and Falling Between 0.4V and 2.4V
Edge Rate
t3
t3
t4
t4
t5
t5
t5
CPUCLK
USBCLK
CPUCLK
USBCLK
CPUCLK
PCICLK
SDRAM
CPU Clock Rise Time
USB Clock Rise Time
CPU Clock Fall Time
USB Clock Fall Time
CPU-CPU Clock Skew
PCI-PCI Clock Skew
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.4
Between 0.4V and 2.0V
2.4
2.5
ns
ns
ns
ns
ps
ps
ps
Between 2.0V and 0.4V, VDDCPU = 2.5V 0.4
Between 2.0V and 0.4V
2.4
2.5
Measured at 1.25V, VDDCPU = 2.5V
Measured at 1.5V
100
2.0
250
400
300
SDRAM-SDRAM Clock
Skew
Measured at 1.5V
t6
t6
t7
CPUCLK, CPU-PCI Clock Skew
PCICLK -1M, -12M
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1.0
6.0
750
600
ns
ps
ps
CPUCLK, CPU-PCI Clock Skew
PCICLK -7M
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
CPUCLK, CPU-SDRAM Clock
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
SDRAM
CPUCLK
SDRAM
PCICLK
Skew
t8
t8
t8
t8
Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks
Cycle-Cycle Clock Jitter Measured at 1.5V
525
600
400
900
ps
ps
ps
ps
Cycle-Cycle Clock Jitter Measured at 1.5V
USBCLK, Cycle-Cycle Clock Jitter Measured at 1.5V
IOCLK
t9
CPUCLK, Power-up Time
PCICLK,
SDRAM
CPU, PCI, and SDRAM clock stabili-
zation from power-up
3
ms
t10
CPU, PCI, Frequency Slew Rate
SDRAM
Rate of change of frequency
2
MHz/
ms
Rev 1.0,November 25, 2006
Page 10 of 18
CY2277A
Switching Characteristics (-12)[9, 10, 11]
Parameter
Output
Description
Test Conditions
t1 = t1A y t1B
Between 0.6V and 1.8V, VDDCPU = 2.5V 1.0
Min. Typ. Max.
Unit
%
t1
t2
All Clocks Output Duty Cycle[12]
45
50
55
CPUCLK, CPU and IOAPIC Clock
4.0
4.0
V/ns
IOAPIC
PCI
Rising and Falling Edge Between 0.4V and 2.4V, VDDCPU = 3.3V 1.0
Rate
CPU clocks at 66.6 MHz
t2
t2
t2
t2
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V, VDDCPU = 3.3V 1.0
4.0
4.0
4.0
2.0
V/ns
V/ns
V/ns
V/ns
REF0
SDRAM
REF0 Clock Rising and
Falling Edge Rate
Between 0.8V and 2.4V, VDDCPU = 3.3V 1.0
SDRAM Rising and
Falling Edge Rate
Between 0.5V and 2.0V
SDRAM clocks at 66.6 MHz
1.5
0.5
REF1
USBCLK
IOCLK
REF1,USBandIORising Between 0.4V and 2.4V
and Falling Edge Rate
t3
t3
t4
t4
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.4
Between 0.4V and 2.4V, VDDCPU = 3.3V 0.4
2.0
2.0
ns
ns
ns
ns
USBCLK, USB Clock and I/O Clock Between 0.4V and 2.4V
Rise Time
1.0
4.0
IOCLK
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V 0.4
Between 2.4V and 0.4V, VDDCPU = 3.3V 0.4
2.0
2.0
USBCLK, USB Clock and I/O Clock Between 2.4V and 0.4V
Fall Time
1.0
4.0
IOCLK
t5
t6
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
100
250
4.0
ps
ns
CPUCLK, CPU-PCI Clock Skew
PCICLK (-12)
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1.0
t7
t8
CPUCLK, CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
500
250
ps
ps
SDRAM
CPUCLK
Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks
t8
t9
PCICLK
Cycle-Cycle Clock Jitter Measured at 1.5V
500
3
ps
CPUCLK, Power-up Time
PCICLK,
SDRAM
CPU, PCI, and SDRAM clock stabili-
zation from power-up
ms
t10
CPU, PCI, Frequency Slew Rate
SDRAM
Rate of change of frequency
2
MHz/
ms
Rev 1.0,November 25, 2006
Page 11 of 18
CY2277A
Switching Characteristics (-12I)[9, 10, 11]
Parameter
Output
Description
Test Conditions
t1 = t1A y t1B
Between 0.6V and 1.8V, VDDCPU = 2.5V 1.0
Min. Typ. Max.
Unit
%
t1
t2
All Clocks Output Duty Cycle[12]
45
50
55
CPUCLK, CPU and IOAPIC Clock
4.0
4.0
V/ns
IOAPIC
PCI
Rising and Falling Edge Between 0.4V and 2.4V, VDDCPU = 3.3V
.8
Rate
CPU clocks at 66.6 MHz
t2
t2
t2
t2
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V, VDDCPU = 3.3V
.9
4.0
4.0
4.0
2.0
V/ns
V/ns
V/ns
V/ns
REF0
SDRAM
REF0 Clock Rising and
Falling Edge Rate
Between 0.8V and 2.4V, VDDCPU = 3.3V 1.0
SDRAM Rising and
Falling Edge Rate
Between 0.5V and 2.0V
SDRAM clocks at 66.6 MHz
1
REF1
USBCLK
IOCLK
REF1,USBandIORising Between 0.4V and 2.4V
and Falling Edge Rate
0.5
t3
t3
t4
t4
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.4
Between 0.4V and 2.4V, VDDCPU = 3.3V 0.4
3.0
2.0
ns
ns
ns
ns
USBCLK, USB Clock and I/O Clock Between 0.4V and 2.4V
Rise Time
1.0
4.0
IOCLK
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V 0.4
Between 2.4V and 0.4V, VDDCPU = 3.3V 0.4
3.0
2.0
USBCLK, USB Clock and I/O Clock Between 2.4V and 0.4V
Fall Time
1.0
4.0
IOCLK
t5
t6
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
100
250
4.0
ps
ns
CPUCLK, CPU-PCI Clock Skew
PCICLK (-12)
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1.0
t7
t8
CPUCLK, CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
625
350
ps
ps
SDRAM
CPUCLK
Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks, VDDCPU =2.5V
t8
t9
PCICLK
Cycle-Cycle Clock Jitter Measured at 1.5V
500
3
ps
CPUCLK, Power-up Time
PCICLK,
SDRAM
CPU, PCI, and SDRAM clock stabili-
zation from power-up
ms
t10
CPU, PCI, Frequency Slew Rate
SDRAM
Rate of change of frequency
2
MHz/
ms
Rev 1.0,November 25, 2006
Page 12 of 18
CY2277A
Timing Requirement for the SMBus
Parameter
Description
Min.
0
Max.
Unit
kHz
Ps
t10
t11
t12
t13
t14
t15
t16
SCLK Clock Frequency
100
Time the bus must be free before a new transmission can start
Hold time start condition. After this period the first clock pulse is generated.
The LOW period of the clock.
4.7
4
Ps
4.7
4
Ps
The HIGH period of the clock.
Ps
Setup time for start condition. (Only relevant for a repeated start condition.)
4.7
Ps
Hold time DATA
for CBUS compatible masters.
for SMBus devices
Ps
5
0
t17
t18
t19
t20
DATA input set-up time
250
ns
Ps
ns
Ps
Rise time of both SDATA and SCLK inputs
Fall time of both SDATA and SCLK inputs
Set-up time for stop condition
1
300
4.0
Switching Waveforms
Duty Cycle Timing
t
1B
t
1A
CPUCLK Outputs HIGH/LOW Time
t
1C
VDD
0V
OUTPUT
t
1D
All Outputs Rise/Fall Time
VDD
0V
OUTPUT
t
2
t
3
t
2
t
4
Rev 1.0,November 25, 2006
Page 13 of 18
CY2277A
Switching Waveforms (continued)
CPU-CPU Clock Skew
CLK
CLK
t
5
CPU-SDRAM Clock Skew
CPUCLK
SDRAM
t
7
CPU-PCI Clock Skew
CPUCLK
PCICLK
t6
CPU_STOP [13, 14]
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPUCLK
(External)
Notes:
13. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.
14. CPU_STOP may be applied asynchronously. It is synchronized internally.
Rev 1.0,November 25, 2006
Page 14 of 18
CY2277A
Switching Waveforms (continued)
PCI_STOP[15, 16]
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
PCI_STOP
PCICLK
(External)
PWR_DOWN
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN#
CPUCLK
(External)
PCICLK
(External)
VCO
Crystal
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Timing Requirements for the SMBus
SDA
t
t
t
t
11
19
18
12
SCL
t
12
t
t
15
20
t
t
t
17
t
13
14
16
Notes:
15. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK.
16. PCI_STOP may be applied asynchronously. It is synchronized internally.
Rev 1.0,November 25, 2006
Page 15 of 18
CY2277A
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done.
Application Circuit
Summary
• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of
this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different
CLOAD is used. Footprints can be laid out for flexibility.
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 PF.
In some cases, smaller value capacitors may be required.
• Thevalueofthe series terminating resistorsatisfies the followingequation, whereRtrace is theloaded characteristic impedance
ofthetrace,Rout istheoutputimpedanceoftheclockgenerator(specifiedinthedatasheet), andRseries istheseriesterminating
resistor.
Rseries > Rtrace – Rout
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers
greater than 50: impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout
and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10 PF– 22 PF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
Rev 1.0,November 25, 2006
Page 16 of 18
CY2277A
Test Circuit
VDDQ3
48
3
0.1 PF
0.1 PF
46
VDDQ2
7
0.1 PF
43
40
10
VDDCPU
0.1 PF
0.1 PF
37
34
15
0.1 PF
17
21
31
28
0.1 PF
0.1 PF
0.1 PF
25
24
OUTPUTS
CLOAD
Note:All capacitors should be placed as close to each pin as possible.
Ordering Information
Package
Name
Operating
Range
Ordering Code
CY2277APVC-1
Package Type
48-Pin SSOP
O48
Z48
O48
Z48
O48
Z48
O48
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
CY2277APAC-1M
CY2277APVC-3
48-Pin TSSOP
48-Pin SSOP
48-Pin TSSOP
48-Pin SSOP
48-Pin TSSOP
48-Pin SSOP
CY2277APAC-7M
CY2277APVC-12
CY2277APAC-12M
CY2277APVI-12
Rev 1.0,November 25, 2006
Page 17 of 18
CY2277A
Package Drawing and Dimension
48-Lead Shrunk Small Outline Package O48
48-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 25, 2006
Page 18 of 18
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