5962-01-418-4492 [CYPRESS]
EEPROM Card, 8KX8, 25ns, CMOS, CQCC28,;
| 型号： | 5962-01-418-4492 |
| 厂家： | 
CYPRESS |
| 描述： | EEPROM Card, 8KX8, 25ns, CMOS, CQCC28, 可编程只读存储器 OTP只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
65
CY7C265
8K x 8 Registered PROM
are enabled. One pin on the CY7C265 is programmed to per-
form either the enable or the initialize function.
Features
• CMOS for optimum speed/power
• High speed (commercial and military)
— 15 ns address set-up
If the asynchronous enable (E) is being used, the outputs may
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the active state by switching the
enable to a logic LOW.
— 12 ns clock to output
• Low power
If the synchronous enable (ES) is being used, the outputs will
go to the OFF or high-impedance state upon the next positive
clock edge after the synchronous enable input is switched to a
HIGH level. If the synchronous enable pin is switched to a logic
LOW, the subsequent positive clock edge will return the output
tothe activestate. Followingapositive clock edge, theaddress
and synchronous enable inputs are free to change since no
change in the output will occur until the next LOW-to-HIGH
transitionof theclock. This uniquefeatureallows the CY7C265
decoders and sense amplifiers to access the next location
whilepreviously addresseddataremains stable on theoutputs.
— 660 mW (commercial)
— 770 mW (military)
• On-chip edge-triggered registers
— Ideal for pipelined microprogrammed systems
• EPROM technology
— 100% programmable
— Reprogrammable (7C265W)
• 5V ±10% VCC, commercial and military
• Capable of withstanding >2001V static discharge
• Slim 28-pin, 300-mil plastic or hermetic DIP
If the E/I pin is used for INIT (asynchronous), then the outputs
are permanently enabled. The initialize function is useful dur-
ing power-up and time-out sequences, and can facilitate im-
plementation of other sophisticated functions such as a built-in
“jump start” address. When activated, the initialize control in-
put causes the contents of a user programmed 8193rd 8-bit
word to be loaded into the on-chip register. Each bit is pro-
grammable and the initialize function can be used to load any
desired combination of 1’s and 0’s into the register. In the un-
programmed state, activating INIT will generate a register
clear (all outputs LOW). If all the bits of the initialize word are
programmed to be a 1, activating INIT performs a register pre-
set (all outputs HIGH).
Functional Description
The CY7C265 is a 8192 x 8 registered PROM. It is organized
as 8,192 words by 8 bits wide, and has a pipeline output reg-
ister. In addition, the device features a programmable initialize
byte that may be loaded into the pipeline register with the ini-
tialize signal. The programmable initialize byte is the 8,193rd
byte in the PROM and its value is programmed at the time of
use.
Packaged in 28 pins, the PROM has 13 address signals (A0
through A12), 8 data out signals (O0 through O7), E/I (enable
or initialize), and CLOCK.
Applying a LOW to the INIT input causes an immediate load of
the programmed initialize word into the pipeline register and
onto the outputs. The INIT LOW disables clock and must return
HIGH to enable clock independent of all other inputs, including
the clock.
CLOCK functions as a pipeline clock, loading the contents of
the addressed memory location into the pipeline register on
each rising edge. The data will appear on the outputs if they
Cypress Semiconductor Corporation
Document #: 38-04012 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised March 14, 2002
CY7C265
Logic Block Diagram
Pin Configurations
DIP/Flatpack
Top View
A
A
1
28
27
26
V
CC
12
7
O
O
7
A
6
2
A
8
A
A
11
A
5
3
A
9
10
6
A
4
A
10
4
25
24
23
22
21
COLUMN
MULTIPLEXER
A
9
ROW
A
3
5
PROGRAMMABLE
ARRAY
A
A
11
ADDRESS
7C265
A
8
A
2
O
5
O
4
O
3
6
12
GND
CLK
A
7
E/E ,I
S
7
GND
GND
8
A
8-BIT
EDGE-
TRIGGERED
REGISTER
ADDRESS
DECODER
6
A
1
9
20
19
18
17
16
A
5
A
0
O
7
10
11
12
13
A
5
O
0
O
6
A
4
O
1
O
5
O
2
O
1
A
3
O
2
O
4
COLUMN
ADDRESS
A
GND
O
3
2
14
15
A
1
A
0
O
0
LCC/PLCC (Opaque Only)
Top View
CLK
PROGRAMMABLE
MULTIPLEXER
A
A
A
A V
A
A
4
5
6
7
CC
8 9
D
C
O
INIT/E/E
S
3
2 1 28 27
4
26
25
CLK
A
A
A
10
3
5
6
7
8
9
A
2
24
23
22
21
20
19
11
12
GND
CLK
A
E/E ,I
S
A
1
GND
A
0
GND
O
7
10
11
O
0
13 14 15 16 17 18
12
O
1
O GND O O O O
2 3 4 5 6
F
Selection Guides
7C265–15
15
7C265–25
25
7C265–40
7C265–50
Minimum Address Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating Current (mA)
40
20
50
25
12
15
Com’l
120
120
100
80
Mil
140
140
120
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Range
Commercial
Industrial[1]
Temperature
VCC
Supply Voltage to Ground Potential............... –0.5V to +7.0V
0°C to +70°C
5V ±10%
5V ±10%
5V ±10%
DC Voltage Applied to Outputs
in High Z State............................................... –0.5V to +7.0V
–40°C to +85°C
–55°C to +125°C
Military[2]
DC Input Voltage............................................ –3.0V to +7.0V
DC Program Voltage.....................................................13.0V
UV Exposure.................................................7258 Wsec/cm2
Notes:
1. Contact a Cypress representative for industrial temperature range spec-
ifications.
2. TA is the “instant on” case temperature.
Document #: 38-04012 Rev. **
Page 2 of 13
CY7C265
Electrical Characteristics Over the Operating Range[3]
7C265-15, 25 7C265-40
7C265-50
Parameter
Description
Test Conditions
VCC = Min., IOH = –2.0 mA
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA Com’l
VCC = Min., IOL = 12.0 mA
VCC = Min., IOL = 6.0 mA Mil
VCC = Min., IOL = 8.0 mA
Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage
2.4
2.0
V
V
2.4
2.0
2.4
VOL
Output LOW Voltage
0.4
0.4
0.4
0.8
0.4
0.4
0.8
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
2.0
V
V
0.8
GND < VIN < VCC
–10
–40
+10 –10 +10 –10 +10 µA
+40 –40 +40 –40 +40 µA
IOZ
GND < VOUT < VCC
,
Output Disabled
[4]
IOS
Output Short Circuit Current VCC = Max., VOUT = GND
90
120
140
13
90
90
80
mA
mA
ICC
VCC Operating Supply
Current
VCC = Max., IOUT = 0 mA Com’l
100
Mil
120
13
VPP
IPP
Programming Supply Voltage
Programming Supply Current
12
12
13
50
12
V
mA
V
50
50
VIHP
Input HIGH Programming
Voltage
3.0
3.0
3.0
VILP
Input LOW Programming
Voltage
0.4
0.4
0.4
V
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
10
10
COUT
pF
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
5. See Introduction to CMOS PROMs in this Data Book for general information on testing.
Document #: 38-04012 Rev. **
Page 3 of 13
CY7C265
AC Test Loads and Waveforms
Test Load for -15 through -25 speeds
R1 500
R1 500Ω
(658Ω MIL)
(658Ω MIL)
5V
5V
OUTPUT
3.0V
GND
90%
10%
OUTPUT
90%
10%
R2 333Ω
(403Ω MIL)
R2 333Ω
(403Ω MIL)
30 pF
5 pF
≤ 5 ns
≤ 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a) NormalLoad
(b) High Z Load
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
200Ω
OUTPUT
250Ω MIL
Test Load for -40 through -50 speeds
R1 250Ω
R1 250Ω
5V
5V
OUTPUT
OUTPUT
30 pF
5 pF
R2 167Ω
R2 167Ω
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(c) Normal Load
(d) High Z Load
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
100Ω
R
TH
2.0V
Switching Characteristics Over the Operating Range[3, 5]
7C265-15
7C265-25
7C265-40
Min. Max.
7C265-50
Min. Max.
Parameter
tAS
Description
Address Set-Up to Clock
Address Hold from Clock
Clock to Output Valid
Clock Pulse Width
Min.
15
0
Max.
Min.
25
0
Max.
Unit
ns
40
0
50
0
tHA
ns
tCO
12
15
20
25
25
35
ns
tPWC
tSES
12
12
15
15
15
15
20
15
ns
ES Set-Up to Clock
(Sync. Enable Only)
ns
tHES
tDI
ES Hold from Clock
INIT to Output Valid
INIT Recovery to Clock
INIT Pulse Width
5
5
5
5
ns
ns
ns
ns
ns
15
18
tRI
12
12
15
15
20
25
25
35
tPWI
tCOS
Output Valid from Clock
(Sync. Mode)
12
12
12
12
15
15
15
15
20
20
20
20
25
25
25
25
tHZC
tDOE
tHZE
Output Inactive from Clock
(Sync. Mode)
ns
ns
ns
Output Valid from E LOW
(Async. Mode)
Output Inactive from E HIGH
(Async. Mode)
Document #: 38-04012 Rev. **
Page 4 of 13
CY7C265
Switching Waveform
ADDRESS
t
AS
t
SYNCHRONOUS
ENABLE
(PROGRAMMABLE)
AH
t
HES
t
SES
CLOCK
t
t
t
CO
PWC
COS
VALID DATA
OUTPUT
t
DOE
t
DI
t
HZC
t
HZE
t
PWI
ASYNCHRONOUS INIT
(PROGRAMMABLE)
t
RI
ASYNCHRONOUS
ENABLE
Control Byte
Erasure Characteristics
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronous initialize
Wavelengths of light less than 4000 angstroms begin to erase
the 7C265 in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM
is exposed to sunlight or fluorescent lighting for extended pe-
riods of time.
Programming Modes
The 7C265 offers a limited selection of programmed architec-
tures. Programming these features should be done with a sin-
gle 10-ms-wide pulse in place of the intelligent algorithm,
mainly because these features are verified operationally, not
with the VFY pin. Architecture programming is implemented by
applying the supervoltage to two additional pins during pro-
gramming. In programming the 7C265 architecture, VPP is ap-
plied to pins 3, 9, and 22. The choice of a particular mode
depends on the states of the other pins during programming,
so it is important that the condition of the other pins be met as
set forth in the mode table. The considerations that apply with
respect to power-up and power-down during intelligent pro-
gramming also apply during architecture programming. Once
the supervoltages have been established and the correct logic
states exist on the other device pins, programming may begin.
Programming is accomplished by pulling PGM from HIGH to
LOW and then back to HIGH with a pulse width equal to 10 ms.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV inten-
sity • exposure time) of 25 Wsec/cm2. For an ultraviolet lamp
with a 12 mW/cm2 power rating the exposure time would be
approximately 45 minutes. The 7C265 needs to be within one
inch of the lamp during erasure. Permanent damage may re-
sult if the PROM is exposed to high-intensity UV light for an
extended period of time. 7258 Wsec/cm2 is the recommended
maximum dosage.
Bit Map Data
Programmer Address (Hex.)
RAM Data
Contents
Decimal
Hex
0
.
.
0
.
.
Data
.
.
8191
8192
8193
1FFF
2000
2001
Data
INIT Byte
Control Byte
Document #: 38-04012 Rev. **
Page 5 of 13
CY7C265
Table 1. Mode Selection
Pin Function
Read or Output Disable
Other
A12
A12
A12
A12
A12
A12
A12
A12
VIHP
VILP
A12
A11
A11
A11
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10 – A7
A6
A6
A5
A5
A4–A3
A2
A2
Mode
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
Asynchronous Enable Read
Synchronous Enable Read
Asynchronous Initialization Read
Program Memory
A6
A5
A2
A11
A6
A5
A2
A11
A6
A5
A2
A11
A6
A5
A2
Program Verify
A11
A6
A5
A2
Program Inhibit
A11
A6
A5
A2
Program Synchronous Enable
Program Initialize
VIHP
VIHP
VILP
VIHP
VIHP
VIHP
VPP
VPP
VPP
VIHP
VILP
VILP
Program Initial Byte
Pin Function
Read or Output Disable
Other
A1
A1
A0
GND
CLK
GND
E, I
O7–O0
D7–D0
O7–O0
O7–O0
O7–O0
D7–D0
O7–O0
High Z
D7–D0
D7–D0
D7–D0
Mode
A0
A0
PGM
GND
GND
GND
VILP
VIHP
VIHP
VILP
VILP
VILP
CLK
VIL
VFY
GND
GND
GND
VIHP
VILP
VPP
VIL
Asynchronous Enable Read
Synchronous Enable Read
Asynchronous Initialization Read
Program Memory
A1
A1
A0
VIL/VIH
VIL
VIL
A1
A0
VIL
A1
A0
VILP
VILP
VILP
VILP
VILP
VILP
VPP
VPP
VPP
VPP
VPP
VPP
Program Verify
A1
A0
Program Inhibit
A1
A0
VIHP
VIHP
VIHP
VIHP
Program Synchronous Enable
Program Initialize
VPP
VPP
VPP
VILP
VILP
VIHP
Program Initial Byte
DIP/Flatpack
LCC/PLCC (Opaque Only)
1
28
27
26
A
7
A
6
A
5
V
CC
2
3
A
8
3
2 1 28 27
4
26
25
A
9
A
A
A
V
NA
VFY
A
10
11
12
5
6
7
8
9
3
A
4
25
24
23
22
21
4
A
A
A
10
11
12
24
23
22
21
20
19
A
2
A
A
5
3
PGM
CLK
6
PP
2
A
1
PGM
CLK
7
8
V
PP
A
0
10
11
NA
D
0
D
7
A
1
9
20
19
18
17
16
VFY
1314151617 18
12
A
0
10
11
12
13
D
7
D
6
D
0
D
1
D
5
D
2
D
4
GND
D
3
14
15
Figure 1. Programming Pinout
programming information, including a listing of software pack-
ages, please see the PROM Programming Information located
at the end of this section. Programming algorithms can be ob-
tained from any Cypress representative.
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
Document #: 38-04012 Rev. **
Page 6 of 13
CY7C265
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
60
50
1.6
1.2
1.1
1.4
1.2
40
30
20
I
CC
1.0
0.9
I
CC
1.0
0.8
0.6
10
0
T =25°C
f=MAX.
A
0.8
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
175
150
35
30
1.6
1.4
125
100
75
25
20
15
1.2
1.0
50
10
5
0.8
V
CC
=4.5V
V
=5.0V
25
0
CC
T =25°C
A
T =25°C
A
0.6
–55
0
0
200 400
600 800 1000
0.0
1.0
2.0
3.0
4.0
25
125
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
CAPACITANCE (pF)
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
1.05
1.00
V
=5.5V
CC
0.95
0.90
0.85
T =25°C
A
0.80
0.75
0.70
0
25
50
75
100
CLOCK PERIOD (ns)
Document #: 38-04012 Rev. **
Page 7 of 13
CY7C265
Ordering Information[6]
Speed
(ns)
ICC
Package
Name
Operating
Range
(mA)
Ordering Code
CY7C265–15JC
CY7C265–15PC
CY7C265–15WC
CY7C265–15DMB
CY7C265–15LMB
CY7C265–15QMB
CY7C265–15WMB
CY7C265–25JC
CY7C265–25PC
CY7C265–25WC
CY7C265–25DMB
CY7C265–25LMB
CY7C265–25QMB
CY7C265–25WMB
CY7C265–40JC
CY7C265–40PC
CY7C265–40WC
CY7C265–50JC
CY7C265–50PC
CY7C265–50WC
CY7C265–50DMB
CY7C265–50LMB
CY7C265–50QMB
CY7C265–50WMB
Package Type
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
15
120
J64
P21
W22
D22
L64
Commercial
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
140
Military
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Q64
W22
J64
25
120
140
Commercial
Military
P21
W22
D22
L64
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Q64
W22
J64
40
50
100
80
Commercial
Commercial
Military
P21
W22
J64
28-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
P21
W22
D22
L64
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
120
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
Q64
W22
Note:
6. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
1, 2, 3
1, 2, 3
Parameter
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
VOH
VOL
VIH
VIL
IIX
tAS
tHA
tCO
tPW
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
tSES
tHES
tCOS
IOZ
ICC
Document #: 38-04012 Rev. **
Page 8 of 13
CY7C265
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032
28-Lead Plastic Leaded Chip Carrier J64
51-85001-A
Document #: 38-04012 Rev. **
Page 9 of 13
CY7C265
Package Diagrams (continued)
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
51-80051
28-Lead (300-Mil) Molded DIP P21
51-85014-B
Document #: 38-04012 Rev. **
Page 10 of 13
CY7C265
Package Diagrams (continued)
28-Pin Windowed Leadless Chip Carrier Q64
MIL–STD–1835 C–4
51-80102
Document #: 38-04012 Rev. **
Page 11 of 13
CY7C265
Package Diagrams (continued)
(300-Mil)
28-Lead
Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
51-80087
Document #: 38-04012 Rev. **
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© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C265
Document Title: CY7C265 8K x 8 Registered PROM
Document Number: 38-04012
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
114139
3/18/02
DSG
Change from Spec number: 38-00084 to 38-04012
Document #: 38-04012 Rev. **
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