5962-01-419-4595 [ALLEGRO]
Peripheral Driver, 8 Driver, BICMOS, PDIP16,;
| 型号： | 5962-01-419-4595 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Peripheral Driver, 8 Driver, BICMOS, PDIP16, 驱动 信息通信管理 光电二极管 驱动器 |
| 文件： | 总8页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5895
BiMOS II 8-BIT SERIAL INPUT,
LATCHED SOURCE DRIVERS
The UCN5895A, UCN5895EP, and A5895SLW BiMOS II serial-
input, latched source drivers are designed for applications emphasizing
low output saturation voltages and currents to -250 mA per output.
These smart high-side octal, driver ICs merge an 8-bit CMOS shift
register, associated CMOS latches, and CMOS control logic (strobe
and output enable) with medium current emitter-follower (sourcing)
outputs. Typical applications include incandescent or LED displays
(both directly driven and multiplexed), non-impact (i.e., thermal)
printers, relays, and solenoids.
UCN5895A
SERIAL
DATA OUT
16
15
GROUND
CLOCK
1
2
3
4
LOGIC
SUPPLY
V
CLK
ST
DD
SHIFT
REGISTER
OUTPUT
ENABLE
SERIAL
DATA IN
OE 14
LOAD
SUPPLY
V
13
STROBE
BB
LATCHES
Each device is suitable for high-side applications to -250 mA per
channel. The maximum supply voltage is 50 V and a minimum output
sustaining voltage rating of 35 V for inductive load applications. Under
normal operating conditions, the UCN5895A and UCN5895EP are
capable of providing -120 mA (8 outputs continuous and simultaneous)
at +65°C with a logic supply of 5 V. Similar devices, with higher output
current ratings, are the UCN5890A and UCN5891A.
12 OUT
11 OUT
OUT
1
5
6
8
7
6
5
OUT
2
OUT
OUT
OUT
3
10
9
7
8
OUT
4
BiMOS II devices can operate at greatly improved data-input rates.
With a 5 V supply, they will typically operate at better than 5 MHz.
At 12 V, significantly higher speeds are obtained.
Dwg. PP-026-2A
Note the UCN5895A (DIP) and the A5895SLW
(SOIC) are electrically identical and share a common
terminal number assignment.
The CMOS inputs provide for minimum loading and are compatible
with standard CMOS, PMOS, and NMOS circuits. TTL or DTL circuits
may require the use of appropriate pull-up resistors to ensure a proper
input-logic high. A CMOS serial data output allows cascading these
devices in multiple drive-line applications required by many dot matrix,
alphanumeric, and bar graph displays.
ABSOLUTE MAXIMUM RATINGS
at T = +25°C
A
Output Voltage, VOUT . . . . . . . . . . . . . . 50 V
Logic Supply Voltage Range,
These devices are rated for continuous operation over the tem-
perature range of -20°C to +85°C. Because of limitations on package
power dissipation, the simultaneous operation of all output drivers may
require a reduction in duty cycle. The UCN5895A is supplied in a
standard 16-pin dual in-line plastic package with a copper lead frame
for increased allowable package power dissipation. The UCN5895EP
is supplied in a 20-lead plastic leaded chip carrier for minimum area,
surface-mount applications. The A5895SLW is supplied in a 16-lead
wide-body plastic SOIC.
VDD . . . . . . . . . . . . . . . . . . 4.5 V to 12 V
Driver Supply Voltage Range,
VBB . . . . . . . . . . . . . . . . . . 5.0 V to 50 V
Input Voltage Range,
VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V
Continuous Output Current,
IOUT . . . . . . . . . . . . . . . . . . . . . -250 mA
Allowable Package Power Dissipation,
PD . . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
TA . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature Range,
FEATURES
ꢀꢀꢀLow Output-Saturation Voltage
ꢀꢀꢀSource Outputs to 50 V
ꢀꢀꢀOutput Current to -250 mA
ꢀꢀꢀTo 3.3 MHz Data-lnput Rate
ꢀꢀꢀLow-Power CMOS Logic & Latches
TS . . . . . . . . . . . . . . . . -55°C to +150°C
Caution: CMOS devices have input-static
protection, but are susceptible to damage when
exposed to extremely high static electrical
charges.
Always order by complete part number, e.g., UCN5895A .
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
2.5
SUFFIX 'EP', R
= 59°C/W
θJA
CLOCK
2.0
1.5
1.0
0.5
0
SUFFIX 'A', R
= 60°C/W
SERIAL
SERIAL
DATA IN
θJA
8-BIT SERIAL-PARALLEL SHIFT REGISTER
LATCHES
DATA OUT
V
STROBE
GROUND
DD
OUTPUT
ENABLE
MOS
BIPOLAR
V
BB
SUFFIX 'LW', R
75
= 80°C/W
θJA
25
50
100
125
150
°
AMBIENT TEMPERATURE IN
C
OUT OUT OUT OUT OUT OUT OUT OUT
8
1
2
3
4
5
6
7
Dwg. GP-024-4
Dwg. No. A-12,654
TYPICAL INPUT CIRCUIT
V
DD
UCN5895EP
IN
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
Dwg. No. A-14,368
Dwg. No. A-12,655
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2004 Allegro MicroSystems, Inc.
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at T = +25°C, V
= 50 V, V = 5 V and 12 V
DD
A
BB
(unless otherwise noted).
Limits
Max.
Characteristic
Symbol
Test Conditions
Min.
—
Units
µA
µA
V
Output Leakage Current
I
T
T
= +25°C
= +70°C
-50
-100
1.1
1.2
—
OUT
A
—
A
Output Saturation Voltage
V
I
I
I
= -60 mA
—
CE(SAT)
OUT
OUT
OUT
= -120 mA
= -120 mA, L = 2 mH
= 5.0 V
—
V
Output Sustaining Voltage
Input Voltage
V
35
V
CE(sus)
V
V
V
V
V
V
V
V
3.5
10.5
-0.3
—
5.3
12.3
+0.8
50
V
IN(1)
DD
DD
DD
DD
DD
DD
DD
= 12 V
V
V
= 5 V to 12 V
V
IN(0)
IN(1)
Input Current
I
= V = 5.0 V
µA
µA
kΩ
kΩ
MHz
kΩ
kΩ
µs
IN
= V = 12 V
IN
—
240
—
Input lmpedance
z
= 5.0 V
= 12 V
100
50
IN
—
Max. Clock Frequency
f
3.3
—
—
CLK
Serial Data-Output
Resistance
r
V
V
= 5.0 V
= 12 V
20
OUT
DD
—
6.0
2.0
10
DD
Turn-ON Delay
Turn-OFF Delay
Supply Current
t
t
Output Enable to Output, I
Output Enable to Output, I
= -120 mA
= -120 mA
—
—
—
—
—
—
—
—
—
—
—
PLH
PHL
OUT
OUT
µs
I
All outputs ON, All outputs open
All outputs OFF
10
mA
µA
µA
µA
mA
mA
µA
µA
V
BB
200
100
200
1.0
3.0
50
I
V
V
V
V
V
V
= 5 V, All outputs OFF, Inputs = 0 V
= 12 V, All outputs OFF, Inputs = 0 V
= 5 V, One output ON, All inputs = 0 V
= 12 V, One output ON, All inputs = 0 V
DD
DD
DD
DD
DD
Diode Leakage Current
Diode Forward Voltage
I
= 25 V, T = +25°C
A
R
R
R
= 25 V, T = +70°C
100
2.0
A
V
I = 120 mA
F
F
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
CLOCK
DATA IN
STROBE
BLANKING
OUTN
A
D
B
E
F
C
G
Dwg. No. A-12,649A
TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)
A.
B.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ................................................................. 75 ns
Minimum Data Active Time After Clock Pulse
(Data Hold Time) ..................................................................... 75 ns
C.
D.
E.
F.
Minimum Data Pulse Width........................................................ 150 ns
Minimum Clock Pulse Width ...................................................... 150 ns
Minimum Time Between Clock Activation and Strobe............... 300 ns
Minimum Strobe Pulse Width..................................................... 100 ns
G.
Typical Time Between Strobe Activation and
Output Transition .................................................................... 1.0 µs
Serial Data present at the input is transferred to the shift register
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE tied
high) will require that the OUTPUT ENABLE input be high during serial
data entry.
When the OUTPUT ENABLE input is high, all of the output buffers
are disabled (OFF) without affecting the information stored in the
latches or shift register. With the OUTPUT ENABLE input low, the
outputs are controlled by the state of their respective latches.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TYPICAL APPLICATION
+ 12 V
UCN5895A
DATA OUT
FOR > 8 SEGMENTS
PER DIGIT
1
2
3
4
5
6
16
15
14
13
12
11
V
CLOCK
DATA IN
STROBE
DD
SHIFT
REGISTER
OUTPUT ENABLE
(ACTIVE LOW)
OE
LATCHES
VBB
7
8
10
9
TO OTHER SEGMENTS
UCN5821A
C
CLOCK
1
16
DATA IN
2
3
4
5
6
15
14
13
12
11
10
TO
OTHER
DIGITS
+ 12 V
DATA OUT
STROBE
OUTPUT
ENABLE
7
8
9
9
Dwg. No. B-1541
TRUTH TABLE
Serial
Data Clock
Input Input I
Shift Register Contents
Serial
Data Strobe
Output Input
Latch Contents
...
Output Contents
... I
Output
Enable
I
I
...
I
I
I
I
I
I
I
I
I
I
I
N-1 N
1
2
3
N-1
N
1
2
3
N-1
N
1
2
3
H
L
H
L
R1 R2 ... RN-2 RN-1
R1 R2 ... RN-2 RN-1
RN-1
RN-1
RN
X
R1 R2 R3 ... RN-1 RN
...
P1 P2 P3 ... PN-1 PN
X
X
X
X
X
X
L
R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
H
L
P1 P2 P3 ... PN-1 PN
... L
X
X
X
...
X
X
H
L
L
L
L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5895A
Dimensions in Inches
(controlling dimensions)
0.014
0.008
9
16
0.430
MAX
0.280
0.240
0.300
BSC
1
8
0.100
BSC
0.070
0.005
MIN
0.045
0.775
0.735
0.210
MAX
0.015
MIN
0.150
0.115
0.022
0.014
Dwg. MA-001-16A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
9
16
10.92
MAX
7.11
6.10
7.62
BSC
1
8
2.54
BSC
1.77
0.13
MIN
1.15
19.68
18.67
5.33
MAX
0.39
MIN
3.81
2.93
0.558
0.356
Dwg. MA-001-16A mm
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5895EP
Dimensions in Inches
(controlling dimensions)
13
9
0.021
0.013
8
14
0.169
0.141
0.032
0.026
0.395
0.385
INDEX AREA
0.356
0.350
0.050
BSC
0.169
0.141
18
4
19 20
1
2
3
0.356
0.350
0.020
MIN
0.395
0.385
0.180
0.165
Dwg. MA-005-20A in
Dimensions in Millimeters
(for reference only)
13
9
0.533
0.331
8
14
4.29
3.58
0.812
10.03
0.661
9.78
INDEX AREA
9.042
8.890
1.27
BSC
4.29
3.58
18
4
19 20
1
2
3
9.042
8.890
0.51
MIN
10.03
9.78
4.57
4.20
Dwg. MA-005-20A mm
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option within limits shown.
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
A5895SLW
Dimensions in Inches
(for reference only)
16
9
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
BSC
3
0° TO 8°
0.4133
0.3977
0.0926
0.1043
Dwg. MA-008-16A in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
16
9
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
BSC
3
0° TO 8°
10.50
10.10
2.65
2.35
Allegro MicroSystems, Inc. reserves the right to make, from time to time,
such departures from the detail specifications as may be required to permit
improvements in the design of its products.
0.10 MIN.
The information included herein is believed to be accurate and reliable.
However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result
from its use.
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option
within limits shown.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
相关型号：
5962-01-421-9344
Battery Charge Controller, Voltage-mode, 0.05A, 56kHz Switching Freq-Max, CMOS, PDIP8
MAXIM
©2020 ICPDF网 联系我们和版权申明