FX839P4 [CMLMICRO]
Analogue Control Interface; 模拟控制接口
| 型号： | FX839P4 |
| 厂家： | 
CML MICROCIRCUITS |
| 描述： | Analogue Control Interface |
| 文件： | 总22页 (文件大小：1141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CML Semiconductor Products
Analogue Control Interface FX839
September 1997
D/839/4
1.0
Features
Advance Information
• Three DACs
• Multiplexed 4 Input ADC
8 or 10-Bit Resolution
10-Bit Resolution
• Custom IRQ Generator with Variable • Scalable ADC Clock Frequencies
8-Bit Reference Settings
• Two Variable Attenuators
• Low Power (3.0V Operation)
from Xtal/Clock
• Serial Interface to Host µC
• 24-Pin SSOP Package
1.1
Brief Description
This product comprises a selection of independent functional blocks vital to modern microcomputer controlled
radio-frequency communications equipment. Examples of possible uses are as follows:
•
The four-way multiplexed ADC with magnitude comparator may be used for monitoring RSSI, battery
voltage, temperatures, reflected signals or error voltages.
•
•
The three DACs may be used to adjust VCOs, reference oscillators, power output, bias current or IF gain.
The two variable attenuators may be used to adjust deviation, modulation depth or baseband gain.
The FX839 is controlled via the standard serial 'C-BUS'. This is complementary to, and compatible with, many
standard microcomputers and other baseband processing blocks.
Consumer Microcircuits Limited
1997
Analogue Control Interface
FX839
CONTENTS
Section
Page
1.0 Features .......................................................................................................... 1
1.1 Brief Description ............................................................................................ 1
1.2 Block Diagram................................................................................................ 3
1.3 Signal List....................................................................................................... 4
1.4 External Components.................................................................................... 6
1.5 General Description....................................................................................... 7
1.5.1 Software Description..................................................................... 8
1.6 Application Notes......................................................................................... 15
1.6.1 General.......................................................................................... 15
1.7 Performance Specification.......................................................................... 16
1.7.1 Electrical Performance ................................................................ 16
1.7.2 Packaging ..................................................................................... 21
Note: As this product is still in development, it is likely that a number of changes and additions will be made to
this specification. Items marked TBD or left blank will be included in later issues. Information in this
data sheet should not be relied upon for final product design.
Consumer Microcircuits Limited
2
1997
D/839/4
Analogue Control Interface
FX839
1.2
Block Diagram
Figure 1: Block Diagram
Consumer Microcircuits Limited
3
1997
D/839/4
Analogue Control Interface
FX839
1.3
Signal List
Package
P4/D2/D5
Signal
Description
Pin No.
Name
XTALN
Type
O/P
I/P
1
2
The inverter output of the on-chip oscillator.
XTAL/CLOCK
The input to the on-chip oscillator, for external Xtal circuit
or clock.
3
4
5
SERIAL
CLOCK
I/P
I/P
The 'C-BUS' serial clock input. This clock, produced by
the µController, is used for transfer timing of commands
and data to and from the device.
See 'C-BUS' Timing Diagram (Figure 4).
COMMAND
DATA
The 'C-BUS' serial data input from the µController. Data is
loaded into this device in 8-bit bytes, MSB (B7) first, and
LSB (B0) last, synchronised to the SERIAL CLOCK.
See 'C-BUS' Timing Diagram (Figure 4).
REPLY DATA
O/P
The 'C-BUS' serial data output to the µController. The
transmission of REPLY DATA bytes is synchronised to the
SERIAL CLOCK under the control of the CSN input.
This 3-state output is held at high impedance when not
sending data to the µController. See 'C-BUS' Timing
Diagram (Figure 4).
6
7
CSN
I/P
The 'C-BUS' data loading control function: this input is
provided by the µController. Data transfer sequences are
initiated, completed or aborted by the CSN signal.
See 'C-BUS' Timing Diagram (Figure 4).
IRQN
O/P
This output indicates an interrupt condition to the
µController by going to a logic '0'. This is a 'wire-ORable'
output, enabling the connection of up to 8 peripherals to 1
interrupt port on the µController. This pin has a low
impedance pulldown to logic '0' when active and a high-
impedance when inactive. An external pullup resistor is
required.
The conditions that cause interrupts are indicated in the
IRQ FLAG register and are effective if not disabled.
8
9
ADCIN1
ADCIN2
I/P
I/P
Analogue to digital converter input 1 (ADC1)
Analogue to digital converter input 2 (ADC2)
Consumer Microcircuits Limited
4
1997
D/839/4
Analogue Control Interface
FX839
1.3
Signal List (continued)
Package
P4/D2/D5
Signal
Description
Pin No.
10
Name
ADCIN3
ADCIN4
Type
I/P
Analogue to digital converter input 3 (ADC3)
Analogue to digital converter input 4 (ADC4)
11
I/P
12
V
SS
POWER
The negative supply rail (ground) for both analogue and
digital supplies.
13
14
V
BIAS
O/P
N/C
An analogue bias line for the internal circuitry, held at ½
AV . This pin must be decoupled by a capacitor mounted
DD
close to the device pins.
No internal connection. Do not make any connection to
this pin.
15
16
17
18
DACOUT1
DACOUT2
DACOUT3
O/P
O/P
O/P
N/C
Digital to analogue converter No. 1 output (DAC1)
Digital to analogue converter No. 2 output (DAC2)
Digital to analogue converter No. 3 output (DAC3)
No internal connection. Do not make any connection to
this pin.
19
AV
POWER
The positive analogue supply rail. Analogue levels and
voltages are dependent upon this supply. This pin should
DD
be decoupled to V by a capacitor.
SS
20
21
22
23
24
MOD1 IN
MOD2 IN
MOD1
I/P
I/P
Input to MOD1 variable attenuator.
Input to MOD2 variable attenuator.
Output of MOD1 variable attenuator.
Output of MOD2 variable attenuator.
O/P
MOD2
O/P
DV
POWER
The positive digital supply rail. Digital levels and voltages
are dependent upon this supply. This pin should be
DD
decoupled to V by a capacitor.
SS
Notes: I/P
O/P
=
=
Input
Output
Consumer Microcircuits Limited
5
1997
D/839/4
Analogue Control Interface
FX839
1.4
External Components
C1 22pF
C2 22pF
C3 0.1µF
C4 0.1µF
C5 0.1µF
±20%
±20%
±20%
±20%
±20%
R1 1M
R2 22k
±5%
±10%
X1 Note 1
Notes: 1. If an external clock is to be used, it should be connected to Pin 2 and the components C1, C2,
R1 and X1 omitted. The ADC clock frequency is derived from the crystal or external clock by
means of internal programmable dividers. Refer to Section 1.7 for details of crystal or external
clock frequency range.
Figure 2: Recommended External Components
Consumer Microcircuits Limited
6
1997
D/839/4
Analogue Control Interface
FX839
1.5
General Description
The device comprises four groups of related functions: variable attenuators, digital to analogue converters, a
multiplexed analogue to digital converter with multiplexer, clock generator and four 8-bit magnitude
comparators with variable reference levels. These functions are all controlled by the 'C-BUS' serial interface
and are described below:
Variable Attenuators
The two variable attenuators have a range of 0 to -12dB and 0 to -6dB respectively and may be controlled
independently.
Digital to Analogue Converters
Three DACs are provided with default resolutions of 8 bits, which are defined at the initial chip reset. In this
mode the 'C-BUS' data is transferred in a single byte. An option is provided to define any one or more of the
DAC resolutions to be 10 bits, then the DAC requires the transfer of two 'C-BUS' data bytes.
The upper and lower DAC reference voltages are defined internally as AV and V respectively. The output
DD
SS
voltage is expressed as:
n
V
OUT
= AV x (DATA / 2 ) [Volts]
DD
Where, n is the DAC resolution (8 or 10 bits) and DATA is the decimal value of the input code. For example: n
= 8 and binary code = 11111111 therefore DATA = 255
V
OUT
= AV x (255 / 256) [Volts]
DD
Any one of the three DAC input latches may be loaded by sending an address/command byte followed by one
or two data bytes to the 'C-BUS' interface. The data is then latched and the static voltage is updated at the
appropriate output.
When a DAC is disabled its output is defined as open-circuit.
Analogue to Digital Converter and ADC Clock Generator
A single successive approximation ADC is provided with four multiplexed inputs. In order to minimise the
sampling time of each input channel, a Sample and Hold circuit has not been included at the input of the ADC.
For the sampling to be accurate the input signal should not change significantly during the conversion time.
Since the typical application is for the monitoring of slowly changing control voltages this should not present
any problems. The maximum signal 'linear rate of change', 'S', can be quantified by the following expression
(for a maximum 1 bit error):
10
S = AV x f
/ (2 x 1000 x (10 + 2)) [mV/µs]
adc_clk
DD
Where f
is the internal ADC clock frequency.
adc_clk
The programmable clock generator is intended to be flexible, making use of an external system clock signal or
a dedicated crystal. This clock signal is scaled to provide the internal ADC clock frequency (f ). The user
adc_clk
has full control of the frequency scaling factor and this should be chosen such that the input clock frequency, at
the XTAL/CLOCK pin, divided by this factor is no more than 1MHz.
Consumer Microcircuits Limited
7
1997
D/839/4
Analogue Control Interface
FX839
The microcontroller is required to wait during the conversion time, T
(Figure 3), before issuing a 'READ
conv_max
ADC DATAx' command. If this is not done, then the converted data returned on 'C-BUS' will be the result of the
previous conversion on the selected channel. It is possible for the data conversion rate to exceed the reply rate
on 'C-BUS'. In such a case, the data returned will be the result of the most recent conversion completed.
Figure 3: Example of a "conversion and read"
* T
is directly related to the ADC clock frequency, which in turn is set by the external clock frequency
conv_max
and the clock divider.
T
= ((10 + 2) x 'NUMBER OF ENABLED MUX INPUTS' / f
adc_clk
) [Seconds]
conv_max
Note that after reading the ADC1 data, it is necessary to re-enable the conversion of data by setting Bit 5 of the
ADC Control Register to ‘1’.
Magnitude Comparators and Interrupt Request
High and low digital comparator reference levels are provided for the four digital magnitude comparators via the
'C-BUS' interface. The digital input to the comparators is provided by the most significant 8 bits of each ADC
data.
When the sampled data falls outside the high or low digital comparator reference levels the status register is
updated and the IRQN pin is pulled low. When a reference level is set to '0', its IRQ is disabled.
1.5.1 Software Description
Address/Commands
Instructions and Data are transferred via the 'C-BUS' in accordance with the timing information given in
Figure 4.
Instruction and data transactions to and from the FX839 consist of an Address/Command byte followed
by either:
(i)
(ii)
a control or DAC data write (1 or 2 bytes) or,
a status or ADC data read (1 or 2 bytes)
Consumer Microcircuits Limited
8
1997
D/839/4
Analogue Control Interface
FX839
Write Only Register (8-Bit and 16-Bit)
HEX
ADDRESS/
COMMAND
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
$01
$D0
$D2
RESET
CLOCK/IRQ
CONTROL
N/A
0
N/A
0
N/A
N/A
0
N/A
0
N/A
N/A
DIVIDER
BIT 1
N/A
0
BIT 2
MOD1
BIT 2
BIT 0
BIT 0
BIT 0
0
VARIABLE
ATTENUATOR (1)
VARIABLE
MOD1
ENABLE
MOD2
0
0
BIT 4
BIT 4
0
BIT 3
BIT 3
BIT 1
BIT 1
MOD2
BIT 2
ATTENUATOR (2)
0
0
ENABLE
DAC
CONTROL
NBIT
DAC1
NBIT
DAC2
NBIT
DAC3
DAC1
ENABLE
DAC2
ENABLE
DAC3
ENABLE
$D3
$D4
DAC1 DATA
(1)
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
BIT 9
BIT 1
BIT 9
BIT 1
BIT 9
BIT 0
BIT 8
BIT 0
BIT 8
BIT 0
BIT 8
0
*See Note 1
(2)
DAC2 DATA
(1)
$D5
$D6
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
*See Note 1
(2)
DAC3 DATA
(1)
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
*See Note 1
(2)
ADC
CONTROL
ADCIN1
ACTIVE
ADCIN2
ACTIVE
ADCIN3
ACTIVE
ADCIN4
ACTIVE
$D7
$D8
0
1
READN
MAG COMP ONE
LEVELS (1)
MAGNITUDE COMPARATOR UPPER LEVEL
BIT 5 BIT 4 BIT 3 BIT 2
MAGNITUDE COMPARATOR LOWER LEVEL
BIT 5 BIT 4 BIT 3 BIT 2
MAGNITUDE COMPARATOR UPPER LEVEL
BIT 5 BIT 4 BIT 3 BIT 2
MAGNITUDE COMPARATOR LOWER LEVEL
BIT 5 BIT 4 BIT 3 BIT 2
MAGNITUDE COMPARATOR UPPER LEVEL
BIT 5 BIT 4 BIT 3 BIT 2
MAGNITUDE COMPARATOR LOWER LEVEL
BIT 5 BIT 4 BIT 3 BIT 2
MAGNITUDE COMPARATOR UPPER LEVEL
BIT 5 BIT 4 BIT 3 BIT 2
MAGNITUDE COMPARATOR LOWER LEVEL
BIT 5 BIT 4 BIT 3 BIT 2
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
BIT 6
BIT 6
BIT 6
BIT 6
BIT 6
BIT 6
BIT 6
BIT 6
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0
MAG COMP ONE
LEVELS (2)
MAG COMP TWO
LEVELS (1)
$D9
$DA
$DB
MAG COMP TWO
LEVELS (2)
MAG COMP THREE
LEVELS (1)
MAG COMP THREE
LEVELS (2)
MAG COMP FOUR
LEVELS (1)
MAG COMP FOUR
LEVELS (2)
Note 1: A second byte is expected by the 'C-BUS' interface only when the 'NBIT DACn' bit of the 'DAC
Control Register' is set high. Otherwise the data transfer is a single byte (Bit 7 to Bit 0).
Consumer Microcircuits Limited
9
1997
D/839/4
Analogue Control Interface
FX839
Read Only Registers (8-Bit and 16-Bit)
HEX
ADDRESS/
COMMAND
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
IRQ
$D1
$DC
FLAGS
ADC DATA1
(1)
HIRQF4
BIT 7
0
LIRQF4
BIT 6
0
HIRQF3
BIT 5
0
LIRQF3
BIT 4
0
HIRQF2
BIT 3
0
LIRQF2
BIT 2
0
HIRQF1
BIT 1
BIT 9
BIT 1
BIT 9
BIT 1
BIT 9
BIT 1
BIT 9
LIRQF1
BIT 0
BIT 8
BIT 0
BIT 8
BIT 0
BIT 8
BIT 0
BIT 8
(2)
ADC DATA2
(1)
$DD
$DE
$DF
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
(2)
ADC DATA3
(1)
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
(2)
ADC DATA4
(1)
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
(2)
Write Only Register Description
RESET Register (Hex Address $01)
The reset command has no data attached to it. It sets the device registers into the specific states listed below:
REGISTER NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(D7)
0
0
(D6)
0
0
(D5)
0
0
(D4)
0
0
(D3)
0
0
(D2)
0
0
(D1)
0
0
(D0)
0
0
CLOCK/IRQ CONTROL
DAC CONTROL
1
DAC1 DATA
0
0
0
0
0
0
0
0
1
DAC2 DATA
0
0
0
0
0
0
0
0
1
DAC3 DATA
0
0
0
0
0
0
0
0
ADC CONTROL
0
0
0
0
0
0
0
0
VARIABLE ATTENUATOR
(1)
(2)
(1)
(2)
(1)
(2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAG COMP ONE LEVELS
MAG COMP TWO LEVELS
MAG COMP THREE LEVELS (1)
(2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAG COMP FOUR LEVELS
(1)
(2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note 1: Default resolution is defined as 8-Bits.
Consumer Microcircuits Limited
10
1997
D/839/4
Analogue Control Interface
FX839
CLOCK/IRQ CONTROL Register (Hex Address $D0)
This register controls the ADC clock divide ratio:
Bits 7 to 3
Reserved for future use. These bits should be set to '0'.
DIVIDER
(Bit 2 to Bit 0)
The input clock divide ratio, which sets the ADC clock frequency is defined in the
following table:
Bit 2
Bit 1
Bit 0
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Powersave
÷1
÷2
÷4
÷8
÷16
÷32
÷64
Consumer Microcircuits Limited
11
1997
D/839/4
Analogue Control Interface
FX839
VARIABLE ATTENUATOR Register (Hex address $D2)
This is a 16-bit register. Byte (1) is sent first. Bits 0 - 5 of the first byte in this register are used to enable and
set the attenuation of the Modulator 1 amplifier and bits 0 - 5 of the second byte in this register are used to
enable and set the attenuation of the Modulator 2 amplifier, according to the tables below:
BYTE 1
0
BYTE 2
0
5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
Mod. 1 Attenuation
5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
Mod. 2 Attenuation
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disabled (VBIAS
>40dB
12.0dB
11.6dB
11.2dB
10.8dB
10.4dB
10.0dB
9.6dB
9.2dB
8.8dB
8.4dB
8.0dB
7.6dB
7.2dB
6.8dB
6.4dB
6.0dB
5.6dB
5.2dB
4.8dB
4.4dB
4.0dB
3.6dB
3.2dB
2.8dB
2.4dB
2.0dB
1.6dB
1.2dB
0.8dB
0.4dB
0dB
)
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disabled (VBIAS
>40dB
6.0dB
5.8dB
5.6dB
5.4dB
5.2dB
5.0dB
4.8dB
4.6dB
4.4dB
4.2dB
4.0dB
3.8dB
3.6dB
3.4dB
3.2dB
3.0dB
2.8dB
2.6dB
2.4dB
2.2dB
2.0dB
1.8dB
1.6dB
1.4dB
1.2dB
1.0dB
0.8dB
0.6dB
0.4dB
0.2dB
0dB
)
X = don't care
MOD1 ENABLE
(Bit 5, first byte)
When this bit is '1' the MOD1 attenuator is enabled.
When this bit is '0' the MOD1 attenuator is disabled (i.e. powersaved).
MOD2 ENABLE
When this bit is '1' the MOD2 attenuator is enabled.
(Bit 5, second byte) When this bit is '0' the MOD2 attenuator is disabled (i.e. powersaved).
(Bits 7 and 6, first
and second bytes)
Reserved for future use. These should be set to '0'.
Consumer Microcircuits Limited
12
1997
D/839/4
Analogue Control Interface
FX839
DAC CONTROL Register (Hex address $D3)
This register controls the resolution and the number of enabled DAC outputs:
NBIT DAC1, NBIT DAC2, NBIT DAC3
(Bit 7 to Bit 5)
Bit 4
These bits define the input resolutions for each of the four DACs. When 'NBIT
DACn' is '0' the resolution of DACn is 8-Bits. When 'NBIT DACn is '1' the
resolution of DACn is 10-Bits.
Reserved for future use. This bit should be set to '0'.
DAC1 ENABLE, DAC2 ENABLE, DAC3 ENABLE
(Bit 3 to Bit 1)
Bit 0
These bits allow any one or more of the three DACs to be powered up. When '0'
the DACn is powered down and the output is high impedance. When '1' the DAC
is powered on and the output voltage is defined by the DAC Data Registers.
Reserved for future use. This bit should be set to '0'.
DAC1 DATA Register (Hex Address $D4)
DAC2 DATA Register (Hex Address $D5)
DAC3 DATA Register (Hex Address $D6)
The data in these three registers sets the analogue voltage at the output of DAC1, DAC2 and DAC3. This data
will consist of one or two bytes depending on the defined input resolution which is set by bits 7, 6 and 5 of the
DAC Control Register. When operating with 10-bit resolution Bit 7 to Bit 2 of the DACn DATA Register second
data byte must be set to "0".
ADC CONTROL Register (Hex Address $D7)
This register controls the resolution, active inputs and conversion modes of the ADC as described below:
Bit 7
Bit 6
Reserved for future use. This bit should be set to '0'.
Reserved for future use. This bit should be set to ‘1’.
(On reset, this bit is set to ‘0’).
READN
(Bit 5)
When this bit is set to '1' all active input channels are continuously sampled and
the latest converted data stored for each channel. When this bit is set to ‘0’ all
conversions are stopped so that they may be read.
ADC1 ACTIVE, ADC2 ACTIVE, ADC3 ACTIVE, ADC4 ACTIVE
(Bit 4 to Bit 1)
These bits allow any one or more of the four ADC input channels to be enabled.
When '0' the ADCINn input voltage is not converted. When '1' the ADCINn input
is defined as active and the input voltage is converted.
Note: ADC1 must always be enabled for any other channel to work.
Reserved for future use. This bit should be set to ‘0’.
(Bit 0)
Consumer Microcircuits Limited
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1997
D/839/4
Analogue Control Interface
FX839
MAG COMP ONE LEVELS
MAG COMP TWO LEVELS
(Hex Address $D8)
(Hex Address $D9)
MAG COMP THREE LEVELS (Hex Address $DA)
MAG COMP FOUR LEVELS (Hex Address $DB)
Each address controls the relevant numbered ADC magnitude comparator.
The first byte, transmitted with the most significant bit first, sets the magnitude comparator upper reference
level and the second byte sets the magnitude comparator lower reference level.
When a reference level's value is set to '0' its IRQ is disabled.
If a reference level’s value is set to ‘FF’, the level will correspond to:
V
REF
= AV x (255 / 256) [Volts]
DD
Read Only Register Description
IRQ FLAGS Register (Hex Address $D1)
HIRQF1,HIRQF2,HIRQF3,HIRQF4
(Bit 1) (Bit 3) (Bit 5) (Bit 7)
These bits are set if the relevant digital magnitude comparator input exceeds its
upper reference level. These bits are reset to '0' immediately after reading the
IRQ FLAGS register. When any of these bits are set, an interrupt will be
generated if the relevant reference level is not zero.
LIRQF1, LIRQF2, LIRQF3, LIRQF4
(Bit 0) (Bit 2) (Bit 4) (Bit 6)
These bits are set if the relevant digital magnitude comparator input falls below
its lower reference level. These bits are reset to '0' immediately after reading the
IRQ FLAGS register. When any of these bits are set, an interrupt will be
generated if the relevant reference level is not zero.
ADC DATA1 Register (Hex Address $DC)
ADC DATA2 Register (Hex Address $DD)
ADC DATA3 Register (Hex Address $DE)
ADC DATA4 Register (Hex Address $DF)
This data will consist of two bytes each. Bit 7 to Bit 2 of the second data byte will be set to '0'.
Consumer Microcircuits Limited
14
1997
D/839/4
Analogue Control Interface
FX839
1.6
Application Notes
1.6.1 General
1.6.1.1 ‘C-BUS’ Clock
Although this is specified as a 500kHz clock for compatibility with other ‘C-BUS’ devices, the FX839 ‘C-
BUS’ will operate over a much wider range. Users should ensure that the ‘C-BUS’ clock is at least 4
times slower than the crystal or external clock on Pin 2 of the FX839.
Consumer Microcircuits Limited
15
1997
D/839/4
Analogue Control Interface
FX839
1.7
Performance Specification
1.7.1 Electrical Performance
Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
Min.
Max.
7.0
Units
V
V
mA
mA
mV
Supply (V - V ) (either AV or DV )
DD
-0.3
-0.3
-30
-20
-100
DD
SS
DD
Voltage on any pin to V
V
DD
+ 0.3
SS
Current into or out of AV , DV and V pins
+30
+20
+100
DD
DD
SS
Current into or out of any other pin
AV - DV
DD
DD
P4/D2 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
800
13
+125
+85
Units
mW
mW/°C
°C
-55
-40
°C
D5 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
550
9
+125
+85
Units
mW
mW/°C
°C
-55
-40
°C
Operating Limits
Correct operation of the device outside these limits is not implied.
Notes
Min.
Max.
5.5
+85
6.0
Units
V
°C
Supply (V - V ) (either AV or DV )
DD
3.0
-40
0.5
DD
SS
DD
Operating Temperature
Xtal Frequency
MHz
Consumer Microcircuits Limited
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1997
D/839/4
Analogue Control Interface
FX839
Operating Characteristics
For the following conditions unless otherwise specified:
AV = DV = V = 3.3V to 5.0V, Tamb = - 40°C to +85°C.
DD
DD
DD
Notes
Min.
Typ.
Max.
Units
DC Parameters
Supply Voltage (DV
)
)
3.0
3.0
-100
-
-
-
-
5.0
5.0
-
250
4.5
150
2.5
5.5
5.5
100
400
7.0
V
V
DD
Supply Voltage (AV
DD
Supply Difference (AV - DV
)
DD
= 5V
= 5V
= 3.3V
= 3.3V
mV
µA
mA
µA
mA
DD
I
I
I
I
(powersaved)
(not powersaved)
(powersaved)
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
250
4.0
(not powersaved)
'C-BUS' Interface
Input Logic '1'
Input Logic '0'
Input Leakage Current (Logic '1' and '0')
Input Capacitance
70%
-1.0
DV
DV
µA
pF
DD
DD
30%
1.0
7.5
Output Logic '1' (I = 120µA)
90%
DV
DV
OH
DD
DD
Output Logic '0' (I = 360µA)
10%
OL
DACs and Output Buffers (Guaranteed monotonic)
(a) Un-loaded Performance
Resolution
8 or 10
Bits
Internal DAC Settling Time (to 0.5 lsb)
Integral non-linearity (8-Bit mode)
Integral non-linearity (10-Bit mode)
Differential non-linearity (8-Bit mode)
Differential non-linearity (10-Bit mode)
Buffer Slew Rate (with 20pF load)
Buffer Output Resistance (open loop)
Zero Error
10.0
3.0
5.0
1.0
1.0
TBD
200
20
µs
6
6
5
5
LSBs
LSBs
LSBs
LSBs
V/µs
Ω
-20
0
mV
RMS Output Noise Voltage
10
µV
(Low Pass Filter of 30kHz bandwidth)
(b) Loaded Performance
1
Output voltage with resistive load to ground
(Digital code = 3FF
)
4.79
V
V
HEX
Output voltage with resistive load to ground
(Digital code = 200 , 10 Bit) or
3
3
2.495
HEX
(Digital code = 80
, 8 Bit)
HEX
Output voltage with resistive load to V
DD
(Digital code = 000
)
200
mV
HEX
Minimum Resistive Load
1.0
kΩ
Consumer Microcircuits Limited
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1997
D/839/4
Analogue Control Interface
FX839
Notes
Min.
Typ.
Max.
Units
ADCs and Multiplexed Inputs
(Guaranteed monotonic)
Resolution
10
Bits
Input signal 'linear rate of change'
0.27
mV/µs
V
DD
= 3.3V, f
= (For 1 Bit error)
adc_clk
Conversion Time f
= 1MHz
adc_clk
12
µs
LSBs
LSBs
mV
Integral non-linearity
Differential non-linearity
Zero error
2.0
1.0
20
-20
ADC Clock Frequency (f
Input Capacitance
)
1.0
TBD
TBD
MHz
pF
adc_clk
Variable Attenuators
Nominal Adjustment Range (MOD1)
(MOD2)
Attenuation Accuracy
0
0
-1.0
0.2
0.1
12.0
6.0
1.0
0.6
0.3
dB
dB
dB
dB
dB
Ω
Step Size
(MOD1)
(MOD2)
0.4
0.2
600
100
15.0
Output Impedance
Bandwidth (-3dB)
Input Impedance (at 100Hz)
2
2
kHz
kΩ
Magnitude Comparators and Interrupt
Request
Resolution
8
Bits
Output Logic '0' at IRQN (I = 360µA and
10%
10
DV
DD
OL
R2 = 22kΩ ± 10% to DV
)
DD
'Off' State Leakage Current at IRQN
(Vout = DV
µA
)
DD
Xtal/Clock Input
Frequency Range
'High' pulse width
'Low' pulse width
4
0.5
40
40
6.0
MHz
ns
ns
Input Impedance (at 100Hz)
Gain (I/P = 1mVrms at 100Hz)
10
20
MΩ
dB
Notes: 1. The extremes of the DAC output range, when resistively loaded, are affected by the output
impedance of the DAC buffer. Under these conditions the output impedance can approach
200Ω. However, when the output is operating well within the supply, the closed loop output
impedance will be significantly lower thereby improving the loaded performance.
2. Small signal impedance, at AV = 5V and Tamb = 25°C.
DD
Consumer Microcircuits Limited
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D/839/4
Analogue Control Interface
FX839
Notes: 3.
R
= 5kΩ AV = 5.0V.
LOAD DD
4. At V
= 5.0V only. The ‘C-BUS’ clock must be at least 4 times slower than this xtal/clock
DD
frequency.
5. Differential non-linearity is defined as the difference in width between adjacent code midpoints
and the width of an ideal LSB, divided by the width of an ideal LSB.
6. Integral non-linearity is defined as the width difference between an actual code midpoint and
the line of best fit through all code midpoints, divided by the width of an ideal LSB.
Consumer Microcircuits Limited
19
1997
D/839/4
Analogue Control Interface
FX839
1.7.1 Electrical Performance (continued)
Timing Diagrams
Figure 4: 'C-BUS' Timing
For the following conditions unless otherwise specified:
DV = 3.3V to 5.0V, Tamb = -40°C to +85°C.
DD
Parameter
Notes
Min.
2.0
4.0
-
Typ.
Max.
Units
t
t
t
t
t
t
"CS-Enable to Clock-High"
Last "Clock-High to CS-High"
"CS-High to Reply Output 3-state"
"CS-High" Time between transactions
"Inter-Byte" Time
-
µs
µs
µs
µs
µs
µs
CSE
CSH
HIZ
-
2.0
-
2.0
4.0
2.0
CSOFF
NXT
CK
-
"Clock-Cycle" time
-
Notes: 1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral
MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB
(Bit 0) last.
2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge.
3. Loaded commands are acted upon at the end of each command.
4. To allow for differing µController serial interface formats 'C-BUS' compatible ICs are able to work
with either polarity SERIAL CLOCK pulses.
Consumer Microcircuits Limited
20
1997
D/839/4
Analogue Control Interface
FX839
1.7.2 Packaging
Figure 5: D2 Mechanical Outline: Order as part no. FX839D2
Figure 6: D5 Mechanical Outline: Order as part no. FX839D5
Consumer Microcircuits Limited
21
1997
D/839/4
Analogue Control Interface
FX839
1.7.2 Packaging
Figure 7: P4 Mechanical Outline: Order as part no. FX839P4
Handling precautions: This product includes input protection, however, precautions should be taken to
prevent device damage from electro-static discharge. CML does not assume any responsibility for the
use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at
any time without notice to change the said circuitry and this product specification. CML has a policy of
testing every product shipped using calibrated test equipment to ensure compliance with this product
specification. Specific testing of all circuit parameters is not necessarily performed.
CONSUMER MICROCIRCUITS LIMITED
1 WHEATON ROAD
WITHAM - ESSEX
CM8 3TD - ENGLAND
Telephone:
Telefax:
e-mail:
+44 1376 513833
+44 1376 518247
sales@cmlmicro.co.uk
http://www.cmlmicro.co.uk
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