CMX612E3_技术文档

CMX612

Calling Line Identifier

with VMWI

D/612/3 February 2002

Advance Information

Features

Applications

· CLI, CIDCW and VMWI System Operation

· CLASS (FSK) and SDT (Stuttered Dial Tone)

· Low Power Operation 0.5mA at 2.7V

· CLI and CIDCW Adjunct Boxes

· CLI and CIDCW Feature Phones

· Computer Telephone Integration

· Zero-Power Detector for Ring or Line Reversal

· Low CAS Tone Falsing in CIDCW Mode

· Bellcore, ETSI, BT and Mercury Compatible

· Call Logging Systems

· Voice-Mail Equipment

1.1

Brief Description

The CMX612 is a low power CMOS integrated circuit for the reception of physical layer signals used in

British Telecom’s Calling Line Identification Service (CLIP), Bellcore’s Calling Identity Delivery system

(CID), the Cable Communications Association’s Caller Display Services (CDS) and similar evolving

systems. It also meets the requirements of emerging Caller Identity with Call Waiting services (CIDCW).

In addition, it provides Visual Message Waiting Indicator (VMWI) detection in both CLASS (FSK) and

(SDT) Stuttered Dial Tone modes. Two different signal inputs are provided to the device, to support

Tip/Ring and Hybrid connectivity. The device includes a ‘zero-power’ ring or line reversal detector, a

dual-tone (2130Hz plus 2750Hz) Tone Alert Signal detector, a dual-tone (350Hz plus 440Hz) stuttered

dial tone detector and a 1200-baud FSK V23/Bell202 compatible asynchronous data demodulator with a

data retiming circuit which removes the need for a UART in the associated mController.

It is suitable for use in systems to BT specifications SIN227 and SIN242, Bellcore GR-30-CORE and SR-

TSV-002476, CCA TW/P&E/312, ETSI ETS 300 659 parts 1 and 2, ETS 300 778 parts 1 and 2 and

Mercury Communications MNR 19.

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CONTENTS

Section

Page

1.0

1.1

1.2

1.3

1.4

1.5

Features and Applications..........................................................1

Brief Description............................................................................1

Block Diagram.................................................................................3

Signal List.........................................................................................4

External Components...................................................................6

General Description......................................................................7

1.5.1 Mode Control Logic ................................................................7

1.5.2 Input Signal Amplifier.............................................................7

1.5.3 Bandpass Filter.......................................................................8

1.5.4 Level Detector .........................................................................8

1.5.5 FSK Demodulator....................................................................9

1.5.6 FSK Data Retiming..................................................................9

1.5.7 Tone Alert Detector...............................................................10

1.5.8 Dial Tone Detector ................................................................11

1.5.9 Ring or Line Polarity Reversal Detector ..............................12

1.5.10 Xtal Osc and Clock Dividers.................................................13

1.6

1.7

Application Notes........................................................................14

1.6.1 'On-Hook' Operation .............................................................14

1.6.2 'Off-Hook' Operation.............................................................17

1.6.3 VMWI Operation ....................................................................19

Performance Specification.......................................................21

1.7.1 Electrical Performance..........................................................21

1.7.2 Packaging..............................................................................26

Note: This product is in development: Changes and additions will be made to this

specification. Items marked TBD or left blank will be included in later issues.

Information in this data sheet should not be relied upon for final product design.

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1.2

Block Diagram

Figure 1 : Block Diagram

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1.3

Signal List

Package Package

Signal

Description

E3

P6

Pin No.

Name

Type

O/P

1

2

3

1

2

3

XTALN

XTAL

RD

The output of the on-chip Xtal oscillator inverter.

The input to the on-chip Xtal oscillator inverter.

I/P

I/P(S)

Input to the Ring or Line Polarity Reversal

Detector.

4

RT

BI

Open-drain output and Schmitt trigger input

forming part of the Ring or Line Polarity

Reversal detector. An external resistor to V_DD

and a capacitor to V_SSshould be connected to

RT to filter and extend the RD input signal.

5

INPUT

SELECT

I/P(S)

Controls the selection of the two Input Signal

Amplifiers. A low level selects Input 1 and a

high level selects Input 2.

6

7

8

9

6

7

AOP1

INV1

BI

I/P

The output of on-chip Input Signal Amplifier 1

and an input to the signal selection multiplexer.

The inverting input to on-chip Input Signal

Amplifier 1.

8

NINV1

V_BIAS

I/P

The non-inverting input to on-chip Input Signal

Amplifier 1.

10

O/P

Internally generated bias voltage, held at ½ V_DD

when the device is not in ‘Zero-Power’ mode.

Should be decoupled to V_SSby a capacitor

mounted close to the device pins.

10

11

12

V_SS

Power

I/P

Negative supply rail (signal ground).

NINV2

The non-inverting input to on-chip Input Signal

Amplifier 2.

12

13

14

15

13

14

15

16

INV2

I/P

BI

The inverting input to on-chip Input Signal

Amplifier 2.

AOP2

The output of on-chip Input Signal Amplifier 2

and an input to the signal selection multiplexer.

MODE 2

MODE 1

I/P(S)

Input used to select the operating mode. See

Section 1.5.1.

As per MODE 2 description.

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Package Package

Signal

Description

E3

P6

Pin No.

Name

Type

16

17

IRQN

O/P

An open-drain active low output that may be

used as an Interrupt Request/Wake-up input to

the associated mC. An external pull-up resistor

should be connected between this output and

V_DD.

17

18

DET

O/P

A logic level output driven by the Ring or Line

Polarity Reversal Detector, the Tone Alert

Detector, the Dial Tone Detector or the FSK

Level detect circuits, depending on the

operating mode. See Section 1.5.1.

18

19

21

RXCK

RXD

I/P(S)

O/P

An input which may be used to clock received

data bits out of the FSK Data Retiming block.

A logic level output carrying either the raw

output of the FSK Demodulator or re-timed 8-bit

characters depending on the state of the RXCK

input. See Section 1.5.6.

20

22

V_DD

Power

The positive supply rail. Levels and thresholds

within the device are proportional to this

voltage. Should be decoupled to V_SSby a

capacitor mounted close to the device pins.

9, 20

Not used. Do not connect to these pins.

Notes: I/P

=

Input

I/P(S)= Schmitt trigger input

O/P = Output

BI

=

Bidirectional

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1.4

External Components

R1

R2

R3, R4, R5

R6, R7

R8

C1, C2

C3, C4

C5

C6, C7

C8, C9

C11, C12 330pF

C13

C14

18pF

470kW

See Section 1.5.8

470kW

470kW for V_DD= 3.3V

680kW for V_DD= 5.0V

(See Section 1.5.2)

240kW for V_DD= 3.3V

200kW for V_DD= 5.0V

(See Section 1.5.2)

160kW

0.1mF

0.33mF

680pF

0.1mF

10nF

100nF

R9

R10

R11 - R14

R15

R16

100kW

600W

120kW

X1

D1 - D4

3.579545MHz

1N4004

R17

100kW

R18

100kW ±20%

Resistors ±1%, capacitors ±20% unless otherwise stated.

Figure 2 : Recommended External Components for Typical Application

It is recommended that the printed circuit board is laid out with a ground plane in the CMX612 area to

provide a low impedance ground connection to the V_SSpin and to the decoupling capacitors C8 and C9.

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1.5

General Description

1.5.1 Mode Control Logic

The CMX612's operating mode and the source of the DET and IRQN outputs are determined by the logic

levels applied to the MODE 1 and MODE 2 input pins;

MODE 1 MODE 2

Mode

Tone Alert Detect

DET o/p from

Tone Alert Signal

Detection.

IRQN o/p from

0

Valid ‘off-hook’ CAS or

Ring or Line Polarity

Reversal Detection.

Ringing Signal present.

CAS tones present.

[1]

0

1

FSK Receive

FSK Level Detection.

FSK present.

FSK Data Retiming

or

Ring or Line Polarity

Reversal Detection.

Ringing Signal present.

Ring or Line Polarity

Reversal Detection.

Ringing Signal present.

1

0

1

'Zero-Power'

Ring or Line Polarity

Reversal Detection.

Ringing Signal present.

Dial Tone Signal Detection. Valid dial tone detected.

Both tones present.

Dial Tone Detect

[1]

If enabled.

In 'Zero-Power' mode, power is removed from all of the internal circuitry except for the Ring or Line

Polarity Reversal Detector and the DET and IRQN outputs.

1.5.2 Input Signal Amplifiers

These amplifiers can be used to convert the balanced FSK, Tone Alert and VMWI signals received over

the telephone line to an unbalanced signal of the correct amplitude for the FSK receiver, Tone Alert and

Dial Tone Detector circuits.

Figure 3a : Input Signal Amplifier, balanced input configuration

The design equations for this circuit are;

Differential voltage gain V

R6 = R7 = 470kW

R10 = 160kW

/ V(b-a) = R8/R6

AOP

R9 = R8 x R10 / (R8 - R10)

The target differential voltage gain depends on the expected signal levels between the A and B wires and

the CMX612's internal threshold levels, which are proportional to the supply voltage.

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The CMX612 has been designed to meet the applicable specifications with R8 = 430kW at V_DD= 3.0V

nominal, rising to 680kW at V_DD= 5.0V, and R9 should be 240kW at V_DD= 3.0V and 200kW at V_DD

=

5.0V as shown in Section 1.4 and Figure 3c.

The Input Signal Amplifiers may also be used with an unbalanced signal source as shown in Figure 3b.

The values of R6 and R8 are as for the balanced input case.

Figure 3b : Input Signal Amplifier, unbalanced input configuration

1000

900

800

700

R8

600

500

400

300

R9

200

100

0

3

3.5

4

4.5

5

Nominal V_DD(V)

Figure 3c : Input Signal Amplifier, optimum values of R8 and R9 vs. V_DD

1.5.3 Bandpass Filters

These are used to attenuate out of band noise and interfering signals which might otherwise reach the

FSK Demodulator, Tone Alert Detector, Dial Tone detector and Level Detector circuits. The

characteristics of these filters differ in FSK, Tone Alert and Dial Tone modes. Most of the filtering is

provided by switched capacitor stages clocked at 57.7kHz or 9.62kHz depending on mode of operation.

1.5.4 Level Detector

This block operates by measuring the level of the signal at the output of the Bandpass Filter, and

comparing it against a threshold which depends on whether FSK Receive, Tone Alert Detect or Dial Tone

Detect mode has been selected.

In Tone Alert Detect mode the output of the Level Detector block provides an input to the Tone Alert

Signal Detector.

In Dial Tone Detect mode the output of the Level Detector block provides an input to the Dial Tone

Signal Detector.

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In FSK Receive mode the CMX612 DET output will be set high when the level has exceeded the

threshold for sufficient time. Amplitude and time hysteresis are used to reduce chattering of the DET

output in marginal conditions.

Note that in FSK Receive mode this circuit may also respond to non-FSK signals such as speech.

See Section 1.7.1 for definitions of Teon and Teoff

Figure 4 : FSK Level Detector operation

1.5.5 FSK Demodulator

This block converts the 1200 baud FSK input signal to a logic level received data signal which is output

via the RXD pin as long as the Data Retiming function is not enabled (see Section 1.5.6). This output

does not depend on the state of the FSK Level Detector output.

Note that in the absence of a valid FSK signal, the demodulator may falsely interpret speech or other

extraneous signals as data.

1.5.6 FSK Data Retiming

The Data Retiming block extracts the 8 data bits of each character from the received asynchronous data

stream, and presents them to the mC under the control of strobe pulses applied to the RXCK input. The

timing of these pulses is not critical and they may easily be generated by a simple software loop. This

facility removes the need for a UART in the mC without incurring an excessive software overhead.

The block operates on a character by character basis by first looking for the mark to space transition

which signals the beginning of the start bit, then, using this as a timing reference, sampling the output of

the FSK Demodulator in the middle of each of the following 8 received data bits, storing the results in an

internal 8-bit shift register.

When the eighth data bit has been clocked into the internal shift register, the CMX612 examines the

RXCK input. If this is low then the IRQN output will be pulled low and the first of the stored data bits put

onto the RXD output pin. On detecting that the IRQN output has gone low, the mC should pulse the

RXCK pin high 8 times. The high to low transition at the end of the first 7 of these pulses will be used by

the CMX612 to shift the next data bit from the shift register onto the RXD output. At the end of the eighth

pulse the FSK Demodulator output will be reconnected to the RXD output pin. The IRQN output will be

cleared the first time the RXCK input goes high.

Thus to use the Data Retiming function, the RXCK input should be kept low until the IRQN output goes

low; if the Data Retiming function is not required the RXCK input should be kept high.

The only restrictions on the timing of the RXCK waveform are those shown in Figure 5a and the need to

complete the transfer of all eight bits into the mC within 8.3ms (the time of a complete character at 1200

baud).

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td = Internal CMX612 delay; max. 1mS

tclo = RXCK low time; min 1mS

tchi = RXCK high time; min 1mS

Figure 5a : FSK Operation With Data Retiming

Note that, if enabled, the Data Retiming block will interpret the FSK Channel Seizure signal (a sequence

of alternating mark and space bits) as valid received characters, with values of 55 (hex). Similarly it may

interpret speech or other signals as random characters.

If the Data Retiming facility is not required, the RXCK input to the CMX612 should be kept high. The

asynchronous data from the FSK Demodulator will then be connected directly to the RXD output pin, and

the IRQN output will not be activated by the FSK signal. This case is illustrated in Figure 5b.

Figure 5b : FSK Operation Without Data Retiming (RXCK always high)

1.5.7 Tone Alert Detector

This block is enabled when the CMX612 is set to Tone Alert Detect mode. It will then monitor the

received signal for the presence of simultaneous 2130Hz and 2750Hz tones of sufficient level and

duration.

Two digital bandpass filters, centred around 2130Hz and 2750Hz, are used within the block to give

additional rejection of interfering signals.

The CMX612 DET output will be set high while a Tone Alert signal is detected. At the end of the Tone

Alert signal the detector will derespond in 5ms typically. Since the deresponse time is governed by a

statistical process, there will be occasions when the maximum figure of 17ms is exceeded.

When the DET output goes low at the end of the Tone Alert signal, then if the DET output had been high

for a time within the CAS qualifying time TqCAS limits (see Section 1.7.1) , then the IRQN output will be

pulled low and will remain low until the CMX612 is switched out of Tone Alert Detect mode. Note that the

TqCAS timing has been optimised for the detection of 75 to 85ms Tone Alert (CAS) signals used in off-

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hook applications, the longer (88 to 110ms) Tone Alert signal employed by BT for on-hook applications

will not necessarily cause IRQN to go low.

See Section 1.7.1 for definitions of Tton, Ttoff and TqCAS

Figure 6 : Tone Alert Detector operation

1.5.8 Dial Tone Detector

This block is enabled when the CMX612 is set to Dial Tone Detect mode. It will then monitor the received

signal for the presence of simultaneous 350Hz and 440Hz tones of sufficient level and duration.

Two digital bandpass filters, centred around 350Hz and 440Hz, are used within the block to give

additional rejection of interfering signals. The CMX612 DET output will be set high while a Dial Tone

signal is detected. At the end of the Dial Tone signal the detector will derespond in 24ms typically. Since

the deresponse time is governed by a statistical process, there will be occasions when the maximum

figure of 33ms is exceeded.

When the DET output goes high the IRQN output will be pulled low and will remain low until the CMX612

is switched out of Dial Tone Detect mode. Note that the Dial Tone Detect timing has been optimised for

the detection of >90ms signals. Shorter dial tone signals will not necessarily be detected.

See Section 1.7.1 for definitions of Tdon and Tdoff

Figure 7 : Dial Tone Detector operation

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1.5.9 Ring or Line Polarity Reversal Detector

These circuits are used to detect the Line Polarity Reversal and Ringing signals associated with the

Calling Line Identification protocol.

Figure 8 illustrates their use in a typical application.

Figure 8 : Ring or Line Polarity Reversal operation

When no signal is present on the telephone line, RD will be at V_SSand RT pulled to V_DDby R5 so the

output of the Schmitt trigger 'B' will be low.

The ring signal is usually applied at the subscriber's exchange as an ac voltage inserted in series with

one of the telephone wires and will pass through either C3 and R3 or C4 and R4 to appear at the top end

of R1 (point X in Figure 8) in a rectified and attenuated form.

The signal at point X will be further attenuated by the potential divider formed by R1 and R2 before being

applied to the CMX612 input RD . If the amplitude of the signal appearing at RD is greater than the input

threshold (Vthi) of Schmitt trigger 'A' then the N transistor connected to RT will be turned on, pulling the

voltage at RT to V_SSby discharging the external capacitor C5. The output of the Schmitt trigger 'B' will

then go high, activating the DET and/or IRQN outputs depending on the states of the MODE 1 and

MODE 2 inputs.

The minimum amplitude ringing signal that is certain to be detected is:

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( 0.7 + Vthi x [R1 + R2 + R3] / R2 ) x 0.707 Vrms

where Vthi is the high-going threshold voltage of the Schmitt trigger A (see Section 1.7).

With R1, R3 and R4 all at 470kW, as Figure 2, setting R2 to 68kW will guarantee detection of ringing

signals of 40Vrms and above for V_DDover the range 2.7 to 5.5V.

A line polarity reversal may be detected using the same circuit but there will be only one pulse at RD.

The BT specification SIN242 says that the circuit must detect a +15V to -15V reversal between the two

lines slewing in 30ms. For a linearly changing voltage at the input to C3 (or C4), then the voltage

appearing at the RD pin will be:

dV/dt x C3 x [ 1 - exp(-t/T) ] x R2

where T = C3 x (R1 + R2 + R3) and dV/dt is the input slew rate.

For dV/dt = 500V/sec (15V in 30ms), R1, R3 and R4 all 470kW and C3, C4 both 0.1mF as Figure 2, then

setting R2 to 390kW will guarantee detection at V_DD= 5.5V.

If the time constant of R5 and C5 is large enough then the voltage on RT will remain below the threshold

of the 'B' Schmitt trigger keeping the DET and/or IRQN outputs active for the duration of a ring cycle.

The time for the voltage on RT to charge from V_SStowards V_DDcan be derived from the formula

V

= V_DDx [1 - exp(-t/(R5 x C5)) ]

RT

As the Schmitt trigger high-going input threshold voltage (Vthi) has a minimum value of 0.56 x V_DD, then

the Schmitt trigger B output will remain high for a time of at least 0.821 x R5 x C5 following a pulse at

RD.

Using the values given in Figure 2 (470kW and 0.33mF) gives a minimum time of 100 ms (independent of

V_DD), which is adequate for ring frequencies of 10Hz or above.

If necessary, the µC can distinguish between a ring and a reversal by timing the length of the IRQN or

DET output.

1.5.10 Xtal Osc and Clock Dividers

Frequency and timing accuracy of the CMX612 is determined by a 3.579545MHz clock present at the

XTAL pin. This may be generated by the on-chip oscillator inverter using the external components C1, C2

and X1 of Figure 2, or may be supplied from an external source to the XTAL input, in which case C1, C2

and X1 should not be fitted.

The oscillator is turned off in 'Zero-Power' mode.

If the clock is provided by an external source which is not always running, then the MODE 1 input must

be set high and the MODE 2 input must be set low when the clock is not available. Failure to observe this

rule may cause a significant rise in the supply current drawn by CMX612 as well as generating undefined

states of the RXD, DET and IRQN outputs.

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1.6

Application Notes

1.6.1 'On-Hook' Operation

The systems described in this section operate when the telephone set is not in use (on-hook) to display

the number of a calling party before the call is answered.

British Telecom System

Figure 9a illustrates the line signalling and CMX612 I/O signals for the BT on-hook Calling Line ID system

as defined in BT specifications SIN227 and SIN242 part 1. A similar system is described in ETS 300 659-

1 Section 6.1.2c. and ETS 300 778-1.

The Tone Alert signal consists of simultaneous 2130Hz and 2750Hz tones, the 'Chan Seize' signal is a

'1010..' FSK bit sequence. Not shown are the requirements for ac and dc loads, including a short initial

Current Wetting Pulse, to be applied to the line 20ms after the end of the Tone Alert signal and to be

maintained during reception of the FSK signal. Note that, for simplicity of presentation, the Data Retiming

function is not used in Figure 9a (RXCK is kept high).

Figure 9a : BT On-hook System Signals

Bellcore System

Figure 9b illustrates the line signalling and CMX612 I/O signals for the Bellcore on-hook Caller ID system

as defined in Bellcore documents GR-30-CORE and SR-TSV-002476 and also in ETS 300 659-1 Section

6.1.1. and ETS 300 778-1.

As for the BT system, the 'Chan Seize' signal is a '1010..' FSK bit sequence. The Bellcore specifications

do not require ac or dc line terminations while the FSK data is being received, however ETS 300 659-1

and ETS 300 778-1 allow for the possibility of an ac termination being applied. Note that, for simplicity of

presentation, the Data Retiming function is not used in Figure 9b (RXCK is kept high).

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Figure 9b : Bellcore On-hook System Signals

Other On-hook Systems

ETS 300 659-1 and ETS 300 778-1 also allow for systems where the FSK transmission is preceded by a

Dual Tone Alerting signal similar to that used by BT but without a line reversal (Section 6.1.2a) or by a

Ringing Pulse Alerting Signal (Section 6.1.2b).

The U.K. CCA (Cable Communications Association) specification TW/P&E/312 precedes the FSK signals

by a 200 to 450ms ring burst. The use of ac and dc line terminations during FSK reception is optional.

Mercury Communications Ltd. specification MNR 19 allows for either the BT system or that specified by

CCA.

As these are all slight variants on the BT and Bellcore systems, they can also be handled by the

CMX612.

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Figure 9c : Flow Chart for On-hook operation of CMX612

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1.6.2 'Off-Hook' Operation

The CIDCW (Calling Identity on Call Waiting) system described in this section operates when the

telephone set is in use (off-hook) to display the number of a waiting caller without interrupting the current

call.

Bellcore documents GR-30-CORE and SR-TSV-002476, BT specifications SIN227 and SIN242 Part 2

and ETS 300-659-2 all describe similar systems in which a successful CIDCW transaction consists of a

sequence of actions between the CPE (Customer Premises Equipment - e.g. a telephone) and the

Central Office as indicated in Figure 10a.

A.

B.

C.

D.

E.

F.

Normal conversation with both near and far end voice present.

Central Office mutes far end voice, sends CAS and becomes silent.

CPE recognises CIDCW initiation and mutes near end voice and keypad.

CPE sends dtmf ACK to Central Office to signal its readiness to receive FSK data.

Central Office recognises ACK and sends FSK Caller ID data to CPE.

CIDCW transaction is complete. CPE unmutes near end voice and the Central Office

unmutes far end voice, returning to normal conversation.

Figure 10a : CIDCW Transaction from Near End CPE Perspective

The CAS signal is transmitted by the Central Office to initiate a CIDCW transaction and consists of an

80ms burst of simultaneous 2130Hz and 2750Hz tones.

CAS detection is very important because a “missed” signal causes Caller ID information to be lost and a

false signal detection produces a disruptive tone which is heard by the far end caller. Because the CAS

signals must be detected in the presence of conversations which both mask and masquerade as the tone

signals, this function is difficult to accomplish correctly.

Because the numbers of false responses (Talk-offs) and missed signals (Talk-downs) are related to the

speech levels at the CMX612 input, and because the level of near end speech from the local handset is

normally greater than that of far end speech coming from the Central Office, a further improvement in

overall performance can be obtained by taking the CMX612’s audio input from the receive side of the

telephone set hybrid where this is possible.

The internal algorithms used by the CMX612 to drive the DET and IRQN outputs in Tone Alert Detect

mode have been optimised for the detection of off-hook CAS signals in the presence of speech when

used according to the following principles:

1.

If it is possible to mute the local speech from the microphone rapidly (within 0.5ms) without

introducing noise (i.e. where the CIDCW equipment is built into the telephone set) then this

should be done whenever the CMX612 is in Tone Detect mode and the DET output is high. Doing

this will markedly reduce the number of false responses generated by local (near end) speech.

Note that the DET output is not used for any other purpose in an off-hook application when the

CMX612 is set to Tone Alert Detect mode.

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2.

3.

The IRQN output going low when in Tone Alert Detect mode indicates that a CAS has been

detected. The local handset and keypad should then be muted as required by the Bellcore

specification and the CMX612 switched to FSK Receive mode to be ready to receive the FSK

data, doing this will also clear the IRQN output.

The CMX612’s DET output should be monitored for a period of 50ms after changing to FSK

Receive mode, before sending the ACK signal, and the transaction abandoned if the DET output

goes high during this time, which would be the case if a false CAS detect had been caused by far

end speech.

Figure 10b : Flow Chart for Off-hook operation of CMX612

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CMX612

1.6.3 VMWI Operation

VMWI is an indicator for a group of services that is offered by telephone companies to their customers.

For example, it allows voice messages to be stored for later retrieval by the subscribing customer (Voice-

Mail Notification). Messages may be entered into a mailbox by any of the following methods:

1. A call placed to the customer’s line is unanswered after a certain number of rings and is then

forwarded to the voice-mail system (forward on do not answer).

2. A call placed to the customer’s line receives a busy signal and is then forwarded to the voice-mail

system (forward on busy).

3. A message is forwarded to the customer’s voice-mail box by a party directly through the voice-mail

system, without the customer’s line ever being called.

In each case, the presence of messages waiting in the customer’s voice-mail box is indicated to the

customer by generation of a VMWI signal. In Bellcore systems, the identification of a VMWI signal can

be performed by detecting either a Stuttered Dial Tone (off-hook) or an FSK signal (on-hook).

SDT Mode

When there is a message waiting in a customer’s voice-mail box, the telephone company’s Central Office

(CO) switch may apply a special dial tone to the customer’s line when it is taken off-hook. The special

dial tone is called Stuttered Dial Tone and is generally characterised as follows:

1. Steady dial tone frequencies (350Hz + 440Hz).

2. Steady dial tone amplitude up to -12dBV per tone applied from the Central Office (CO) switch to the

line.

3. A cadenced signal of 100ms on, 100ms off, repeated between 3 and 10 times and then steady dial

tone.

According to the US-FCC Alameda order, the Customer Premises Equipment (CPE) will make a

Stuttered Dial Tone check either:

1. When the subscriber takes the phone off-hook to make a call or

2. within 4 minutes of an unanswered call or

3. within 30 seconds of a completed call.

The telephone is taken off-hook to make a Stuttered Dial Tone check. The CPE then puts the CMX612

from ‘Zero-Power’ mode into Dial Tone Detect mode. If both dial tones are detected, then the DET output

will be set high and the IRQN output will be set low.

The DET output may then be polled every 40 - 80ms to check if it has been cleared. The DET output will

only be cleared if one or both tones are removed. If this occurs within 100ms, a counter may be

incremented in the CPE (external to the CMX612) and the IRQN output should then be cleared. This may

be done by taking the CMX612 out of Dial Tone Detect mode into ‘Zero-Power’ mode and back into Dial

Tone Detect mode.

On receiving another interrupt, the polling routine described above should be repeated. If the counter

reaches an appropriate value (e.g. 10) within an appropriate time (e.g. 2.3 seconds) then Stuttered Dial

Tone has been detected and a visual message indicator will then be lit by the CPE.

Other algorithms to detect Stuttered Dial Tone (e.g. continuous polling of the DET output once an

interrupt has been received) are also possible.

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CMX612

CLASS (FSK) Mode

When there is a message waiting in a customer’s voice-mail box, the telephone company’s Central Office

(CO) switch may send on-hook FSK data to the customer’s line. This can be received by the CMX612

and used to indicate waiting voice-mail (Voice-Mail Notification) and other CLASS services, by using the

FSK Receive mode.

Figure 11 : Flow Chart for VMWI-SDT operation of CMX612

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CMX612

1.7

Performance Specification

1.7.1 Electrical Performance

1.7.1.1 Absolute Maximum Ratings

Exceeding these maximum ratings can result in damage to the device.

Min.

Max.

7.0

V_DD+ 0.3

+30

Units

V

mA

Supply (V_DD- V_SS

)

-0.3

-30

Voltage on any pin to V_SS

Current into or out of V_DDand V_SSpins

Current into or out of any other pin

-20

+20

E3 Package

Total Allowable Power Dissipation at Tamb = 25°C

... Derating

Storage Temperature

Operating Temperature

Min.

Max.

300

5

+125

+85

Units

mW

mW/°C

°C

-55

-40

°C

P6 Package

Total Allowable Power Dissipation at Tamb = 25°C

... Derating

Storage Temperature

Operating Temperature

Min.

Max.

800

13

+125

+85

Units

mW

mW/°C

°C

-55

-40

°C

1.7.1.2 Operating Limits

Correct operation of the device outside these limits is not implied.

Notes

Min.

2.7

Max.

5.5

Units

V

Supply (V_DD- V_SS

)

Operating Temperature

Xtal Frequency

2

1

-40

3.575965

+85

3.583125

°C

MHz

Notes: 1. An Xtal frequency of 3.579545MHz ±0.1% is required for correct Tone Alert and FSK

detection.

2. Operating temperature range -10°C to +60°C at V_DD< 3.0V.

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CMX612

1.7.1.3 Operating Characteristics

Details in this section represent design target values and are not currently

guaranteed.

For the following conditions unless otherwise specified:

V_DD= 2.7V at Tamb = -10 to +60°C and V_DD= 3.0V to 5.5V at Tamb = -40°C to +85°C,

Xtal Frequency = 3.579545MHz ± 0.1%, 0dBV corresponds to 1.0Vrms.

Notes

Min.

Typ.

Max.

Units

DC Parameters

I_DD(in ‘Zero-Power’ mode)

I_DD(not in ‘Zero-Power’ mode) at V_DD= 3.0V

I_DD(not in ‘Zero-Power’ mode) at V_DD= 5.0V

at V_DD= 5.0V

1, 2

1

0.02

0.5

1.0

TBD

µA

mA

Logic ‘1’ input level (RXCK and XTAL inputs)

Logic ‘0’ input level (RXCK and XTAL inputs)

70%

-1.0

V_DD

µA

30%

+1.0

Logic input leakage current (Vin = 0 to V_DD

excluding XTAL input

)

Output logic ‘1’ level (l_OH= 360µA)

V_DD

-

V

0.4V

Output logic ‘0’ level (l_OL= 360µA)

IRQN o/p ‘off’ state current (Vout = V_DD

0.4

1.0

V

µA

)

Schmitt Trigger input thresholds, see Fig 12

High going (Vthi)

0.56V_DD

+0.6V

V

Low going (Vtlo)

0.44V_DD

-0.6V

0.44V_DD

Tone Alert Detector

‘Low’ tone nominal frequency

‘High’ tone nominal frequency

Start of Tone Alert signal to DET high time

(Fig 6 Tton)

2130

2750

55.0

Hz

ms

End of Tone Alert signal to DET and IRQN low

time (Fig 6 Ttoff)

DET high time to ensure IRQN goes low

(Fig 6 TqCAS)

0.5

8.0

5.0

17.0

45.0

ms

3

To ensure detection:

‘Low’ tone frequency tolerance

‘High’ tone frequency tolerance

±0.5

%

Level (total)

2750Hz tone level wrt

2130Hz tone level

Signal to Noise ratio

Dual tone burst duration for DET output

Dual tone burst duration to ensure

IRQN goes low

4

5

-40.0

-2.2

dBV

-6.0

20.0

75.0

+6.0

dB

ms

75.0

85.0

ms

6

4

To ensure non-detection:

‘Low’ tone frequency tolerance

‘High’ tone frequency tolerance

Level (total)

±75.0

±95.0

Hz

dBV

ms

-46.0

45.0

Dual tone burst duration

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CMX612

Notes

Min.

Typ.

Max.

Units

FSK Receiver

Transmission rate

1188

1280

2068

1188

2178

-40.0

1200

1300

2100

1200

2200

1212

1320

2132

1212

2222

-8.0

Baud

Hz

V23 Mark (logical 1) frequency

V23 Space (logical 0) frequency

Bell202 Mark (logical 1) frequency

Bell202 Space (logical 0) frequency

Valid input level range

4

dBV

Acceptable twist (mark level wrt space level)

V23

-6.0

-10.0

+6.0

+10.0

dB

Bell202

Acceptable Signal to Noise ratio

V23

5

4

20.0

30.0

dB

dBV

ms

Bell202

Level Detector ‘on’ threshold level

Level Detector ‘off’ to ‘on’ time (Fig 4 Teon)

Level Detector ‘on’ to ‘off’ time (Fig 4 Teoff)

-40.0

25.0

8.0

Input Signal Amplifier

Input impedance

Voltage gain

7

10.0

MW

V/V

500

XTAL Input

‘High’ pulse width

‘Low’ pulse width

8

100

ns

Dial Tone Detector

‘Low’ tone nominal frequency

‘High’ tone nominal frequency

Start of Dial Tone signal to DET high time

(Fig 7 Tdon)

350

440

60.0

Hz

ms

End of Dial Tone signal to DET and IRQN low

time (Fig 7 Tdoff)

DET high time (100ms tone duration)

3.0

1.3

24.0

40.0

33.0

60.0

ms

3

4

To ensure detection:

‘Low’ tone frequency tolerance

‘High’ tone frequency tolerance

Level (per tone)

±7.0

-12.2

Hz

dBV

-31.2

350Hz tone level wrt

440Hz tone level

Signal to Noise ratio

Dual tone burst duration for DET output

Dual tone burst duration to ensure

IRQN goes low

-6.0

20.0

80.0

+6.0

dB

ms

5

9

6

80.0

ms

To ensure non-detection:

‘Low’ tone frequency tolerance

‘High’ tone frequency tolerance

Level (total)

-45.0

-30.0

+30.0

+40.0

-36.0

30.0

Hz

dBV

ms

4

Dual tone burst duration

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D/612/3

Calling Line Identifier with VMWI

CMX612

Notes:

1. At 25°C, not including any current drawn from the CMX612 pins by external circuitry

other than X1, C1 and C2.

2. RD, RXCK, MODE 2 inputs at V_SS, MODE 1 input at V_DD. See also Figure 13.

3. All conditions must be met to ensure detection.

4. For V_DD= 3.3V with equal level tones and with the input signal amplifier external

components as Section 1.4. The internal threshold levels are proportional to V_DD. To

cater for other supply voltages or different signal level ranges the voltage gain of the

input signal amplifier should be adjusted by selecting the appropriate external

components as described in Section 1.5

5. Flat noise in 300 - 3400Hz band for V23, 200 - 3200Hz for Bell202.

6. Meeting any of these conditions will ensure non-detection.

7. Open loop, small signal low frequency measurements.

8. Timing for an external input to the CLOCK/XTAL pin.

9. Tone duration between 80ms and 90ms will normally give 100% detection.

However, under certain conditions (e.g. exact 4:5 ratio between tone frequencies and

adverse twist conditions) up to 0.3% of tones may not be detected. Above 90ms,

detection is 100%.

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D/612/3

Calling Line Identifier with VMWI

CMX612

4

3.5

3

Vthi

2.5

2

1.5

1

Vtlo

0.5

0

3

3.5

4

4.5

5

5.5

V_DD(V)

Figure 12 : Schmitt Trigger typical input voltage thresholds vs. V_DD

10

1

0.1

0.01

0.001

0.0001

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

Temperature (^oC)

Figure 13 : Typical 'Zero Power' I_DDvs. Temperature (V_DD= 5.0V)

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CMX612

1.7.2

Packaging

Figure 14 : 20-pin TSSOP (E3) Mechanical Outline: Order as part no. CMX612E3

Figure 15 : 22-pin DIL (P6) Mechanical Outline: Order as part no. CMX612P6

ã 2002 Consumer Microcircuits Limited

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D/612/3

Calling Line Identifier with VMWI

CMX612

Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from

electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences

are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a

policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific

testing of all circuit parameters is not necessarily performed.

Oval Park - LANGFORD

MALDON - ESSEX

Telephone: +44 (0)1621 875500

Telefax:

e-mail:

+44 (0)1621 875600

sales@cmlmicro.co.uk

http://www.cmlmicro.co.u

CM9 6WG - ENGLAND

k

CML Microcircuits

COMMUNICATION SEMICONDUCTORS

CML Product Data

In the process of creating a more global image, the three standard product semiconductor

companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc

(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst

maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)

Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Micro-

circuits.

These companies are all 100% owned operating companies of the CML Microsystems Plc

Group and these changes are purely changes of name and do not change any underlying legal

entities and hence will have no effect on any agreements or contacts currently in force.

CML Microcircuits Product Prefix Codes

Until the latter part of 1996, the differentiator between products manufactured and sold from

MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX

respectively. These products use the same silicon etc. and today still carry the same prefixes.

In the latter part of 1996, both companies adopted the common prefix: CMX.

This notification is relevant to the product information to which it is attached.

Company contact information is as below:

CML Microcircuits

(UK)Ltd

CML Microcircuits

(USA) Inc.

CML Microcircuits

(Singapore)PteLtd

COMMUNICATION SEMICONDUCTORS

Oval Park, Langford, Maldon,

Essex, CM9 6WG, England

Tel: +44 (0)1621 875500

Fax: +44 (0)1621 875600

uk.sales@cmlmicro.com

www.cmlmicro.com

4800 Bethania Station Road,

Winston-Salem, NC 27105, USA

Tel: +1 336 744 5050,

0800 638 5577

Fax: +1 336 744 5054

us.sales@cmlmicro.com

www.cmlmicro.com

No 2 Kallang Pudding Road, 09-05/

06 Mactech Industrial Building,

Singapore 349307

Tel: +65 7450426

Fax: +65 7452917

sg.sales@cmlmicro.com

www.cmlmicro.com

D/CML (D)/1 February 2002


型号：	CMX612E3
厂家：	CML MICROCIRCUITS
描述：	Telephone Calling No Identification Circuit, CMOS, PDSO20, TSSOP-20 电信光电二极管电信集成电路
文件：	总28页 (文件大小：618K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CMX612E3 [CMLMICRO]

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