概述
数据手册CMX615 概述
Digital Line to POTS Interface 数字线划到POTS接口
CMX615 数据手册
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Digital Line to
POTS Interface
D/615/4 December 1999
Provisional Issue
Features
Applications
· Pre-Programmed Tone Generators
· Fully Integrated DTMF Encoder
· SPM Generator
· Digital Line to POTS Interface
· Subscriber Terminal Adapters
· Wireless Local Loop
· Simple Serial Control Interface
· ‘Zero-Power’ (1µA) Standby Mode
· 3.58MHz Xtal/Clock
· Computer Telephony Integration
· Telephone/Radio Patch Systems
· Pair Gain Systems
· V23/Bell 202 FSK Generator
· Digital Ringing Voltage Generator
· Billing/SPM Systems
1.1
Brief Description
The CMX615 is an integrated telecom tone generator and DTMF encoder designed for ISDN interfaces,
Wireless Local Loop and Analogue to Digital Phone Conversion systems. The tone generator covers an
extensive range of pre-programmed tones used in analogue phone systems (POTS). Three outputs are
provided: ‘Ringing signals’, ‘In-band tones or FSK data’, and ‘12kHz/16kHz Metering pulses’. Simple software
control facilitates the interface to a wide range of commonly used µCs and SLICs, enabling a comprehensive
analogue telephone line presentation.
The DTMF encoder generates the appropriate DTMF tones for the POTS interface. DTMF tone pairs can be
encoded along with each tone singly or with other dual tone signals, such as those used in CIDCW systems
and ‘On Hook’ signalling systems.
Other tone standards supported are: Fax and Modem ‘answer’ and ‘originate’, ITU (CCITT) ‘R1’ and ‘R2’
signals, and sufficient tones for simple melody generation. Communication to and from the host µController is
performed by a ‘C-BUS’ serial interface, which is compatible with the ‘SPI’ interface.
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CONTENTS
Section
Page
1.1 Brief Description.........................................................................................1
1.2 Block Diagram ............................................................................................3
1.3 Signal List...................................................................................................4
1.4 External Components.................................................................................6
1.5 General Description....................................................................................7
1.5.1 Xtal Osc and Clock Dividers.......................................................7
1.5.2 Uncommitted Amplifier...............................................................7
1.5.3 Tone/FSK Encoder and Tone Encoder ......................................7
1.5.4 SPM Generator ..........................................................................10
1.5.5 Transmit Operator.....................................................................10
1.5.6 Tx UART.....................................................................................10
1.5.7 ‘C-BUS’ Interface.......................................................................11
1.5.8 ‘C-BUS’ Registers......................................................................13
1.6 Application Notes.....................................................................................14
1.6.1 ‘Telecom Tones.........................................................................14
1.6.2 ‘C-BUS Timing...........................................................................17
1.7 Performance Specification.......................................................................21
1.7.1 Electrical Performance..............................................................21
1.7.2 Packaging..................................................................................25
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1.2
Block Diagram
Figure 1 Block Diagram
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1.3
Signal List
CMX615
D4/P3
Signal
Name
Description
Pin No.
Type
1
XTALN
XTAL/CLOCK
SERCK
O/P
The output of the on-chip Xtal oscillator
inverter.
2
3
4
5
I/P
I/P
The input to the oscillator inverter from the
Xtal circuit or external clock source.
The ‘C-BUS’ serial clock input from the host
mC. See section 1.5.8
COMDATA
REPDATA
I/P
The ‘C-BUS’ serial data input from the host
mC.
T/S
A 3-state ‘C-BUS’ serial data output to the
host mC. This output is high impedance when
not sending data to the host mC.
6
7
CSN
I/P
The ‘C-BUS’ transfer control input provided by
the host mC.
IRQN
O/P
A ‘wire-ORable’ output for connection to a host
mC Interrupt Request input. This output is
pulled down to V
when active and is high
SS
impedance when inactive. An external pullup
resistor is required.
8
9
VSS
Power The negative supply rail (ground).
TONEFSK
O/P
The sinewave output of the Tones and FSK
signal generators.
10
SPM
O/P
The sinewave output of the SPM signal
generator.
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Signal
Description
CMX615
D4/P3
Pin No.
Name
Type
11
VBIAS
O/P
An internally generated bias voltage of VDD/2,
except when the device is in ‘Zero Power’ mode
when VBIAS will discharge to VSS. It should be
decoupled to VSS by a capacitor mounted close
to the device pins.
12
OPPIN
I/P
The non-inverting input to the uncommitted
amplifier.
13
14
15
OPNIN
OPOUT
RING
I/P
The inverting input to the uncommitted amplifier.
The output of the uncommitted amplifier.
O/P
O/P
The squarewave output of the Ringing Signal
generator.
16
VDD
Power The positive supply rail. Levels within the device
are proportional to this voltage. It should be
decoupled to VSS by a capacitor mounted close
to the device pins.
Notes:
I/P
O/P
T/S
=
=
=
Input
Output
3-state Output
It is recommended that the printed circuit board is laid out with a ground plane in the CMX615 area
to provide a low impedance connection between the VSS pin and the VDD and VBIAS decoupling
capacitors.
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1.4
External Components
Figure 2 Recommended External Components
R1
X1
100kW
3.579545 MHz
C1, C2
C3, C4
18pF
1.0µF
Resistors ±5%, capacitors ±10% unless otherwise stated.
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1.5
General Description
The CMX615 is a telecom tone generator and DTMF tone encoder. It has separate output ports for the three
different classes of signals encoded. These include Ringing signal, In-band tones or FSK data at 1200bps and
High frequency metering pulses (SPM tones). It has a transmit level attenuator for In-band tones or FSK data
and an envelope control for SPM tones. It also has an uncommitted amplifier and uses the industry standard
3.58MHz Xtal for its oscillator. These functions are controlled over a ‘C-BUS‘ serial µC interface, which also
carries the transmit FSK data.
The CMX615 may be powersaved into ‘Zero-Power’ mode for minimum power consumption by issuing a
‘C-BUS’ RESET command. Individual functions may be powersaved by the use of bits 6 and 7 in the SETUP
Register. Not powersaving the Tx Powersave (set bit 6 of the SETUP Register to ‘1’) will take the Tx functions
(tone/FSK encoding, DTMF, SPM and Ringing signal generation) out of powersave. Not powersaving the
Uncommitted Amplifier (Set bit 7 of the SETUP Register to ‘1’) will take the amplifier out of powersave.
Approximately 50ms should be allowed for the Tx dc level to settle at VBIAS before enabling the Tx functions
(set bit 6 of the MODE Register to ‘1’).
1.5.1 Xtal Osc and Clock Dividers
Frequency and timing accuracy of the CMX615 is determined by a 3.579545MHz clock present at the
XTAL/CLOCK pin. This may be generated by the on-chip oscillator inverter using the external components C1,
C2 and X1 of Figure 2, or may be supplied from an external source to the XTAL/CLOCK input. If the clock is
supplied from an external source, C1, C2 and X1 should not be fitted.
The on-chip oscillator is turned off in the 'Zero-Power' mode.
If the clock is provided by an external source which is not always running, then the 'Zero-Power' mode must be
set when the clock is not available. Failure to observe this rule may cause a rise in the supply current drawn by
CMX615.
1.5.2 Uncommitted Amplifier
This amplifier, with suitable external components, can be used for adjusting the transmit signal level (for the
line hybrid).
1.5.3 Tone/FSK Encoder and Tone Encoder
When bit 5 of the MODE Register is set to ‘1’ then these blocks generate FSK signals as determined by bit 0
of the SETUP Register and the Tx data bits from the UART block, as shown in the table below:
SETUP Register
Tone/FSK Generator
FSK Signal Frequency
‘0’ (Space)
FSK Signal Frequency
‘1’ (Mark)
Bit 0
0
1
V23 1200bps FSK
Bell 202 1200bps FSK
2100Hz
2200Hz
1300Hz
1200Hz
When bit 5 of the MODE Register is set to ‘0’, these blocks generate single or dual tones from the range
shown in the tables on the following pages. Bit 6 of the MODE Register is then used to enable or disable the
block’s output to the Tx Signal Control, RING and TONEFSK outputs. There are four tone fields addressed by
bits 0 and 1 of the MODE Register.
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Tone Field 0, MODE Register bit 1 and bit 0 = ‘0’ and ‘0’ respectively.
TX TONES Register Bits 4-7
Frequency
(Hz)
TX TONES Register Bits 0-3
Frequency
(Hz)
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 = OFF
252.4
268.7
285.3
315.5
330.5
375.2
404.3
468.0
495.8
520.6
548.0
562.8
578.4
595.0
612.5
0 = OFF
* 17.1
* 20.5
* 24.9
* 34.1
* 41.0
* 51.2
-
262.9
293.6
348.2
392.6
1600
1633
1827
587.2
NOTE: * These outputs are routed to the RING digital output instead of the TONEFSK output. Any single
tone output level at TONEFSK output is 0dBm.
Tone Field 1, MODE Register bit 1 and bit 0 = ‘0’ and ‘1’ respectively
TX TONES Register Bits 4-7
Frequency
(Hz)
0 = OFF
120
TX TONES Register Bits 0-3
Frequency
(Hz)
0 = OFF
330
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
150
154
250
300
350
360
367
375
380
383
400
450
475
480
416
420
425
433
440
450
460
480
500
600
620
720
930
-
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Tone Field 2, MODE Register bit 1 and bit 0 = ‘1’ and ‘0’ respectively
TX TONES Register Bits 4-7
Frequency
(Hz)
0 = OFF
700
TX TONES Register Bits 0-3
Frequency
(Hz)
0 = OFF
700
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
900
900
1100
1300
1500
1700
-
1100
1300
1500
1700
-
2100
2225
-
2750
1209
1336
1477
1633
950
1400
1800
2130
697
770
852
941
Tone Field 3, MODE Register bit 1 and bit 0 = ‘1’ and ‘1’ respectively
TX TONES Register Bits 4-7
Frequency
(Hz)
0 = OFF
540
TX TONES Register Bits 0-3
Frequency
(Hz)
0 = OFF
540
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
660
780
900
660
780
900
1020
1140
-
1380
1500
1620
1740
1860
1980
-
1020
1140
-
1380
1500
1620
1740
1860
1980
-
-
-
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1.5.4 SPM Generator
This block operates independently and has its own output pin. It can transmit 12kHz or 16kHz and is
controlled by bit 4 of the SETUP Register. Bit 7 of the MODE Register is used to enable or disable this block.
The signal has a rise and fall time each of about 4.5ms. The SPM signal rises from the bias level to 0dBm in
16 steps of »2dB magnitude, and falls from 0dBm to bias level in 16 steps of »2dB magnitude.
1.5.5 Transmit Signal Control
This block adjusts the amplitude of the FSK transmit signal output level, the level skew between DTMF tones
and the signal routing to the output ports.
Output signal levels are proportional to VDD. The nominal output signal levels (at 0dB attenuation and VDD
5.0V) are:
=
Single Tone
0dBm
-3dBm
-3dBm
-5dBm
0dBm
Dual Tone (per tone)
DTMF High Frequency Tone
DTMF Low Frequency Tone
FSK Signal
The RING signal is digital: a square wave with amplitude of » VDD peak to peak. When the RING signal is not
selected, the RING output pin is connected to VSS.
The level attenuator provides for level adjustment from 0dB to -14dB in -2dB steps. The typical level is
determined by bits 2 to 4 of the MODE Register as shown in the table below:
MODE Register
Signal Level Adjustment
Bit 4
0
Bit 3
0
Bit 2
0
(dB)
0
0
0
1
-2
0
1
0
-4
0
1
1
-6
1
0
0
-8
1
1
1
0
1
1
1
0
1
-10
-12
-14
1.5.6 Tx UART
This block connects the µC, via the ‘C-BUS’ interface, to the FSK Encoder.
The block can be programmed to convert transmit data from 8-bit bytes to asynchronous data characters by
adding Start and Stop bits. The transmit data is then passed to the FSK Encoder.
Data to be transmitted should be loaded by the µC into the TX DATA Register when the Tx Data Ready bit (bit
6) of the STATUS Register goes high. It will then be treated by the Tx UART block in one of two ways,
depending on the setting of bit 1 of the SETUP Register:
If bit 1 of the SETUP Register is ‘0’ (Tx Sync mode) then the 8 bits from the TX DATA Register will be
transmitted sequentially at 1200bps, lsb (D0) first.
If bit 1 of the SETUP Register is ‘1’ (Tx Async mode) then bits will be transmitted as asynchronous
data characters at 1200 bps according to the following format:
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One Start bit (Space)
Eight Data bits (D0-D7) from the TX DATA Register, with the lsb (D0) transmitted first
One Stop bit (Mark)
Failure to load the TX DATA Register with a new value when required will result in bit 7 (Tx Data Underflow) of
the STATUS Register being set to ‘1’. If the ‘Tx Async’ mode of operation is selected then a continuous Mark
(‘1’) signal will be transmitted until a new value is loaded into TX DATA. If the ‘Tx Sync’ mode is selected then
the byte already in the TX DATA Register will be re-transmitted.
Figure 3a Async mode
Figure 3b Sync mode
1.5.7 ‘C-BUS’ Interface
This block provides for the transfer of data and control or status information between the CMX615’s internal
registers and the µC over the ‘C-BUS’ serial bus. Each transaction consists of a single Register Address byte
sent from the µC which may be followed by a single data byte sent from the µC to be written into one of the
CMX615’s Write Only Registers, or a single byte of data read out from one of the CMX615’s Read Only
Registers, as illustrated in Figure 4.
Data sent from the µC on the Command Data (COMDATA) line is clocked into the CMX615 on the rising edge
of the Serial Clock (SERCK) input. Reply Data (REPDATA) sent from the CMX615 to the µC is valid when the
Serial Clock is high. The interface is compatible with the most common µC serial interfaces such as SCI, SPI
and Microwire, and may also be easily implemented with general purpose µC I/O pins controlled by a simple
software routine. See Figure 8 for detailed ‘C-BUS’ timing requirements.
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Figure 4 ‘C-BUS’ Transactions
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1.5.8 ‘C-BUS’ Registers
Write Only Registers
Command Data Byte (Bits 7 - 0)
Addr. Register
7
6
5
4
3
2
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
$01
$D0
RESET
SETUP
Uncommitted
Amplifier:
0 = Powersave
1 = Not
Powersave
SPM O/P:
0 = Disable
1 = Enable
D7
Tx Powersave:
0 = Powersave
1 = Not
Reserved
set to 0
SPM:
0 = 12kHz
1 = 16kHz
Reserved
set to 0
Reserved FSK mode: FSK
set to 0 0 = Sync mode:
1 = Async 0 = V23
Powersave
1 = Bell
202
Tone
Fields:
(lsb)
D0
Tone/FSK:
0 = Disable
1 = Enable
D6
Tone/FSK: Tx Level:
0 = Tone
1 = FSK
D5
Tx Level:
Tx Level: Tone
Fields:
(lsb)
D2
$D1
MODE
(msb)
D4
(msb)
D1
D3
D3
$D3
$D4
TX
DATA
TX
D7
D6
D5
D4
D2
D1
D0
TONES
Read Only Registers
Reply Data Byte (Bits 7 - 0)
Addr. Register
$DF STATUS
7
6
5
4
Reserved
set to 0
3
2
1
0
FSK Mode:
FSK Tx Data FSK Tx
Underflow Data Ready
FSK Mode: Reserved
Reserved
set to 0
Reserved
set to 0
Reserved
set to 0
Reserved
set to 0
set to 0
Notes:
1. Accessing the RESET Register over the ‘C-BUS’ clears all of the bits in the SETUP, MODE,
TX DATA, TX TONES and STATUS registers. This will set the device into the Zero Power mode.
Note that this is a single-byte ‘C-BUS’ transaction consisting solely of the address byte value $01.
2. If any of bits 6 or 7 of the STATUS Register is ‘1’ then the IRQN output will be pulled low.
3. Reading the STATUS Register clears the IRQN output. Bits 6 and 7 of the STATUS Register are
cleared on writing to the TX DATA Register.
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1.6
Application Notes
When using the Tone/FSK bit (bit 6) of the MODE Register, each tone starts from VBIAS, and returns to
VBIAS before ending:
Figure 5 Tone Starting and Stopping
When switching between tones in the same column (bits 4 - 7 or bits 0 - 3) of the TX TONES
Register), the transition will be phase continuous. However, switching to the “OFF” state will
immediately take the output of that tone generator to VBIAS
.
Figure 6 Tone Changing
TX TONES Register decodes which do not have a frequency allocated are indicated by a dash (-) in
the Tone Field tables. These values should not be used.
1.6.1 ‘Telecom Tones
The following tables give the hex codes to be programmed into the particular tone field location for
various telecommunications systems applications. The tables are not exhaustive, but list the more
commonly used tones.
Ringing Signals
(f +-2.5%)
(Hz)
Off
Field 0
(Hex)
$00
16.7
20
$01
$02
25
$03
35
$04
40
$05
50
$06
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On Hook ‘CPE Alert Tones
Single Tone
Dual Tone
Field 0
(Hex)
$60
$70
$80
Field 0
(Hex)
$6E
£7E
$8E
(Hz)
375.2
404.3
468
(Hz)
375.2+1827
404.3+1827
468+1827
495.8
520.6
548
562.8
578.4
1633
$90
495.8+1827
520.6+1827
548+1827
562.8+1827
578.4+1827
$9E
$A0
$B0
$C0
$D0
$0D
$AE
$BE
$CE
$DE
NYNEX (MRAA) - AMR Alert Tones (Single Tone)
Group A
Field 0
Group B
Field 0
(Hex)
$80
$90
$A0
$C0
$E0
$F0
(Hz)
(Hex)
$10
$20
$30
$40
$50
$60
(Hz)
468
495.8
520.6
562.8
595
252.4
268.7
285.3
315.5
330.5
375.2
612.5
Single Frequency Call Progress Tones
Field 1
(Hz)
Off
(Hex)
$00
$10
$20
$30
$40
$50
$60
$C0
$04
$06
$07
$09
$0A
$0B
$0C
120
150
154
250
300
350
400
425
440
450
480
500
600
620
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Digital Line to POTS Interface
CMX615
Dual Frequency Call Progress Tones
Additive Mixing
Multiplicative
Mixing
Field 1
Field 1
(Hex)
(Hz)
Off
(Hex)
$00
$66
$F6
$FC
$C4
$C7
$D4
$F4
$1C
$27
(Hz)
350+440
440+480
480+620
400+425
400+450
425+450
425+480
120+620
150+450
400*16.2
400*20
400*25
400*33
400*40
400*50
450*25
600*120
$B2
$A3
$94
$85
$76
$67
$E4
$FD
Dual Tone Multi Frequency Generation
Field 2
(Hz)
Off
(Hex)
$00
941+1633
697+1209
697+1336
697+1477
770+1209
770+1336
770+1477
852+1209
852+1336
852+1477
941+1336
941+1209
941+1477
697+1633
770+1633
852+1633
$FF
$CC
$CD
$CE
$DC
$DD
$DE
$EC
$ED
$EE
$FD
$FC
$FE
$CF
$DF
$EF
Special Information Tones, Fax and Modem Tones and Customer Premises Alert Tones
Field 2
(Hz)
Off
950
1100
1300
1400
1800
2100
2225
(Hex)
$00
$80
$30
$40
$90
$A0
$08
$09
$BB
2130+2750
ã 1999 Consumer Microcircuits Limited
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D/615/4
Digital Line to POTS Interface
CMX615
CCITT ‘R1’ Signalling Tones
Field 2
(Hex)
$12
$13
$23
$14
$24
$34
$15
$25
$35
$45
$16
$26
$36
$46
$56
(Hz)
700+900
700+1100
900+1100
700+1300
900+1300
1100+1300
700+1500
900+1500
1100+1500
1300+1500
700+1700
900+1700
1100+1700
1300+1700
1500+1700
CCITT ‘R2’ Signalling Tones
Forward mode
Backward mode
Field 3
(Hex)
$00
Field 3
(Hex)
$00
$65
$64
$54
$63
$53
$43
$62
$52
$42
$32
$61
$51
$41
$31
$21
(Hz)
Off
(Hz)
Off
1380+1500
1380+1620
1500+1620
1380+1740
1500+1740
1620+1740
1380+1860
1500+1860
1620+1860
1740+1860
1380+1980
1500+1980
1620+1980
1740+1980
1860+1980
$89
1140+1020
1140+900
1020+900
1140+780
1020+780
900+780
1140+660
1020+660
900+660
780+660
1140+540
1020+540
900+540
780+540
660+540
$8A
$9A
$8B
$9B
$AB
$8C
$9C
$AC
$BC
$8D
$9D
$AD
$BD
$CD
1.6.2 ‘C-BUS Timing
The relationship between bytes loaded onto the C-BUS and the transmission of FSK bytes is shown
diagrammatically in Figures 7a, 7b and 7c.
There are many ways in which the C-BUS can be used to program a device and three suggestions
(one for asynchronous FSK - Figure 7a - and two for synchronous FSK -Figures 7b and 7c) are shown
here, together with typical timings. Please note that the C-BUS timing is not shown to the same scale
as the FSK output (it has been magnified by at least 20 times to make it visible on the same scale).
ã 1999 Consumer Microcircuits Limited
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Digital Line to POTS Interface
CMX615
Figure 7a ASYNC mode after General Reset
ã 1999 Consumer Microcircuits Limited
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D/615/4
Digital Line to POTS Interface
CMX615
Figure 7b SYNC mode after General Reset
ã 1999 Consumer Microcircuits Limited
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D/615/4
Digital Line to POTS Interface
CMX615
Figure 7c SYNC mode after General Reset
(using alternative order of commands)
ã 1999 Consumer Microcircuits Limited
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Digital Line to POTS Interface
CMX615
1.7
Performance Specification
1.7.1 Electrical Performance
1.7.1.1 Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
Min.
Max.
7.0
VDD + 0.3
+50
Unit
V
V
mA
mA
Supply (VDD - VSS
)
-0.3
-0.3
-50
-20
Voltage on any pin to VSS
Current into or out of VDD and VSS pins
Current into or out of any other pin
+20
D4/P3 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
800
13
+125
+85
Unit
mW
mW/°C
°C
°C
-55
-40
1.7.1.2 Operating Limits
Correct operation of the device outside these limits is not implied.
Notes
Min.
2.7
Max.
5.5
Unit
V
Supply (VDD - VSS
)
Operating Temperature
Xtal Frequency
-40
3.575965
+85
3.583125
°C
MHz
1
Notes:
1. A Xtal frequency of 3.579545MHz ±0.1% is required for correct operation.
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CMX615
1.7.1.3 Operating Characteristics
For the following conditions unless otherwise specified:
VDD = 2.7V at Tamb = 25°C and VDD = 3.0V to 5.5V at Tamb = -40 to +85°C,
Xtal Frequency = 3.579545MHz ± 0.1%
0dBm corresponds to 775mVrms.
DC Parameters
Notes
Min.
Typ.
Max.
Unit
IDD Zero-Power Mode
1, 2
1
1
1
1
3
3
3
-
-
-
-
-
<1.0
1.5
0.75
5.0
3.0
-
-
-
-
mA
mA
mA
mA
mA
VDD
VDD
µA
OpAmp only Enabled, VDD = 5.0V
OpAmp only Enabled, VDD = 3.3V
All Enabled, VDD = 5.0V
7.5
4.5
-
30%
+1.0
All Enabled, VDD = 3.3V
Logic ‘1’ Input Level
Logic ‘0’ Input Level
70%
-
-1.0
-
-
Logic Input Leakage Current (Vin = 0 to VDD),
(excluding XTAL/CLOCK input)
Output Logic ‘1’ Level (IOH = 360µA)
Output Logic ‘0’ Level (IOL = 360µA)
IRQN O/P ‘Off State Current (VOUT = VDD)
VDD-0.4
-
-
-
-
V
V
µA
-
-
0.4
1.0
FSK Encoder and Tx UART
Notes
Min.
Typ.
Max.
Unit
Level at TONEFSK pin
Twist (Mark level WRT Space level)
Tx 1200bits/sec (V23 mode)
4
-1.0
-2.0
0.0
0
1.0
+2.0
dBm
dB
Baud Rate (set by UART and Xtal frequency)
Mark (Logical 1) Frequency
Space (Logical 0) Frequency
1194
1297
2097
1200
1300
2100
1206
1303
2103
Baud
Hz
Hz
Tx 1200bits/sec (Bell 202 mode)
Baud Rate (set by UART and Xtal frequency)
Mark (Logical 1) Frequency
1194
1197
2197
1200
1200
2200
1206
1203
2203
Baud
Hz
Hz
Space (Logical 0) Frequency
TONEFSK Signal Level
Notes
Min.
Typ.
Max.
Unit
Level at TONEFSK pin for:
Single tone
4
4
4
4
-1.0
-4.0
-4.0
-6.0
-
0
1.0
-2.0
-2.0
-4.0
-
dBm
dBm
dBm
dBm
kW
Dual tone (per tone)
-3.0
-3.0
-5.0
10.0
-
DTMF High Frequency Group
DTMF Low Frequency Group
Output Impedance
Tone frequency resolution
Tone output distortion
-2.0
-
2.0
-
Hz
%
5
0.8
Notes:
1. At 25°C, not including any current drawn from the CMX615 pins by external circuitry other
than X1, C1 and C2.
2. All logic inputs at VSS except for CSN input which is at VDD
3. Excluding XTAL/CLOCK pin.
.
4. At VDD = 5.0V, load resistance greater than 40kW, signal levels are proportional to VDD
5. Frequency above 300Hz.
.
6. SPM has a soft rise and fall time of about 4.5ms. The level changes between VBIAS and 0dBm
in 2dB steps, 16 steps per rise and fall. When SPM is disabled, an extra 4.5ms falling tail end
of signal should be taken into consideration.
ã 1999 Consumer Microcircuits Limited
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D/615/4
Digital Line to POTS Interface
CMX615
SPM Signal Level
Notes
Min.
Typ.
Max.
Unit
Level at SPM pin
4, 6
4,6,8
-1.5
-1.0
-14.0
-
0
0
-
1.2
10.0
1.0
0.5
14.0
-
dBm
dBm
Hz
%
kW
Tone frequency accuracy
Tone output distortion
Output Impedance
5
-
-
Uncommitted Amplifier
Notes
Min.
Typ.
Max.
Unit
Open Loop Gain (I/P = 1mVrms at 100Hz)
Unity Gain Bandwidth
Input Impedance (at 100Hz)
Output Impedance (Open Loop)
-
60.0
5.0
-
-
-
-
-
dB
MHz
MW
kW
-
10.0
-
10.0
Power-Up Timing
Notes
Notes
Min.
Typ.
Max.
Unit
Zero-Power to reliable signal at OPOUT, RING,
SPM or TONEFSK output pins.
-
50
-
ms
XTAL/CLOCK Input
Min.
Typ.
Max.
Unit
'High' Pulse Width
'Low' Pulse Width
Input Impedance (at 100Hz)
Gain (I/P = 1mVrms at 100Hz)
7
7
100
100
-
-
-
-
-
-
-
ns
ns
MW
dB
1.0
-
20.0
Notes:
7. Timing for an external input to the XTAL/CLOCK pin.
8. Over the range VDD = 3.0 to 5.5V at Tamb = 25°C.
ã 1999 Consumer Microcircuits Limited
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D/615/4
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CMX615
Notes
Min.
Typ.
Max.
Unit
‘C-BUS’ Timings (See Figure 8)
tCSE
tCSH
tLOZ
tHIZ
CSN-Enable to Clock-High time
100
100
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
Last Clock-High to CSN-High time
Clock-Low to Reply Output enable time
CSN-High to Reply Output 3-state time
CSN-High Time between transactions
Inter-Byte Time
-
-
1.0
tCSOFF
tNXT
tCK
1.0
500
500
200
200
75
-
-
-
-
-
-
-
-
-
Clock-Cycle time
tCH
Serial Clock-High time
tCL
Serial Clock-Low time
tCDS
tCDH
tRDS
tRDH
Command Data Set-Up time
Command Data Hold time
Reply Data Set-Up time
25
75
Reply Data Hold time
0
Note: These timings are for the latest version of the ‘C-BUS’ as embodied in the CMX615, and allow faster
transfers than the original ‘C-BUS’ timings given in CML Publication D/800/Sys/3 July 1994.
Notes
Min.
Typ.
Max.
Unit
Typical UART Timings (See Figure 3a and 3b)
TFSK
TDLY
TDRDY
TUFL
(delay through the modulator)
(1 bit-period)
-
-
-
-
106
833
208
625
-
-
-
-
µs
µs
µs
µs
(1/4 bit-period)
(3/4 bit-period)
Figure 8 ‘C-BUS’ Timing
ã 1999 Consumer Microcircuits Limited
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Digital Line to POTS Interface
CMX615
1.7.2 Packaging
Figure 9 16-pin SOIC (D4) Mechanical Outline: Order as part no. CMX615D4
Figure 10 16-pin DIL (P3) Mechanical Outline: Order as part no. CMX615P3
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from
electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent
licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML
has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification.
Specific testing of all circuit parameters is not necessarily performed.
Oval Park - LANGFORD Telephone: +44 (0)1621 875500
Telefax:
e-mail:
+44 (0)1621 875600
sales@cmlmicro.co.uk
http://www.cmlmicro.co.uk
MALDON - ESSEX
CM9 6WG - ENGLAND
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Micro-
circuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
uk.sales@cmlmicro.com
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
us.sales@cmlmicro.com
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
sg.sales@cmlmicro.com
www.cmlmicro.com
D/CML (D)/1 February 2002
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