EP7309-IR-C [CIRRUS]
HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE; 高性能,低功耗片上系统增强型数字音频接口型号: | EP7309-IR-C |
厂家: | CIRRUS LOGIC |
描述: | HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE |
文件: | 总46页 (文件大小:1825K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EP7309 Data Sheet
FEATURES
I ARM720T Processor
High-Performance,
Low-Power System on Chip
Enhanced
— ARM7TDMI CPU
— 8 KB of four-way set-associative cache
— MMU with 64-entry TLB
Digital Audio Interface
— Thumb code support enabled
I Ultra low power
OVERVIEW
— 90 mW at 74 MHz typical
The Maverick™ EP7309 is designed for ultra-low-power
applications such as digital music players, internet
appliances, smart cellular phones or any hand-held
device that features the added capability of digital audio
decompression. The core-logic functionality of the device
is built around an ARM720T processor with 8 KB of four-
way set-associative unified cache and a write buffer.
Incorporated into the ARM720T is an enhanced memory
management unit (MMU) which allows for support of
sophisticated operating systems like Microsoft®
Windows® CE and Linux®.
— 30 mW at 18 MHz typical
— 10 mW in the Idle State
— <1 mW in the Standby State
I Advanced audio decoder/decompression capability
— Supports bit streams with adaptive bit rates
— Allows for support of multiple audio
decompression algorithms (MP3, WMA, AAC,
ADPCM, Audible, etc.)
(cont.)
(cont.)
BLOCK DIAGRAM
Digital
Audio
Interface
EPB Bus
Clocks &
Timers
ICE-JTAG
ARM720T
Power
Management
Serial
Interface
Interrupts,
PWM & GPIO
ARM7TDMI CPU Core
8 KB
Cache
Write
Buffer
Keypad&
Touch
Screen I/F
(2) UARTs
w/ IrDA
Boot
ROM
Bus
Bridge
MMU
Internal Data Bus
SRAM &
FLASH I/F
On-chip SRAM
48 KB
LCD
Controller
MaverickKeyTM
MEMORY AND STORAGE
Copyright 2001 Cirrus Logic (All Rights Reserved)
June ’01
DS507PP1
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
1
EP7309
High-Performance, Low-Power System on Chip
FEATURES (cont)
I Dynamically programmable clock speeds of 18, 36, 49,
and 74 MHz
I 48 KB of on-chip SRAM
— 8×8 Keypad Scanner
— 27 General Purpose Input/Output pins
— Dedicated LED flasher pin from the RTC
I Internal Peripherals
— Two 16550 compatible UARTs
— IrDA Interface
™
I MaverickKey IDs
— 32-bit unique ID can be used for SDMI compliance
— 128-bit random ID
— Two PWM Interfaces
— Real-time Clock
— Two general purpose 16-bit timers
— Interrupt Controller
— Boot ROM
I LCD controller
— Interfaces directly to a single-scan panel
monochrome STN LCD
— Interfaces to a single-scan panel color STN LCD
with minimal external glue logic
I Full JTAG boundary scan and Embedded ICE
I Package
support
— 208-Pin LQFP
I Integrated Peripheral Interfaces
— 256-Ball PBGA
— 8/32/16-bit SRAM/FLASH/ROM Interface
— 204-Ball TFBGA
— Digital Audio Interface providing glueless
I The fully static EP7309 is optimized for low power
dissipation and is fabricated on a 0.25 micron CMOS
process
interface to low-power DACs, ADCs and CODECs
— Two Synchronous Serial Interfaces (SSI1, SSI2)
— CODEC Sound Interface
OVERVIEW (cont.)
The EP7309 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/O has an
operation range of 2.5 V–3.3 V. The device has three basic
power states: operating, idle and standby.
The EP7309 integrates an interface to enable a direct
connection to many low cost, low power, high quality
audio converters. In particular, the DAI can directly
interface with the Crystal‚ CS43L41/42/43 low-power
audio DACs and the Crystal‚ CS53L32 low-power ADC.
Some of these devices feature digital bass and treble
boost, digital volume control and compressor-limiter
functions.
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Simply by adding desired memory and peripherals to the
highly integrated EP7309 completes a low-power system
solution. All necessary interface logic is integrated on-
chip.
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information de-
scribes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this
document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).
No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property
of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval
system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from
any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval
system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore,
no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus
Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Digital Music Initiative) or any other authentication
mechanism.
Processor Core - ARM720T
The EP7309 incorporates an ARM 32-bit RISC
microcontroller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key
features include:
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7309 through the use of laser
probing technology. These IDs can then be used to match
secure copyrighted content with the ID of the target
device the EP7309 is powering, and then deliver the
copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
• ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
• Enhanced MMU for Microsoft Windows CE and other
operating systems
• 8 KB of 4-way set-associative cache.
• Translation Look Aside Buffers with 64 Translated
Memory Interfaces
Entries
The EP7309 is equiped with a ROM/SRAM/FLASH-
style interface that has programmable wait-state timings
and includes burst-mode capability, with six chip selects
decoding six 256 MB sections of addressable space. For
maximum flexibility, each bank can be specified to be 8-,
16-, or 32-bits wide. This allows the use of 8-bit-wide
boot ROM options to minimize overall system cost. The
on-chip boot ROM can be used in product manufacturing
to serially download system code into system FLASH
memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-
leading code density.
Power Management
The EP7309 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/O has an
operation range of 2.5 V–3.3 V allowing the device to
achieve a performance level equivalent to 60 MIPS. The
device has three basic power states:
• Operating — This state is the full performance
state. All the clocks and peripheral logic are
enabled.
• Idle — This state is the same as the Operating
State, except the CPU clock is halted while
waiting for an event such as a key press.
• Standby — This state is equivalent to the
computer being switched off (no display), and
the main oscillator shut down. An event such as
a key press can wake-up the processor.
Pin Mnemonic
I/O
Pin Description
nCS[5:0]
O
O
Chip select out
Address output
A[27:0]
D[31:0]
nMOE
nMWE
I/O Data I/O
Pin Mnemonic
I/O
Pin Description
O
O
ROM expansion OP enable
BATOK
I
Battery ok input
ROM expansion write enable
External power supply sense
input
Halfword access select
output
nEXTPWR
I
HALFWORD
O
nPWRFL
I
I
Power fail sense input
WORD
WRITE
O
O
Word access select output
Transfer direction
nBATCHG
Battery changed sense input
Table A. Power Management Pin Assignments
Table B. Static Memory Interface Pin Assignments
MaverickKey™ Unique ID
Digital Audio Capability
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
The EP7309 uses its powerful 32-bit RISC processing
engine to implement audio decompression algorithms in
software. The nature of the on-board RISC processor, and
the availability of efficient C-compilers and other
software development tools, ensures that a wide range of
audio decompression algorithms can easily be ported to
and run on the EP7309
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
3
EP7309
High-Performance, Low-Power System on Chip
Universal Asynchronous
CODEC Interface
Receiver/Transmitters (UARTs)
The EP7309 includes an interface to telephony-type
CODECs for easy integration into voice-over-IP and
other voice communications systems. The CODEC
interface is multiplexed to the same pins as the DAI and
SSI2.
The EP7309 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte
FIFOs for receiving and transmitting data. The UARTs
support bit rates up to 115.2 kbps. An IrDA SIR protocol
encoder/decoder can be optionally switched into the
RX/TX signals to/from UART 1 to enable these signals
to drive an infrared communication interface directly.
Pin Mnemonic
I/O
Pin Description
PCMCLK
O
O
I
Serial bit clock
PCMOUT
PCMIN
Serial data out
Serial data in
Frame sync
Pin Mnemonic
I/O
Pin Description
TXD[1]
O
I
UART 1 transmit
PCMSYNC
O
RXD[1]
CTS
UART 1 receive
Table E. CODEC Interface Pin Assignments
I
UART 1 clear to send
UART 1 data carrier detect
UART 1 data set ready
UART 2 transmit
DCD
I
Note: See Table Q on page 7 for information on pin
multiplexes.
DSR
I
TXD[2]
RXD[2]
LEDDRV
PHDIN
O
I
SSI2 Interface
UART 2 receive
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode
communications. The SSI2 unit shares the same pins as
the DAI and CODEC interfaces through a multiplexer.
O
I
Infrared LED drive output
Photo diode input
Table C. Universal Asynchronous Receiver/Transmitters Pin
Assignments
• Synchronous clock speeds of up to 512 kHz
• Separate 16 entry TX and RX half-word wide FIFOs
• Half empty/full interrupts for FIFOs
Digital Audio Interface (DAI)
The EP7309 integrates an interface to enable a direct
connection to many low cost, low power, high quality
audio converters. In particular, the DAI can directly
interface with the Crystal‚ CS43L41/42/43 low-power
audio DACs and the Crystal‚ CS53L32 low-power ADC.
Some of these devices feature digital bass and treble
boost, digital volume control and compressor-limiter
functions.
• Separate RX and TX frame sync signals for
asymmetric traffic
Pin Mnemonic
I/O
Pin Description
SSICLK
I/O
O
Serial bit clock
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
Serial data out
I
Serial data in
Pin Mnemonic
I/O
Pin Description
I/O
I/O
Transmit frame sync
Receive frame sync
SCLK
O
O
I
Serial bit clock
SDOUT
SDIN
Serial data out
Serial data in
Table F. SSI2 Interface Pin Assignments
Note: See Table Q on page 7 for information on pin
multiplexes.
LRCK
O
I
Sample clock
MCLKIN
MCLKOUT
Master clock input
Master clock output
O
Table D. DAI Interface Pin Assignments
Note: See Table Q on page 7 for information on pin
multiplexes.
4
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
• Column outputs can be individually set high with the
remaining bits left at high-impedance
• Column outputs can be driven all-low, all-high, or all-
high-impedance
• Keyboard interrupt driven by OR'ing together all Port
Synchronous Serial Interface
• ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
• Selectable serial clock polarity
A bits
• Keyboard interrupt can be used to wake up the
Pin Mnemonic
I/O
Pin Description
system
ADCLK
O
I
SSI1 ADC serial clock
SSI1 ADC serial input
SSI1 ADC serial output
SSI1 ADC chip select
SSI1 ADC sample clock
• 8×8 keyboard matrix usable with no external logic,
ADCIN
extra keys can be added with minimal glue logic
ADCOUT
nADCCS
SMPCLK
O
O
O
Pin Mnemonic
I/O
Pin Description
COL[7:0]
O
Keyboard scanner column drive
Table G. Serial Interface Pin Assignments
Table I. Keypad Interface Pin Assignments
LCD Controller
Interrupt Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The
display frame buffer start address is programmable,
allowing the LCD frame buffer to be in SDRAM, internal
SRAM or external SRAM.
When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the
same time, a fixed priority system determines the order
in which they are handled. The EP7309 interrupt
controller has two interrupt types: interrupt request
(IRQ) and fast interrupt request (FIQ). The interrupt
controller has the ability to control interrupts from 22
different FIQ and IRQ sources.
• Interfaces directly to a single-scan panel monochrome
STN LCD
• Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
• Panel width size is programmable from 32 to 1024
• Supports 22 interrupts from a variety of sources (such
pixels in 16-pixel increments
as UARTs, SSI1, and key matrix.)
• Video frame buffer size programmable up to
• Routes interrupt sources to the ARM720T’s IRQ or
128 KB
FIQ (Fast IRQ) inputs
• Bits per pixel of 1, 2, or 4 bits
• Five dedicated off-chip interrupt lines operate as level
sensitive interrupts
Pin Mnemonic
I/O
Pin Description
.
Pin Mnemonic
I/O
Pin Description
CL1
O
O
O
O
O
LCD line clock
nEINT[2:1]
I
I
I
I
External interrupt
CL2
LCD pixel clock out
EINT[3]
External interrupt
DD[3:0]
FRM
M
LCD serial display data bus
LCD frame synchronization pulse
LCD AC bias drive
nEXTFIQ
External Fast Interrupt input
Media change interrupt input
nMEDCHG/nBROM
(Note)
Table J. Interrupt Controller Pin Assignments
Table H. LCD Interface Pin Assignments
Note: Pins are multiplexed. See Table R on page 7 for more
information.
64-Keypad Interface
Matrix keyboards and keypads can be easily read by the
Real-Time Clock
EP7309.
A dedicated 8-bit column driver output
generates strobes for each keyboard column signal. The
pins of Port A, when configured as inputs, can be
selectively OR'ed together to provide a keyboard
interrupt that is capable of waking the system from a
STANDBY or IDLE state.
The EP7309 contains a 32-bit Real Time Clock (RTC) that
can be written to and read from in the same manner as
the timer counters. It also contains a 32-bit output match
register which can be programmed to generate an
interrupt.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
5
EP7309
High-Performance, Low-Power System on Chip
• Driven byan external 32.768 kHz crystal oscillator
Pin Mnemonic
I/O
Pin Description
PA[7:0]
I
I
GPIO port A
Pin Mnemonic
Pin Description
PB[7:0]
GPIO port B
GPIO port D
GPIO port D
GPIO port D
GPIO port E
GPIO port E
RTCIN
Real-Time Clock Oscillator Input
Real-Time Clock Oscillator Output
Real-Time Clock Oscillator Power
Real-Time Clock Oscillator Ground
PD[0]/LEDFLSH
PD[5:1]
(Note)
(Note)
I/O
I/O
I/O
I
RTCOUT
VDDRTC
VSSRTC
PD[7:6]/SDQM[1:0]
PE[1:0]/BOOTSEL[1:0] (Note)
PE[2]/CLKSEL (Note)
Table K. Real-Time Clock Pin Assignments
I
Table N. General Purpose Input/Output Pin Assignments
PLL and Clocking
• Processor and Peripheral Clocks operate from a single
Note: Pins are multiplexed. See Table R on page 7 for more
information.
3.6864 MHz crystal or external 13 MHz clock
• Programmable clock speeds allow the peripheral bus
to run at 18 MHz when the processor is set to 18 MHz
and at 36 MHz when the processor is set to 36, 49 or
74 MHz
Hardware debug Interface
• Full JTAG boundary scan and Embedded ICE
support
Pin Mnemonic
Pin Description
Pin Mnemonic
I/O
Pin Description
MOSCIN
Main Oscillator Input
TCLK
I
I
JTAG clock
MOSCOUT
VDDOSC
VSSOSC
Main Oscillator Output
Main Oscillator Power
Main Oscillator Ground
TDI
JTAG data input
TDO
nTRST
TMS
O
I
JTAG data output
JTAG async reset input
JTAG mode select
Table L. PLL and Clocking Pin Assignments
I
Table O. Hardware Debug Interface Pin Assignments
DC-to-DC converter interface (PWM)
• Provides two 96 kHz clock outputs with
programmable duty ratio (from 1-in-16 to 15-in-16)
that can be used to drive a positive or negative DC to
DC converter
LED Flasher
A dedicated LED flasher module can be used to generate
a low frequency signal on Port D pin 0 for the purpose of
blinking an LED without CPU intervention. The LED
flasher feature is ideal as a visual annunciator in battery
powered applications, such as a voice mail indicator on a
portable phone or an appointment reminder on a PDA.
Pin Mnemonic
I/O
Pin Description
DRIVE[1:0]
FB[1:0]
I/O
I
PWM drive output
PWM feedback input
• Software adjustable flash period and duty cycle
• Operates from 32 kHz RTC clock
• Will continue to flash in IDLE and STANDBY states
• 4 mA drive current
Table M. DC-to-DC Converter Interface Pin Assignments
Timers
• Internal (RTC) timer
• Two internal 16-bit programmable hardware count-
Pin Mnemonic
I/O
Pin Description
down timers
PD[0]/LEDFLSH
(Note)
O
LED flasher driver
General Purpose Input/Output (GPIO)
Table P. LED Flasher Pin Assignments
• Three 8-bit and one 3-bit GPIO ports
• Supports scanning keyboard matrix
Note: Pins are multiplexed. See Table R on page 7 for more
information.
6
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Internal Boot ROM
Pin
Mnemonic
I/O
DAI
SSI2
CODEC
The internal 128 byte Boot ROM facilitates download of
saved code to the on-board SRAM/FLASH.
SSITXFR
I/O
I
LRCK
MCLKIN
MCLKOUT
SSITXFR PCMSYNC
SSIRXFR p/u
SSIRXFR
BUZ
Packaging
O
The EP7309 is available in a 208-pin LQFP package, 256-
ball PBGA package or a 204-ball TFBGA package.
Table Q. DAI/SSI2/CODEC Pin Multiplexing
Pin Multiplexing
The following table shows the pins that have been
multiplexed in the EP7309.
The following table shows the pin multiplexing of the
DAI, SSI2 and the CODEC. The selection between SSI2
and the CODEC is controlled by the state of the SERSEL
bit in SYSCON2. The choice between the SSI2, CODEC,
and the DAI is controlled by the DAISEL bit in SYSCON3
(see the EP7309 User’s Manual for more information).
Signal
Block
Signal
Block
System
Configuration
System
Configuration
RUN
CLKEN
Interrupt
Controller
Boot ROM
select
nMEDCHG
PD[0]
nBROM
Pin
Mnemonic
I/O
DAI
SSI2
CODEC
GPIO
GPIO
LEDFLSH
BOOTSEL[1:0]
LED Flasher
System
Configuration
PE[1:0]
SSICLK
I/O
O
I
SCLK
SDOUT
SDIN
SSICLK
SSITXDA
SSIRXDA
PCMCLK
PCMOUT
PCMIN
SSITXDA
SSIRXDA
System
Configuration
PE[2]
GPIO
CLKSEL
Table R. Pin Multiplexing
Table Q. DAI/SSI2/CODEC Pin Multiplexing
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
7
EP7309
High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding
desired memory and peripherals to the highly integrated
EP7309 completes a low-power system solution. All
necessary interface logic is integrated on-chip.
DD[0-3]
CRYSTAL
CRYSTAL
MOSCIN
RTCIN
CL1
LCD
CL2
FRM
M
COL[0-7]
KEYBOARD
PA[0-7]
nCS[4]
PB0
EXPCLK
PB[0-7]
PD[0-7]
DC
INPUT
D[0-31]
A[0-27]
PE[0-2]
POWER
SUPPLY UNIT
PC CARD
SOCKET
PC CARD
CONTROLLER
AND
COMPARATORS
nPOR
nPWRFL
BATOK
nMOE
WRITE
nEXTPWR
nBATCHG
RUN
BATTERY
WAKEUP
DRIVE[0-1]
FB[0-1]
DC-TO-DC
CONVERTERS
nCS[0]
nCS[1]
×16
FLASH
×16
FLASH
SSICLK
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
CODEC/SSI2/
DAI
×16
FLASH
×16
FLASH
IR LED AND
PHOTODIODE
LEDDRV
PHDIN
CS[n]
WORD
RXD1/2
TXD1/2
DSR
2× RS-232
TRANSCEIVERS
EXTERNAL MEMORY-
MAPPED EXPANSION
BUFFERS
CTS
DCD
ADCCLK
nADCCS
ADCOUT
ADCIN
nCS[2]
nCS[3]
ADC
DIGITIZER
BUFFERS
AND
LATCHES
LEDFLSH
ADDITIONAL I/O
SMPCLK
Figure 1. A Maximum EP7309 Based System
Note: A system can only use one of the following peripheral
interfaces at any given time: SSI2,CODEC or DAI.
8
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
DC Core, PLL, and RTC Supply Voltage
DC I/O Supply Voltage (Pad Ring)
DC Pad Input Current
2.9 V
3.6 V
10 mA/pin; 100 mA cumulative
Storage Temperature, No Power
–40°C to +125°C
Recommended Operating Conditions
DC core, PLL, and RTC Supply Voltage
DC I/O Supply Voltage (Pad Ring)
DC Input / Output Voltage
2.5 V 0.2 V
2.3 V - 3.6 V
O–I/O supply voltage
Extended -20°C to +70°C; Commercial 0°C to +70°C;
Industrial -40°C to +85°C
Operating Temperature
DC Characteristics
All characteristics are specified at VDD = 2.5 V and VSS = 0 V over an operating temperature of 0°C to +70°C for all
frequencies of operation. The current consumption figures relate to typical conditions at 2.5 V, 18.432 MHz operation
with the PLL switched “on.”
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
0.65 × V
V
+ 0.3
V
V
= 2.5 V
VIH
VIL
CMOS input high voltage
CMOS input low voltage
V
V
DDIO
DDIO
DDIO
0.25 × V
= 2.5 V
-0.3
DDIO
DDIO
Schmitt trigger positive going
threshold
VT+
1.6 (Typ)
2.0
V
Schmitt trigger negative going
threshold
VT-
0.8
0.1
1.2 (Typ)
0.4
V
V
Vhst
Schmitt trigger hysteresis
VIL to VIH
a
CMOS output high voltage
V
– 0.2
V
V
V
IOH = 0.1 mA
IOH = 4 mA
IOH = 12 mA
DD
a
VOH
VOL
2.5
2.5
Output drive 1
a
Output drive 2
a
CMOS output low voltage
0.3
0.5
0.5
V
V
V
IOL = –0.1 mA
IOL = –4 mA
IOL = –12 mA
a
Output drive 1
a
Output drive 2
VIN = V or GND
IIN
1.0
100
10.0
µA
µA
pF
Input leakage current
DD
Bidirectional 3-state leakage
VOUT = V or GND
IOZ
CIN
25
8
DD
b c
current
Input capacitance
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
9
EP7309
High-Performance, Low-Power System on Chip
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
COUT
CI/O
Output capacitance
8
8
10.0
10.0
pF
pF
Transceiver capacitance
Only 32 kHz oscillator running,
Cache disabled, all other I/O
Standby current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDD
TBD
TBD
300
4.2
µA
standby
static, VIH = V
0.1 V,
DD
VIL = GND 0.1 V
Both oscillators running, CPU
static, Cache disabled, LCD
Idle current consumption
Core, Osc, RTC @2.5 V
I/O @ 2.5 V
IDD
refresh active, VIH = V
0.1 V,
TBD
TBD
mA
idle
DD
VIL = GND 0.1 V
At 13 MHz
Operating current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
All system active, running typical
program, cache disabled, and
LCD inactive
IDD
TBD
TBD
mA
V
operatin
Minimum standby voltage for
state retention and RTC
operation only
V
Standby supply voltage
See Table S on page 23.
TBD
DDstandby
a.
b.
c.
Assumes buffer has no pull-up or pull-down resistors.
The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
Note: 1) All power dissipation values can be derived from taking the particular IDD current and multiplying by 2.5 V.
2) The RTC of the EP7309 should be brought up at room temperature. This is required because the RTC OSC will NOT function
properly if it is brought up at –40°C. Once operational, it will continue to operate down to –20°C extended and 0°C
commercial.
3) A typical design will provide 3.3 V to the I/O supply (i.e., V IO), and 2.5 V to the remaining logic. This is to allow the I/O to be
DD
compatible with 3.3 V powered external logic.
4) Pull-up current = 50 µA typical at V = 3.3 V.
DD
10
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these
diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached
unless specifically stated.
Clock
High to Low
High/Low to High
Bus Change
Bus Valid
Undefined/Invalid
Valid Bus to Tristate
Bus/Signal Omission
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are
specified at VDD = 2.3 - 2.7 V and VSS = 0 V over an operating temperature of 0°C to +70°C. Those characteristics
marked with a # will be significantly different for 13 MHz mode because the EXPCLK is provided as an input rather
than generated internally. These timings are estimated at present. The timing values are referenced to 1/2 VDD
.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
11
EP7309
High-Performance, Low-Power System on Chip
Static Memory
Figure 2 through Figure 5 define the timings associated with all phases of the Static Memory. The following table
contains the values for the timings of each of the Static Memory modes.
Parameter
Symbol
Min
Typ
Max
Unit
t
EXPCLK rising edge to nCS assert delay time
EXPCLK falling edge to nCS deassert hold time
EXPCLK rising edge to A assert delay time
EXPCLK falling edge to A deassert hold time
EXPCLK rising edge to nMWE assert delay time
EXPCLK rising edge to nMWE deassert hold time
EXPCLK falling edge to nMOE assert delay time
EXPCLK falling edge to nMOE deassert hold time
EXPCLK falling edge to HALFWORD deassert delay time
EXPCLK falling edge to WORD assert delay time
EXPCLK rising edge to data valid delay time
EXPCLK falling edge to data invalid delay time
Data setup to EXPCLK falling edge time
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
8
4
4
8
4
4
4
4
4
4
20
8
-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CSd
t
CSh
t
Ad
t
Ah
t
MWd
t
MWh
t
MOEd
t
MOEh
t
HWd
t
WDd
t
Dv
t
Dnv
t
Ds
t
EXPCLK falling edge to data hold time
-
Dh
t
EXPCLK rising edge to WRITE assert delay time
EXPREADY setup to EXPCLK falling edge time
EXPCLK falling edge to EXPREADY hold time
8
-
WRd
t
EXs
t
-
EXh
12
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
A
nMWE
tMOEd
tMOEh
nMOE
tHWd
HALF
WORD
tWDd
WORD
tDs
tDh
D
tEXs
tEXh
EXPRDY
tWRd
WRITE
Figure 2. Static Memory Single Read Cycle Timing Measurement
Note: 1. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and
77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
13
EP7309
High-Performance, Low-Power System on Chip
Static Memory Single Write Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
A
tMWd
tMWh
nMWE
nMOE
tHWd
HALF
WORD
tWDd
WORD
tDv
D
tEXs
tEXh
EXPRDY
WRITE
Figure 3. Static Memory Single Write Cycle Timing Measurement
Note: 1. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and
77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
14
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
EXPCLK
tCSd
tCSh
nCS
tAh
tAd
tAh
tAh
A
nMWE
tMOEd
tMOEh
nMOE
tHWd
HALF
WORD
tWDd
WORD
D
tDs tDh
tDs tDh
tDs tDh
tDs tDh
tEXs
tEXh
EXPRDY
WRITE
tWRd
Figure 4. Static Memory Burst Read Cycle Timing Measurement
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and
77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
15
EP7309
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
EXPCLK
tCSd
tCSh
nCS
tAh
tAh
tAh
tAd
A
nMWE
nMOE
tMWd
tMWd
tMWd
tMWd
tMWh
tMWh
tMWh
tMWh
tHWd
HALF
WORD
tWDd
WORD
D
tDv
tDnv
tDv tDnv
tDv tDnv
tDv
tEXs
tEXh
EXPRDY
WRITE
Figure 5. Static Memory Burst Write Cycle Timing Measurement
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and
77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
16
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter
Symbol
Min
Max
Unit
t
ADCCLK falling edge to nADCCSS deassert delay time
ADCIN data setup to ADCCLK rising edge time
ADCIN data hold from ADCCLK rising edge time
ADCCLK falling edge to data valid delay time
ADCCLK falling edge to data invalid delay time
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
Cd
t
INs
t
INh
t
Ovd
t
Od
ADC
CLK
tCd
nADC
CSS
tINs
tINh
ADCIN
tOvd
tOd
ADC
OUT
Figure 6. SSI1 Interface Timing Measurement
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
17
EP7309
High-Performance, Low-Power System on Chip
SSI2 Interface
Parameter
Symbol
Min
Max
Unit
t
SSICLK period (slave mode)
0
512
1025
1025
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clk_per
t
SSICLK high time
925
925
clk_high
t
SSICLK low time
clk_low
t
SSICLK rise/fall time
clkrf
t
SSICLK rising edge to RX and/or TX frame sync high time
SSICLK rising edge to RX and/or TX frame sync low time
SSIRXFR and/or SSITXFR period
SSIRXDA setup to SSICLK falling edge time
SSIRXDA hold from SSICLK falling edge time
SSICLK rising edge to SSITXDA data valid delay time
SSITXDA valid time
528
448
FRd
t
FRa
t
750
30
FR_per
t
RXs
t
40
RXh
t
80
TXd
t
TXv
tclk_per
tclk_high
tclk_low
SSI
CLK
tclkrf
tFR_per
tFRd
tFRa
SSIRXFR/
SSITXFR
tRXh
tRXs
SSI
RXDA
D7
D2
D2
D1
D1
D0
D0
tTXd
SSI
TXDA
D7
tTXv
Figure 7. SSI2 Interface Timing Measurement
18
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
LCD Interface
Parameter
Symbol
Min
Max
Unit
t
CL[1] falling to CL[2] falling time
LCD CL[2] low time
200
80
6,950
3,475
3,475
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
clk
t
clk_low
t
LCD CL[2] high time
80
clk_high
t
CL[2] falling to CL[1] rising delay time
CL[1] falling to CL[2] rising delay time
LCD CL[1] high time
0
CL1d
t
80
3,475
3,475
10,425
20
CL2d
t
80
CL2h
t
CL[1] falling to FRM transition time
CL[1] falling to M transition time
CL[2] rising to DD (display data) transition time
300
− 10
− 10
FRMd
t
Md
t
20
DDd
tclk
tclk_low
tclk_high
CL[2]
tCL1d
tCL2d
tCL2h
CL[1]
FRM
tFRMd
tMd
M
tDDd
DD [3:0]
Figure 8. LCD Controller Timing Measurement
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
19
EP7309
High-Performance, Low-Power System on Chip
JTAG
Parameter
Symbol
Min
Max
Units
t
TCK clock period
100
50
50
20
45
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
clk_per
t
TCK clock high time
clk_high
t
TCK clock low time
-
clk_low
t
JTAG port setup time
-
JPs
t
JTAG port hold time
-
JPh
t
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
25
25
25
JPco
t
-
JPzx
t
-
JPxz
tclk_per
tclk_high
tclk_low
TCK
tJPh
tJPs
TMS
TDI
tJPzx
tJPco
tJPxz
TDO
Figure 9. JTAG Timing Measurement
20
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Packages
208-Pin LQFP Package Characteristics
208-Pin LQFP Package Specifications
29.60 (1.165)
30.40 (1.197)
27.80 (1.094)
28.20 (1.110)
0.17 (0.007)
0.27 (0.011)
27.80 (1.094)
28.20 (1.110)
29.60 (1.165)
30.40 (1.197)
EP7309
208-Pin LQFP
0.50
(0.0197)
BSC
Pin 1 Indicator
Pin 208
Pin 1
1.35 (0.053)
1.45 (0.057)
1.00 (0.039) BSC
0.45 (0.018)
0.75 (0.030)
0.09 (0.004)
0.20 (0.008)
0° MIN
7° MAX
0.05 (0.002)
0.15 (0.006)
1.40 (0.055)
1.60 (0.063)
Figure 10. 208-Pin LQFP Package Outline Drawing
Note: 1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.
2) Drawing above does not reflect exact package pin count.
3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
4) For pin locations, please see Figure 11. For pin descriptions see the EP7309 User’s Manual.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
21
EP7309
High-Performance, Low-Power System on Chip
208-Pin LQFP Pin Diagram
D[25]
A[25]
D[26]
A[26]
D[27]
A[27]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
157
158
159
160
161
162
163
VDDOSC
MOSCIN
MOSCOUT
VSSOSC
WAKEUP
nPWRFL
A[6]
164
D[6]
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
A[5]
D[5]
VDDIO
VSSIO
A[4]
D[4]
A[3]
D[3]
A[2]
VSSIO
D[2]
A[1]
D[1]
A[0]
D[0]
VSSCORE
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
FRM
EP7309
VSSIO
FB[1]
SMPCLK
ADCOUT
ADCCLK
DRIVE[0]
DRIVE[1]
VDDIO
VSSIO
VDDCORE
VSSCORE
nADCCS
ADCIN
SSIRXFR
SSIRXDA
SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]
PD[2]
PD[3]
TMS
VDDIO
PD[4]
PD[5]
PD[6]
PD[7]
208-Pin LQFP
(Top View)
M
DD[3]
DD[2]
VSSIO
DD[1]
DD[0]
N/C
N/C
N/C
N/C
VDDIO
VSSIO
N/C
N/C
nMWE
nMOE
VSSIO
nCS[0]
nCS[1]
nCS[2]
nCS[3]
nCS[4]
Figure 11. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
Note: 1. N/C should not be grounded but left as no connects.
2. Pin differences between the EP7212 and the EP7309 are bolded.
22
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
208-Pin LQFP Numeric Pin Listing
Table S. 208-Pin LQFP Numeric Pin Listing (Continued)
Reset
Table S. 208-Pin LQFP Numeric Pin Listing
Pin
Pin
No.
Signal
Type
Strength
Reset
State
State
Signal
Type
Strength
No.
38
39
40
41
42
43
44
45
DSR
nTEST[1]
nTEST[0]
EINT[3]
I
1
nCS[5]
VDDIO
VSSIO
EXPCLK
WORD
WRITE
RUN/CLKEN
EXPRDY
TXD[2]
RXD[2]
TDI
O
1
High
I
With p/u*
With p/u*
2
Pad Pwr
I
3
Pad Gnd
I
4
I/O
1
1
1
1
1
1
nEINT[2]
I
I
5
Out
Low
Low
Low
nEINT[1]
6
Out
nEXTFIQ
PE[2]/CLKSEL
I
7
O
I/O
1
1
Input
Input
8
I
PE[1]/
BOOTSEL[1]
46
47
I/O
I/O
9
O
High
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I
PE[0]/
BOOTSEL[0]
1
Input
I
with p/u*
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
VSSRTC
RTCOUT
RTCIN
RTC Gnd
VSSIO
PB[7]
Pad Gnd
O
I/O
1
1
1
1
1
1
1
1
Input
Input
Input
Input
Input
Input
Input
Input
I
PB[6]
I/O
VDDRTC
N/C
RTC power
PB[5]
I/O
PB[4]
I/O
PD[7]
I/O
1
1
1
1
Low
Low
Low
Low
PB[3]
I/O
PD[6]
I/O
PB[2]
I/O
PD[5]
I/O
PB[1]/PRDY2
PB[0]/PRDY1
VDDIO
TDO
I/O
PD[4]
I/O
I/O
VDDIO
Pad Pwr
Pad Pwr
TMS
I
with p/u*
O
1
1
1
1
1
1
1
1
1
1
1
1
Three state
Input
Input
Input
Input
Input
Input
Input
Input
Low
PD[3]
I/O
1
1
1
1
1
Low
Low
Low
Low
Input
PA[7]
I/O
PD[2]
I/O
PA[6]
I/O
PD[1]
I/O
PA[5]
I/O
PD[0]/LEDFLSH
SSICLK
VSSIO
I/O
PA[4]
I/O
I/O
PA[3]
I/O
Pad Gnd
PA[2]
I/O
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
ADCIN
I/O
1
1
Low
Low
PA[1]
I/O
O
PA[0]
I/O
I
LEDDRV
TXD[1]
VSSIO
PHDIN
CTS
O
I/O
I
Input
High
O
High
Pad Gnd
High
nADCCS
VSSCORE
VDDCORE
VSSIO
O
1
I
I
I
I
Core Gnd
Core Pwr
Pad Gnd
RXD[1]
DCD
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
23
EP7309
High-Performance, Low-Power System on Chip
Table S. 208-Pin LQFP Numeric Pin Listing (Continued)
Table S. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Reset
State
Pin
No.
Reset
State
Signal
Type
Strength
Signal
Type
Strength
74
75
VDDIO
Pad Pwr
I/O
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
D[23]
A[22]
D[22]
A[21]
D[21]
VSSIO
A[20]
D[20]
A[19]
D[19]
A[18]
D[18]
VDDIO
VSSIO
nTRST
A[17]
D[17]
A[16]
D[16]
A[15]
D[15]
A[14]
D[14]
A[13]
D[13]
A[12]
D[12]
A[11]
VDDIO
VSSIO
D[11]
A[10]
D[10]
A[9]
I/O
1
1
1
1
1
Low
Low
Low
Low
Low
High /
Low
O
DRIVE[1]
2
2
I/O
High /
Low
76
DRIVE[0]
I/O
O
I/O
77
78
ADCCLK
ADCOUT
SMPCLK
FB[1]
O
1
1
1
Low
Low
Low
Pad Gnd
O
O
1
1
1
1
1
1
Low
Low
Low
Low
Low
Low
79
O
I/O
80
I
O
81
VSSIO
FB[0]
Pad Gnd
I/O
82
I
O
83
COL[7]
COL[6]
COL[5]
COL[4]
COL[3]
COL[2]
VDDIO
TCLK
O
1
1
1
1
1
1
High
High
High
High
High
High
I/O
84
O
Pad Pwr
85
O
Pad Gnd
86
O
I
O
87
O
1
1
1
1
1
1
1
1
1
1
1
1
1
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
88
O
I/O
O
89
Pad Pwr
90
I
I/O
O
91
COL[1]
COL[0]
BUZ
O
1
1
1
1
1
1
1
High
High
Low
Low
Low
Low
Low
92
O
I/O
O
93
O
94
D[31]
I/O
I/O
O
95
D[30]
I/O
96
D[29]
I/O
I/O
O
97
D[28]
I/O
98
VSSIO
A[27]
Pad Gnd
I/O
O
99
O
2
1
2
1
2
1
1
1
Low
Low
Low
Low
Low
Low
Low
Low
—
100
101
102
103
104
105
106
107
108
109
110
D[27]
I/O
Pad Pwr
Pad Gnd
I/O
O
A[26]
O
D[26]
I/O
1
1
1
1
1
1
1
1
Low
Low
Low
Low
Low
Low
Low
Low
A[25]
O
D[25]
I/O
I/O
O
HALFWORD
A[24]
O
O
D[9]
I/O
O
VDDIO
VSSIO
D[24]
Pad Pwr
Pad Gnd
I/O
A[8]
—
D[8]
I/O
O
1
1
Low
Low
A[7]
A[23]
O
24
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Table S. 208-Pin LQFP Numeric Pin Listing (Continued)
Table S. 208-Pin LQFP Numeric Pin Listing (Continued)
Reset
Pin
No.
Reset
State
Pin
No.
Signal
Type
Strength
Signal
Type
Strength
State
149
150
151
152
153
154
VSSIO
D[7]
Pad Gnd
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
M
O
1
1
1
Low
Low
Low
I/O
1
Low
DD[3]
DD[2]
VSSIO
DD[1]
DD[0]
N/C
I/O
nBATCHG
nEXTPWR
BATOK
nPOR
I
I
I
I
I/O
Pad Gnd
I/O
1
1
1
1
2
2
Low
Low
High
High
Low
Low
Schmitt
Schmitt
I/O
nMEDCHG/
nBROM
O
155
I
N/C
O
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
nURESET
VDDOSC
MOSCIN
MOSCOUT
VSSOSC
WAKEUP
nPWRFL
A[6]
I
N/C
I/O
Osc Pwr
N/C
I/O
Osc
VDDIO
VSSIO
N/C
Pad Pwr
Osc
Pad Gnd
Osc Gnd
I/O
2
2
1
1
Low
Low
High
High
I
Schmitt
N/C
I/O
I
nMWE
nMOE
VSSIO
nCS[0]
nCS[1]
nCS[2]
nCS[3]
nCS[4]
O
O
1
1
1
1
Low
Low
Low
Low
O
D[6]
I/O
Pad Gnd
A[5]
Out
O
O
O
O
O
1
1
1
1
1
High
High
High
High
High
D[5]
I/O
VDDIO
VSSIO
A[4]
Pad Pwr
Pad Gnd
O
1
1
2
1
2
Low
Low
Low
Low
Low
D[4]
I/O
A[3]
O
*With p/u’ means with internal pull-up on the pin.
D[3]
I/O
A[2]
O
VSSIO
D[2]
Pad Gnd
I/O
1
2
1
2
1
Low
Low
Low
Low
Low
A[1]
O
D[1]
I/O
O
A[0]
D[0]
I/O
VSS CORE
VDD CORE
VSSIO
VDDIO
CL[2]
Core Gnd
Core Pwr
Pad Gnd
Pad Pwr
O
1
1
1
Low
Low
Low
CL[1]
O
FRM
O
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
25
EP7309
High-Performance, Low-Power System on Chip
204-Ball TFBGA Package Characteristics
204-Ball TFBGA Package Specifications
TOP VIEW
BOTTOM VIEW
Ø0.08 M
C
Ø0.15 M C A B
Ø0.25~0.35(204X)
A1 CORNER
A1 CORNER
1
2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 18 19 20
20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
T
M
N
P
R
T
U
V
W
Y
U
V
W
Y
A
0.65
12.35
B
13 0.05
C
0.15(4X)
Substrate Thickness :
0.36
Ball Pitch :
0.65
0.3
Ball Diameter :
Mold Thickness :
SEATING PLANE
C
0.53
Figure 12. 204-Ball TFBGA Package
26
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
204-Ball TFBGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
A2
14
15
16
17
18
19
20
A
B
C
D
E
F
VDDR EXPCLK nCS3 nCS1 nMWE N/C
N/C
DD2
FRM
CL1
GNDD
D1
D4
A5 nPWRFLMOSCOUT GNDR
GNDR
GNDR
A
WORD
VDDR
nCS5 nCS2 nMOE
N/C
N/C
N/C
N/C
DD1
DD0
M
CL2
D0
A0
A1
D2
D3
A3
A4
D5
D6 WAKEUP MOSCIN
GNDR
GNDR
GNDR nURESET B
RUN/
CLKEN
EXPRDY VDDR nCS4 nCS0
DD3
VDDD
A6
GNDO
VDDO
BATOK
nPOR
A7
C
D
E
F
PB7
PB4
PB3
PB1
PA7
PA4
PA1
RXD2
VDDR
GNDR nBATCHG
nMEDCHG
nEXTPWR
/nBROM
TXD2 WRITE
D9
PB6
PB2
TDO
PA5
PA2
TDI
PB5
D7
D8
A8
D10
D11
A12
A13
D15
A16
nTRST
A18
D20
A21
G
H
J
A9
G
H
J
PB0
A10
A11
D14
VDDR
A15
D17
D18
A19
D12
D13
A14
D16
A17
D19
A20
D22
PA6
K
L
VDDR
K
L
TXD1 LEDDRV PA3
M
N
P
RXD1
DSR
CTS
PA0
M
N
P
R
nTEST1 PHDIN
EINT3 nEINT2
PE2/
DCD
R nEXTFIQ
nTEST0
CLKSEL
PE1/
PE0/
T
BOOT
SEL1
BOOT nEINT1
SEL0
D21
D23
A22
T
HALF
WORD
U
V
GNDC RTCOUT RTCIN
D24
A23
A24
D25
U
V
VDDC
GNDR
GNDR GNDR PD7
PD4
TMS
PD2
SSICLK SSIRXDAnADCCS VDDR ADCCLK COL7 COL4 TCLK BUZ
D29
D30
A26
A27
VDDR
D26
VDDR
VDDR
W
GNDR GNDR PD6
GNDR GNDR PD5
PD1 SSITXFR SSIRXFR GNDD1 DRIVE1 ADCOUT FB0 COL5 COL2 COL0
W
PD0/
Y
GNDR
PD3
LED SSITXDA ADCIN VDD1 DRIVE0 SMPLCK FB1 COL6 COL3 COL1
D31
D28
D27
A25
VDDR
Y
FLSH
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
27
EP7309
High-Performance, Low-Power System on Chip
TFBGA Ball List
Table T. 204-Ball TFBGA Ball List (Continued)
Table T. 204-Ball TFBGA Ball List
Die Pad
Bond Pad Package Ball
Signal
Die Pad
Bond Pad Package Ball
Signal
U2.38
U2.39
U2.40
U2.41
U2.42
U2.43
U2.44
U2.45
U2.46
U2.47
U2.48
U2.49
U2.50
U2.51
U2.53
U2.54
U2.55
U2.56
U2.57
U2.58
U2.59
U2.60
U2.61
U2.62
U2.63
U2.64
U2.65
U2.66
U2.67
U2.68
U2.69
U2.70
U2.71
U2.72
U2.73
U2.74
U2.75
U2.76
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
N1
N2
R3
P1
DSR
nTEST1
nTEST0
EINT3
U2.1
U2.2
1
B3
Y20
B18
A2
B1
E3
C1
C2
E2
D2
F3
nCS5
VDDR
GNDR
EXPCLK
WORD
WRITE
RUN/CLKEN
EXPRDY
TXD2
RXD2
TDI
2
U2.3
3
U2.4
4
P2
nEINT2
nEINT1
nEXTFIQ
PE2/CLKSEL
PE1/BOOTSEL1
PE0/BOOTSEL0
GNDC
U2.5
5
T3
U2.6
6
R1
R2
T1
U2.7
7
U2.8
8
U2.9
9
T2
U2.10
U2.11
U2.12
U2.13
U2.14
U2.15
U2.16
U2.17
U2.18
U2.19
U2.20
U2.21
U2.22
U2.23
U2.24
U2.25
U2.26
U2.27
U2.28
U2.29
U2.30
U2.31
U2.32
U2.33
U2.34
U2.35
U2.36
U2.37
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
U1
U2
U3
V1
RTCOUT
RTCIN
B18
D1
F2
GNDR
PB7
VDDC
PB6
V4
PD7
G3
E1
F1
PB5
W4
Y4
PD6
PB4
PD5
PB3
V5
PD4
G2
G1
H3
Y20
H2
H1
J3
PB2
L18
W5
Y5
VDDR
PB1
TMS
PB0
PD3
VDDR
TDO
V6
PD2
W6
Y6
PD1
PA7
PD0/LEDFLSH
SSICLK
GNDR
PA6
V7
J2
PA5
D18
W7
Y7
J1
PA4
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
ADCIN
L3
PA3
K2
K1
M3
L2
PA2
V8
PA1
W8
Y8
PA0
LEDDRV
TXD1
GNDR
PHDIN
CTS
V9
nADCCS
GNDD1
VDD1
L1
W9
Y9
B18
N3
M2
M1
P3
W3
V10
L18
W10
GNDR
VDDR
RXD1
DCD
VDDR
DRIVE1
28
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Table T. 204-Ball TFBGA Ball List (Continued)
Table T. 204-Ball TFBGA Ball List (Continued)
Die Pad
Bond Pad Package Ball
Signal
Die Pad
Bond Pad Package Ball
Signal
U2.77
U2.78
U2.79
U2.80
U2.81
U2.82
U2.83
U2.84
U2.85
U2.86
U2.87
U2.88
U2.89
U2.90
U2.91
U2.92
U2.93
U2.94
U2.95
U2.96
U2.97
U2.98
U2.99
U2.100
U2.101
U2.102
U2.103
U2.104
U2.105
U2.106
U2.107
U2.108
U2.109
U2.110
U2.111
U2.112
U2.113
U2.114
U2.115
76
77
Y10
V11
W11
Y11
Y12
Y3
DRIVE0
ADCCLK
ADCOUT
SMPLCK
FB1
U2.116
U2.117
U2.118
U2.119
U2.120
U2.121
U2.122
U2.123
U2.124
U2.125
U2.126
U2.127
U2.128
U2.129
U2.130
U2.131
U2.132
U2.133
U2.134
U2.135
U2.136
U2.137
U2.138
U2.139
U2.140
U2.141
U2.142
U2.143
U2.144
U2.145
U2.146
U2.147
U2.148
U2.149
U2.150
U2.151
U2.152
U2.153
U2.154
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
T18
Y3
D21
GNDR
A20
78
P19
P20
R18
N19
N20
P18
A1
79
D20
80
A19
81
GNDR
FB0
D19
82
W12
V12
Y13
W13
V13
Y14
W14
A1
A18
83
COL7
COL6
COL5
COL4
COL3
COL2
VDDR
TCLK
COL1
COL0
BUZ
D18
84
VDDR
GNDR
nTRST
A17
85
Y3
86
M20
M19
N18
L20
L19
M18
K20
K19
K18
J20
J19
H20
H19
J18
K3
87
88
D17
89
A16
90
V14
Y15
W15
V15
Y16
W16
V16
Y17
Y3
D16
91
A15
92
D15
93
A14
94
D31
D14
95
D30
A13
96
D29
D13
97
D28
A12
98
GNDR
A27
D12
99
W17
Y18
V17
W18
Y19
W20
U18
V20
A1
A11
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
D27
VDDR
GNDR
D11
A26
Y3
D26
G20
H18
F20
G19
E20
F19
G18
D20
Y3
A25
A10
D25
D10
HALFWORD
A24
A9
D9
VDDR
GNDR
D24
A8
Y3
D8
U19
U20
T19
T20
R19
R20
A7
A23
GNDR
D7
D23
F18
D19
E19
C19
A22
nBATCHG
nEXTPWR
BATOK
D22
A21
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
29
EP7309
High-Performance, Low-Power System on Chip
Table T. 204-Ball TFBGA Ball List (Continued)
Table T. 204-Ball TFBGA Ball List (Continued)
Die Pad
Bond Pad Package Ball
Signal
Die Pad
Bond Pad Package Ball
Signal
U2.155
U2.156
U2.157
U2.158
U2.159
U2.160
U2.161
U2.162
U2.163
U2.164
U2.165
U2.166
U2.167
U2.168
U2.169
U2.170
U2.171
U2.172
U2.173
U2.174
U2.175
U2.176
U2.177
U2.178
U2.179
U2.180
U2.181
U2.182
U2.183
U2.184
U2.185
U2.186
U2.187
U2.188
U2.189
U2.190
U2.191
U2.192
U2.193
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
C20
E18
B20
C17
B17
A17
C16
B16
A16
C15
B15
A15
C14
A1
nPOR
nMEDCHG/nBROM
nURESET
VDDO
MOSCIN
MOSCOUT
GNDO
WAKEUP
nPWRFL
A6
U2.194
U2.195
U2.196
U2.197
U2.198
U2.199
U2.200
U2.201
U2.202
U2.203
U2.204
U2.205
U2.206
U2.207
U2.208
U2.209
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
A7
B7
N/C
N/C
C7
N/C
A6
N/C
V18
B18
B6
VDDR
GNDR
N/C
C6
N/C
A5
nMWE
nMOE
GNDR
nCS0
nCS1
nCS2
nCS3
nCS4
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
GNDR
GNDR
GNDR
GNDR
GNDR
GNDR
GNDR
GNDR
GNDR
GNDR
GNDR
GNDR
B5
D6
B18
C5
A5
D5
A4
VDDR
GNDR
A4
B4
Y3
A3
B14
A14
C13
B13
A13
Y3
C4
D4
A1
A3
B2
D3
C3
A2
D3
GNDR
D2
K3
C12
B12
A12
C11
B11
A11
C10
Y3
L18
V18
V19
W19
Y20
A18
A19
A20
B18
B19
C18
D18
V2
A1
D1
A0
D0
GNDD
VDDD
GNDR
VDDR
CL2
Y20
B10
A10
A9
CL1
FRM
B9
M
C9
DD3
V3
A8
DD2
W1
W2
W3
Y3
GNDR
DD1
B8
C8
DD0
30
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Table T. 204-Ball TFBGA Ball List (Continued)
Die Pad
Bond Pad Package Ball
Signal
Y1
Y2
Y3
GNDR
GNDR
GNDR
256-Ball PBGA Package Characteristics
256-Ball PBGA Package Specifications
Figure 13. 256-Ball PBGA Package
Note: 1) For pin locations see Table U.
2) Dimensions are in millimeters (inches), and controlling dimension is millimeter
3) Before beginning any new EP7309 design, contact Cirrus Logic for the latest package information.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
31
EP7309
High-Performance, Low-Power System on Chip
0.85 (0.034)
0.05 (.002)
17.00 (0.669)
0.20 (.008)
0.40 (0.016)
0.05 (.002)
Pin 1 Corner
(0.590)
15.00
0.20 (.008)
D1
30° TYP
Pin 1 Indicator
17.00 (0.669)
0.20 (.008)
E1
15.00 (0.590)
0.20 (.008)
2 Layer
0.36 (0.014)
0.09 (0.004)
TOP VIEW
SIDE VIEW
D
17.00 (0.669)
Pin 1 Corner
1.00 (0.040)
1.00 (0.040)
REF
E
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1.00 (0.040)
A
B
C
D
E
F
REF
G
H
J
1.00 (0.040)
17.00 (0.669)
K
L
M
N
P
R
T
0.50
BOTTOM VIEW
R
3 Places
JEDEC #: MO-151
Ball Diameter: 0.50 mm 0.10 mm
17 ¥ 17 ¥ 1.61 mm body
32
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
256-Ball PBGA Pinout (Top View))
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
VDDIO
nCS[4]
nCS[1]
N/C
N/C
DD[1]
M
VDDIO
D[0]
D[2]
A[3]
VDDIO
A[6]
MOSCOUT VDDOSC VSSIO
WAKEUP VDDIO nURESET
A
B
nCS[5]
VDDIO
WRITE
RXD[2]
PB[5]
VDDIO
EXPCLK
EXPRDY
PB[7]
nCS[3]
VSSIO
VSSIO
TDI
nMOE
VDDIO
VDDIO
WORD
TXD[2]
PB[4]
VDDIO
VSSIO
nCS[2]
VSSIO
N/C
DD[2]
VSSIO
N/C
CL[1]
VDDIO
CL[2]
FRM
VDDCORE
VSSIO
VSSRTC
A[0]
D[1]
VSSIO
D[4]
A[2]
A[4]
A[5]
VSSIO
nMWE
nCS[0]
VSSIO
VSSIO
VDDIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
nTRST
VSSIO
VSSIO
VDDIO
nPOR nEXTPWR C
nPWRFL MOSCIN
D[7]
D[9]
D[8]
D[10]
D
E
F
nMEDCHG/
nBROM
N/C
D[5]
VSSOSC
VSSRTC
A[7]
VSSIO
BATOK
A[8]
RUN/
CLKEN
PB[3]
VSSIO
TDO
N/C
DD[3]
DD[0]
A[1]
D[6]
nBATCHG
A[9]
D[11]
D[12]
D[14]
D[16]
VDDIO
A[18]
A[20]
D[22]
D[24]
VDDIO
D[25]
VDDIO
D[13]
G
H
J
PB[1]
VDDIO
PA[5]
PB[6]
PA[6]
PA[0]
VSSRTC VSSRTC
D[3]
VSSRTC
A[10]
G
H
J
PA[7]
VSSIO
VSSIO
VSSIO
VDDIO
VDDIO
VSSIO
VSSIO
PD[4]
PA[4]
PB[0]
PB[2]
CTS
VSSRTC VSSRTC
VSSRTC VSSRTC
A[11]
A[12]
A[15]
D[19]
A[22]
VSSIO
D[26]
VSSIO
D[30]
BUZ
A[13]
D[15]
PA[3]
PA[1]
PA[2]
TXD[1]
A[17]
A[16]
A[14]
D[17]
K
L
LEDDRV
RXD[1]
PHDIN
DSR
DCD
nTEST[1] EINT[3]
VSSRTC
ADCIN
COL[4]
COL[6]
FB[0]
TCLK
D[31]
D[20]
D[18]
A[21]
VDDIO
A[19]
K
L
PE[2]/
PD[0]/
LEDFLSH
nEINT[1]
VSSRTC
CLKSEL
VSSRTC
VSSRTC
D[27]
PE[0]/
BOOTSEL[0]
M
N
P
R
T
nTEST[0] nEINT[2]
TMS
PD[5]
VDDIO
VDDIO
PD[2]
SSITXFR DRIVE[1]
COL[0]
COL[2]
VDDIO
COL[3]
COL[5]
A[23]
D[21]
M
N
P
R
T
PE[1]/
nEXTFIQ
VDDIO
VSSIO
PD[1]
SSIRXDA ADCCLK SMPCLK
D[29]
HALFWORD VSSIO
D[23]
BOOTSEL[1]
VSSRTC RTCOUT
VSSIO
VSSIO
VDDIO
VDDIO
VSSIO
COL[7]
FB[1]
VSSIO
COL[1]
VDDIO
VDDIO
A[27]
VSSIO
A[25]
VDDIO
A[24]
RTCIN
VDDIO
PD[7]
SSITXDA nADCCS
ADCOUT
VDDRTC
PD[6]
PD[3]
SSICLK SSIRXFR VDDCORE DRIVE[0]
D[28]
A[26]
VSSIO
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table U. 256-Ball PBGA Ball Listing (Continued)
Table U. 256-Ball PBGA Ball Listing
Ball Location
Name
Type
Description
Ball Location
Name
VDDIO
Type
Description
A12
A13
A14
VDDIO
A[6]
Pad power Digital I/O power, 3.3V
A1
A2
Pad power Digital I/O power, 3.3V
O
O
System byte address
Main oscillator out
nCS[4]
nCS[1]
N/C
O
O
O
O
O
O
Chip select out
MOSCOUT
A3
Chip select out
Oscillator
power
A15
VDDOSC
Oscillator power in, 2.5V
A4
A5
N/C
A16
B1
B2
B3
B4
B5
B6
VSSIO
nCS[5]
VDDIO
nCS[3]
nMOE
VDDIO
N/C
Pad ground I/O ground
A6
DD[1]
M
LCD serial display data
LCD AC bias drive
O
Chip select out
A7
Pad power I/O ground
A8
VDDIO
D[0]
Pad power Digital I/O power, 3.3V
O
O
Chip select out
ROM, expansion OP enable
A9
I/O
I/O
O
Data I/O
A10
A11
D[2]
Data I/O
Pad power Digital I/O power, 3.3V
O
A[3]
System byte address
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
33
EP7309
High-Performance, Low-Power System on Chip
Table U. 256-Ball PBGA Ball Listing (Continued)
Table U. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
LCD serial display data
LCD line clock
Ball Location
Name
Type
Description
B7
B8
DD[2]
CL[1]
O
O
E7
E8
N/C
FRM
A[0]
D[5]
O
O
LCD frame synchronization pulse
System byte address
Data I/O
B9
VDDCORE
D[1]
Core power Digital core power, 2.5V
E9
O
B10
B11
B12
B13
B14
B15
B16
C1
I/O
O
O
O
I
Data I/O
E10
I/O
A[2]
System byte address
System byte address
System byte address
System wake up input
Oscillator
ground
E11
E12
E13
VSSOSC
VSSIO
PLL ground
A[4]
Pad ground I/O ground
A[5]
Media change interrupt input / internal
rom boot enable
nMEDCHG/nBROM
I
WAKEUP
VDDIO
nURESET
VDDIO
EXPCLK
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
nPOR
Pad power Digital I/O power, 3.3V
User reset input
Pad power Digital I/O power, 3.3V
Expansion clock input
E14
E15
E16
F1
VDDIO
D[9]
Pad power Digital I/O power, 3.3V
I
I/O
Data I/O
D[10]
I/O
Data I/O
C2
I
PB[5]
I
I
GPIO port B
GPIO port B
C3
Pad ground I/O ground
F2
PB[3]
C4
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
F3
VSSIO
TXD[2]
RUN/CLKEN
VSSIO
N/C
Pad ground I/O ground
C5
F4
O
O
UART 2 transmit data output
Run output / clock enable output
C6
Pad ground I/O ground
F5
C7
Pad ground I/O ground
F6
Pad ground I/O ground
O
C8
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
F7
C9
F8
DD[3]
O
O
LCD serial display data
C10
C11
C12
C13
C14
C15
C16
D1
Pad ground I/O ground
F9
A[1]
System byte address
Data I/O
Pad ground I/O ground
F10
F11
F12
F13
F14
F15
F16
D[6]
I/O
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
VSSRTC
BATOK
nBATCHG
VSSIO
D[11]
RTC ground Real time clock ground
I
I
Battery ok input
Pad ground I/O ground
Battery changed sense input
I
I
Power-on reset input
Pad ground I/O ground
I/O Data I/O
Pad power Digital I/O power, 3.3V
nEXTPWR
WRITE
EXPRDY
VSSIO
VDDIO
nCS[2]
nMWE
N/C
External power supply sense input
Transfer direction
O
I
VDDIO
D2
Expansion port ready input
GPIO port B / CL-PS6700 interface
signal
G1
PB[1]/PRDY[2]
I
D3
Pad ground I/O ground
G2
G3
VDDIO
TDO
Pad power Digital I/O power, 3.3V
D4
Pad power Digital I/O power, 3.3V
O
I
JTAG data out
GPIO port B
GPIO port B
D5
O
O
O
O
Chip select out
G4
PB[4]
PB[6]
VSSRTC
VSSRTC
DD[0]
D[3]
D6
ROM, expansion write enable
G5
I
D7
G6
Core ground Real time clock ground
RTC ground Real time clock ground
D8
CL[2]
LCD pixel clock out
G7
D9
VSSRTC
D[4]
Core ground Real time clock ground
G8
O
LCD serial display data
Data I/O
D10
D11
D12
D13
D14
D15
D16
E1
I/O
Data I/O
G9
I/O
nPWRFL
MOSCIN
VDDIO
VSSIO
D[7]
I
I
Power fail sense input
Main oscillator input
G10
G11
G12
G13
G14
G15
G16
H1
VSSRTC
A[7]
RTC ground Real time clock ground
O
O
O
System byte address
System byte address
System byte address
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
A[8]
A[9]
I/O
Data I/O
VSSIO
D[12]
Pad ground I/O ground
D[8]
I/O
Data I/O
I/O
Data I/O
RXD[2]
PB[7]
I
I
UART 2 receive data input
GPIO port B
D[13]
I/O
Data I/O
E2
PA[7]
I
I
GPIO port A
GPIO port A
E3
TDI
I
JTAG data input
Word access select output
H2
PA[5]
E4
WORD
VSSIO
nCS[0]
O
H3
VSSIO
PA[4]
Pad ground I/O ground
E5
Pad ground I/O ground
Chip select out
H4
I
I
GPIO port A
GPIO port A
E6
O
H5
PA[6]
34
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Table U. 256-Ball PBGA Ball Listing (Continued)
Table U. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
Ball Location
Name
Type
Description
GPIO port B / CL-PS6700 interface
signal
L6
L7
VSSRTC
PD[0]/LEDFLSH
VSSRTC
COL[6]
RTC ground Real time clock ground
H6
PB[0]/PRDY[1]
I
I
I/O
GPIO port D / LED blinker output
H7
H8
PB[2]
VSSRTC
VSSRTC
A[10]
GPIO port B
L8
Core ground Real time clock ground
RTC ground Real time clock ground
RTC ground Real time clock ground
L9
O
Keyboard scanner column drive
Data I/O
H9
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
D[31]
I/O
H10
H11
H12
H13
H14
H15
H16
J1
O
O
O
O
System byte address
System byte address
System byte address
System byte address
VSSRTC
A[22]
RTC ground Real time clock ground
A[11]
O
O
System byte address
System byte address
A[12]
A[21]
A[13]
VSSIO
Pad ground I/O ground
VSSIO
D[14]
Pad ground I/O ground
A[18]
O
O
I
System byte address
I/O
Data I/O
A[19]
System byte address
Test mode select input
External interrupt input
D[15]
I/O
Data I/O
nTEST[0]
nEINT[2]
VDDIO
PA[3]
I
I
GPIO port A
GPIO port A
I
J2
PA[1]
Pad power Digital I/O power, 3.3V
GPIO port E / Boot mode select
JTAG mode select
Pad power Digital I/O power, 3.3V
J3
VSSIO
PA[2]
Pad ground I/O ground
PE[0]/BOOTSEL[0]
TMS
I
J4
I
I
GPIO port A
I
J5
PA[0]
GPIO port A
VDDIO
J6
TXD[1]
CTS
O
I
UART 1 transmit data out
UART 1 clear to send input
SSITXFR
DRIVE[1]
FB[0]
I/O
I/O
I
DAI/CODEC/SSI2 frame sync
PWM drive output
J7
J8
VSSRTC
VSSRTC
A[17]
RTC ground Real time clock ground
RTC ground Real time clock ground
PWM feedback input
Keyboard scanner column drive
Data I/O
J9
COL[0]
O
J10
J11
J12
J13
J14
J15
J16
K1
O
O
O
O
I
System byte address
System byte address
System byte address
System byte address
JTAG async reset input
Data I/O
D[27]
I/O
A[16]
VSSIO
Pad ground I/O ground
A[15]
A[23]
O
System byte address
A[14]
VDDIO
Pad power Digital I/O power, 3.3V
nTRST
D[16]
A[20]
O
I/O
I
System byte address
Data I/O
I/O
I/O
O
I
D[21]
D[17]
Data I/O
nEXTFIQ
PE[1]/BOOTSEL[1]
VSSIO
External fast interrupt input
GPIO port E / boot mode select
LEDDRV
PHDIN
VSSIO
DCD
IR LED drivet
N2
I
K2
Photodiode input
N3
Pad ground I/O ground
K3
Pad ground I/O ground
N4
VDDIO
Pad power Digital I/O power, 3.3V
K4
I
I
I
UART 1 data carrier detect
N5
PD[5]
I/O
I/O
I/O
O
GPIO port D
K5
nTEST[1]
EINT[3]
VSSRTC
ADCIN
COL[4]
TCLK
Test mode select input
External interrupt
N6
PD[2]
GPIO port D
K6
N7
SSIRXDA
ADCCLK
SMPCLK
COL[2]
DAI/CODEC/SSI2 serial data input
SSI1 ADC serial clock
SSI1 ADC sample clock
Keyboard scanner column drive
Data I/O
K7
RTC ground Real time clock ground
N8
K8
I
SSI1 ADC serial input
Keyboard scanner column drive
JTAG clock
N9
O
K9
O
N10
N11
N12
N13
N14
N15
N16
P1
O
K10
K11
K12
K13
K14
K15
K16
L1
I
D[29]
I/O
I/O
O
D[20]
I/O
I/O
I/O
Data I/O
D[26]
Data I/O
D[19]
Data I/O
HALFWORD
VSSIO
Halfword access select output
D[18]
Data I/O
Pad ground I/O ground
VSSIO
VDDIO
VDDIO
RXD[1]
DSR
Pad ground I/O ground
D[22]
I/O
I/O
Data I/O
Data I/O
Pad power Digital I/O power, 3.3V
Pad power Digital I/O power, 3.3V
D[23]
VSSRTC
RTCOUT
VSSIO
RTC ground Real time clock ground
I
I
UART 1 receive data input
UART 1 data set ready input
P2
O
Real time clock oscillator output
L2
P3
Pad ground I/O ground
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
L3
VDDIO
nEINT[1]
PE[2]/CLKSEL
Pad power Digital I/O power, 3.3V
P4
VSSIO
L4
I
I
External interrupt input
P5
VDDIO
L5
GPIO port E / clock input mode select
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
35
EP7309
High-Performance, Low-Power System on Chip
Table U. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
P6
P7
VSSIO
VSSIO
VDDIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
D[24]
Pad ground I/O ground
Pad ground I/O ground
P8
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
P9
P10
P11
P12
P13
P14
P15
P16
R1
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
Pad ground I/O ground
Pad power Digital I/O power
Pad ground I/O ground
I/O
Data I/O
VDDIO
RTCIN
VDDIO
PD[4]
Pad power Digital I/O power, 3.3V
I/O
Real time clock oscillator input
R2
Pad power Digital I/O power, 3.3V
R3
I/O
I/O
O
GPIO port D
R4
PD[1]
GPIO port D
R5
SSITXDA
nADCCS
VDDIO
ADCOUT
COL[7]
COL[3]
COL[1]
D[30]
DAI/CODEC/SSI2 serial data output
SSI1 ADC chip select
R6
O
R7
Pad power Digital I/O power, 3.3V
R8
O
O
SSI1 ADC serial data output
Keyboard scanner column drive
Keyboard scanner column drive
Keyboard scanner column drive
Data I/O
R9
R10
R11
R12
R13
R14
R15
R16
T1
O
O
I/O
O
A[27]
System byte address
A[25]
O
System byte address
VDDIO
A[24]
Pad power Digital I/O power, 3.3V
System byte address
RTC power Real time clock power, 2.5V
O
VDDRTC
PD[7]
T2
I/O
I/O
I/O
I/O
–
GPIO port D
T3
PD[6]
GPIO port D
T4
PD[3]
GPIO port D
T5
SSICLK
SSIRXFR
VDDCORE
DRIVE[0]
FB[1]
DAI/CODEC/SSI2 serial clock
DAI/CODEC/SSI2 frame sync
T6
T7
Core power Core power, 2.5V
T8
I/O
I
PWM drive output
T9
PWM feedback input
T10
T11
T12
T13
T14
T15
T16
COL[5]
VDDIO
BUZ
O
Keyboard scanner column drive
Pad power Digital I/O power, 3.3V
O
I/O
O
Buzzer drive output
Data I/O
D[28]
A[26]
System byte address
Data I/O
D[25]
I/O
VSSIO
Pad ground I/O ground
36
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
JTAG Boundary Scan Signal Ordering
Table V. JTAG Boundary Scan Signal Ordering
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
1
B3
A2
B1
E3
C1
C2
E2
D2
F3
D1
F2
G3
E1
F1
G2
G1
H3
H1
J3
B1
C2
E4
D1
F5
D2
F4
E1
E2
G5
F1
G4
F2
H7
G1
H6
H1
H5
H2
H4
J1
nCS[5]
EXPCLK
WORD
WRITE
RUN/CLKEN
EXPRDY
TXD2
O
I/O
O
1
4
3
5
6
6
O
8
7
O
10
13
14
16
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
67
69
70
71
72
73
74
75
76
77
78
8
I
9
O
10
13
14
15
16
17
18
19
20
23
24
25
26
27
28
29
30
31
32
34
35
36
37
38
39
40
41
42
43
RXD2
I
PB[7]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]/PRDY2
PB[0]/PRDY1
PA[7]
PA[6]
PA[5]
J2
PA[4]
J1
PA[3]
L3
J4
PA[2]
K2
K1
M3
L2
J2
PA[1]
J5
PA[0]
K1
J6
LEDDRV
TXD1
O
L1
K2
J7
PHDIN
CTS
I
N3
M2
M1
P3
N1
N2
R3
P1
P2
I
L1
K4
L2
K5
M1
K6
M2
L4
RXD1
I
DCD
I
DSR
I
nTEST1
nTEST0
EINT3
nEINT2
nEINT1
I
I
I
I
I
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
37
EP7309
High-Performance, Low-Power System on Chip
Table V. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
44
45
46
47
53
54
55
56
59
60
61
62
68
69
70
75
76
77
78
79
80
82
83
84
85
86
87
88
91
92
93
94
95
96
97
99
100
101
T3
R1
N1
L5
nEXTFIQ
PE[2]/CLKSEL
PE[1]/BOOTSEL1
PE[0]/BOOTSEL0
PD[7]
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
79
80
R2
N2
83
T1
M4
T2
86
T2
89
V4
T3
PD[6]
92
W4
Y4
N5
PD[5]
95
R3
PD[4]
98
V5
T4
PD[3]
101
104
107
110
122
125
126
128
131
134
136
138
140
141
142
144
146
148
150
152
154
156
158
160
163
166
169
172
174
177
W5
Y5
N6
PD[2]
R4
PD[1]
V6
L7
PD[0]/LEDFLSH
SSIRXFR
ADCIN
nADCCS
DRIVE1
DRIVE0
ADCCLK
ADCOUT
SMPCLK
FB1
W6
Y6
T6
I/O
I
K8
W8
Y8
R6
O
M8
T8
I/O
I/O
O
V9
W10
Y10
V11
W11
Y11
Y12
W12
V12
Y13
W13
V13
Y14
W14
A1
N8
R8
O
N9
O
T9
I
M9
R9
FB0
I
COL7
O
L9
COL6
O
T10
K9
COL5
O
COL4
O
R10
N10
R11
M10
T12
L10
R12
N11
T13
R13
M11
T14
COL3
O
COL2
O
COL1
O
COL0
O
BUZ
O
V14
Y15
W15
V15
Y16
W16
V16
D[31]
I/O
I/O
I/O
I/O
Out
I/O
O
D[30]
D[29]
D[28]
A[27]
D[27]
A[26]
38
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Table V. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
102
103
104
105
106
109
110
111
112
113
114
115
117
118
119
120
121
122
126
127
128
129
130
131
132
133
134
135
136
137
138
141
142
143
144
145
146
147
Y17
W17
Y18
V17
W18
Y19
W20
U18
V20
U19
U20
T19
T20
R19
R20
T18
P19
P20
R18
N19
N20
P18
M19
N18
L20
L19
M18
K20
K19
K18
J20
J19
H20
H19
J18
K3
N12
R14
T15
N13
R16
P15
M13
N16
L12
N15
L13
M16
M15
K11
L16
K12
L15
K13
J10
D[26]
A[25]
D[25]
HALFWORD
A[24]
D[24]
A[23]
D[23]
A[22]
D[22]
A[21]
D[21]
A[20]
D[20]
A[19]
D[19]
A[18]
D[18]
A[17]
D[17]
A[16]
D[16]
A[15]
D[15]
A[14]
D[14]
A[13]
D[13]
A[12]
D[12]
A[11]
D[11]
A[10]
D[10]
A[9]
I/O
O
179
182
184
187
189
191
194
196
199
201
204
206
209
211
214
216
219
221
224
226
229
231
234
236
239
241
244
246
249
251
254
256
259
261
264
266
269
271
I/O
O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
J16
I/O
O
J11
J15
I/O
O
J12
H16
J13
I/O
O
H15
H13
G16
H12
G15
H11
F15
H10
E16
G13
E15
G12
D16
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
D[9]
I/O
O
Y3
A[8]
G20
D[8]
I/O
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
39
EP7309
High-Performance, Low-Power System on Chip
Table V. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
148
150
151
152
153
154
155
156
161
162
163
164
165
166
169
170
171
172
173
175
176
177
178
179
184
185
186
187
188
189
191
192
193
194
195
196
199
200
H18
F20
G19
E20
F19
G18
D20
F18
D19
E19
C19
C20
E18
B20
B16
A16
C15
B15
A15
C14
B14
A14
C13
B13
A13
C12
B12
A12
C11
B11
B10
A10
A9
G11
D15
F13
C16
F12
C15
E13
B16
B14
D11
A13
F10
B13
E10
B12
D10
A11
G9
A[7]
D[7]
O
I/O
I
274
276
279
280
281
282
283
284
285
286
287
289
292
294
297
299
302
304
307
309
312
314
317
319
322
324
326
328
330
333
336
339
342
344
346
349
352
355
nBATCHG
nEXTPWR
BATOK
nPOR
nMEDCHG/nBROM
nURESET
WAKEUP
nPWRFL
A[6]
I
I
I
I
I
I
I
O
D[6]
I/O
O
A[5]
D[5]
I/O
O
A[4]
D[4]
I/O
O
A[3]
D[3]
I/O
O
B11
A10
F9
A[2]
D[2]
I/O
O
A[1]
B10
E9
D[1]
I/O
O
A[0]
A9
D[0]
I/O
O
D8
CL2
B8
CL1
O
E8
FRM
O
A7
M
O
F8
DD[3]
DD[2]
DD[1]
DD[0]
N/C
I/O
I/O
I/O
I/O
O
B7
A6
G8
B6
B9
D7
N/C
O
C9
A5
N/C
I/O
I/O
I/O
I/O
A8
E7
N/C
B8
F7
N/C
C8
A4
N/C
40
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Table V. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
201
202
204
205
206
207
208
A7
B7
C7
A6
B6
C6
A5
D6
B4
E6
A3
D5
B3
A2
nMWE
nMOE
nCS[0]
nCS[1]
nCS[2]
nCS[3]
nCS[4]
O
O
O
O
O
O
O
358
360
362
364
366
368
370
1) See EP7309 Users’ Manual for pin naming / functionality.
2) For each pad, the JTAG connection ordering is input,
output, then enable as applicable.
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
41
EP7309
High-Performance, Low-Power System on Chip
Table W. Acronyms and Abbreviations (Continued)
CONVENTIONS
This section presents acronyms, abbreviations, units of
measurement, and conventions used in this data sheet.
Acronym/
Definition
Abbreviation
TAP
TLB
test access port
Acronyms and Abbreviations
translation lookaside buffer
Table W lists abbreviations and acronyms used in this
data sheet.
UART
universal asynchronous receiver
Table W. Acronyms and Abbreviations
Units of Measurement
Acronym/
Definition
Table X. Unit of Measurement
Abbreviation
Symbol
Unit of Measure
A/D
analog-to-digital
degree Celsius
°C
fs
ADC
CODEC
D/A
analog-to-digital converter
coder / decoder
sample frequency
hertz (cycle per second)
kilobits per second
kilobyte (1,024 bytes)
kilohertz
Hz
digital-to-analog
kbps
KB
DMA
EPB
FCS
FIFO
FIQ
direct-memory access
embedded peripheral bus
frame check sequence
first in / first out
kHz
kΩ
kilohm
Mbps
MB
MBps
MHz
µA
megabits (1,048,576 bits) per second
megabyte (1,048,576 bytes)
megabytes per second
megahertz (1,000 kilohertz)
microampere
fast interrupt request
general purpose I/O
in circuit test
GPIO
ICT
IR
infrared
IRQ
standard interrupt request
Infrared Data Association
Joint Test Action Group
liquid crystal display
light-emitting diode
µF
microfarad
IrDA
JTAG
LCD
LED
LQFP
LSB
MIPS
MMU
MSB
PBGA
PCB
PDA
PLL
µW
µs
microwatt
microsecond (1,000 nanoseconds)
milliampere
mA
mW
ms
milliwatt
low profile quad flat pack
least significant bit
millisecond (1,000 microseconds)
nanosecond
ns
millions of instructions per second
memory management unit
most significant bit
V
volt
W
watt
plastic ball grid array
printed circuit board
personal digital assistant
phase locked loop
p/u
pull-up resistor
RISC
RTC
SIR
reduced instruction set computer
Real-Time Clock
slow (9600–115.2 kbps) infrared
static random access memory
synchronous serial interface
SRAM
SSI
42
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
General Conventions
Pin Description Conventions
Hexadecimal numbers are presented with all letters in
uppercase and a lowercase “h” appended or with a 0x at
the beginning. For example, 0x14 and 03CAh are
hexadecimal numbers. Binary numbers are enclosed in
single quotation marks when in text (for example, ‘11’
designates a binary number). Numbers not indicated by
an “h”, 0x or quotation marks are decimal.
Abbreviations used for signal directions are listed in
Table Y.
Table Y. Pin Description Conventions
Abbreviation
Direction
I
Input
O
I/O
Output
Registers are referred to by acronym, with bits listed in
Input or Output
brackets separated by
a colon (:) (for example,
CODR[7:0]), and are described in the EP7309 User’s
Manual. The use of “TBD” indicates values that are “to
be determined,” “n/a” designates “not available,” and
“n/c” indicates a pin that is a “no connect.”
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
43
EP7309
High-Performance, Low-Power System on Chip
ORDERING INFORMATION
The order number for the device is:
EP7309 — CV — C
Revision †
Package Type:
V = Low Profile Quad Flat Pack
B = Plastic Ball Grid Array (17 mm x 17 mm)
R = Reduced Ball Grid Array (13 mm x 13 mm)
Temperature Range:
Part Number C = Commercial
E = Extended Operating Version
I = Industrial Operating Version
Product Line:
Embedded Processor
Note: Contact Cirrus Logic for up-to-date information on revisions. Go to the Cirrus Logic Internet site at
http://cirrus.com/corporate/contacts to find contact information for your local sales representative.
44
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
• Notes •
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