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CS8411 [CIRRUS]

DIGITAL AUDIO INTER FACE RECEIVER; DIGITAL AUDIO INTER FACE接收器
CS8411
型号： CS8411
厂家： CIRRUS LOGIC    CIRRUS LOGIC
描述：

DIGITAL AUDIO INTER FACE RECEIVER
DIGITAL AUDIO INTER FACE接收器
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中文：  中文翻译
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CS8411  
CS8412  
Digital Audio Interface Receiver  
Features  
Description  
The CS8411/12 are monolithic CMOS devices which re-  
ceive and decode audio data according to the AES/EBU,  
IEC958, S/PDIF, & EIAJ CP-340 interface standards.  
The CS8411/12 receive data from a transmission line,  
recover the clock and synchronization signals, and de-  
multiplex the audio and digital data. Differential or single  
ended inputs can be decoded.  
l Monolithic CMOS Receiver  
l Low-Jitter, On-Chip Clock Recovery  
256x Fs Output Clock Provided  
l Supports: AES/EBU, IEC958, S/PDIF, &  
EIAJ CP-340 Professional and Consumer  
Formats  
l Extensive Error Reporting  
The CS8411 has a configurable internal buffer memory,  
read via a parallel port, which may be used to buffer  
channel status, auxiliary data, and/or user data.  
- Repeat Last Sample on Error Option  
l On-Chip RS422 Line Receiver  
l Configurable Buffer Memory (CS8411)  
The CS8412 de-multiplexes the channel, user, and va-  
lidity data directly to serial output pins with dedicated  
output pins for the most important channel status bits.  
ORDERING INFORMATION  
See page 32.  
I
VD+  
7
DGND  
8
VA+  
22  
FILT  
20  
AGND  
21  
MCK  
CS8411  
19  
26  
12  
11  
SDATA  
SCK  
Audio  
Serial Port  
9
FSYNC  
RXP  
RXN  
13  
RS422  
Receiver  
De-MUX  
A4/FCK  
A3-A0  
Clock and Data Recovery  
10  
4
8
Configurable  
Buffer  
Memory  
D7-D0  
IEnable and Status  
25 14  
ERF INT  
24  
23  
CS  
RD/WR  
VD+  
DGND  
VA+  
22  
FILT  
20  
AGND  
21  
MCK  
19  
M3 M2  
17 18  
M1 M0  
24 23  
CS8412  
7
8
26  
12  
11  
SDATA  
SCK  
Audio  
9
Serial Port  
Registers  
RXP  
RXN  
FSYNC  
RS422  
Receiver  
De-MUX  
Clock and Data Recovery  
MUX  
10  
1
14  
C
U
28  
MUX  
13  
VERF  
16  
6
5
4
3
2
27  
C0/ Ca/ Cb/ Cc/ Cd/ Ce/  
E0 E1 E2 F0 F1 F2  
25  
15  
CS12/  
FCK  
SEL  
ERF CBL  
Cirrus Logic, Inc.  
Copyright Cirrus Logic, Inc. 1998  
(All Rights Reserved)  
Crystal Semiconductor Products Division  
P.O. Box 17847, Austin, Texas 78760  
(512) 445 7222 FAX: (512) 445 7581  
http://www.crystal.com  
OCT ‘98  
DS61F1  
1
CS8411 CS8412  
TABLE OF CONTENTS  
CHARACTERISTICS/SPECIFICATIONS ............................................................ 3  
ABSOLUTE MAXIMUM RATINGS .............................................................. 3  
RECOMMENDED OPERATING CONDITIONS.......................................... 3  
DIGITAL CHARACTERISTICS.................................................................... 3  
DIGITAL CHARACTERISTICS - RS422 RECEIVERS................................ 4  
SWITCHING CHARACTERISTICS - CS8411 PARALLEL PORT............... 4  
SWITCHING CHARACTERISTICS - SERIAL PORTS................................ 5  
GENERAL DESCRIPTION .................................................................................. 7  
Line Receiver .............................................................................................. 7  
Clocks and Jitter Attenuation ...................................................................... 7  
CS8411 DESCRIPTION ....................................................................................... 8  
Parallel Port ................................................................................................ 8  
Status and IEnable Registers ..................................................................... 8  
Control Registers ...................................................................................... 11  
Audio Serial Port ....................................................................................... 13  
Normal Modes .................................................................................... 14  
Special Modes .................................................................................... 14  
Buffer Memory .......................................................................................... 15  
Buffer Mode 0 ..................................................................................... 15  
Buffer Mode 1 ..................................................................................... 16  
Buffer Mode 2 ..................................................................................... 18  
Buffer Updates and Interrupt Timing ......................................................... 19  
ERF Pin Timing ......................................................................................... 19  
PIN DESCRIPTIONS: CS8411 .......................................................................... 20  
CS8412 DESCRIPTION ..................................................................................... 23  
Audio Serial Port ....................................................................................... 23  
Normal Modes (M3 = 0) ..................................................................... 23  
Special Modes (M3 = 1) ..................................................................... 24  
C, U, VERF, ERF, and CBL Serial Outputs .............................................. 26  
Multifunction Pins ...................................................................................... 26  
Channel Status Reporting .................................................................. 27  
Professional Channel Status (C0 = 0) ................................................ 28  
Consumer Channel Status (C0 = 1) ................................................... 28  
SCMS ................................................................................................. 28  
PIN DESCRIPTIONS: CS8412 .......................................................................... 29  
ORDERING GUIDE ............................................................................................ 32  
PACKAGE DIMENSIONS .................................................................................. 33  
APPE2NDIX A: RS422 RECEIVER INFORMATION ........................................ 35  
Professional Interface ............................................................................... 35  
Consumer Interface .................................................................................. 36  
TTL/CMOS Levels .................................................................................... 36  
Transformers ............................................................................................ 36  
APPENDIX B ..................................................................................................... 37  
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance  
product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts  
to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice  
and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this  
information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no  
license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval sys-  
tem, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publication  
may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of  
Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners  
which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.  
2
DS61F1  
CS8411 CS8412  
CHARACTERISTICS/SPECIFICATIONS  
ABSOLUTE MAXIMUM RATINGS (GND = 0V, all voltages with respect to ground)  
Parameter  
Symbol  
VD+, VA+  
Iin  
Min  
Max  
6.0  
Units  
V
Power Supply Voltage  
Input Current, Any Pin Except Supply  
Input Voltage, Any Pin except RXP, RXN  
Input Voltage, RXP and RXN  
Note 1  
± 10  
mA  
V
VIN  
-0.3  
-12  
-55  
-65  
VD+ + 0.3  
12  
VIN  
V
Ambient Operating Temperature (power applied)  
Storage Temperature  
TA  
125  
°C  
°C  
Tstg  
150  
Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up.  
WARNING: Operation beyond these limits may result in permanent damage to the device.  
Normal operation is not guaranteed at these extremes.  
RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground)  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Power Supply Voltage  
Supply Current  
VD+, VA+  
4.5  
5.0  
5.5  
V
VA+  
VD+  
IA  
ID  
20  
20  
30  
30  
mA  
mA  
Ambient Operating Temperature:  
Power Consumption  
CS8411/12-CP or -CS  
CS8411/12-IP or -IS  
Note 2  
TA  
0
-40  
25  
70  
85  
°C  
°C  
PD  
135  
248  
mW  
Notes: 2. The '-CP' and '-CS' parts are specified to operate over 0 to 70 °C but are tested at 25 °C only.  
The '-IP' and '-IS' parts are tested over the full -40 to 85 °C temperature range.  
DIGITAL CHARACTERISTICS (TA = 25 °C for suffixes '-CP' & '-CS', TA = -40 to 85 °C for '-IP' & '-IS';  
VD+, VA+ = 5V ± 10%)  
Parameter  
Symbol  
VIH  
Min  
Typ  
Max  
Unit  
V
High-Level Input Voltage  
Low-Level Input Voltage  
except RXP, RXN  
except RXP, RXN  
(IO = 200 µA)  
2.4  
VIL  
0.4  
V
High-Level Output Voltage  
Low-Level Output Voltage  
Input Leakage Current  
VOH  
VOL  
Iin  
VD+ - 1.0  
V
(IO = -3.2 mA)  
0.5  
10  
V
1.0  
µA  
Input Sample Frequency  
CS8411/12-CP or -CS  
CS8411/12-IP or -IS  
FS  
FS  
25  
30  
55  
50  
kHz  
kHz  
Note 3  
Master Clock Frequency  
MCK Clock Jitter  
Note 3 MCK  
tj  
6.4  
256 X FS 14.08  
MHz  
ps RMS  
%
200  
50  
MCK Duty Cycle (high time/cycle time)  
3. FS is defined as the incoming audio sample frequency per channel.  
DS61F1  
3
 
 
 
CS8411 CS8412  
DIGITAL CHARACTERISTICS - RS422 RECEIVERS (RXP, RXN pins only; VD+ = 5V ±  
10%)  
Parameter  
(-7V < VCM < 7V)  
Differential Input Voltage, RXP to RXN (-7V < VCM < 7V)  
Note 4,5  
Symbol  
ZIN  
Min  
Typ  
Max  
Unit  
kΩ  
Input Resistance  
Note 4  
10  
VTH  
200  
mV  
Input Hysteresis  
VHYST  
50  
mV  
Notes: 4. VCM - Input Common Mode Range  
5. When the receiver inputs are configured for singe ended operation (e.g. consumer configuration) the  
signal amplitude must exceed 400m Vp-p for the differential voltage on RXP to RXN to exceed 200mV.  
This represents twice the minimum signal level of 200 mVp-p specified in CP340/1201 and IEC-958  
(which are not RS-422 compliant).  
SWITCHING CHARACTERISTICS - CS8411 PARALLEL PORT (TA = 25 °C for suf-  
fixes '-CP' and '-CS'; TA = -40 to 85 °C for suffixes '-IP' and '-IS'; VD+, VA+ = 5V ± 10%; Inputs: Logic 0 = DGND,  
logic 1 = VD+; CL = 20 pF)  
Parameter  
ADDRESS valid to CS low  
Symbol  
tadcss  
tcsadh  
trwcss  
tcsrwi  
Min  
13.5  
0
Typ  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CS high to ADDRESS invalid  
RD/WR valid to CS low  
CS low to RD/WR invalid  
CS low  
10  
35  
35  
32  
0
tcsl  
DATA valid to CS rising  
CS high to DATA invalid  
CS falling to DATA valid  
CS rising to DATA Hi-Z  
RD/WR low (writing)  
RD/WR low (writing)  
RD/WR high (reading)  
RD/WR high (reading)  
tdcssw  
tcsdhw  
tcsddr  
tcsdhr  
35  
5
A4 - A0  
adcss  
t
t
csadh  
CS  
t
csl  
t
t
csrwi  
rwcss  
RD/WR  
Writing  
t
t
dcssw  
csdhw  
D7 - D0  
RD/WR  
Reading  
t
t
csddr  
csdhr  
D7 - D0  
CS8411 Parallel Port Timing  
4
DS61F1  
 
 
CS8411 CS8412  
SWITCHING CHARACTERISTICS - SERIAL PORTS  
(TA = 25 °C for suffixes '-CP' and '-CS'; TA = -40 to 85 °C for suffixes '-IP' and '-IS';  
VD+, VA+ = 5V ± 10%; Inputs: Logic 0 = DGND, logic 1 = VD+; CL = 20 pF)  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
SCK Frequency  
Master Mode Notes 6, 7  
Slave Mode Note 7  
Master Mode Notes 7, 8  
fsck  
OWRx32  
Hz  
Hz  
OWRx32  
-20  
128xFs  
20  
SCK falling to FSYNC delay  
SCK Pulse Width Low  
SCK Pulse Width High  
tsfdm  
tsckl  
tsckh  
tsfds  
tfss  
ns  
ns  
ns  
ns  
ns  
ns  
s
Slave Mode  
Slave Mode  
Note 7  
Note 7  
40  
40  
SCK rising to FSYNC edge delay Slave Mode Notes 7,8  
FSYNC edge to SCK rising setup Slave Mode Notes 7,8  
20  
20  
SCK falling (rising) to SDATA valid  
C, U, CBL valid to FSYNC edge  
MCK to FSYNC edge delay  
Note 8  
Note 8  
tssv  
20  
CS8412  
tcuvf  
tmfd  
1/fsck  
15  
FSYNC from RXN/RXP  
ns  
6. The output word rate, OWR, refers to the frequency at which an audio sample is output from the part.  
(A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK periods in  
one audio sample. In Slave mode, exactly 32 SCK periods per audio sample must be provided in most  
serial port formats. Therefor, if SCK is 128 x Fs, then SCK must be gated to provide exactly 32 periods  
per audio sample.  
7. In master mode SCK and FSYNC are outputs. In Slave mode they are inputs. In the CS8411, control  
reg. 2 bit 1, MSTR, selects master. In the CS8412, formats 1, 3 and 9 are slaves.  
8. The table above assumes data is output on the falling edge and latched on the rising edge. With the  
CS8411 the edge is selectable. The table is defined for the CS8411 with control reg. 2 bit 0, SCED, set  
to one, and for the CS8412 in formats 2, 3, 5, 6 and 7. For the other formats, the table and figure edges  
must be reversed (i.e.. "rising" to "falling" and vice versa).  
FSYNC  
MCK  
FSYNC  
t
t
t
fss  
mfd  
sfds  
t
t
sckl sckh  
SCK  
FSYNC Generated From  
Received Data  
t
ssv  
MSB  
SDATA  
(Mode 1)  
C, U  
t
cuvf  
FSYNC  
FSYNC  
t
t
t
t
fss  
t
sfdm  
sfds  
sckl sckh  
SCK  
(Modes 2,3,5,6,  
7,10,12, and 13)  
SCK  
t
ssv  
t
ssv  
MSB  
SDATA  
SCK  
(Modes 0,1,4,  
8,9, and 11)  
(Mode 3)  
Serial Output Timing - Slave Mode  
SDATA  
Serial Output Timing -  
Master Mode & C, U Port  
DS61F1  
5
 
 
 
CS8411 CS8412  
+5V digital  
+5V analog  
22  
VA+  
0.1  
F
µ
5 k  
Ω
7
µ
0.1 F  
19  
VD+  
MCK  
21  
AGND  
11  
12  
26  
FSYNC  
SCK  
Audio  
Data  
SDATA  
Processor  
9
RXP  
RXN  
FILT  
Receiver  
Circuit  
(See Appendix A)  
25  
14  
24  
23  
ERF  
INT  
CS8411  
10  
Audio  
Data  
CS  
Processor  
20  
RD/WR  
A0 - A4  
or  
Micro-  
1 k  
Ω
controller  
DGND  
D0 - D7  
0.047  
F
µ
8
Figure 1. CS8411 Typical Connection Diagram  
+5V digital  
+5V analog  
0.1  
F
µ
22  
VA+  
7
19  
28  
0.1  
µ
F
VD+  
MCK  
21  
9
AGND  
VERF  
SCK  
Audio  
12  
Data  
RXP  
26  
11  
Receiver  
Circuit  
SDATA  
Processor  
(See Appendix A)  
10  
FSYNC  
RXN  
CS8412  
13  
16  
25  
CS12/FCK  
SEL  
Micro-  
controller  
1
C
Channel Status  
and/or  
or  
14  
15  
U
Logic  
Error/Frequency  
Reporting  
ERF  
CBL  
6 C / E-F bits  
FILT  
20  
DGND  
8
1 k  
Ω
µ
0.047 F  
Figure 2. CS8412 Typical Connection Diagram  
6
DS61F1  
CS8411 CS8412  
GENERAL DESCRIPTION  
Clocks and Jitter Attenuation  
The CS8411/12 are monolithic CMOS circuits that  
receive and decode audio and digital data accord-  
The primary function of these chips is to recover  
audio data and low jitter clocks from a digital audio  
ing to the AES/EBU, IEC958, S/PDIF, and EIAJ transmission line. The clocks that can be generated  
CP-340 interface standards. Both chips contain  
RS422 line receivers and Phase-Locked Loops  
(PLL) that recover the clock and synchronization  
are MCK (256 × FS), SCK (64 × FS), and FSYNC  
(FS or 2 × FS). MCK is the output of the voltage  
controlled oscillator which is a component of the  
signals, and de-multiplex the audio and digital data. PLL. The PLL consists of phase and frequency de-  
The CS8411 contains a configurable internal buffer  
memory, read via a parallel port, which can buffer  
tectors, a second-order loop filter, and a voltage  
controlled oscillator. All components of the PLL  
channel status, user, and optionally auxiliary data. are on chip with the exception of a resistor and ca-  
The CS8412 de-multiplexes the channel status, us- pacitor used in the loop filter. This filter is connect-  
er, and validity information directly to serial output  
pins with dedicated pins for the most important  
ed between the FILT pin and AGND. The closed-  
loop transfer function, which specifies the PLL's  
channel status bits. Both chips also contain exten- jitter attenuation characteristics, is shown in Figure  
sive error reporting as well as incoming sample fre-  
quency indication for auto-set applications.  
3. Since most data jitter introduced by the transmis-  
sion line is high in frequency, it will be strongly at-  
tenuated.  
Familiarity with the AES/EBU and IEC958 speci-  
fications are assumed throughout this document.  
Multiple frequency detectors are used to minimize  
The App Note, Overview of Digital Audio Inter- the time it takes the PLL to lock to the incoming  
face Data Structures, contains information on digi- data stream and to prevent false lock conditions.  
tal audio specifications; however, it is not meant to When the PLL is not locked to the incoming data  
be a complete reference. To guarantee compliance,  
the proper standards documents should be ob-  
tained. The AES/EBU standard, AES3-1985,  
should be obtained from the Audio Engineering  
Society or ANSI (ANSI document # ANSI S4.40-  
1985); the IEC958 standard from the International  
Electrotechnical Commission; and the EIAJ CP-  
340 standard from the Japanese Electronics Bu-  
reau.  
stream, the frequency detectors pull the VCO fre-  
quency within the lock range of the PLL. When no  
digital audio data is present, the VCO frequency is  
pulled to its minimum value.  
As a master, SCK is always MCK divided by four,  
producing a frequency of 64 × FS. In the CS8411,  
FSYNC can be programmed to be a divided version  
of MCK or it can be generated directly from the in-  
coming data stream. In the CS8412, FSYNC is al-  
ways generated from the incoming data stream.  
When FSYNC is generated from the data, its edges  
are extracted at times when intersymbol interfer-  
ence is at a minimum. This provides a sample fre-  
quency clock that is as spectrally pure as the digital  
audio source clock for moderate length transmis-  
sion lines. For long transmission lines, the CS8411  
can be programmed to generate FSYNC from  
MCK instead of from the incoming data.  
Line Receiver  
The RS422 line receiver can decode differential as  
well as single ended inputs. The receiver consists  
of a differential input Schmitt trigger with 50 mV  
of hysteresis. The hysteresis prevents noisy signals  
from corrupting the phase detector. Appendix A  
contains more information on how to configure the  
line receivers for differential and single ended sig-  
nals.  
DS61F1  
7
CS8411 CS8412  
5
0
- 5  
- 10  
- 15  
- 20  
- 25  
- 30  
102  
103  
104  
105  
106  
Jitter Frequency (Hz)  
Figure 3. Jitter Attenuator Characteristics  
lects the two registers, either status or interrupt en-  
able, that occupy addresses 0 and 1 in the memory  
map. The address bus and the RD/WR line should  
be valid when CS goes low. If RD/WR is low, the  
value on the data bus will be written into the buffer  
memory at the specified address. If RD/WR is high,  
the value in the buffer memory, at the specified ad-  
dress, is placed on the data bus. Detailed timing for  
the parallel port can be found in the Switching  
Characteristics - Parallel Port table.  
CS8411 DESCRIPTION  
The CS8411 is more flexible than the CS8412 but  
requires a microcontroller or DSP to load internal  
registers. The CS8412 does not have internal regis-  
ters so it may be used in a stand-alone mode where  
no microprocessor or DSP is available.  
The CS8411 accepts data from a transmission line  
coded according to the digital audio interface stan-  
dards. The I.C. recovers clock and data, and sepa-  
rates the audio data from control information. The  
audio data is output through a configurable serial  
port and the control information is stored in internal  
dual-port RAM. Extensive error reporting is avail-  
able via internal registers with the option of repeat-  
ing the last sample when an error occurs. A block  
diagram of the CS8411 is shown in Figure 4.  
The memory space on the CS8411 is allocated as  
shown in Figure 5. There are three defined buffer  
modes selectable by two bits in control register 1.  
Further information on the buffer modes can be  
found in the Control Registers section.  
Status and IEnable Registers  
The status and interrupt enable registers occupy the  
same address space. The IER/SR bit in control reg-  
ister 1 selects whether the status registers (IER/SR  
= 0) or the IEnable registers (IER/SR = 1) occupy  
addresses 0 and 1. Upon power-up, the control and  
IEnable registers contain all zeros; therefore, the  
Parallel Port  
The parallel port accesses two status registers, two  
interrupt enable registers, two control registers, and  
28 bytes of dual-port buffer memory. The status  
registers and interrupt enable registers occupy the  
same address space. A bit in control register 1 se-  
8
DS61F1  
CS8411 CS8412  
VA+  
22  
FILT AGND MCK  
20 21 19  
11  
Bi-phase  
Decoder  
FSYNC  
Audio  
12  
Serial  
Port  
SCK  
9
RXP  
RXN  
26  
Clock & Data  
Recovery  
De-Multiplexor  
SDATA  
10  
Control  
Registers  
2 X 8  
crc  
aux  
check  
Buffer  
Memory  
7
8
user  
C.S.  
VD+  
28 X 8  
DGND  
slipped  
parity  
validity  
crc  
14  
25  
INT  
IEnable  
&
ERF  
Status  
Bi-phase  
no lock  
24  
23  
4 X 8  
CS  
RD/WR  
Frequency  
Comparator  
4
8
13  
A4/ A0- D0-  
FCK A3 D7  
Figure 4. CS8411 Block Diagram  
status registers are visible and all interrupts are dis- FLAG2 causes an interrupt on the rising edge only.  
abled. The IER/SR bit must be set to make the IEn- Further information, including timing, on the flags  
able registers visible.  
can be found in the Buffer Memory section.  
Status register 1 (SR1), shown in Figure 6, reports  
The next five bits; ERF, SLIP, CCHG,  
all the conditions that can generate a low pulse, CRCE/CRC1, and CSDIF/CRC2, are latches  
four SCLK cycles wide, on the interrupt pin (INT).  
The three least significant bits, FLAG2-FLAG0,  
which are set when their corresponding conditions  
occur, and are reset when SR1 is read. Interrupt  
are used to monitor the ram buffer. These bits con- pulses are generated the first time that condition oc-  
tinually change and indicate the position of the curs. If the status register is not read, further in-  
buffer pointer which points to the buffer memory stances of that same condition will not generate  
location currently being written. Each flag has a another interrupt. ERF is the error flag bit and is set  
corresponding interrupt enable bit in IEnable regis- when the ERF pin goes high. It is an OR’ing of the  
ter 1 which, when set, allows a transition on the flag errors listed in status register 2, bits 0 through 4,  
to generate a pulse on the interrupt pin. FLAG0 and  
FLAG1 cause interrupts on both edges whereas  
AND’ed with their associated interrupt enable bits  
in IEnable register 2.  
DS61F1  
9
CS8411 CS8412  
SLIP is only valid when the audio port is in slave  
mode (FSYNC and SCK are inputs to the CS8411).  
This flag is set when an audio sample is dropped or  
reread because the audio data output from the part  
is at a different frequency than the data received  
from the transmission line. CCHG is set when any  
bit in channel status bytes 0 through 3, stored in the  
buffer, changes from one block to the next. In buff-  
er modes 0 and 1, only one channel of channel sta-  
tus data is buffered, so CCHG is only affected by  
that channel. (CS2/CS1 in CR1 selects which chan-  
nel is buffered.) In buffer mode 2 both channels are  
buffered, so both channels affect CCHG. This bit is  
updated after each byte (0 to 3) is written to the  
buffer. The two most significant bits in SR1,  
CRCE/CRC1 and CSDIF/CRC2, are dual function  
flags. In buffer modes 0 and 1, they are CRCE and  
CSDIF, and in buffer mode 2, they are CRC1 and  
CRC2. In buffer modes 0 and 1, the channel select-  
ed by the CS2/CS1 bit is stored in RAM and CRCE  
indicates that a CRC error occurred in that channel.  
CSDIF is set if there is any difference between the  
channel status bits of each channel. In buffer mode  
2 channel status from both channels is buffered,  
with CRC1 indicating a CRC error in channel 1 and  
CRC2 indicating a CRC error in channel 2. CRCE,  
CRC1, and CRC2 are updated at the block bound-  
ary. Block boundary violations also cause CRC1,2  
or CRCE to be set.  
Status 1 / IEnable 1  
Status 2 / IEnable 2  
Control Register 1  
Control Register 2  
0
1
2
3
4
5
User Data  
6
7
U
N
D
E
F
I
N
E
D
8
1st Four  
1st Four  
Bytes of  
C. S. Data C. S. Data  
1st Four  
Bytes of  
9
Bytes of  
Left C. S.  
Data  
A
B
C
Left  
C. S.  
Data  
A
D
D
R
E
S
S
D
C. S.  
Data  
Last  
E
F
20 Bytes  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
1st Four  
Bytes of  
Right  
Channel  
Status  
Data  
C. S. Data  
Right  
C. S.  
Data  
Auxiliary  
Data  
0
1
2
3
Memory Mode  
Figure 5. CS8411 Buffer Memory Map  
IEnable register 1, which occupies the same ad-  
dress space as status register 1, contains interrupt  
enable bits for all conditions in status register 1. A  
"1" in a bit location enables the same bit location in  
status register 1 to generate an interrupt pulse. A  
"0" masks that particular status bit from causing an  
interrupt.  
X:00  
7
6
5
4
3
2
1
0
SR1.  
CSDIF/ CRCE/ CCHG SLIP ERF FLAG2 FLAG1 FLAG0  
CRC2 CRC1  
IER1.  
INTERRUPT ENABLE BITS FOR ABOVE  
SR1: CSDIF:  
CRC2:  
CS different between sub-frames. Buffer modes 0 & 1  
CRC Error - sub-frame 2. Buffer mode 2 only.  
CRC Error - selected sub-frame. Buffer modes 0 & 1  
CRC Error - sub-frame 1. Buffer mode 2 only.  
Channel Status changed  
CRCE:  
CRC1:  
CCHG:  
SLIP:  
Slipped an audio sample  
ERF:  
Error Flag. ORing of all errors in SR2.  
High for first four bytes of channel status  
Memory mode dependent - See Figure 1. 1  
High for last two bytes of user data.  
Status register 2 (SR2) reports all the conditions  
that can affect the error flag bit in SR1 and the error  
pin (ERF), and can specify the received clock fre-  
quency. As previously mentioned, the first five bits  
of SR2 are AND’ed with their interrupt enable bits  
(in IER2) and then OR’ed to create ERF. The V,  
FLAG2:  
FLAG1:  
FLAG0:  
IER1: Enables the corresponding bit in SR1.  
A “1” enables the interrupt. A “0” masks the interrupt.  
Figure 6. Status/IEnable Register 1  
10  
DS61F1  
 
CS8411 CS8412  
PARITY, CODE and LOCK bits are latches which can be accessed. Table 1 lists the frequency ranges  
are set when their corresponding conditions occur, reported. The FREQ bits are updated three times  
and are reset when SR2 is read. The ERF pin is as- per block and the clock on the FCK pin must be val-  
serted each time the error occurs assuming the in- id for two thirds of a block for the FREQ bits to be  
terrupt enable bit in IER2 is set for that particular accurate. The vast majority of audio systems must  
error. When the ERF pin is asserted, the ERF bit in meet the 400 ppm tolerance listed in the table. The  
SR1 is set. If the ERF bit was not set prior to the 4% tolerance is provided for unique situations  
ERF pin assertion, an interrupt will be generated where the approximate frequency needs to be  
(assuming bit 3 in IER1 is set). Although the ERF  
pin is asserted for each occurrence of an enabled er-  
ror condition, the ERF bit will only cause an inter-  
rupt once if SR1 is not read.  
known, even though that frequency is outside the  
normal audio specifications.  
FREQ2 FREQ1 FREQ0  
Sample Frequency  
Out of Range  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V is the validity status bit which is set any time the  
received validity bit is high. PARITY is set when a  
parity error is detected. CODE is set when a bi-  
phase coding error is detected. LOCK is asserted  
when the receiver PLL is not locked and occurs  
when there is no input on RXP/RXN, or if the re-  
ceived frequency is out of the receiver lock range  
(25 kHz to 55 kHz). Lock is achieved after receiv-  
ing three frame preambles followed by one block  
preamble, and is lost after four consecutive frame  
preambles are not received.  
48 kHz ± 4%  
44.1 kHz ± 4%  
32 kHz ± 4%  
48 kHz ± 400 ppm  
44.1 kHz ± 400 ppm  
44.056 kHz ± 400 ppm  
32 kHz ± 400 ppm  
Table 1. Incoming Sample Frequency Bits  
IEnable register 2 has corresponding interrupt en-  
able bits for the first five bits in SR2. A "1" enables  
the condition in SR2 to cause ERF to go high, while  
a "0" masks that condition. Bit 5 is unused and bits6  
and 7, the two most significant bits, are factory test  
bits and must be set to zero when writing to this  
register. The CS8411 sets these bits to zero on pow-  
er-up.  
X:01  
7
6
5
4
3
2
1
0
SR2. FREQ2 FREQ1 FREQ0 Reserved LOCK CODE PARITY  
V
IER2. TEST1 TEST0  
INT. ENABLE BITS  
FOR ABOVE  
SR2: FREQ2:  
FREQ1:  
The 3 FREQ bits indicate incoming sample frequency.  
(must have 6.144 MHz clock on FCK pin and FCEN  
must be “1”)  
FREQ0:  
LOCK:  
Out-of-Lock error  
CODE:  
PARITY: Parity error  
Coding violation  
Control Registers  
V:  
Validity bit high  
The CS8411 contains two control registers. Control  
register1 (CR1), at address 2, selects system level  
features, while control register 2 (CR2), at address  
3, configures the audio serial port.  
IER2: TEST1,0: (0 on power-up) Must stay at “0”.  
INT. ENABLES: Enables the corresponding bit in SR2.  
A “1” enables the interrupt. A “0” masks the interrupt.  
Figure 7. Status/IEnable Register 2  
In control register 1, when RST is low, all outputs  
are reset except MCK (FSYNC and SCLK are high  
impedance). After the user sets RST high, the  
CS8411 comes fully out of reset when the block  
boundary is found. It is recommended to reset the  
CS8411 after power-up and any time the user per-  
forms a system-wide reset. The serial port, in mas-  
ter mode, will begin to operate as soon as RST goes  
The upper three bits in SR2, FREQ2-FREQ0, can  
report the receiver frequency when the receiver is  
locked. These bits are only valid when FCEN in  
control register 1 is set, and a 6.144 MHz clock is  
applied to the FCK pin. When FCEN is set, the  
A4/FCK pin is used as FCK and A4 is internally set  
to zero; therefore, only the lower half of the buffer  
DS61F1  
11  
CS8411 CS8412  
B1  
0
B0  
0
Mode Buffer Memory Contents  
0
1
2
3
Channel Status  
Auxiliary Data  
X:02  
7
6
5
4
3
2
1
0
CR1. FPLL FCEN  
0
1
IER/SR CS2/CS1  
B1  
B0  
RST  
1
0
Independent Channel Status  
Reserved  
CR1: FPLL:  
FCEN:  
0 - FSYNC from RXP/RXN, 1 - FSYNC from PLL  
enables freq. comparator (FCK must be 6.144 MHz).  
[X:00,01] 0 - status, 1 - interrupt enable registers.  
1
1
IER/SR:  
CS2/CS1: ch. status to buffer; 0 - sub-frame 1, 1 - sub-frame 2.  
Table 2. Buffer Memory Modes  
B1:  
with B0, selects the buffer memory mode.  
B0:  
with B1, selects the buffer memory mode.  
RST:  
Resets internal counters. Set to “1” for normal operation.  
can be configured as inputs or outputs. FSYNC and  
SDATA can have a variety of relationships to each  
other, and the polarity of SCK can be controlled.  
The large variety of audio data formats provides an  
easy interface to most DSPs and other audio pro-  
cessors. SDATA is normally just audio data, but  
special modes are provided that output received bi-  
phase data, or received NRZ data with zeros substi-  
tuted for preamble. Another special mode allows an  
asynchronous SCK input to read audio data from  
the serial port without slipping samples. In this  
mode FSYNC and SDATA are outputs synchro-  
nized to the SCK input. Since SCK is asynchronous  
to the received clock, the number of SCK cycles  
between FSYNC edges will vary.  
Figure 8. Control Register 1  
high. B0 and B1 select one of three buffer modes  
listed in Table 2 and illustrated in Figure 5. In all  
modes four bytes of user data are stored. In mode 0,  
one entire block of channel status is stored. In mode  
1 eight bytes of channel status and sixteen bytes of  
auxiliary data are stored. In mode 2, eight bytes of  
channel status from each sub-frame are stored. The  
buffer modes are discussed in more detail in the  
Buffer Memory section. The next bit, CS2/CS1, se-  
lects the particular sub-frame of channel status to  
buffer in modes 0 and 1, and has no effect in mode  
2. When CS2/CS1 is low, sub-frame 1 is buffered,  
and when CS2/CS1 is high, sub-frame 2 is buff-  
ered. IER/SR selects which set of registers, either  
IEnable or status, occupy addresses 0 and 1. When  
IER/SR is low, the status registers occupy the first  
two addresses, and when IER/SR is high, the IEn-  
able registers occupy those addresses. FCEN en-  
ables the internal frequency counter. A 6.144 MHz  
clock must be connected to the FCK pin as a refer-  
ence. The value of the FREQ bits in SR2 are not  
valid until two thirds of a block of data is received.  
Since FCK and A4, the most significant address bit,  
occupy the same pin, A4 is internally set to zero  
when FCEN is high. Since A4 is forced to zero, the  
upper half of the buffer is not accessible while us-  
ing the frequency compare feature. FPLL deter-  
mines how FSYNC is derived. When FPLL is low,  
FSYNC is derived from the incoming data, and  
when FPLL is high, it is derived from the internal  
phase-locked loop.  
X:03  
7
6
5
4
3
2
1
0
CR2. ROER SDF2 SDF1 SDF0 FSF1 FSF0 MSTR SCED  
CR2: ROER:  
SDF2:  
Repeat previous value on error (audio data)  
with SDF0 & SDF1, select serial data format.  
with SDF0 & SDF2, select serial data format.  
with SDF1 & SDF2, select serial data format.  
with FSF0, select FSYNC format.  
SDF1:  
SDF0:  
FSF1:  
FSF0:  
with FSF1, select FSYNC format.  
MSTR:  
SCED:  
When set, SCK and FSYNC are output  
When set, falling edge of SCK outputs data.  
When clear, rising edge of SCK outputs data.  
Figure 9. Control Register 2  
ROER, when set, causes the last audio sample to be  
reread if the error pin, ERF, is active. When out of  
lock, the CS8411 will output zeros if ROER is set  
and output random data if ROER is not set. The  
conditions that activate ERF are those reported in  
SR2 and enabled in IER2. Figure 10 illustrates the  
modes selectable by SDF2-SDF0 and FSF1-FSF0.  
MSTR, which in most applications will be set to  
one, determines whether FSYNC and SCK are out-  
puts (MSTR = 1) or inputs (MSTR = 0). When  
FSYNC and SCK are inputs (slave mode) the audio  
Control Register 2 configures the serial port which  
consists of three pins: SCK, SDATA, and FSYNC.  
SDATA is always an output, but SCK and FSYNC  
12  
DS61F1  
CS8411 CS8412  
data can be read twice or missed if the device con- SCK, SDATA, and FSYNC. SCK clocks the data  
trolling FSYNC and SCK is on a different time- out on the SDATA line. The edge that SCK uses to  
base than the CS8411. If the audio data is read output data is programmable from CR2. FSYNC  
twice or missed, the SLIP bit in SR1 is set. SCED delineates the audio samples and may indicate the  
selects the SCK edge to output data on. SCED high particular channel, left or right. Figure 10 illus-  
causes data to be output on the falling edge, and  
SCED low causes data to be output on the rising  
edge.  
trates the multitude of formats that SDATA and  
FSYNC can take.  
Normal Modes  
Audio Serial Port  
SCK and FSYNC can be inputs (MSTR = 0) or out-  
puts (MSTR = 1), and are usually programmed as  
outputs. As outputs, SCK contains 32 periods for  
The audio serial port outputs the audio data portion  
from the received data and consists of three pins:  
FSF MSTR  
32 Bits  
32 Bits  
10 (bit)  
00  
01  
10  
0
0
0
FSYNC Input  
FSYNC Input  
FSYNC Input  
11  
00  
01  
10  
0
1
1
1
1
FSYNC Input  
FSYNC Output  
FSYNC Output  
FSYNC Output  
FSYNC Output  
16 Clocks  
16 Clocks  
16 Clocks  
16 Clocks  
32 Clocks  
32 Clocks  
32 Clocks  
11  
32 Clocks  
Left Sample  
24 Bits, Incl. Aux  
Right Sample  
24 Bits, Incl. Aux  
SDF  
210 (bit)  
000  
Name  
MSB  
LSB  
LSB  
MSB  
MSB  
MSB First - 32  
24 Bits, Incl. Aux  
24 Bits, Incl. Aux  
001  
011  
101  
111  
MSB Last  
LSB  
MSB  
LSB  
LSB  
LSB  
MSB  
LSB  
LSB  
LSB  
LSB  
MSB  
LSB  
LSB  
LSB  
16 Bits  
MSB  
16 Bits  
MSB  
LSB Last - 16  
LSB Last - 18  
LSB Last - 20  
18 Bits  
18 Bits  
MSB  
MSB  
20 Bits  
20 Bits  
MSB  
MSB  
SPECIAL MODES:  
SDF  
210 MSTR Name  
24 Bits, Incl. Aux  
24 Bits, Incl. Aux  
MSB  
MSB  
MSB  
MSB  
MSB  
LSB  
LSB  
MSB  
MSB  
100  
0
Async SCK  
24 Bits, Incl. Aux  
16 Bits  
24 Bits, Incl. Aux  
16 Bits  
110  
0
MSB First - 24  
LSB  
LSB  
010  
0
MSB First - 16  
LSB MSB  
VUCP  
LSB MSB  
MSB  
VUCP  
32 Bits  
LSB  
32 Bits  
AUX LSB  
AUX  
MSB  
AUX  
010*  
100*  
1
1
NRZ Data  
Bi-Phase Mark Data  
Bi-Phase Mark Data  
Bi-Phase Data  
* Error flags are not accurate in these modes  
Figure 10. CS8411 Serial Port SDATA and FSYNC Timing  
DS61F1  
13  
 
CS8411 CS8412  
each sample and FSYNC has four formats. The  
first two output formats of FSYNC (shown in Fig-  
ure 10) delineate each word and the identification  
of the particular channel must be kept track of ex-  
ternally. This may be done using the rising edge of  
FLAG2 to indicate the next data word is left chan-  
nel data. The last two output formats of FSYNC  
also delineate each channel with the polarity of  
FSYNC indicating the particular channel. The last  
format has FSYNC change one SCK cycle before  
the frame containing the data and may be used to  
Special Modes  
Five special modes are included for unique applica-  
tions. In these modes, the master bit, MSTR, must  
be defined as shown in Figure 10. In the first mode,  
Asynchronous SCK, FSYNC (which is an output in  
this mode) is aligned to the incoming SCK. This  
mode is useful when the SCK is locked to an exter-  
nal event and cannot be derived from MCK. Since  
SCK is asynchronous, the number of SCK cycles  
per sample frame will vary. The data output will be  
MSB first, 24 bits, and aligned to the beginning of  
a sample frame. The second and third special  
modes are unique in that they contain 24 and 16  
SCK cycles respectively per sample frame, where-  
as all normal modes contain 32 SCK cycles. In  
these two modes, the data is MSB first and fills the  
entire frame. The fourth special mode outputs NRZ  
data including the V, U, C, and P bits and the pre-  
amble replaced with zeros. SCK is an output with  
32 SCK cycles per sample frame. The fifth mode  
outputs the biphase data recovered from the trans-  
mission line with 64 SCK cycles output per sample  
frame, with data changing on the rising edge.  
2
generate an I S compatible interface.  
When SCK is programmed as an input, 32 SCK cy-  
cles per sample must be provided. (There are two  
formats in the Special Modes section where SCK  
can have 16 or 24 clocks per sample.) The four  
modes where FSYNC is an input are similar to the  
FSYNC output modes. The first two require a tran-  
sition of FSYNC to start the sample frame, whereas  
the last two are identical to the corresponding  
FSYNC output modes. If the circuit generating  
SCK and FSYNC is not locked to the master clock  
of the CS8411, the serial port will eventually be re-  
read or a sample will be missed. When this occurs,  
the SLIP bit in SR1 will be set.  
Normally, data recovered by the CS8411 is delayed  
by two frames in propagating through the part, but  
in the fourth and fifth special modes, the data is de-  
layed only a few bit periods before being output.  
However, error codes, and the C, U and V bits fol-  
low their normal pathways with a two frame delay  
(so that the error code would be output with the of-  
fending data in the other modes). As a result, in  
special modes four and five, the error codes are  
nearly two frames behind the data output on SDA-  
TA.  
SDATA can take on five formats in the normal se-  
rial port modes. The first format (see Figure 10),  
MSB First, has the MSB aligned with the start of a  
sample frame. Twenty-four audio bits are output  
including the auxiliary bits. This mode is compati-  
ble with many DSPs. If the auxiliary bits are used  
for something other than audio data, they must be  
masked off. The second format, MSB Last, outputs  
data LSB first with the MSB aligned to the end of  
the sample frame. This format is conducive to seri-  
al arithmetic. Both of the above formats output all  
audio bits from the received data. The last three for-  
mats are LSB Last formats that output the most sig-  
nificant 16, 18, and 20 bits respectively, with the  
LSB aligned to the end of the sample frame. These  
formats are used by many interpolation filters.  
Buffer Memory  
In all buffer modes, the status, mask, and control  
registers are located at addresses 0-3, and the user  
data is buffered at locations 4 through 7. The paral-  
lel port can access any location in the user data  
buffer at any time; however, care should be taken  
not to read a location when that location is being  
14  
DS61F1  
CS8411 CS8412  
updated internally. This internal writing is done  
through a second port of the buffer and is done in a  
data, with a pair defined as a frame. This is further  
expanded showing the first sub-frame (A0) to con-  
cyclic manner. As data is received, the bits are as- tain 32 bits defined as per the digital audio stan-  
sembled in an internal 8-bit shift register which, dards. When receiving stereo, channel A is left and  
when full, is loaded into the buffer memory. The  
first bit received is stored in D0 and, after D7 is re-  
ceived, the byte is written into the proper buffer  
memory location.  
channel B is right.  
For all three buffer modes, the three most signifi-  
cant bits in SR1, shown in Figure 6, can be used to  
monitor the channel status data. In buffer mode 2,  
bits 7 and 6 change definition and are described in  
that section. Channel status data, as described in the  
The user data is received one bit per sub-frame. At  
the channel status block boundary, the internal  
pointer for writing user data is initialized to 04H standards, is independent for each channel. Each  
(Hex). After receiving eight user bits, the byte is channel contains its own block of channel status  
written to the address indicated by the user pointer data, and in most systems, both channels will con-  
which is then incremented to point to the next ad- tain the same channel status data. Buffer modes 0  
dress. After receiving all four bytes of user data, 32 and 1 operate on one block of channel status with  
audio samples, the user pointer is set to 04H again  
and the cycle repeats. FLAG0, in SR1 can be used  
to monitor the user data buffer. When the last byte  
the particular block selected by the CS2/CS1 bit in  
CR1. CSDIF, bit 7 in SR1, indicates when the  
channel status data for each channel is not the same  
of the user buffer, location 07H, is written, FLAG0 even though only one channel is being buffered.  
is set low and when the second byte, location 05H, CRCE, bit 6 in SR1, indicates a CRC error oc-  
is written, FLAG0 is set high. If the corresponding curred in the buffered channel. CCHG, bit 5 in  
bit in the interrupt enable register (IER1, bit 0) is  
set, a transition of FLAG0 will generate a low pulse  
on the interrupt pin. The level of FLAG0 indicates  
which two bytes the part will write next, thereby in-  
dicating which two bytes are free to be read.  
SR1, is set when any bit in the buffered channel sta-  
tus bytes 0 to 3, change from one block to the next.  
Buffer Mode 0  
The user data buffer previously described is identi-  
cal for all modes. Buffer mode 0 allocates the rest  
of the buffer to channel status data. This mode  
stores an entire block of channel status in 24 mem-  
ory locations from address 08H to 1FH. Channel  
status (CS) data is different from user data in that  
channel status data is independent for each channel.  
A block of CS data is defined as one bit per frame,  
not one bit per sub-frame; therefore, there are two  
blocks of channel status. The CS2/CS1 bit in CR1  
selects which channel is stored in the buffer. In a  
typical system sending stereo data, the channel sta-  
tus data for each channel would be identical.  
FLAG1 is buffer mode dependent and is discussed  
in the individual buffer mode sections. A transition  
of FLAG1 will generate an interrupt if the appro-  
priate interrupt enable bit is set.  
FLAG2 is set high after channel status byte 23, the  
last byte of the block, is written and set low after  
channel status byte 3 is written to the buffer mem-  
ory. FLAG2 is unique in that only the rising edge  
can cause an interrupt if the appropriate interrupt  
enable bit in IER1 is set.  
Figure 11 illustrates the flag timing for an entire  
channel status block which includes 24 bytes of  
channel status data per channel and 384 audio sam-  
ples. The lower portion of Figure 11 expands the  
first byte of channel status showing eight pairs of  
FLAG1 in status register 1, SR1, can be used to  
monitor the channel status buffer. In mode 0,  
FLAG1 is set low after channel status byte 23 (the  
last byte) is written, and is set high when channel  
DS61F1  
15  
CS8411 CS8412  
Block  
(384 Audio Samples)  
Flag 2  
Flag 1  
Mode 0  
Flag 1  
Modes 1 & 2  
Flag 0  
23 0  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
Channel Status Byte  
0
1
(Expanded)  
Frame  
B 0  
B 1  
A 2  
B 2  
A 0  
A 1  
B 7  
A 7  
(Expanded)  
Sub-frame  
Audio Data  
bit 0  
3
4
7 8  
27 28 29 30 31  
MSB V U C P  
Preamble Aux Data  
LSB  
Validity  
User Data  
Channel Status Data  
Parity Bit  
Figure 11. CS8411 Status Register Flag Timing  
status byte 15, location 17H is written. If the corre-  
Buffer Mode 1  
sponding interrupt enable bit in IER1 is set, a tran-  
sition of FLAG1 will generate a pulse on the  
interrupt pin. Figure 12 illustrates the memory  
write sequence for buffer mode 0 along with flag  
timing. The arrows on the flag timing indicate  
when an interrupt will occur if the appropriate in-  
terrupt enable bit is set. FLAG0 can cause an inter-  
rupt on either edge, which is only shown in the  
expanded portion of the figure for clarity.  
In buffer mode 1, eight bytes are allocated for chan-  
nel status data and sixteen bytes for auxiliary data  
as shown in Figure 5. The user data buffer is the  
same for all modes. The channel status buffer, loca-  
tions 08H to 0FH, is divided into two sections. The  
first four locations always contain the first four  
bytes of channel status, identical to mode 0, and are  
written once per channel status block. The second  
four locations, addresses 0CH to 0FH, provide a  
cyclic buffer for the last 20 bytes of channel status  
data. The channel status buffer is divided in this  
fashion because the first four bytes are the most im-  
16  
DS61F1  
CS8411 CS8412  
Block  
(384 Audio Samples)  
FLAG2  
FLAG1  
FLAG0  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 0  
1F 08  
1
C.S. Byte  
0B 0C  
C.S. Address 08  
(Expanded)  
FLAG0  
C.S. Addr. 1F  
User Addr. 07  
08  
05  
09  
06 07  
0A  
05  
0B  
07  
(Addresses are in Hex)  
04  
04  
06  
Figure 12. CS8411 Buffer Memory Write Sequence - MODE 0  
Block  
(384 Audio Samples)  
FLAG2  
FLAG1  
FLAG0  
0
1
2
3
4
5
6
7 8  
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 0  
0F 0C 0F 0C 0F 0C 0F 08  
1
C.S. Byte  
08  
0B 0C  
0F 0C  
C.S. Address  
(Addresses are in Hex)  
(Expanded)  
FLAG1  
FLAG0  
C.S. Addr. 0F  
08  
05  
09  
07  
1F 10 13,14  
0A  
05  
0B  
07  
1F  
User Addr. 07  
04  
13,14  
06  
04  
06  
Aux. Addr. 1F 10  
17 18 1B,1C  
17 18 1B,1C  
Figure 13. CS8411 Buffer Memory Write Sequence - MODE 1  
DS61F1  
17  
 
CS8411 CS8412  
portant ones; whereas, the last 20 bytes are often  
not used (except for byte 23, CRC).  
Buffer Mode 2  
In buffer mode 2, two 8-byte buffers are available  
to independently buffer each channel of channel  
status data. Both buffers are identical to the channel  
status buffer in mode 1 and are written to simulta-  
neously, with locations 08H to 0FH containing CS  
data for channel A and locations 10H to 17H con-  
taining CS data for channel B. Both CS buffers can  
be monitored using FLAG1 and FLAG2 as de-  
scribed in the BUFFER MODE 1 section.  
FLAG1 and FLAG2 can be used to monitor this  
buffer as shown in Figure 13. FLAG1 is set high  
when CS byte 1, location 09H, is written and is tog-  
gled when every other byte is written. FLAG2 is set  
high after CS byte 23 is written and set low after CS  
byte 3, location 0BH, is written. FLAG2 deter-  
mines whether the channel status pointer is writing  
to the first four-byte section of the channel status  
buffer or the second four-byte section, while  
FLAG1 indicates which two bytes of the section  
are free to update.  
The two most significant bits in SR1 change defini-  
tion for buffer mode 2. These two bits, when set, in-  
dicate CRC errors for their respective channels. A  
CRC error occurs when the internal calculated  
CRC for channel status bytes 0 through 22 does not  
match channel status byte 23. CCHG, bit 5 in SR1,  
is set when any bit in the first four channel status  
bytes of either channel changes from one block to  
the next. Since channel status doesn’t change very  
often, this bit may be monitored rather than check-  
ing all the bits in the first four bytes. These bits are  
illustrated in 6.  
The auxiliary data buffer, locations 10H to 1FH, is  
written to in a cyclic manner similar to the other  
buffers. Four auxiliary data bits are received per  
audio sample (sub-frame) and, since the auxiliary  
data is four times larger than the user data, the aux-  
iliary data buffer on the CS8411 is four times larger  
allowing FLAG0 to be used to monitor both.  
Block  
(384 Audio Samples)  
FLAG2  
FLAG1  
FLAG0  
C.S. Byte  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 0  
1
08  
0B 0C  
13 14  
0F 0C  
0F 0C  
17 14  
0F 0C  
17 14  
0F 0C  
17 14  
0F 08  
17 10  
Left C.S. Ad.  
Right C.S. Ad.  
10  
17 14  
(Addresses are in Hex)  
(Expanded)  
FLAG1  
FLAG0  
Left C.S. Ad.  
Right C.S. Ad.  
User Address  
08  
10  
05  
09  
11  
07  
0A  
12  
0B  
13  
07  
04  
06  
04  
05  
06  
Figure 14. CS8411 Buffer Memory Write Sequence - MODE 2  
18  
DS61F1  
CS8411 CS8412  
entire data buffer may be read starting with the next  
byte to be updated by the internal pointer.  
Buffer Updates and Interrupt Timing  
As mentioned previously in the buffer mode sec-  
tions, conflicts between externally reading the  
buffer RAM and the CS8411 internally writing to it  
may be averted by using the flag levels to avoid the  
section currently being addressed by the part. How-  
ever, if the interrupt line, along with the flags, is  
utilized, the actual byte that was just updated can be  
determined. In this way, the entire buffer can be  
read without concern for internal updates. Figure  
15 shows the detailed timing for the interrupt line,  
flags, and the RAM write line. SCK is 64 times the  
incoming sample frequency, and is the same SCK  
output in master mode. The FSYNC shown is valid  
ERF Pin Timing  
ERF signals that an error occurred while receiving  
the audio sample that is currently being read from  
the serial port. ERF changes with the active edge of  
FSYNC and is high during the erroneous sample.  
ERF is affected by the error conditions reported in  
SR2: LOCK, CODE, PARITY, and V. Any of  
these conditions may be masked off using the cor-  
responding bits in IER2. The ERF pin will go high  
for each error that occurs. The ERF bit in SR1 is  
different from the ERF pin in that it only causes an  
interrupt the first time an error occurs until SR1 is  
read. More information on the ERF pin and bit is  
contained at the end of the Status and IEnable Reg-  
isters section.  
2
for all master modes except the I S compatible  
mode. The interrupt pulse is shown to be 4 SCK pe-  
riods wide and goes low 5 SCK periods after the  
RAM is written. Using the above information, the  
SCK  
FSYNC  
IWRITE  
Left 191  
Right 191  
Left 0  
(FLAG0,1)  
(FLAG2)  
INT  
INT  
FSF1,0 = 1 0  
MSTR = 1  
SCED = 1  
Figure 15. RAM/Buffer - Write and Interrupt Timing  
DS61F1  
19  
 
CS8411 CS8412  
PIN DESCRIPTIONS: CS8411  
CS8411  
DATA BUS BIT 2  
DATA BUS BIT 3  
D2  
D3  
1
2
3
4
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
D1  
DATA BUS BIT 1  
D0  
DATA BUS BIT 0  
SERIAL OUTPUT DATA  
ERROR FLAG  
DATA BUS BIT 4  
D4  
SDATA  
ERF  
CS  
DATA BUS BIT 5  
D5  
DATA BUS BIT 6  
D6  
CHIP SELECT  
DATA BUS BIT 7  
READ/WRITE SELECT  
ANALOG POWER  
ANALOG GROUND  
FILTER  
D7  
RD/WR  
VA+  
DIGITAL POWER  
DIGITAL GROUND  
RECEIVE POSITIVE  
RECEIVE NEGATIVE  
FRAME SYNC  
VD+  
DGND  
RXP  
21 AGND  
20  
19  
18  
17  
FILT  
MCK  
A0  
RXN 10  
MASTER CLOCK  
ADDRESS BUS BIT 0  
ADDRESS BUS BIT 1  
ADDRESS BUS BIT 2  
ADDRESS BUS BIT 3  
11  
12  
FSYNC  
SCK  
SERIAL DATA CLOCK  
ADD BUS BIT 4 / FCLOCK  
INTERRUPT  
A1  
A4/FCK 13  
14  
16 A2  
15  
INT  
A3  
Power Supply Connections  
VD+ - Positive Digital Power, PIN 7.  
Positive supply for the digital section. Nominally +5 volts.  
VA+ - Positive Analog Power, PIN 22.  
Positive supply for the analog section. Nominally +5 volts. This supply should be as quiet as  
possible since noise on this pin will directly affect the jitter performance of the recovered  
clock.  
DGND - Digital Ground, PIN 8.  
Ground for the digital section. DGND should be connected to same ground as AGND.  
AGND - Analog Ground, PIN 21.  
Ground for the analog section. AGND should be connected to same ground as DGND.  
Audio Output Interface  
SCK - Serial Clock, PIN 12.  
Serial clock for SDATA pin which can be configured (via control register 2) as an input or  
output, and can sample data on the rising or falling edge. As an input, SCK must contain 32  
clocks for every audio sample in all normal audio serial port formats.  
20  
DS61F1  
CS8411 CS8412  
FSYNC - Frame Sync, PIN 11.  
Delineates the serial data and may indicate the particular channel, left or right. Also, FSYNC  
may be configured as an input or output. The format is based on bits in control register 2.  
SDATA - Serial Data, PIN 26.  
Audio data serial output pin.  
ERF - Error Flag, PIN 25.  
Signals that an error has occurred while receiving the audio sample currently being read from  
the serial port. The errors that cause ERF to go high are enumerated in status register 2 and  
enabled by setting the corresponding bit in IEnable register 2.  
A4/FCK - Address Bus Bit 4/Frequency Clock, PIN 13.  
This pin has a dual function and is controlled by the FCEN bit in control register 1. A4 is the  
address bus pin as defined below. When used as FCK, an internal frequency comparator  
compares a 6.144 MHz clock input on this pin to the received clock frequency and stores the  
value in status register 1 as three FREQ bits. These bits indicate the incoming frequency as  
well as the tolerance. When defined as FCK, A4 is internally set to 0.  
Parallel Interface  
CS - Chip Select, PIN 24.  
This input is active low and allows access to the 32 bytes of internal memory. The address bus  
and RD/WR must be valid while CS is low.  
RD/WR - Read/Write, PIN 23.  
If RD/WR is low when CS goes active (low), the data on the data bus is written to internal  
memory. If RD/WR is high when CS goes active, the data in the internal memory is placed on  
the data bus.  
A4-A0 - Address Bus, PINS 13, 15-18.  
Parallel port address bus that selects the internal memory location to be read from or written to.  
Note that A4 is the dual function pin A4/FCK as described above.  
D0-D7 - Data Bus, PINS 27-28, 1-6.  
Parallel port data bus used to check status, read or write control words, or read internal buffer  
memory.  
INT - Interrupt, PIN 14.  
Open drain output that can signal the state of the internal buffer memory as well as error  
information. A 5kΩ resistor to VD+ is typically used to support logic gates. All bits affecting  
INT are maskable to allow total control over the interrupt mechanism.  
DS61F1  
21  
CS8411 CS8412  
Receiver Interface  
RXP, RXN - Differential Line Receivers, PINS 9, 10.  
RS422 compatible line receivers. Described in detail in Appendix A.  
Phase Locked Loop  
MCK - Master Clock, PIN 19.  
Low jitter clock output of 256 times the received sample frequency.  
FILT - Filter, PIN 20.  
An external 1kΩ resistor and 0.047 µF capacitor are required from the FILT pin to analog  
ground.  
22  
DS61F1  
CS8411 CS8412  
provide error correction. A block diagram of the  
CS8412 is illustrated in Figure 16.  
CS8412 DESCRIPTION  
The CS8412 does not need a microprocessor to  
handle the non-audio data (although a micro may  
The line receiver and jitter performance are de-  
be used with the C and U serial ports). Instead, ded- scribed in the sections directly preceding the  
icated pins are available for the most important  
channel status bits. The CS8412 is a monolithic  
CMOS circuit that receives and decodes digital au-  
dio data which was encoded according to the digital  
audio interface standards. It contains an RS422 line  
receiver and clock and data recovery utilizing an  
on-chip phase-locked loop. The audio data is out-  
put through a configurable serial port that supports  
14 formats. The channel status and user data have  
their own serial pins and the validity flag is OR’ed  
with the ERF flag to provide a single pin, VERF,  
indicating that the audio output may not be valid.  
This pin may be used by interpolation filters that  
CS8411 sections in the beginning of this data sheet.  
Audio Serial Port  
The audio serial port is used primarily to output au-  
dio data and consists of three pins: SCK, FSYNC,  
and SDATA. These pins are configured via four  
control pins: M0, M1, M2, and M3. M3 selects be-  
tween eight normal serial formats (M3 = 0), and six  
special formats (M3 = 1).  
Normal Modes (M3 = 0)  
When M3 is low, the normal serial port formats  
shown in Figure 17 are selected using M2, M1, and  
M0. These formats are also listed in Table 3,  
VA+  
22  
FILT AGND MCK  
20 21 19  
M3 M2 M1 M0  
17 18 24 23  
Timing  
9
Clock & Data  
Recovery  
RXP  
RXN  
11  
FSYNC  
10  
12  
26  
Audio  
Serial  
Port  
Bi-phase  
SCK  
Decoder  
and  
De-Multiplexer  
Frame  
Sync  
SDATA  
1
14  
28  
7
8
C
U
R
e
g
i
s
t
e
r
s
VD+  
CRC  
check  
Parity  
Check  
DGND  
VERF  
13  
CS12/  
FCK  
15  
25  
Channel  
Error  
Frequency  
CBL  
Status  
Latch  
Comparator  
Encoder  
3
3
ERF  
6
6
16  
SEL  
Multiplexer  
6
5
4
3
2
27  
C0/ Ca/ Cb/ Cc/ Cd/ Ce/  
E0 E1 E2 F0 F1 F2  
Figure 16. CS8412 Block Diagram  
DS61F1  
23  
 
CS8411 CS8412  
wherein the first word past the format number modes 0-2 the previous valid sample is output.)  
(Out-In) indicates whether FSYNC and SCK are  
outputs from the CS8412 or are inputs. The next  
word (L/R-WSYNC) indicates whether FSYNC in-  
dicates the particular channel or just delineates  
each word. If an error occurs (ERF = 1) while using  
one of these formats, the previous valid audio data  
Similarly, when out of lock, the CS8412 will still  
output all the recovered data, which should be ze-  
ros if there is no input to the RXP, RXN pins. For-  
mat 11 is similar to format 0 except that SCK is an  
input and FSYNC is an output. In this mode  
FSYNC and SDATA are synchronized to the in-  
for that channel will be output. As long as ERF is coming SCK, and the number of SCK periods be-  
high, that same data word will be output. If the tween FSYNC edges will vary since SCK is not  
CS8412 is not locked, it will output all zeroes. In synchronous to received data stream. This mode  
some modes FSYNC and SCK are outputs and in  
others they are inputs. In Table 3, LSBJ is short for  
LSB justified where the LSB is justified to the end  
of the audio frame and the MSB varies with word  
length. As outputs the CS8412 generates 32 SCK  
periods per audio sample (64 per stereo sample)  
and, as inputs, 32 SCK periods must be provided  
per audio sample. When FSYNC and SCK are in-  
puts, one stereo sample is double buffered. For  
those modes which output 24 bits of audio data, the  
auxiliary bits will be included. If the auxiliary bits  
are not used for audio data, they must be masked  
off.  
may be useful when writing data to storage.  
M2 M1 M0  
Format  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 - Format 0 - No repeat on error  
9 - Format 1 - No repeat on error  
10 - Format 2 - No repeat on error  
11 - Format 0 - Async. SCK input  
12 - Received NRZ Data  
13 - Received Bi-phase Data  
14 - Reserved  
15 - CS8412 Reset  
Table 4. Special Audio Port Modes (M3=1)  
Format 12 is similar to format 7 except that SDA-  
TA is the entire data word received from the trans-  
mission line including the C, U, V, and P bits, with  
zeros in place of the preamble. In format 13 SDA-  
TA contains the entire biphase encoded data from  
the transmission line including the preamble, and  
SCK is twice the normal frequency. The normal  
two frame delay of data from input to output is re-  
duced to only a few bit periods in formats 12 and  
13. However, the C, U, V bits and error codes fol-  
low their normal pathways and therefore follow the  
output data by nearly two frames. Figure 18 illus-  
trates formats 12 and 13. Format 14 is reserved and  
not presently used, and format 15 causes the  
CS8412 to go into a reset state. While in reset all  
outputs will be inactive except MCK. The CS8412  
comes out of reset at the first block boundary after  
leaving the reset state. It is recommended to reset  
the CS8412 after power-up and any time the user  
performs a system-wide reset. A suggested reset  
circuit is shown in Appendix B.  
M2 M1 M0  
Format  
0 - Out, L/R, 16-24 Bits  
1 - In, L/R, 16-24 Bits  
0
0
0
0
0
1
0
1
0
2 - Out, L/R, I2S Compatible  
3 - In, L/R, I2S Compatible  
4 - Out, WSYNC, 16-24 Bits  
5 - Out, L/R, 16 Bits LSBJ  
6 - Out, L/R, 18 Bits LSBJ  
7 - Out, L/R, MSB Last  
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Table 3. Normal Audio Port Modes (M3=0)  
Special Modes (M3 = 1)  
When M3 is high, the special audio modes de-  
scribed in Table 4 are selected via M2, M1, and  
M0. In formats 8, 9, and 10, SCK, FSYNC, and  
SDATA are the same as in formats 0, 1, and 2 re-  
spectively; however, the recovered data is output as  
is even if ERF is high, indicating an error. (In  
24  
DS61F1  
CS8411 CS8412  
FMT  
No.  
M2 M1 M0  
0 0 0  
Right  
FSYNC (out)  
SCK (out)  
Left  
Left  
0
LSB  
LSB  
MSB  
MSB  
MSB  
MSB  
LSB  
LSB  
MSB  
MSB  
SDATA (out)  
Right  
FSYNC (in)  
1
0 0 1  
SCK (in)  
SDATA (out)  
Left  
FSYNC (out)  
SCK (out)  
Right  
2
0 1 0  
SDATA (out)  
LSB  
MSB  
MSB  
LSB  
MSB  
MSB  
MSB  
FSYNC (in)  
SCK (in)  
Left  
Right  
3
4
0
1
1
0
1
0
SDATA (out)  
MSB  
LSB  
MSB  
LSB  
Right  
FSYNC (out)  
SCK (out)  
Left  
SDATA (out)  
MSB  
LSB  
LSB  
MSB  
Right  
MSB  
Right  
MSB  
Right  
LSB  
FSYNC (out)  
SCK (out)  
Left  
5
6
1
1
0
1
1
0
SDATA (out)  
LSB  
MSB  
LSB  
LSB  
MSB  
LSB  
16 Bits  
16 Bits  
FSYNC (out)  
SCK (out)  
Left  
MSB  
LSB  
LSB  
SDATA (out)  
18 Bits  
18 Bits  
FSYNC (out)  
Left  
7
1
1
1
SCK (out)  
SDATA (out)  
MSB  
LSB  
MSB  
Figure 17. CS8412 Audio Serial Port Formats  
DS61F1  
25  
CS8411 CS8412  
No.  
12*  
Right  
FSYNC (out)  
SCK (out)  
Left  
V U C P  
V U C P  
V U C P  
V U C P  
AUX LSB  
Left  
MSB  
MSB  
AUX LSB  
MSB  
MSB  
SDATA (out)  
13*  
Right  
FSYNC (out)  
SCK (out)  
AUX  
AUX  
LSB  
LSB  
SDATA (out)  
* Error flags are not accurate in these modes.  
Figure 18. Special Audio Port Formats 12 and 13  
or 320 samples). The U output contains the User  
Channel data. The Vbit is OR’ed with the ERF flag  
and output on the VERF pin. This indicates that the  
audio sample may be in error and can be used by in-  
terpolation filters to interpolate through the error.  
ERF being high indicates a serious error occurred  
on the transmission line. There are three errors that  
cause ERF to go high: a parity error or biphase  
coding violation during that sample, or an out of  
lock PLL receiver. Timing for the above pins is il-  
lustrated in Figure 19.  
C, U, VERF, ERF, and CBL Serial Outputs  
The C and U bits and CBL are output one SCK pe-  
riod prior to the active edge of FSYNC in all serial  
2
port formats except 2, 3 and 9 (I S modes). The ac-  
tive edge of FSYNC may be used to latch C, U, and  
CBL externally. In formats 2, 3 and 9, the C and U  
bits and CBL are updated with the active edge of  
FSYNC. The validity + error flag (VERF) and the  
error flag (ERF) are always updated at the active  
edge of FSYNC. This timing is illustrated in Figure  
19.  
Multifunction Pins  
The C output contains the channel status bits with  
CBL rising indicating the start of a new channel  
status block. CBL is high for the first four bytes of  
channel status (32 frames or 64 samples) and low  
for the last 20 bytes of channel status (160 frames  
There are seven multifunction pins which contain  
either error and received frequency information, or  
channel status information, selectable by SEL.  
CBL  
C0,  
Ca-Ce  
Right 191  
Left 0  
Right 0  
Left 1  
Right 31  
Left 32  
Right 191  
Left 0  
SDATA  
FSYNC  
ERF,  
VERF  
C, U  
Figure 19. CBL Timing  
26  
DS61F1  
 
CS8411 CS8412  
lation occurred. The no lock error indicates that the  
PLL is not locked onto the incoming data stream.  
Lock is achieved after receiving three frame pre-  
ambles then one block preamble, and is lost after  
not receiving four consecutive frame preambles.  
Error and Frequency Reporting  
When SEL is low, error and received frequency in-  
formation are selected. The error information is en-  
coded on pins E2, E1, and E0, and is decoded as  
shown in Table 5. When an error occurs, the corre-  
sponding error code is latched. Clearing is then ac-  
complished by bringing SEL high for more than  
eight MCK cycles. The errors have a priority asso-  
ciated with their error code, with validity having  
the lowest priority and no lock having the highest  
priority. Since only one code can be displayed, the  
error with the highest priority that occurred since  
the last clearing will be selected.  
The received frequency information is encoded on  
pins F2, F1, and F0, and is decoded as shown in Ta-  
ble 6. The on-chip frequency comparator compares  
the received clock frequency to an externally sup-  
plied 6.144 MHz clock which is input on the FCK  
pin. The ’F’ pins are updated three times during a  
channel status block including prior to the rising  
edge of CBL. CBL may be used to externally latch  
the ’F’ pins. The clock on FCK must be valid for  
two thirds of a block for the ’F’pins to be accurate.  
E2 E1  
E0  
0
1
0
1
0
1
0
1
Error  
No Error  
Validity Bit High  
Reserved  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
F2  
0
F1  
0
F0  
0
Sample Frequency  
Out of Range  
Slipped Sample  
CRC Error (PRO only)  
Parity Error  
Bi-Phase Coding Error  
No Lock  
0
0
1
48 kHz ± 4%  
0
1
0
44.1 kHz ± 4%  
0
1
1
32 kHz ± 4%  
1
1
1
1
0
0
1
1
0
1
0
1
48 kHz ± 400 ppm  
44.1 kHz ± 400 ppm  
44.056 kHz ± 400 ppm  
32 kHz ± 400 ppm  
Table 5. Error Decoding  
The validity flag indicates that the validity bit for a  
previous sample was high since the last clearing of  
the error codes. The slipped sample error can only  
occur when FSYNC and SCK of the audio serial  
port are inputs. In this case, if FSYNC is asynchro-  
nous to the received data rate, periodically a stereo  
sample will be dropped or reread depending on  
whether the read rate is slower or faster than the re-  
ceived data rate. When this occurs, the slipped sam-  
ple error code will appear on the ’E’pins. The CRC  
error is updated at the beginning of a channel status  
block, and is only valid when the professional for-  
mat of channel status data is received. This error is  
indicated when the CS8412 calculated CRC value  
does not match the CRC byte of the channel status  
block or when a block boundary changes (as in re-  
moving samples while editing). The parity error oc-  
curs when the incoming sub-frame does not have  
even parity as specified by the standards. The bi-  
phase coding error indicates a biphase coding vio-  
Table 6. Sample Frequency Decoding  
Channel Status Reporting  
When SEL is high, channel status is displayed on  
C0, and Ca-Ce for the channel selected by CS12. If  
CS12 is low, channel status for sub-frame1 is dis-  
played, and if CS12 is high, channel status for sub-  
frame 2 is displayed. The contents of Ca-Ce depend  
upon the C0 professional/consumer bit. The infor-  
mation reported is shown in Table 7.  
Pin  
Professional  
Consumer  
0 (low)  
1 (high)  
C0  
Ca  
C1  
EM0  
C1  
C2  
Cb  
Cc  
Cd  
Ce  
EM1  
C3  
C9  
ORIG  
IGCAT  
CRCE  
Table 7. Channel Status Pins  
DS61F1  
27  
CS8411 CS8412  
sis bit of channel status, with C3 low indicating the  
data has had pre-emphasis added.  
Professional Channel Status (C0 = 0)  
When C0 is low, the received channel status block  
is encoded according to the professional/broadcast  
format. The Ca through Ce pins are defined for  
some of the more important professional bits. As  
listed in Table 7, Ca is the inverse of channel status  
bit1. Therefore, if the incoming channel status bit 1  
is 1, Ca, defined as C1, will be 0. C1 indicates  
whether audio (C1=1) or non-audio (C1=0) data is  
being received. Cb and Cc, defined as EM0 and  
EM1 respectively, indicate emphasis and are en-  
coded versions of channel status bits 2, 3, and 4.  
The decoding is listed in Table 8. Cd, defined as  
C9, is the inverse of channel status bit 9, which  
gives some indication of channel mode. (Bit 9 is  
also defined as bit 1 of byte 1.) When Ce, defined  
as CRCE, is low, the CS8412 calculated CRC value  
does not match the received CRC value. This signal  
may be used to qualify Ca through Cd. If Ca  
through Ce are being displayed, Ce going low can  
indicate not to update the display.  
The audio standards, in consumer mode, describe  
bit 15, L, as the generation status which indicates  
whether the audio data is an original work or a copy  
(1st generation or higher). The definition of the  
Lbit is reversed for three category codes: two  
broadcast codes, and laser-optical (CD’s). There-  
fore, to interpret the L bit properly, the category  
code must be decoded. The CS8412 does this de-  
coding internally and provides the ORIG signal  
that, when low, indicates that the audio data is orig-  
inal over all category codes.  
SCMS  
The consumer audio standards also mention a serial  
copy management system, SCMS, for dealing with  
copy protection of copyrighted works. SCMS is de-  
signed to allow unlimited duplication of the origi-  
nal work, but no duplication of any copies of the  
original. This system utilizes the channel status bit  
2, Copy, and channel status bit 15, L or generation  
status, along with the category codes. If the Copy  
bit is 0, copyright protection is asserted over the  
material. Then, the L bit is used to determine if the  
material is an original or a duplication. (As men-  
tioned in the previous paragraph, the definition of  
the L bit can be reversed based on the category  
codes.) There are two category codes that get spe-  
cial attention: general and A/D converters without  
C or L bit information. For these two categories the  
SCMS standard requires that equipment interfacing  
to these categories set the C bit to 0 (copyright pro-  
tection asserted) and the L bit to1 (original). To  
support this feature, Ce, in the consumer mode, is  
defined as IGCAT (ignorant category) which is low  
for the "general" (0000000) and "A/D converter  
without copyright information" (01100xx) catego-  
ries.  
EM1 EM0 C2 C3 C4  
Emphasis  
CCITT J.17 emphasis  
50/15 µs emphasis  
No Emphasis  
0
0
1
1
0
1
0
1
1
1
1
0
1
1
0
0
1
0
0
0
Not Indicated  
Table 8. Emphasis Encoding  
Consumer Channel Status (C0 = 1)  
When C0 is high, the received channel status block  
is encoded according to the consumer format. In  
this case Ca through Ce are defined differently as  
shown in Table 7. Ca is the inverse of channel sta-  
tus bit 1, C1, indicating audio (C1 = 1) or non-audio  
(C1 = 0). Cb is defined as the inverse of channel  
status bit 2, C2, which indicates copy inhibit/copy-  
right information. Cc, defined as C3, is the empha-  
28  
DS61F1  
CS8411 CS8412  
PIN DESCRIPTIONS: CS8412  
CS8412  
CHANNEL STATUS OUTPUT  
CS d / FREQ REPORT 1  
CS c / FREQ REPORT 0  
CS b / ERROR CONDITION 2  
CS a / ERROR CONDITION 1  
CS 0 / ERROR CONDITION 0  
DIGITAL POWER  
C
Cd/F1  
Cc/F0  
Cb/E2  
Ca/E1  
C0/E0  
VD+  
1
2
3
4
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VERF  
Ce/F2  
SDATA  
ERF  
M1  
VALIDITY + ERROR FLAG  
CS e / FREQ REPORT 2  
SERIAL OUTPUT DATA  
ERROR FLAG  
SERIAL PORT MODE SELECT 1  
SERIAL PORT MODE SELECT 2  
ANALOG POWER  
M0  
VA+  
AGND  
FILT  
MCK  
M2  
DIGITAL GROUND  
DGND  
RXP  
ANALOG GROUND  
RECEIVE POSITIVE  
FILTER  
RECEIVE NEGATIVE  
FRAME SYNC  
RXN 10  
FSYNC 11  
SCK 12  
MASTER CLOCK  
SERIAL PORT MODE SELECT 2  
SERIAL PORT MODE SELECT 3  
FREQ/CS SELECT  
SERIAL DATA CLOCK  
M3  
CHANNEL SELECT / FCLOCK CS12/FCK 13  
SEL  
CBL  
USER DATA OUTPUT  
U
14  
CS BLOCK START  
Power Supply Connections  
VD+ - Positive Digital Power, PIN 7.  
Positive supply for the digital section. Nominally +5 volts.  
VA+ - Positive Analog Power, PIN 22.  
Positive supply for the analog section. Nominally +5 volts.  
DGND - Digital Ground, PIN 8.  
Ground for the digital section. DGND should be connected to same ground as AGND.  
AGND - Analog Ground, PIN 21.  
Ground for the analog section. AGND should be connected to same ground as DGND.  
Audio Output Interface  
SCK - Serial Clock, PIN 12.  
Serial clock for SDATA pin which can be configured (via the M0, M1, M2, and M3 pins) as an  
input or output, and can sample data on the rising or falling edge. As an output, SCK will  
generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample must  
be provided in all normal modes.  
DS61F1  
29  
CS8411 CS8412  
FSYNC - Frame Sync, PIN 11.  
Delineates the serial data and may indicate the particular channel, left or right, and may be an  
input or output. The format is based on M0, M1, M2, and M3 pins.  
SDATA - Serial Data, PIN 26.  
Audio data serial output pin.  
M0, M1, M2, M3 - Serial Port Mode Select, PINS 23, 24, 18, 17.  
Selects the format of FSYNC and the sample edge of SCK with respect to SDATA. M3 selects  
between eight normal modes (M3 = 0), and six special modes (M3 = 1).  
Control Pins  
VERF - Validity + Error Flag, PIN 28.  
A logical OR’ing of the validity bit from the received data and the error flag. May be used by  
interpolation filters to interpolate through errors.  
U - User Bit, PIN 14.  
Received user bit serial output port. FSYNC may be used to latch this bit externally. (Except in  
2
I S modes when this pin is updated at the active edge of FSYNC.)  
C - Channel Status Output, PIN 1.  
Received channel status bit serial output port. FSYNC may be used to latch this bit externally.  
2
(Except in I S modes when this pin is updated at the active edge of FSYNC.)  
CBL - Channel Status Block Start, PIN 15.  
The channel status block output is high for the first four bytes of channel status and low for the  
last 20 bytes.  
SEL - Select, PIN 16.  
Control pin that selects either channel status information (SEL = 1) or error and frequency  
information (SEL = 0) to be displayed on six of the following pins.  
C0, Ca, Cb, Cc, Cd, Ce - Channel Status Output Bits, PINS 2-6, 27.  
These pins are dual function with the ’C’ bits selected when SEL is high. Channel status  
information is displayed for the channel selected by CS12. C0, which is channel status bit 0,  
defines professional (C0 = 0) or consumer (C0 = 1) mode and further controls the definition of  
the Ca-Ce pins. These pins are updated with the rising edge of CBL.  
CS12 - Channel Select, PIN 13.  
This pin is also dual function and is selected by bringing SEL high. CS12 selects sub-frame1  
(when low) or sub-frame2 (when high) to be displayed by channel status pins C0 and Ca  
through Ce.  
30  
DS61F1  
CS8411 CS8412  
FCK - Frequency Clock, PIN 13.  
Frequency Clock input that is enabled by bringing SEL low. FCK is compared to the received  
clock frequency with the value displayed on F2 through F0. Nominal input value is 6.144 MHz.  
E0, E1, E2 - Error Condition, PINS 4-6.  
Encoded error information that is enabled by bringing SEL low. The error codes are prioritized  
and latched so that the error code displayed is the highest level of error since the last clearing  
of the error pins. Clearing is accomplished by bringing SEL high for more than 8 MCK cycles.  
F0, F1, F2 - Frequency Reporting Bits, PINS 2-3, 27.  
Encoded sample frequency information that is enabled by bringing SEL low. A proper clock on  
FCK must be input for at least two thirds of a channel status block for these pins to be valid.  
They are updated three times per block, starting at the block boundary.  
ERF - Error Flag, PIN 25.  
Signals that an error has occurred while receiving the audio sample currently being read from  
the serial port. Three errors cause ERF to go high: a parity or biphase coding violation during  
the current sample, or an out of lock PLL receiver.  
Receiver Interface  
RXP, RXN - Differential Line Receivers, PINS 9, 10.  
RS422 compatible line receivers.  
Phase Locked Loop  
MCK - Master Clock, PIN 19.  
Low jitter clock output of 256 times the received sample frequency.  
FILT - Filter, PIN 20.  
An external 1 kΩ resistor and 0.047 µF capacitor is required from FILT pin to analog ground.  
DS61F1  
31  
CS8411 CS8412  
ORDERING GUIDE  
Model  
Temperature Range  
Package  
CS8411 - CP  
CS8411 - IP  
CS8411 - CS  
CS8411 - IS  
0 to 70 °C*  
-40 to 85 °C  
0 to 70 °C*  
-40 to 85 °C  
28-Pin Plastic .6” DIP  
28-Pin Plastic .6” DIP  
28-Pin Plastic SOIC  
28-Pin Plastic SOIC  
CS8412 - CP  
CS8412 - IP  
CS8412 - CS  
CS8412 - IS  
0 to 70 °C*  
-40 to 85 °C  
0 to 70 °C*  
-40 to 85 °C  
28-Pin Plastic .6” DIP  
28-Pin Plastic .6” DIP  
28-Pin Plastic SOIC  
28-Pin Plastic SOIC  
* Although the ‘-CP’ and ‘-CS’ suffixed parts are guaranteed to operate over 0 to 70 °C, they are tested at 25 °C  
only. If testing over temperature is desired, the ‘-IP’ and ‘-IS’ suffixed parts are tested over their speci-  
fied temperature range.  
32  
DS61F1  
CS8411 CS8412  
PACKAGE DIMENSIONS  
28 PIN PLASTIC (PDIP) (600 MIL) PACKAGE DRAWING  
eB  
D
eC  
E
E1  
1
A2  
A1  
A
SEATING  
PLANE  
TOP VIEW  
L
c
e
eA  
b1  
b
SIDE VIEW  
BOTTOM VIEW  
INCHES  
MILLIMETERS  
DIM  
A
A1  
A2  
b
b1  
c
D
E
E1  
e
eA  
eB  
eC  
L
MIN  
0.000  
0.015  
0.125  
0.014  
0.030  
0.008  
1.380  
0.600  
0.485  
0.090  
0.580  
0.600  
0.000  
0.115  
0°  
MAX  
0.250  
0.025  
0.195  
0.022  
0.070  
0.014  
1.565  
0.625  
0.580  
0.110  
0.620  
0.700  
0.060  
0.200  
15°  
MIN  
0.00  
0.38  
3.18  
0.36  
0.76  
0.20  
35.05  
15.24  
12.32  
2.29  
14.73  
15.24  
0.00  
2.92  
0°  
MAX  
6.35  
0.64  
4.95  
0.56  
1.78  
0.36  
39.75  
15.88  
14.73  
2.79  
15.75  
17.78  
1.52  
5.08  
15°  
DS61F1  
33  
CS8411 CS8412  
28L SOIC (300 MIL BODY) PACKAGE DRAWING  
E
H
1
b
c
D
L
SEATING  
PLANE  
A
e
A1  
INCHES  
MILLIMETERS  
DIM  
A
A1  
B
C
D
E
e
H
L
MIN  
0.093  
0.004  
0.013  
0.009  
0.697  
0.291  
0.040  
0.394  
0.016  
0°  
MAX  
0.104  
0.012  
0.020  
0.013  
0.713  
0.299  
0.060  
0.419  
0.050  
8°  
MIN  
2.35  
0.10  
0.33  
0.23  
17.70  
7.40  
1.02  
10.00  
0.40  
0°  
MAX  
2.65  
0.30  
0.51  
0.32  
18.10  
7.60  
1.52  
10.65  
1.27  
8°  
34  
DS61F1  
CS8411 CS8412  
APPENDIX A: RS422 RECEIVER  
INFORMATION  
CS8411/12  
XLR  
* See Text  
RXP  
The RS422 receivers on the CS8411 and CS8412  
are designed to receive both the professional and  
consumer interfaces, and meet all specifications  
listed in the digital audio standards. Figure 20 illus-  
trates the internal schematic of the receiver portion  
of both chips. The receiver has a differential input.  
A Schmitt trigger is incorporated to add hysteresis  
which prevents noisy signals from corrupting the  
phase detector.  
110  
Twisted  
Pair  
Ω
110  
Ω
RXN  
1
Figure 21. Professional Input Circuit  
CS8411/12  
XLR  
0.01  
0.01  
µF  
* See Text  
110  
RXP  
RXN  
110  
Ω
µ
F
Ω
Twisted  
Pair  
1
8 k  
Ω
8 k  
Ω
16 k  
Ω
Figure 22. Transformerless Professional Circuit  
9
RXP  
+
-
Although transformers are not required by AES  
they are strongly recommended. The EBU requires  
transformers. Figures 21 and 22 show an optional  
DC blocking capacitor on the transmission line. A  
0.1 to 0.47 µF ceramic capacitor may be used to  
block any DC voltage that is accidentally connect-  
ed to the digital audio receiver. The use of this ca-  
pacitor is an issue of robustness as the digital audio  
transmission line does not have a DC voltage com-  
ponent.  
16 k  
4 k  
Ω
Ω
10 RXN  
4 k  
Ω
Figure 20. RS422 Receiver Internal Circuit  
Professional Interface  
The digital audio specifications for professional  
use call for a balanced receiver, using XLR connec-  
tors, with 110Ω ± 20% impedance. (The XLR con-  
nector on the receiver should have female pins with  
a male shell.) Since the receiver has a very high im-  
pedance, a 110Ω resistor should be placed across  
the receiver terminals to match the line impedance,  
as shown in Figure 21, and, since the part has inter-  
nal biasing, no external biasing network is needed.  
If some isolation is desired without the use of trans-  
formers, a 0.01 µF capacitor should be placed on  
the input of each pin (RXP and RXN) as shown in  
Figure 22. However, if transformers are not used,  
high frequency energy could be coupled between  
transmitter and receiver causing degradation in an-  
alog performance.  
Grounding the shield of the cable is a tricky issue.  
In the configuration of systems, it is important to  
avoid ground loops and DC current flowing down  
the shield of the cable that could result when boxes  
with different ground potentials are connected.  
Generally, it is good practice to ground the shield  
to the chassis of the transmitting unit, and connect  
the shield through a capacitor to chassis ground at  
the receiver. However, in some cases it is advanta-  
gous to have the ground of two boxes held to the  
same potential, and the cable shield might be de-  
pended upon to make that electrical connection.  
Generally, it may be a good idea to provide the op-  
tion of grounding or capacitively coupling to  
ground with a "ground-lift" circuit.  
DS61F1  
35  
 
 
 
CS8411 CS8412  
Consumer Interface  
TTL/CMOS Levels  
The circuit shown in Figure 24 may be used when  
In the case of the consumer interface, the standards  
call for an unbalanced circuit having a receiver im- external RS422 receivers or TTL/CMOS logic  
pedance of 75Ω ± 5%. The connector for the con- drive the CS8411/12 receiver section.  
sumer interface is an RCA phono plug (fixed  
TTL/CMOS  
Gate  
CS8411/12  
socket described in Table IV of IEC268-11). The  
receiver circuit for the consumer interface is shown  
in Figure 23.  
µ
0.01 F  
RXP  
RXN  
0.01  
CS8411/12  
µF  
µ
F
0.01  
RCA Phono  
75  
RXP  
RXN  
Figure 24. TTL/CMOS Interface  
75  
Ω
Ω
Coax  
0.01  
Transformers  
µF  
Please refer to Application Note AN134: AES and  
S/PDIF Recommended Transformers for further  
information.  
Figure 23. Consumer Input Circuit  
36  
DS61F1  
 
 
CS8411 CS8412  
APPENDIX B: SUGGESTED RESET  
CIRCUIT FOR CS8412  
M0  
M0  
M1  
M2  
M1  
CS8412  
M2  
M3  
M3  
RESET  
Figure 25. CS8412 Reset Circuit  
The CS8412 should be reset immediately after Mode Select pins high. Figure 25 shows a simple  
power-up and any time the user issues a system- circuit to implement this. The OR gates can be  
wide reset. This is accomplished by pulling all four 74LS32 type gates.  
DS61F1  
37  
 

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