CS8406-DZZR [CIRRUS]
192 kHz Digital Audio Interface Transmitter; 192千赫数字音频接口发射器
| 型号： | CS8406-DZZR |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 192 kHz Digital Audio Interface Transmitter |
| 文件： | 总42页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8406
192 kHz Digital Audio Interface Transmitter
Features
General Description
The CS8406 is a monolithic CMOS device which en-
codes and transmits audio data according to the AES3,
IEC60958, S/PDIF, or EIAJ CP1201 standards. The
CS8406 accepts audio and digital data, which is then
multiplexed, encoded, and driven onto a cable.
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-compatible Transmitter
+3.3 V or 5.0 V Digital Supply (VD)
+3.3 V or 5.0 V Digital Interface (VL)
The audio data is input through a configurable, 3-wire
input port. The channel status and user bit data are in-
On-Chip Channel Status and User Bit Buffer
TM
put through an SPI™ or I²C microcontroller port, and
Memories Allow Block-Sized Updates
may be assembled in block-sized buffers. For systems
with no microcontroller, a Stand-Alone Mode allows di-
rect access to channel status and user bit data pins.
Flexible 3-Wire Serial Digital Audio Input Port
Up to 192-kHz Frame Rate
The CS8406 is available in 28-pin TSSOP, SOIC, and
QFN packages in both Commercial (-10º to +70ºC) and
Automotive grades (-40º to +85ºC). The CDB8416
Demonstration board is also available for device
evaluation and implementation suggestions. Please
refer to “Ordering Information” on page 37 for complete
details.
Microcontroller Write Access to Channel Status
and User Bit Data
On-Chip Differential Line Driver
Generates CRC Codes and Parity Bits
Target applications include A/V Receivers, CD-R, DVD
receivers, digital mixing consoles, effects processors,
set-top boxes, and computer and automotive audio
systems.
Stand-Alone Mode Allows Use Without a
Microcontroller
GND
VL
VD
RXP
AES3
S/PDIF
Encoder
TXP
C or U Data Buffer
Driver
TXN
TCBL
ILRCK
ISCLK
SDIN
Serial
Audio
Input
Output Clock
Generator
Control Port &
Registers
Misc.
Control
H/S RST
U
SDA/
SCL/ AD1/ AD0/ AD2 INT
OMCK
CDOUT CCLK CDIN CS
Copyright Cirrus Logic, Inc. 2009
OCT '09
DS580F5
(All Rights Reserved)
http://www.cirrus.com
CS8406
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4
SPECIFIED OPERATING CONDITIONS.............................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4
DC ELECTRICAL CHARACTERISTICS ............................................................................................... 4
DIGITAL INPUT CHARACTERISTICS.................................................................................................. 5
DIGITAL INTERFACE SPECIFICATIONS ............................................................................................ 5
TRANSMITTER CHARACTERISTICS .................................................................................................. 5
SWITCHING CHARACTERISTICS ....................................................................................................... 5
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS ............................................................. 6
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE................................................... 7
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE.................................................... 8
2. TYPICAL CONNECTION DIAGRAMS .................................................................................................. 9
3. GENERAL DESCRIPTION .................................................................................................................. 11
3.1 AES3 and S/PDIF Standards Documents .................................................................................... 11
4. THREE-WIRE SERIAL INPUT AUDIO PORT ..................................................................................... 12
5. AES3 TRANSMITTER ......................................................................................................................... 13
5.1 TXN and TXP Drivers ................................................................................................................... 13
5.2 Mono Mode Operation .................................................................................................................. 13
5.3 Transmitted Frame and Channel Status Boundary Timing ........................................................... 13
6. CONTROL PORT DESCRIPTION ....................................................................................................... 16
6.1 SPI Mode ...................................................................................................................................... 16
6.2 I²C Mode ....................................................................................................................................... 17
7. CONTROL PORT REGISTER SUMMARY ......................................................................................... 18
8. CONTROL PORT REGISTER BIT DEFINITIONS .............................................................................. 19
8.1 Memory Address Pointer (MAP) ................................................................................................... 19
8.2 Default = ‘000000’Control 1 (01h) ................................................................................................. 19
8.3 Control 2 (02h) .............................................................................................................................. 19
8.4 Data Flow Control (03h) ............................................................................................................... 20
8.5 Clock Source Control (04h) .......................................................................................................... 20
8.6 Serial Audio Input Port Data Format (05h) ................................................................................... 21
8.7 Interrupt 1 Status (07h) (Read Only) ............................................................................................ 22
8.8 Interrupt 2 Status (08h) (Read Only) ............................................................................................ 22
8.9 Interrupt 1 Mask (09h) .................................................................................................................. 22
8.10 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh) ................................................... 23
8.11 Interrupt 2 Mask (0Ch) ................................................................................................................ 23
8.12 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh) .................................................. 23
8.13 Channel Status Data Buffer Control (12h) .................................................................................. 23
8.14 User Data Buffer Control (13h) ................................................................................................... 24
8.15 Channel Status Bit or User Bit Data Buffer (20h - 37h) .............................................................. 24
8.16 CS8406 I.D. and Version Register (7Fh) (Read Only) ................................................................ 24
9. PIN DESCRIPTION - SOFTWARE MODE ........................................................................................ 25
10. HARDWARE MODE .......................................................................................................................... 28
10.1 Channel Status, User and Validity Data ..................................................................................... 28
10.2 Serial Audio Port ......................................................................................................................... 29
11. PIN DESCRIPTION - HARDWARE MODE ..................................................................................... 30
12. APPLICATIONS ................................................................................................................................ 33
12.1 Reset, Power Down and Start-Up .............................................................................................. 33
12.2 ID Code and Revision Code ....................................................................................................... 33
12.3 Power Supply, Grounding, and PCB layout ................................................................................ 33
12.4 Synchronization of Multiple CS8406s ......................................................................................... 33
13. PACKAGE DIMENSIONS ................................................................................................................ 34
14. ORDERING INFORMATION ............................................................................................................. 37
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DS580F5
CS8406
15. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS ................... 38
15.1 AES3 Transmitter External Components .................................................................................... 38
15.2 Isolating Transformer Requirements .......................................................................................... 38
16. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........................ 39
16.1 AES3 Channel Status(C) Bit Management ................................................................................. 39
16.1.1 Accessing the E buffer ................................................................................................... 39
16.1.2 Serial Copy Management System (SCMS) .................................................................... 40
16.1.3 Channel Status Data E Buffer Access ........................................................................... 40
16.2 AES3 User (U) Bit Management ................................................................................................. 41
16.2.1 Mode 1: Transmit All Zeros ............................................................................................ 41
16.2.2 Mode 2: Block Mode ...................................................................................................... 41
17. REVISION HISTORY ......................................................................................................................... 42
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing ................................................................................................... 6
Figure 2. Audio Port Slave Mode and Data Input Timing............................................................................. 6
Figure 3. SPI Mode Timing .......................................................................................................................... 7
Figure 4. I²C Mode Timing ........................................................................................................................... 8
Figure 5. Recommended Connection Diagram for Software Mode ............................................................. 9
Figure 6. Recommended Connection Diagram for Hardware Mode.......................................................... 10
Figure 7. Serial Audio Input Example Formats .......................................................................................... 12
Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data, Stereo Mode..................................... 14
Figure 9. AES3 Transmitter Timing for C, U, and V Pin Input Data, Mono Mode ...................................... 15
Figure 10. Control Port Timing in SPI Mode .............................................................................................. 16
Figure 11. Control Port Timing, I²C Slave Mode Write............................................................................... 17
Figure 12. Control Port Timing, I²C Slave Mode Read............................................................................... 17
Figure 13. Hardware Mode Data Flow ....................................................................................................... 28
Figure 14. Professional Output Circuit ....................................................................................................... 38
Figure 15. Consumer Output Circuit (VL = 5.0 V) ...................................................................................... 38
Figure 16. TTL/CMOS Output Circuit......................................................................................................... 38
Figure 17. Channel Status Data Buffer Structure....................................................................................... 39
Figure 18. Flowchart for Writing the E Buffer............................................................................................. 40
LIST OF TABLES
Table 1. Control Register Map Summary................................................................................................... 18
Table 2. Hardware Mode COPY/C and ORIG Pin Functions..................................................................... 29
Table 3. Hardware Mode Serial Audio Port Format Selection ................................................................... 29
Table 4. Hardware Mode OMCK Clock Ratio Selection............................................................................. 29
Table 5. Equivalent Register Settings of Serial Audio Input Formats in Hardware Mode.......................... 29
DS580F5
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CS8406
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and T = 25°C.)
A
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V)
Parameter
Symbol
Min
Typ
Max
Units
Power Supply Voltage
VD
VL
3.14
3.14
3.3 or 5.0
3.3 or 5.0
5.25
5.25
V
V
Ambient Operating Temperature:
Commercial Grade
Automotive Grade
TA
TA
-10
-40
-
-
+70
+85
°C
°C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the
device. Normal operation is not guaranteed at these extremes.)
Parameter
Symbol
VD, VL
Iin
Min
-
Max
6.0
Units
V
Power Supply Voltage
Input Current, Any Pin Except Supplies
Input Voltage
(Note 1)
-
±10
mA
V
Vin
-0.3
-55
-65
VL + 0.3
125
Ambient Operating Temperature (power applied)
Storage Temperature
TA
°C
Tstg
150
°C
Notes:
1. Transient currents of up to 100 mA will not cause SCR latch-up.
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V.)
Parameters
Power-Down Mode (Note 2)
Symbol
Min
Typ
Max
Units
Supply Current in power down
VD = 3.3 V
VD = 5.0 V
VL = 3.3 V
VL = 5.0 V
ID
ID
IL
IL
-
-
-
-
20
40
0
-
-
-
-
μA
μA
μA
μA
0
Normal Operation (Note 3)
Supply Current at 48 kHz frame rate (Note 4)
VD = 3.3 V
VD = 5.0 V
VL = 3.3 V
VL = 5.0 V
ID
ID
IL
IL
-
-
-
-
1.9
3.5
6.5
-
-
-
-
mA
mA
mA
mA
10.6
Supply Current at 192 kHz frame rate (Note 4)
VD = 3.3 V
VD = 5.0 V
VL = 3.3 V
VL = 5.0 V
ID
ID
IL
IL
-
-
-
-
7.6
12.7
7.2
12
-
-
-
-
mA
mA
mA
mA
2. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
3. Normal operation is defined as RST = HI.
4. Assumes that no inputs are left floating. It is recommended that all digital inputs be driven high or low
at all times.
4
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CS8406
DIGITAL INPUT CHARACTERISTICS
Parameters
Symbol
Min
Typ
-
Max
±0.5
-
Units
μA
Input Leakage Current
Iin
-
-
Input Hysteresis (all inputs except OMCK)
0.25
V
DIGITAL INTERFACE SPECIFICATIONS
(GND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol
Min
Max
Units
High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN
Low-Level Output Voltage (IOH = 3.2 mA), except TXP/TXN
VOH
VOL
VL - 1.0
-
-
V
V
0.4
High-Level Output Voltage, TXP, TXN
Low-Level Output Voltage, TXP, TXN
High-Level Input Voltage
(21 mA at VL = 5.0 V)
(15 mA at VL = 3.3 V)
VL - 0.7
VL - 0.7
VL
VL
V
V
(21 mA at VL = 5.0 V)
(16 mA at VL = 3.3 V)
-
-
0.7
0.7
V
V
VD = 5.0 V
VD = 3.3 V
VIH
VIL
2.75
2.0
VL + 0.3
VL + 0.3
V
V
Low-Level Input Voltage
VD = 5.0 V
VD = 3.3 V
-0.3
-0.3
0.8
0.8
V
V
TRANSMITTER CHARACTERISTICS
Parameters
Symbol
Typ
Units
TXP Output Resistance
VL = 5.0 V
VL = 3.3 V
RTXP
26.5
33.5
Ω
Ω
TXN Output Resistance
VL = 5.0 V
VL = 3.3 V
RTXN
26.5
33.5
Ω
Ω
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C = 20 pF)
L
Parameter
RST pin Low Pulse Width
Symbol
Min
Typ
Max
Units
μs
200
4.1
4.1
3.1
6.1
2.0
8.1
1.0
18.3
8
-
-
OMCK Frequency for OMCK = 512*Fs
OMCK Low and High Width for OMCK = 512*Fs
OMCK Frequency for OMCK = 384*Fs
OMCK Low and High Width for OMCK = 384*Fs
OMCK Frequency for OMCK = 256*Fs
OMCK Low and High Width for OMCK = 256*Fs
OMCK Frequency for OMCK = 128*Fs
OMCK Low and High Width for OMCK = 128*Fs
Frame Rate
-
98.4
MHz
ns
-
-
-
73.8
MHz
ns
-
-
49.2
-
-
MHz
ns
-
-
24.6
-
MHz
ns
-
-
192
-
kHz
ps RMS
AES3 Transmitter Output Jitter
-
200
DS580F5
5
CS8406
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C = 20 pF)
L
Parameter
SDIN Setup Time Before ISCLK Active Edge
SDIN Hold Time After ISCLK Active Edge
Master Mode
Symbol
tds
Min
10
8
Typ
Max
Units
ns
(Note 5)
(Note 5)
-
-
-
-
tdh
ns
OMCK to ISCLK active edge delay
OMCK to ILRCK delay
(Note 5)
(Note 6)
tsmd
tlmd
0
0
-
-
-
17
16
-
ns
ns
%
ISCLK and ILRCK Duty Cycle
Slave Mode
50
ISCLK Period
tsckw
tsckl
36
14.4
14.4
10
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ISCLK Input Low Width
ISCLK Input High Width
tsckh
tlrckd
tlrcks
ISCLK Active Edge to ILRCK Edge
ILRCK Edge Setup Before ISCLK Active Edge
(Note 7)
(Note 8)
10
Notes:
5. The active edge of ISCLK is programmable in Software Mode.
6. The polarity of ILRCK is programmable in Software Mode.
7. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed.
8. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.
ILRCK
(input)
ISCLK
(output)
t
t
t
sckh
t
lrckd
lrcks
sckl
ISCLK
(input)
ILRCK
(output)
t
sckw
t
smd
t
lmd
SDIN
OMCK
(input)
t
t
ds
dh
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing
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DS580F5
CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C = 20 pF)
L
Parameter
Symbol
Min
Typ
Max
Units
CCLK Clock Frequency
(Note 9)
fsck
0
-
6.0
MHz
CS High Time Between Transmissions
tcsh
1.0
-
-
μs
CS Falling to CCLK Edge
CCLK Low Time
tcss
tscl
tsch
tdsu
tdh
tpd
tr1
20
66
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CCLK High Time
(Note 10)
(Note 11)
MAX ((1/256 FS + 8), 66)
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
40
15
-
-
-
-
-
-
-
-
-
-
50
25
25
100
100
-
Fall Time of CDOUT
tf1
-
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 12)
(Note 12)
tr2
-
tf2
-
Notes:
9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is dic-
tated by the timing requirements necessary to access the Channel Status and User Bit buffer memory.
Access to the control register file can be carried out at the full 6 MHz rate.
10. T
must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns.
sch
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For f < 1 MHz.
sck
CS
t
t
scl
sch
t
t
csh
css
CCLK
t
t
r2
f2
CDIN
t
dsu
t
dh
t
pd
CDOUT
Figure 3. SPI Mode Timing
DS580F5
7
CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C = 20 pF)
L
Parameter
SCL Clock Frequency
Symbol
fscl
Min
-
Typ
Max
Units
kHz
μs
-
-
-
-
-
-
-
-
-
-
-
100
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
tbuf
4.7
4.0
4.7
4.0
4.7
0
-
thdst
tlow
-
μs
-
μs
Clock High Time
thigh
tsust
thdd
tsud
tr
-
μs
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
-
μs
(Note 13)
-
-
μs
250
-
ns
1000
300
-
ns
tf
-
ns
tsusp
4.7
μs
13. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Repeated
Start
Stop
t
Start
Stop
SDA
SCL
t
t
t
t
buf
t
high
hdst
f
susp
hdst
t
t
t
t
t
sust
sud
r
hdd
low
Figure 4. I²C Mode Timing
8
DS580F5
CS8406
2. TYPICAL CONNECTION DIAGRAMS
+3.3 V or +5.0 V
+3.3 V or +5.0 V
0.1μF
0.1μF
VD
VL
AES3 /
S/PDIF
Source
RXP
ILRCK
ISCLK CS8406
SDIN
TXP
TXN
Transmission
Serial
Audio
Source
Interface
Clock Source
and Control
OMCK
User Data
Source
U
AD0 / CS
AD1 / CDIN
AD2
47kΩ
SCL / CCLK
SDA / CDOUT
Microcontroller
H/S
RST
INT
TCBL
GND
To/from other
CS8406's
Figure 5. Recommended Connection Diagram for Software Mode
DS580F5
9
CS8406
+3.3 V or +5.0 V
0.1μF
+3.3 V or +5.0 V
0.1μF
VD
VL
H/S
ILRCK
ISCLK
SDIN
Serial
Audio
Source
TXP
TXN
Transmission
Interface
CS8406
Clock Source
and Control
OMCK
C Data
Source
COPY/C
U
HWCK1
HWCK0
SFMT0
SFMT1
APMS
User Data
Source
47kΩ
47kΩ
TCBLD
Hardware
Control
RST
CEN
EMPH
Validity
Source
V
AUDIO
ORIG
TCBL
GND
To/from other
CS8406's
Figure 6. Recommended Connection Diagram for Hardware Mode
10
DS580F5
CS8406
3. GENERAL DESCRIPTION
The CS8406 is a monolithic CMOS device which encodes and transmits audio data according to the AES3,
IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8406 accepts audio, channel status and user da-
ta, which is then multiplexed, encoded, and driven onto a cable.
The audio data is input through a configurable, 3-wire input port. The channel status bits and user bit data are input
through an SPI or I²C Mode microcontroller port and may be assembled in separate block sized buffers.
For systems with no microcontroller, a Stand-Alone Mode allows direct access to channel status and user data input
pins.
Target applications include CD-R, DAT, DVD, MD and VTR equipment, mixing consoles, digital audio transmission
equipment, high quality A/D converters, effects processors, set-top TV boxes, and computer audio systems.
Figure 5 shows the supply and external connections to the CS8406 when configured for operation with a microcon-
troller. Figure 6 shows the supply and external connections to the CS8406 when configured for operation without a
microcontroller.
3.1
AES3 and S/PDIF Standards Documents
This data sheet assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable to
have current copies of the AES3 and IEC60958 specifications on hand for easy reference.
The latest AES3 standard is available from the Audio Engineering Society or ANSI at www.aes.org or
www.ansi.org. Obtain the latest IEC60958 standard from ANSI or from the International Electrotechnical
Commission at www.iec.ch. The latest EIAJ CP-1201 standard is available from the Japanese Electronics
Bureau.
Application Note 22: Overview of Digital Audio Interface Data Structures contains a useful tutorial on digital
audio specifications, but it should not be considered a substitute for the standards.
The paper An Understanding and Implementation of the SCMS Serial Copy Management System for Digital
Audio Transmission, by Clifton Sanchez, is an excellent tutorial on SCMS. It is available from the AES as
reprint 3518.
DS580F5
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CS8406
4. THREE-WIRE SERIAL INPUT AUDIO PORT
A 3-wire serial audio input port is provided. The interface format can be adjusted to suit the attached device through
the control registers. The following parameters are adjustable:
•
•
•
•
•
•
•
Master or slave
Serial clock frequency
Audio data resolution
Left or right justification of the data relative to left/right clock
Optional one-bit cell delay of the first data bit
Polarity of the bit clock
Polarity of the left/right clock (by setting the appropriate control bits, many formats are possible.)
Figure 7 shows a selection of common input formats with the corresponding control bit settings.
In Master Mode, the left/right clock and the serial bit clock are outputs, derived from the OMCK input pin master
clock.
In Slave Mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the
OMCK master clock, but the serial bit clock can be asynchronous and discontinuous if required. The left/right clock
should be continuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks
are present in each phase to clock all the data bits.
Right
Left
ILRCK
ISCLK
SDIN
Left
Justified
(In)
MSB
LSB
MSB
LSB
MSB
Left
Right
ILRCK
I2 S
(In)
ISCLK
SDIN
LSB
MSB
LSB
MSB
MSB
Right
MSB
Left
ILRCK
ISCLK
Right
Justified
(In)
LSB
MSB
LSB
LSB
SDIN
SIMS*
SISF*
SIRES[1:0]*
SIJUST*
SIDEL*
SISPOL*
SILRPOL*
Left Justified
X
X
X
X
X
X
00+
00+
XX
0
0
1
0
1
0
0
0
0
0
1
0
I²S
Right Justified
X = don’t care to match format, but does need to be set to the desired setting
+ I²S can accept an arbitrary number of bits, determined by the number of ISCLK cycles
* See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 7. Serial Audio Input Example Formats
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CS8406
5. AES3 TRANSMITTER
The CS8406 includes an AES3 digital audio transmitter. A comprehensive buffering scheme provides write access
to the channel status and user data. This buffering scheme is described in “Appendix B: Channel Status and User
Data Buffer Management” on page 39.
The AES3 transmitter encodes and transmits audio and digital data according to the AES3, IEC60958 (S/PDIF), and
EIAJ CP-1201 interface standards. Audio and control data are multiplexed together and bi-phase mark encoded.
The resulting bit stream is driven to an output connector either directly or through a transformer. The transmitter is
clocked from the clock input pin, OMCK. If OMCK is asynchronous to the data source, an interrupt bit (TSLIP) is
provided that will go high every time a data sample is dropped or repeated.
The channel status (C) and user (U) bits in the transmitted data stream are taken from storage areas within the
CS8406. The user can access the internal storage or configure the CS8406 to run in one of several automatic
modes. “Appendix B: Channel Status and User Data Buffer Management” on page 39 provides detailed descriptions
of each automatic mode and describes methods of accessing the storage areas. The transmitted user bit data can
optionally be input through the U pin, under the control of a control port register bit.
Figures 8 and 9 show the C/U/V timing requirements.
5.1
TXN and TXP Drivers
The AES3 transmitter line drivers are low skew, low impedance, differential outputs capable of driving ca-
bles directly. Both drivers are set to ground during reset (RST = LOW), when no AES3 transmit clock is pro-
vided, and optionally under the control of a register bit. The CS8406 also allows immediate muting of the
AES3 transmitter audio data through a control register bit.
External components are used to terminate and isolate the external cable from the CS8406. These compo-
nents are detailed in “Appendix A: External AES3/SPDIF/IEC60958 Transmitter Components” on page 38.
5.2
Mono Mode Operation
An alternate method for transmitting an AES3 192 kHz sample rate stream is Mono Mode. Mono Mode is
implemented by using the two sub-frames in a 96 kHz biphase encoded stream to carry consecutive sam-
ples of a single channel of a 192 kHz PCM stream (i.e. a mono signal). This allows older equipment, whose
AES3 transmitters and receivers are not rated for 192 kHz frame rate operation, to handle 192 kHz sample
rate information. In this Mono Mode, two AES3 cables and two CS8406's are needed for stereo data trans-
fer. The CS8406 is set to Mono Mode by the MMT control bit.
In Mono Mode, the input port will run at the audio sample rate (Fs), while the AES3 transmitter frame rate
will be at Fs/2. Consecutive left or right channel serial audio data samples may be selected for transmission
on the A and B sub-frames, and the channel status block transmitted is also selectable.
Using Mono Mode is only necessary if the incoming audio sample rate is already at 192 kHz and contains
both left and right audio data words. The “Mono Mode” AES3 output stream may also be achieved by keep-
ing the CS8406 in normal stereo mode, and placing consecutive audio samples in the left and right positions
in an incoming 96 kHz word rate data stream. Figure 9 shows the C/U/V timing requirements.
5.3
Transmitted Frame and Channel Status Boundary Timing
The TCBL pin is used to indicate the start of transmitted channel status block boundaries and may be an
input or an output.
In some applications, it may be necessary to control the precise timing of the transmitted AES3 frame
boundaries. This may be achieved in two ways:
DS580F5
13
CS8406
a) With TCBL set to input, driving TCBL high for >3 OMCK clocks will cause a frame start, as well as a new
channel status block start.
b) If the serial audio input port is in Slave Mode and TCBL is set to output, the start of the A channel sub-
frame will be aligned with the leading edge of ILRCK.
The timing of TCBL, VLRCK, C, U, and V are illustrated in Figure 8 and Figure 9. VLRCK is the internal vir-
tual word clock signal, and is used here only to illustrate the timing of the C, U, and V bits. In Stereo Mode
VLRCK = AES3 frame rate and in Mono Mode VLRCK = 2 x AES3 frame rate. If the serial audio input port
is set to Slave Mode and TCBL is an output, VLRCK = ILRCK when SILRPOL = 0 and VLRCK = ILRCK
when SILRPOL = 1. If the serial audio input port is set to master mode and TCBL is an input,
VLRCK = ILRCK when SILRPOL = 0 and VLRCK = ILRCK when SILRPOL = 1.
Tth
TCBL
VLRCK
Tsetup
Thold
V/C/U
VCU[0]
VCU[1]
VCU[2]
VCU[3]
VCU[4]
Data [4]
Data [0]
Data [5]
Data [1]
Data [6]
Data [2]
Data [7]
Data [3]
Data [8]
Data [4]
SDIN
TXP(N)
Z
Y
X
Y
X
Note:
1.
T
T
≥ 15% AES3 frame rate
= 0
setup
2.
hold
3. T > 3 OMCKS if TCBL is an input
th
Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data, Stereo Mode
14
DS580F5
CS8406
TCBL
Tth
VLRCK
U
U[0]
U[2]
Data [4]
Data [5]
Data [6]
Data [7]
Data [8]
SDIN
Z
Data [0]*
Y
Y
Data [2]*
Data [3]*
X
X
Data [4]*
TXP(N)
* Assume MMTLR = 0
TXP(N)
Z
Data [1]*
Data [5]*
* Assume MMTLR = 1
Note:
1.
T
T
≥ 15% AES3 frame rate
= 0
setup
2.
hold
3. T > 3 OMCKS if TCBL is an input
th
Figure 9. AES3 Transmitter Timing for C, U, and V Pin Input Data, Mono Mode
DS580F5
15
CS8406
6. CONTROL PORT DESCRIPTION
The control port is used to access the registers, allowing the CS8406 to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to the audio
sample rates. However, to avoid potential interference problems, the control port pins should remain static if no op-
eration is required.
The control port has two modes: SPI and I²C, with the CS8406 acting as a slave device. SPI Mode is selected if
there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C Mode is selected
by connecting the AD0/CS pin through a resistor to VL or GND, thereby permanently selecting the desired AD0 bit
address state.
6.1
SPI Mode
In SPI Mode, CS is the CS8406 chip select signal, CCLK is the control port bit clock (input into the CS8406
from the microcontroller), CDIN is the input data line from the microcontroller, and CDOUT is the output data
line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 10 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first
seven bits on CDIN form the chip address and must be 0010000. The eighth bit is a read/write indicator
(R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is
set to the address of the register that is to be updated. The next eight bits are the data which will be placed
into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be
externally pulled high or low with a 47 kΩ resistor, if desired.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip address
and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed
register (CDOUT will leave the high impedance state). The MAP automatically increments so data for suc-
cessive registers will appear consecutively.
CS
C C L K
C H IP
C H IP
M A P
DATA
A D D R E S S
ADDRESS
0010000
0010000
LSB
MSB
b y te 1
R/W
R/W
C D IN
b y te n
High Impedance
LSB
LSB
MSB
MSB
C D O U T
MAP = Memory Address Pointer, 7 bits, MSB first
Figure 10. Control Port Timing in SPI Mode
16
DS580F5
CS8406
6.2
I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There
is no CS pin. Pins AD0, AD1, and AD2 form the three least significant bits of the chip address and should
be connected to VL or GND as desired.
The signal timing for both a read and write cycle are shown in Figure 11 and Figure 12. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the
clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS8406 after
a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The
upper 4 bits of the 7-bit address field are fixed at 0010. To communicate with a CS8406, the chip address
field, which is the first byte sent to the CS8406, should match 0010 followed by the settings of the AD2, AD1,
and AD0 pins. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read,
the contents of the register pointed to by the MAP will be output. The MAP automatically increments, so
consecutive registers can read from or written to easily. Each byte is separated by an acknowledge bit
(ACK). The ACK bit is output from the CS8406 after each input byte is read, and is input to the CS8406 from
the microcontroller after each transmitted byte.
26
27 28
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
24 25
SCL
DATA +1
DATA +n
CHIP ADDRESS (WRITE)
0 1 AD2 AD1 AD0 0
MAP
DATA
6
5
4
3
2
1
7
6
1
0
7
6
1
0
7
6
1
0
0
0
SDA
ACK
ACK
ACK
ACK
STOP
START
Figure 11. Control Port Timing, I²C Slave Mode Write
0
1
2
3
4
5
6
7
0
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28
SCL
SDA
STOP
CHIP ADDRESS (WRITE)
AD2 AD1 AD0
MAP
3
CHIP ADDRESS (READ)
AD2 AD1 AD0
DATA
DATA +1 DATA + n
0
0
1
0
0
0
1
0
1
7
0
7
0
7
0
6
5
4
2
1
0
ACK
ACK
START
ACK
ACK
NO
ACK
START
STOP
Figure 12. Control Port Timing, I²C Slave Mode Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 12, the write operation is aborted after the acknowledge for the MAP by sending a stop condition.
DS580F5
17
CS8406
7. CONTROL PORT REGISTER SUMMARY
Addr
Function
7
6
5
4
3
2
1
0
(HEX)
00 Reserved
01 Control 1
02 Control 2
0
0
0
0
0
0
VSET
0
TXOFF AESBP
RUN CLK1
SISF SIRES1
0
0
0
0
0
0
0
0
0
0
INT1
0
INT0
0
MUTEAES
TCBLD
0
0
MMT MMCST MMTLR
0
0
03 Data Flow Control
04 Clock Source Control
05 Serial Input Format
06 Reserved
07 Interrupt 1 Status
08 Interrupt 2 Status
09 Interrupt 1 Mask
0A Interrupt 1 Mode (MSB) TSLIP1
0B Interrupt 1 Mode (LSB) TSLIP0
0C Interrupt 2 Mask
0D Interrupt 2 Mode (MSB)
0E Interrupt 2 Mode (LSB)
0F-11 Reserved
0
0
0
0
CLK0
SIMS
0
TSLIP
0
SIRES0 SIJUST SIDEL SISPOL SILRPOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
UD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EFTU
0
EFTC
0
TSLIPM
EFTCM
EFTC1
EFTC0
0
0
0
0
CAM
0
0
0
0
0
0
0
0
0
0
EFTUM
EFTU1
EFTU0
0
0
0
0
0
BSEL
0
12 CS Data Buffer Control
13 U Data Buffer Control
1D-1F Reserved
EFTCI
0
EFTUI
0
UBM1 UBM0
0
0
0
0
20-37 C or U Data Buffer
7F ID and Version
ID3
ID2
ID1
ID0
VER3
VER2
VER1
VER0
Table 1. Control Register Map Summary
Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for
test modes, which can completely alter the normal operation of the CS8406.
18
DS580F5
CS8406
8. CONTROL PORT REGISTER BIT DEFINITIONS
8.1
Memory Address Pointer (MAP)
Not a register
7
6
5
4
3
2
1
0
0
MAP6
MAP5
MAP4
MAP3
MAP2
MAP1
MAP0
MAP[6:0] - Memory Address Pointer. Will automatically increment after each read or write.
8.2
Default = ‘000000’Control 1 (01h)
7
6
5
4
3
2
1
0
0
VSET
0
MUTEAES
0
INT1
INT0
TCBLD
VSET - Transmitted Validity bit level
Default = ‘0’
0 - Indicates data is valid, linear PCM audio data
1 - Indicates data is invalid or not linear PCM audio data
MUTEAES - Mute control for the AES transmitter output
Default = ‘0’
0 - Not Muted
1 - Muted
INT1:0 - Interrupt output pin (INT) control
Default = ‘00’
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier
Default = ‘0’
0 - TCBL is an input
1 - TCBL is an output
8.3
Control 2 (02h)
7
6
5
4
3
2
1
0
0
0
0
0
0
MMT
MMTCS
MMTLR
MMT - Select AES3 transmitter mono or stereo operation
Default = ‘0’
0 - Normal stereo operation
1 - Output either left or right channel inputs into consecutive subframe outputs (Mono Mode, left or right is
determined by MMTLR bit)
DS580F5
19
CS8406
MMTCS - Select A or B channel status data to transmit in Mono Mode
Default = ‘0’
0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe
1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the left channel CS
data. If MMTLR = 1, use the right channel CS data.
MMTLR - Channel Selection for AES Transmitter Mono Mode
Default = ‘0’
0 - Use left channel input data for consecutive subframe outputs
1- Use right channel input data for consecutive subframe outputs
8.4
Data Flow Control (03h)
7
6
5
4
3
2
1
0
0
TXOFF
AESBP
0
0
0
0
0
The Data Flow Control register configures the flow of audio data. The output data should be muted prior to
changing bits in this register to avoid transients.
TXOFF - AES3 Transmitter Output Driver Control
Default = ‘0
0 - AES3 transmitter output pin drivers normal operation
1 - AES3 transmitter output pin drivers drive to 0 V.
AESBP - AES3 bypass mode selection
Default = ‘0’
0 - Normal operation
1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL
threshold digital input.
8.5
Clock Source Control (04h)
7
6
5
4
3
2
1
0
0
RUN
CLK1
CLK0
0
0
0
0
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control reg-
ister, various Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8406 to be placed in a “powered down” low current con-
sumption, state.
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
control port registers are operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low.
1 - Normal part operation. This bit must be set to 1 to allow the CS8406 to begin operation.
All input clocks should be stable in frequency and phase when RUN is set to 1.
CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector. If these bits
are changed during normal operation, always stop the CS8406 first (RUN = 0), write the new value, then
start the CS8406 (RUN = 1).
20
DS580F5
CS8406
Default = ‘00’
00 - OMCK frequency is 256*Fs
01 - OMCK frequency is 384*Fs
10 - OMCK frequency is 512*Fs
11 - OMCK frequency is 128*Fs
8.6
Serial Audio Input Port Data Format (05h)
7
6
5
4
3
2
1
0
SIMS
SISF
SIRES1
SIRES0
SIJUST
SIDEL
SISPOL
SILRPOL
SIMS - Master/Slave Mode Selector
Default = ‘0’
0 - Serial audio input port is in Slave Mode
1 - Serial audio input port is in Master Mode
SISF - ISCLK frequency (for Master Mode)
Default = ‘0’
0 - 64*Fs
1 - 128*Fs
SIRES1:0 - Resolution of the input data, for right-justified formats
Default = ‘00’
00 - 24-bit resolution
01 - 20-bit resolution
10 - 16-bit resolution
11 - Reserved
SIJUST - Justification of SDIN data relative to ILRCK
Default = ‘0’
0 - Left-justified
1 - Right-justified
SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats
Default = ‘0’
0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (Left-Justified Mode)
1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge (I²S Mode)
SISPOL - ISCLK clock polarity
Default = ‘0’
0 - SDIN sampled on rising edges of ISCLK
1 - SDIN sampled on falling edges of ISCLK
SILRPOL - ILRCK clock polarity
Default = ‘0’
0 - SDIN data is for the left channel when ILRCK is high
1 - SDIN data is for the right channel when ILRCK is high
DS580F5
21
CS8406
8.7
Interrupt 1 Status (07h) (Read Only)
7
6
5
4
3
2
1
0
TSLIP
0
0
0
0
0
EFTC
0
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be ‘0’ in this register. This register defaults to 00h.
TSLIP - AES3 transmitter source data slip interrupt
In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit
will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit will go high
on receipt of a new TCBL signal.
EFTC - E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer in
the C bit buffer management process.
8.8
Interrupt 2 Status (08h) (Read Only)
7
6
5
4
3
2
1
0
0
0
0
0
0
EFTU
0
0
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be ‘0’ in this register. This register defaults to 00h.
EFTU - E to F U-buffer transfer interrupt. (Block Mode only) The source of this bit is true during the E to F
buffer transfer in the U bit buffer management process.
8.9
Interrupt 1 Mask (09h)
7
6
5
4
3
2
1
0
TSLIPM
0
0
0
0
0
EFTCM
0
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is un-
masked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0,
the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit
positions align with the corresponding bits in Interrupt 1 register. This register defaults to 00h.
22
DS580F5
CS8406
8.10 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)
7
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
0
TSLIP1
TSLIP0
EFTC1
EFTC0
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three
ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode,
the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT
pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin be-
comes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends
on the INT[1:0] bits. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.11 Interrupt 2 Mask (0Ch)
7
6
5
4
3
2
1
0
0
0
0
0
0
EFTUM
0
0
The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is un-
masked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0,
the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit
positions align with the corresponding bits in Interrupt 2 register. This register defaults to 00h.
8.12 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)
7
0
0
6
0
0
5
0
0
4
0
0
3
0
0
2
1
0
0
0
0
0
EFTU1
EFTU0
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three
ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode,
the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT
pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin be-
comes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends
on the INT[1:0] bits. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.13 Channel Status Data Buffer Control (12h)
7
6
5
4
3
2
1
0
0
0
BSEL
0
0
EFTCI
CAM
0
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
Default = ‘0’
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
DS580F5
23
CS8406
Note: There are separate complete buffers for the Channel Status and User bits. This control bit deter-
mines which buffer appears in the address space.
EFTCI - E to F C-data buffer transfer inhibit bit.
Default = ‘0’
0 - Allow C-data E to F buffer transfers
1 - Inhibit C-data E to F buffer transfers
CAM - C-data buffer control port access mode bit
Default = ‘0’
0 - One-Byte Mode
1 - Two-Byte Mode
8.14 User Data Buffer Control (13h)
7
6
5
4
3
2
1
0
0
0
0
UD
UBM1
UBM0
0
EFTUI
UD - User bit data source specifier
Default = ‘0’
0 - U Pin is the source of transmitted U data
1 - U data buffer is the source of transmitted U data
UBM1:0 - Sets the operating mode of the AES3 User bit manager
Default = ‘00’
00 - Transmit all zeros mode
01 - Block Mode
10 - Reserved
11 - Reserved
EFTUI - E to F U-data buffer transfer inhibit bit (valid in Block Mode only).
Default = ‘0’
0 - Allow U-data E to F buffer transfers
1 - Inhibit U-data E to F buffer transfers
8.15 Channel Status Bit or User Bit Data Buffer (20h - 37h)
Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to
Block Mode) is accessible through these register addresses.
8.16 CS8406 I.D. and Version Register (7Fh) (Read Only)
7
6
5
4
3
2
1
0
ID3
ID2
ID1
ID0
VER3
VER2
VER1
VER0
ID[3:0] - ID code for the CS8406. Permanently set to 1110
VER[3:0] = 0001 (revision A)
VER[3:0] = 0010 (revision B)
24
DS580F5
CS8406
9. PIN DESCRIPTION - SOFTWARE MODE
SDA / CDOUT
AD0 / CS
AD2
SCL / CCLK
AD1 / CDIN
TXP
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
3
RXP
TXN
4
TSTN
VD
H/S
5
VL
6
TEST
GND
7
TEST
OMCK
U
8
RST
9
TEST
INT
10
11
12
13
14
TEST
TEST
TEST
TEST
TCBL
ILRCK
ISCLK
SDIN
28 27 26 25 24 23 22
SDA / CDOUT
1
2
3
4
5
6
7
21
20
19
18
OMCK
U
AD0 / CS
AD2
INT
TEST
RXP
Thermal Pad
17 TEST
TEST
TSTN
VD
16
Top-Down (Through Package) View
28-Pin QFN Package
TEST
15 TCBL
8
9
10
12 13 14
11
DS580F5
25
CS8406
VD
6
Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V.
VL
23 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
22 Ground (Input) - Ground for I/O and core logic.
GND
Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset.
On initial power up, RST must be held low until the power supply is stable, and all input clocks are sta-
ble in frequency and phase. This is particularly true in Hardware Mode with multiple CS8406 devices,
where synchronization between devices is important.
RST
H/S
9
Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation
of the CS8406, and the method of accessing CS and U data. In Software Mode, device control and CS
and U data access is primarily through the control port, using a microcontroller. To select Software
Mode, this pin should be permanently tied to GND.
24
TXN
TXP
25 Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are pulled
26 low while the CS8406 is in the reset state.
OMCK
ISCLK
21 Master Clock (Input) - The frequency can be set through the control port registers.
13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN
pin.
ILRCK
SDIN
12
14 Serial Audio Data Port (Input) - Audio data serial input pin.
Serial Control Data I/O (I²C Mode) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control
SDA/CDOUT
SCL/CCLK
1
I/O data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is
the output data from the control port interface on the CS8406
Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and
out of the CS8406. In I²C Mode, SCL requires an external pull-up resistor to VL.
28
Address Bit 0 (I²C Mode) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the
CS8406 into SPI Control Port Mode. With no falling edge, the CS8406 defaults to I²C Mode. In I²C
Mode, AD0 is a chip address pin. In SPI Mode, CS is used to enable the control port interface on the
CS8406
AD0/CS
2
Address Bit 1 (I²C Mode) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address
pin. In SPI Mode, CDIN is the input data line for the control port interface.
AD1/CDIN
27
Address Bit 2 (I²C Mode) (Input) - Determines the AD2 address bit for the control port in I²C Mode,
and should be connected to GND or VL. If SPI Mode is used, the AD2 pin should be connected to either
GND or VL.
AD2
RXP
3
4
Auxiliary AES3 Receiver Port (Input) - Input for an alternate, already AES3 coded, audio data source.
Interrupt (Output) - Indicates key events during the operation of the CS8406. All bits affecting INT may
be unmasked through bits in the control registers. Indication of the condition(s) that initiated an interrupt
INT
19 are readable in the control registers. The polarity of the INT output, as well as selection of a standard or
open drain output, is set through a control register. Once set true, the INT pin goes false only after the
interrupt status registers have been read and the interrupt status bits have returned to zero.
Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
TCBL
15
the start of a channel status block.
User Data (Input) - May optionally be used to input User data for transmission by the AES3 transmitter,
20 see Figure 4 for timing information. If not driven, a 47 kΩ pull-down resistor is recommended for the U
pin. If the U pin is driven by a logic level output, a 100 Ω series resistor is recommended.
U
TSTN
5
Test In (Input) - This pin is an input used for test purposes. It must be tied to ground for normal operation.
26
DS580F5
CS8406
7
8
10 Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or
TEST
11 GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how-
16 ever current consumption from VL will increase by 25 μA per TEST pin that is left floating.
17
18
Thermal Pad (QFN package only) - Thermal relief pad for optimized heat dissipation. This pad must be
Thermal Pad
-
electrically connected to GND. See“Power Supply, Grounding, and PCB layout” on page 33 for more
information.
DS580F5
27
CS8406
10.HARDWARE MODE
The CS8406 has a Hardware Mode that allows the use of the device without a microcontroller. Hardware Mode is
selected by connecting the H/S pin to VL. The flexibility of the CS8406 is necessarily limited in Hardware Mode.
Various pins change function as described in the Hardware Mode pin description section.
The Hardware Mode data flow is shown in Figure 13. Audio data is input through the serial audio input port and rout-
ed to the AES3 transmitter.
10.1 Channel Status, User and Validity Data
The transmitted channel status, user and validity data can be input in two methods, determined by the state
of the CEN pin. Mode A is selected when the CEN pin is low. In Mode A, the user bit data and the validity
bit are input through the U and V pins, clocked by both edges of ILRCK. The channel status data is derived
from the state of the COPY/C, ORIG, EMPH, and AUDIO pins. Table 2 shows how the COPY/C and ORIG
pins map to channel status bits. In Consumer Mode, the transmitted category code is set to General (00h).
Mode B is selected when the CEN pin is high. In Mode B, the channel status, user data bits and the validity
bit are input serially through the COPY/C, U and V pins. Data is clocked into these pins at both edges of
ILRCK. Figure 9 shows the timing requirements.
VL
Output
Clock
Source
RST
H/S
OMCK
TCBLD
ILRCK
ISCLK
SDIN
TXP
TXN
TCBL
Serial
Audio
Input
AES3
Encoder
& Tx
CEN
U
C, U, V Data Buffer
V
APMS SFMT1 SFMT0
COPY/C
ORIG EMPH AUDIO
Power supply pins are omitted from this diagram.
Please refer to the Typical Connection Diagram for hook-up details.
Figure 13. Hardware Mode Data Flow
28
DS580F5
CS8406
The channel status block pin (TCBL) may be an input or an output, determined by the state of the TCBLD
pin.
Function
COPY/C
ORIG
0
0
1
1
0
1
0
1
PRO=0, COPY=0, L=0 copyright
PRO=0, COPY=0, L=1 copyright, pre-recorded
PRO=0, COPY=1, L=0 non-copyright
PRO=1
Table 2. Hardware Mode COPY/C and ORIG Pin Functions
10.2 Serial Audio Port
The serial audio input port data format is selected as shown in Table 3, and may be set to master or slave
by the state of the APMS input pin. The OMCK clock ratio is selected as shown in Table 4. Table 5 describes
the equivalent Software Mode, bit settings for each of the available formats. Timing diagrams are shown in
Figure 7.
SFMT1 SFMT0
Function
0
0
1
1
0
1
0
1
Serial Input Format IF1 - Left Justified
Serial Input Format IF2 - I²S
Serial Input Format IF3 - Right-Justified, 24-bit data
Serial Input Format IF4 - Right-Justified, 16-bit data
Table 3. Hardware Mode Serial Audio Port Format Selection
HWCK1 HWCK0
Function
0
0
1
1
0
1
0
1
OMCK Frequency is 256*Fs
OMCK Frequency is 128*Fs
OMCK Frequency is 512*Fs
OMCK Frequency is 256*Fs
Table 4. Hardware Mode OMCK Clock Ratio Selection
SISF SIRES1/0 SIJUST SIDEL SISPOL SILRPOL
IF1 - Left Justified
IF2 - I²S
IF3 - Right-Justified, 24-bit data
IF4 - Right-Justified, 16-bit data
0
0
0
0
00
00
00
10
0
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
Table 5. Equivalent Register Settings of Serial Audio Input Formats in Hardware Mode
DS580F5
29
CS8406
11.PIN DESCRIPTION - HARDWARE MODE
COPY / C
TEST
ORIG
HWCK1
TXP
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
EMPH
SFMT0
SFMT1
VD
3
TXN
4
H/S
5
VL
6
TEST
GND
OMCK
HWCK0
AUDIO
U
7
TEST
8
RST
9
APMS
TCBLD
ILRCK
ISCLK
SDIN
10
11
12
13
14
V
CEN
TCBL
28 27 26 25 24 23 22
COPY / C
1
2
3
4
5
6
7
21
20
19
18
OMCK
HWCK0
AUDIO
U
TEST
EMPH
SFMT0
SFMT1
VD
Thermal Pad
17 V
CEN
16
Top-Down (Through Package) View
28-Pin QFN Package
TEST
15 TCBL
8
9
10
12 13 14
11
30
DS580F5
CS8406
VD
6
Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V.
VL
23 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
22 Ground (Input) - Ground for I/O and core logic.
GND
Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset.
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase. This is particularly true in Hardware Mode with multiple CS8406 devices, where
synchronization between devices is important.
RST
H/S
9
Hardware/Software Control Mode Select (Input) - Determines the method of controlling the operation
of the CS8406, and the method of accessing CS and U data. Hardware Mode provides an alternate
mode of operation, and access to CS and U data is provided by dedicated pins. To select Hardware
Mode, this pin should be permanently tied to VL.
24
TXN
TXP
25 Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are pulled
26 low while the CS8406 is in the reset state.
OMCK
ISCLK
21 Master Clock (Input) - The frequency can be set through the HWCK[1:0] pins.
13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN
pin.
ILRCK
12
SDIN
14 Serial Audio Data Port (Input) - Audio data serial input pin.
SFMT0
SFMT1
4
5
Serial Audio Data Format Select (Input) - Selects the serial audio input port format. See Table 3 on
page 29.
Serial Audio Data Port Master/Slave Select (Input) - APMS should be connected to VL to set serial
audio input port as a master or connected to GND to set the port as a slave.
APMS
10
HWCK0
HWCK1
20 OMCK Clock Ratio Select (Input) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to
27 VL or pull-down to GND is required to set the appropriate mode. See Table 4 on page 29.
Transmit Channel Status Block Direction (Input) - Connect TCBLD to VL to set TCBL as an output.
Connect TCBLD to GND to set TCBL as an input.
TCBLD
11
Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
TCBL
15
the start of a channel status block.
C Bit Enable (Input) - Determines how the channel status data bits are input. When CEN is low, Hard-
ware Mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected
channel status data. When CEN is high, Hardware Mode B is selected, where the COPY/C pin is used
CEN
16
to enter serial channel status data.
Validity Bit (Input) - In Hardware Modes A and B, the V pin input determines the state of the validity bit
in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
V
U
17
User Data Bit (Input) - In Hardware Modes A and B, the U pin input determines the state of the user
data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
18
COPY Channel Status Bit/C Bit (Input) - In Hardware Mode A (CEN = 0), the COPY/C and ORIG pins
determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream,
see Table 2 on page 29. In Hardware Mode B, the COPY/C pin becomes the direct C bit input data pin,
COPY/C
1
which is sampled on both edges of LRCK.
Pre-Emphasis Indicator (Input) - In Hardware Mode A (CEN = 0), the EMPH pin low sets the 3 empha-
EMPH
AUDIO
ORIG
3
sis channel status bits to indicate 50/15 μs pre-emphasis of the transmitted audio data. If EMPH is high,
then the three EMPH channel status bits are set to 000, indicating no pre-emphasis.
Audio Channel Status Bit (Input) - In Hardware Mode A (CEN = 0), the AUDIO pin determines the
state of the audio/non audio Channel Status bit in the outgoing AES3 data stream.
19
ORIG Channel Status Bit Control (Input) - In Hardware Mode A (CEN = 0), the ORIG and COPY/C
28 pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data
stream, see Table 2 on page 29.
DS580F5
31
CS8406
2
7
8
Test Pins (Input) - These pins are unused inputs. It is recommended that these pins be tied to a supply
(VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left float-
ing, however current consumption from VL will increase by 25 μA per TEST pin that is left floating.
TEST
Thermal Pad (QFN package only) - Thermal relief pad for optimized heat dissipation. This pad must be
electrically connected to GND. See“Power Supply, Grounding, and PCB layout” on page 33 for more
information.
Thermal Pad
-
32
DS580F5
CS8406
12.APPLICATIONS
12.1 Reset, Power Down and Start-Up
When RST is low, the CS8406 enters a low power mode and all internal states are reset, including the con-
trol port and registers, and the outputs are disabled. In Software Mode when RST is high, the control port
becomes operational and the desired settings should be loaded into the control registers. Writing a 1 to the
RUN bit will then cause the part to leave the low power state and begin operation. In Hardware Mode when
RST is high, the part will automatically leave the low power state and begin operation.
12.2 ID Code and Revision Code
The CS8406 has a register that contains a four-bit code to indicate that the addressed device is a CS8406.
This is useful when other CS84XX family members are resident in the same or similar systems, allowing
common software modules.
The CS8406 four-bit revision level code is also available. This allows the software driver for the CS8406 to
identify which revision of the device is in a particular system, and modify its behavior accordingly. To allow
for future revisions, it is strongly recommended that the revision code is read into a variable area within the
microcontroller, and used wherever appropriate as revision details become known.
12.3 Power Supply, Grounding, and PCB layout
The CS8406 operates from a VD = +3.3 V or +5.0 V and VL = +3.3 V or +5.0 V supply. These supplied may
be set independently. Follow normal supply decoupling practices, see Figures 5 and 6. The VD and VL sup-
plies should be decoupled with a 0.1 μF capacitor to GND to minimize AES3 transmitter induced transients.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as
the CS8406 to minimize inductance effects, and all decoupling capacitors should be as close to the CS8406
as possible.
The CS8406 is available in the compact QFN package. The underside of the QFN package reveals a metal
pad; this pad must mate with an equally dimensioned copper pad on the PCB and must be electrically con-
nected to ground. A series of vias should be used to connect this copper pad to one or more ground planes
on other PCB layers.
12.4 Synchronization of Multiple CS8406s
The AES3 transmitters of multiple CS8406s can be synchronized if all devices share the same master clock,
TCBL, and RST signals. The TCBL pin is used to synchronize multiple CS8406 AES3 transmitters at the
channel status block boundaries. One CS8406 must have its TCBL set to master; the others must be set to
slave TCBL. Alternatively, TCBL can be derived from external logic, whereby all CS8406 devices should be
set to slave TCBL.
DS580F5
33
CS8406
13.PACKAGE DIMENSIONS
28L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
∝
L
SEATING
PLANE
A
e
A1
INCHES
NOM
0.098
0.008
0.017
0.011
0.705
0.295
0.050
0.407
0.026
4°
MILLIMETERS
NOM
2.50
DIM
A
MIN
0.093
0.004
0.013
0.009
0.697
0.291
0.040
0.394
0.016
0°
MAX
0.104
0.012
0.020
0.013
0.713
0.299
0.060
0.419
0.050
8°
MIN
2.35
0.10
0.33
0.23
17.70
7.40
1.02
10.00
0.40
0°
MAX
2.65
0.30
0.51
0.32
18.10
7.60
1.52
10.65
1.27
8°
A1
b
0.20
0.42
C
0.28
D
17.90
7.50
E
e
1.27
H
10.34
0.65
L
µ
4°
JEDEC #: MS-013
Controlling Dimension is Millimeters
34
DS580F5
CS8406
28L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
A
E
∝
A1
b2
e
L
END VIEW
SEATING
PLANE
SIDE VIEW
1
2
3
TOP VIEW
INCHES
MILLIMETERS
NOTE
DIM
A
MIN
NOM
--
MAX
0.47
MIN
--
NOM
--
MAX
1.20
0.15
1.00
0.30
9.80 BSC
6.50
4.50
--
--
0.002
0.03150
0.00748
0.378 BSC
0.248
0.169
--
A1
A2
b
0.004
0.006
0.04
0.05
0.80
0.19
0.10
0.035
0.90
0.0096
0.382 BSC
0.2519
0.1732
0.026 BSC
0.024
0.012
0.386 BSC
0.256
0.177
--
0.245
9.70 BSC
6.40
2,3
1
D
9.60 BSC
6.30
4.30
--
E
E1
e
4.40
1
0.65 BSC
0.60
L
0.020
0°
0.029
8°
0.50
0°
0.75
8°
µ
4°
4°
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes:
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re-
duce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS580F5
35
CS8406
28L QFN (4.00 mm BODY) PACKAGE DRAWING
D
b
e
PIN #1
1.00 REF
CORNER
PIN #1 IDENTIFIER
LASER MARKING
E
E2
A1
A
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
INCHES
MILLIMETERS
NOTE
DIM
A
A1
b
e
D
D2
E
E2
L
MIN
0.031496
NOM
MAX
MIN
0.800
0.000
0.150
--
3.900
2.500
3.900
2.500
0.300
NOM
0.900
0.020
0.200
0.400
4.000
2.600
4.000
2.600
0.400
MAX
1.000
0.050
0.250
--
4.100
2.700
4.100
2.700
0.500
0.035433
0.000787
0.007874
0.015748
0.15748
0.102362
0.15748
0.102362
0.015748
0.03937
0.001969
0.009843
--
0.161417
0.106299
0.161417
0.106299
0.019685
0.000
0.005906
--
0.153543
0.098425
0.153543
0.098425
0.011811
1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
Note:
1. Dimensioning lead width applies to the metallized terminal and is measured between 0.15 mm and
0.25 mm from the terminal tip.
36
DS580F5
CS8406
14.ORDERING INFORMATION
Product
Description
Pb-Free Package
Grade
Temp Range Container
Order#
CS8406-CSZ
Rail
Commercial -10º to +70ºC
Automotive -40º to +85ºC
Commercial -10º to +70ºC
Automotive -40º to +85ºC
Commercial -10º to +70ºC
Automotive -40º to +85ºC
Tape and Reel CS8406-CSZR
SOIC
Rail
Tape and Reel CS8406-DSZR
Rail CS8406-CZZ
Tape and Reel CS8406-CZZR
Rail CS8406-DZZ
Tape and Reel CS8406-DZZR
Rail CS8406-CNZ
Tape and Reel CS8406-CNZR
Rail CS8406-DNZ
Tape and Reel CS8406-DNZR
CS8406-DSZ
192 kHz Digital Audio
Transmitter
CS8406
YES
TSSOP
QFN
-
CS8406 & CS8416 Evaluation
Board
CDB8416
-
-
-
CDB8416
DS580F5
37
CS8406
15.APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER
COMPONENTS
This section details the external components required to interface the AES3 transmitter to cables and fiber-optic
components.
15.1 AES3 Transmitter External Components
The output drivers on the CS8406 are designed to drive both the professional and consumer interfaces. The
AES3 and IEC60958-4 specifications call for a balanced output drive of 2-7 V peak-to-peak into a 110 Ω ±
20% load with no cable attached. Using the circuit in Figure 14, the output of the transformer is short-circuit
protected, has the proper source impedance, and provides a 5 V peak-to-peak signal into a 110 Ω load.
Lastly, the two output pins should be attached to an XLR connector with male pins and a female shell, and
with pin 1 of the connector grounded.
In the case of consumer use, the IEC60958-3 specification calls for an unbalanced drive circuit with an out-
put impedance of 75 Ω ± 20% and a output drive level of 0.5 V peak-to-peak ± 20% when measured across
a 75 Ω load using no cable. The circuit shown in Figure 15 only uses the TXP pin and provides the proper
output impedance and drive level using standard 1% resistors. If VL is set to +3.3 V, change 374 Ω to 243 Ω
and change 90.9 Ω to 107 Ω. The connector for a consumer application would be an RCA phono socket.
This circuit is also short circuit protected.
The TXP pin may be used to drive TTL or CMOS gates as shown in Figure 16. This circuit may be used for
optical connectors for digital audio since they usually have TTL or CMOS compatible inputs. This circuit is
also useful when driving multiple digital audio outputs since RS422 line drivers have TTL compatible inputs.
15.2 Isolating Transformer Requirements
Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources on
transformer selection.
CS8406
TXP
CS8406
TXP
110-(RTXP+RTXN
)
374-RTXP
RCA
Phono
XLR
90.9 Ω
TXN
TXN
Pin 1
Figure 14. Professional Output Circuit
Figure 15. Consumer Output Circuit (VL = 5.0 V)
CS8406
TXP
TTL or
CMOS Gate
TXN
Figure 16. TTL/CMOS Output Circuit
38
DS580F5
CS8406
16.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER
MANAGEMENT
The CS8406 has a comprehensive channel status (C) and user (U) data buffering scheme which allows the user to
manage the C and U data through the control port.
16.1 AES3 Channel Status(C) Bit Management
The CS8406 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384
bits), and also 384 bits of U information. The user may read from or write to these RAM buffers through the
control port.
The CS8406 manages the flow of channel status data at the block level, meaning that entire blocks of chan-
nel status information are buffered at the input, synchronized to the output timebase, and then transmitted.
The buffering scheme involves a cascade of 2 block-sized buffers, named E and F, as shown in Figure 17.
The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0
(which is at control port address 20h) is the consumer/professional bit for channel status block A.
The E buffer is accessible from the control port, allowing read and writing of the C data. The F buffer is used
as the source of C data for the AES3 transmitter. The F buffer accepts block transfers from the E buffer.
A
B
8-bits
8-bits
To
AES3
E
F
Transmitter
24
words
Transmit
Data
Buffer
Control Port
Figure 17. Channel Status Data Buffer Structure
16.1.1 Accessing the E buffer
The user can monitor the data being transferred by reading the E buffer, which is mapped into the register
space of the CS8406, through the control port. The user can modify the data to be transmitted by writing
to the E buffer.
The user can configure the interrupt enable register to cause interrupts to occur whenever “E to F” buffer
transfers occur. This allows determination of the allowable time periods to interact with the E buffer.
Also provided is an “E to F” inhibit bit. The “E to F” buffer transfer is disabled whenever the user sets this
bit. This may be used whenever “long” control port interactions are occurring.
A flowchart for reading and writing to the E buffer is shown in Figure 18. For writing, the sequence starts
after a E to F transfer, which is based on the output timebase.
If the channel status block to transmit indicates PRO Mode, then the CRCC byte is automatically calcu-
lated by the CS8406, and does not have to be written into the last byte of the block by the host microcon-
DS580F5
39
CS8406
troller. This is also true if the channel status data is entered serially through the COPY/C pin when the part
is in Hardware Mode.
E to F interrupt occurs
Optionally set E to F inhibit
Write E data
If set, clear E to F inhibit
Wait for E to F transfer
Return
Figure 18. Flowchart for Writing the E Buffer
16.1.2 Serial Copy Management System (SCMS)
In Software Mode, the CS8406 allows read/modify/write access to all the channel status bits. For Con-
sumer Mode SCMS compliance, the host microcontroller needs to manipulate the Category Code, Copy
bit and L bit appropriately.
In Hardware Mode, the SCMS protocol can be followed by either using the COPY and ORIG input pins,
or by using the C bit serial input pin. These options are documented in the Hardware Mode section of this
data sheet.
16.1.3 Channel Status Data E Buffer Access
The E buffer is organized as 24 x 16-bit words. For each word the MS Byte is the A channel data, and the
LS Byte is the B channel data (see Figure 17).
There are two methods of accessing this memory, known as One-Byte Mode and Two-Byte Mode. The
desired mode is selected through a control register bit.
16.1.3.1 One-Byte Mode
In many applications, the channel status blocks for the A and B channels will be identical. In this situation,
if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel will
be the same. Similarly, if the user wrote a byte to one channel's block, it would be necessary to write the
same byte to the other block. One-Byte Mode takes advantage of the often identical nature of A and B chan-
nel status data.
When reading data in One-Byte Mode, a single byte is returned, which can be from channel A or B data,
depending on a register control bit. If a write is being done, the CS8406 expects a single byte to be input
to its control port. This byte will be written to both the A and B locations in the addressed word.
One-Byte Mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth
of information in 1 byte's worth of access time. If the control port's auto increment addressing is used in
combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially
efficiently.
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CS8406
16.1.3.2 Two-Byte Mode
There are those applications in which the A and B channel status blocks will not be the same, and the user
is interested in accessing both blocks. In these situations, Two-Byte Mode should be used to access the E
buffer.
In this mode, a read will cause the CS8406 to output two bytes from its control port. The first byte out will
represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is
similar, in that two bytes must now be input to the CS8406's control port. The A channel status data is first;
B channel status data second.
16.2 AES3 User (U) Bit Management
The CS8406 U bit manager has two operating modes:
Mode 1. Transmit all zeros.
Mode 2. Block mode.
16.2.1 Mode 1: Transmit All Zeros
Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents. This
mode is intended for the user who wants the output U channel to contain no data.
16.2.2 Mode 2: Block Mode
Mode 2 is very similar to the scheme used to control the C bits. Entire blocks of U data are buffered using
2 block-sized RAMs to perform the buffering. The user has access to the first buffer, denoted the E buffer,
through the control port. It is the only mode in which the user can merge his own U data into the transmit-
ted AES3 data stream. The U buffer access only operates in Two-Byte Mode, since there is no concept
of A and B blocks for user data. The arrangement of the data is as followings: Bit15[A7] Bit14[B7]
Bit13[A6] Bit12 [B6]...Bit1 [A0] Bit0[B0]. The arrangement of the data in the each byte is that the MSB is
the first transmitted bit. The bit for the A subframe is followed by the bit for the B subframe.
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CS8406
17.REVISION HISTORY
Release
Date
Changes
- Updated Packaging Information to include Lead Free devices and updated “Table of
Contents” on page 2.
F3
July 2005
- Removed references to “Autoincrement” feature in “Control Port Description” on
page 16. Indicated that the MAP will always increment.
- Corrected definition of pin 5 in “Pin Description - Software Mode” on page 25.
F4
F5
April 2006
- Added QFN package option to “General Description” on page 1, “Package Dimen-
sions” on page 34, and “Ordering Information” on page 37.
- Added QFN pin-out drawing and thermal pad description to “Pin Description - Software
Mode” on page 25 and “Pin Description - Hardware Mode” on page 30.
- Added QFN thermal pad guidelines to “Power Supply, Grounding, and PCB layout” on
page 33.
October 2009
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com
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