TMC22071A [CADEKA]
Genlocking Video Digitizer; 同步锁相视频数字化
| 型号： | TMC22071A |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Genlocking Video Digitizer |
| 文件： | 总24页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.cadeka.com
TMC2 2 0 7 1 A
Ge n lo c k in g Vid e o Dig it ize r
Features
Description
• Fully integrated acquisition
• 3-channel video input multiplexer
• Two-stage video clamp
• Automatic gain adjustment
• Sync detection and separation
• Pixel and subpixel adjustment of HSYNC-to-Video
timing
• Genlock to NTSC or PAL inputs
• Clock generation
• 8-bit video A/D converter
The TMC22071A Genlocking Video Digitizer converts stan-
dard baseband composite NTSC or PAL video into 8-bit dig-
ital composite video data. It extracts horizontal and vertical
sync signals and generates a pixel clock for the on-board
8-bit A/D converter and a 2x clock for the transfer of data to
subsequent video processing decoding or encoding with the
TMC22x5y Video Decoder or TMC22x9x Digital Video
Encoder family. It also measures the color subcarrier phase
and frequency and provides this data to the Encoder (for gen-
locked color NTSC or PAL encoding), or a frame buffer (for
frame capture) over the digital composite video port.
• Microprocessor interface
• Line-locked pixel rates
- 12.27 MHz NTSC
- 13.5 MHz NTSC or PAL
• Direct interface to TMC22x9x encoders
• Built-in circuitry for crystal oscillator
• No tuning or external voltage reference required
• 68 Lead PLCC or 100 Lead MQFP package
The TMC22071A includes a three-channel video input mul-
tiplexer, analog clamp, variable gain amplifier, and digital
back porch clamp. The on-board oscillator circuitry gener-
ates the clock from a 20 MHz crystal or the clock source may
be an external oscillator. It is programmable over a micro-
processor interface for NTSC or PAL operation. No external
component changes and no production tuning or service
adjustments are ever required.
Applications
• Frame grabber
• Digital VCR/VTR
• Desktop video
The TMC22071A is fabricated in an advanced CMOS
process, and is packaged in a 68 Lead PLCC or 100 Lead
MQFP. Its performance is guaranteed from 0°C to 70°C.
Block Diagram
BACK PORCH
CLAMP
DATA
SELECTOR
CVBS
7-0
V
V
V
IN1
IN2
IN3
ANALOG
CLAMP
SUBCARRIER
PHASE-LOCKED
LOOP
GAIN
A/D
LOWPASS
FILTER
D/A
D/A
GVSYNC
GHSYNC
SYNC
SEPARATOR
PXCK
LDV
VALID
DIRECT
DIGITAL
SYNTHESIZER
HORIZONTAL
PHASE-LOCKED
LOOP
CONTROL
+1.2V
65-22071-01
MICROPROCESSOR
INTERFACE
ANALOG INTERFACE
DDS/PIXEL CLOCK INTERFACE
Rev. 1.0.5
TMC22071A
PRODUCT SPECIFICATION
amplitudes during initial genlock acquisition, and then
(optionally) holds the gain constant. This results in a stable
picture under variable signal conditions.
Functional Description
The TMC22071A is a fully-integrated genlocking video A/D
converter which digitizes NTSC or PAL baseband composite
video under program control. It accepts video on three
selectable input channels, adjusts gain, clamps to the back
porch, and digitizes the video at a multiple of the horizontal
line frequency. It extracts horizontal and vertical sync, mea-
sures the subcarrier frequency and phase (relative to the sam-
pling clock), and provides the data along with digital
composite video data over an 8-bit digital video port. Two
sync outputs (GHSYNC and GVSYNC) are also provided. It
generates 1x (LDV) and 2x (PXCK) pixel clocks for data
transfer. PXCK also serves as a master clock for the compan-
ion TMC22x9x Encoders and TMC22x5y decoders.
Improperly terminated or weak video signals are handled in
the TMC22071A by a selectable gain of +1.0 or +1.5. The
higher gain can amplify a doubly-terminated signal which is
reduced in amplitude by 2/3.
If the input signal levels are well controlled, the automatic
gain adjustment can be disabled and the gain held at its nom-
inal value (unity or 1.5X).
Analog-to-Digital Converter
The TMC22071A contains a high-performance 8-bit A/D
converter. Its gain and offset are automatically set as a part of
the automatic gain adjustment process during initial signal
acquisition, and require no user attention.
Operating parameters are set up via a serial microprocessor
port. Internal or external voltage reference operation is avail-
able
The reference voltages to the A/D converter are set up by
internal D/A converters under automatic control during gen-
lock acquisition. These voltages determine the gain and off-
set of the A/D converter with respect to the video level
presented at its input.
Timing
The TMC22071A operates from an internally-synthesized
clock, PXCK, which runs at twice the pixel data rate. The
nominal pixel rates may be set to 12.27 Mpps for NTSC and
13.5 Mpps for NTSC and PAL. Customers requiring 14.75 or
15 Mpps PAL operation should consult factory.
Low-Pass Filter
The digitized composite video stream is digitally low-pass
filtered to remove chrominance components from the sync
separator. Filtering provides robust operation by optimizing
the signal-to-noise ratio of the synchronizing/blanking por-
tion of the video, improving the accuracy of the back porch
blanking level detector.
Video Input
Three high-impedance video inputs are selected by an inter-
nal multiplexer under host processor control. The device
accepts industry-standard video levels of 1.23 Volts (sync tip
to peak color = 1 volt sync tip to reference white). Good
channel-to-channel isolation allows active video on all three
inputs simultaneously. Antialiasing filtering (if used) and
line termination resistors must be provided externally. The
input selection is controlled by two bits in the Control Regis-
ter.
A digital sync separator provides the output sync signals,
GHSYNC and GVSYNC, and times internal operations.
Horizontal Phase-Locked Loop
A phase-locked loop generates PXCK, at twice the pixel
rate. The reference signal for the horizontal phase-locked
loop is generated by the Direct Digital Synthesizer (DDS).
The DDS output is constructed with an internal D/A con-
verter and is output from the TMC22071A via the DDS OUT
pin. This signal is passed through an external LC filter and
input to the horizontal phase-comparator.
Analog Clamp
The front-end analog clamp ensures that the input video falls
within the active range of the A/D converter. The digitized
composite video output can be clamped to the back porch by
a secondary digital clamp.
Automatic Gain Adjustment
Since video signals may vary substantially from nominal lev-
els, the TMC22071A performs an automatic level setting
routine to establish correct signal amplitudes for digitizing.
The frequency of the DDS output is one ninth of that of
PXCK.
A 20 MHz clock is required to drive the DDS. Preferably,
this may be input to the TMC22071A via CMOS levels on
the CLK IN pin. Alternately, a 20 MHz crystal may be
directly connected between CLK IN and CLK OUT with
tuning capacitors to activate the internal crystal oscillator cir-
cuitry.
The TMC22071A relies upon the presence of the sync
tip-to-back porch voltage to determine the gain required for
the input video signal.
Sync tip compression or clipping is often affected by APL
(Average Picture Level) variation. Rather than tracking
minor variations in sync tip amplitude and constantly adjust-
ing video gain, the TMC22071A establishes proper signal
If incoming video is lost or disconnected after the
TMC22071A has acquired and locked, PXCK, GHSYNC,
2
PRODUCT SPECIFICATION
TMC22071A
GVSYNC and GRS data will continue. The GRS data will
be the initial subcarrier frequency and phase values selected
by the Format select bits of the Control Register. The
TMC22071A will acquire and lock to incoming video within
two frames after video is restored.
Subcarrier frequency, subcarrier phase, and Field ID data
(GRS) are transmitted in 4-bit nibbles over CVBS during
3-0
the horizontal sync tip period at the PXCK rate.
Microprocessor Interface
Since microprocessor buses are notoriously noisy from a
wide-band analog point of view, the microprocessor inter-
face bus is only one bit wide, rather than the more customary
eight. The operation of this bus is similar to other bus-
controlled devices except that the TMC22071A internal
Control Register is accessed one bit at a time.
Subcarrier Phase-Locked Loop
A fully-digital phase-locked loop is used to extract the phase
and frequency of the incoming color burst. These frequency
and phase values are output over the CVBS bus during the
horizontal sync period. Fairchild’s video decoder and gen-
lockable encoder chips will accept these data directly.
A sequence of 47 bits is written to or read from the LSB of a
standard microprocessor port. Writing to or reading from the
secondary address results in the transfer of data to or from
the internal shift register.
Back Porch Digital Clamp
A digital back-porch clamp is employed to ensure a constant
blanking level. It digitally offsets the data from the A/D con-
verter to set the back porch level to precisely 3C for NTSC
and 40 for PAL. When the digital clamp is enabled, the
h
CVBS video output data is determined from the A/D conver-
h
The RESET input, when LOW, sets all internal state
machines to their initialized conditions. Returning the
RESET pin HIGH starts the signal acquisition sequence
which lasts until locking with the gain-adjusted and clamped
video signal is achieved.
sion result minus the back porch level + 3C (40 for PAL).
h
h
Digitized Video Output
The digitized 8-bit video output is provided over an 8-bit
wide CVBS data port, synchronous with PXCK and LDV.
Pin Assignments
1 68
Pin Name
Pin Name
18
19 PXCK
Pin Name
Pin Name
52
1
2
3
4
5
6
7
8
9
V
V
DD
35
36
37
38
39
40
41
42
A
V
DD
DD
GND
CVBS
CVBS
CVBS
CVBS
CVBS
R
T
53 CLK OUT
54 EXT PXCK
0
1
2
3
4
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
D
A
GND
GND
D
GND
V
REF
55
56
57
58
59
60
D
GND
V
DD
A
GND
D
GND
V
DDA
V
DDA
D
GND
V
DD
A
GND
A
GND
V
DD
D
GND
V
DDA
C
BYP
V
DD
CVBS
V
DDA
43 PFD IN
44
45 DDS OUT 62 CS
46 PXCK SEL 63
47 64 RESET
48 COMP
A
0
5
6
7
10 CVBS
11 CVBS
A
GND
A
GND
61 R/W
R
B
12 GHSYNC
13 GVSYNC
14 VALID
V
IN3
V
DD
V
DDA
V
DDA
V
IN2
65
66
D
GND
15
16
D
A
GND
49
50
A
D
0
GND
GND
65-22071-02
D
GND
V
DDA
D
GND
67 INT
68
17 LDV
V
IN1
51 CLK IN
D
GND
3
TMC22071A
PRODUCT SPECIFICATION
Pin Assignments (continued)
Pin Name
Pin Name
Pin Name
Pin Name
76 NC
80
51
1
2
3
4
5
6
7
8
9
A
26
27
V
51
52
V
DDA
0
DD
NC
NC
R/W
CS
D
GND
V
DDA
77 PFD IN
78 NC
50
81
28 CVBS
29 CVBS
30 CVBS
31 NC
53 NC
54 NC
5
6
7
79 NC
55
A
GND
80 NC
V
DD
56 NC
81
A
GND
RESET
32 GHSYNC
33 GVSYNC
34 VALID
35 NC
57
58
R
82 DDS OUT
83 NC
B
D
GND
V
IN3
D
0
59 NC
84 NC
10 NC
11 NC
12 NC
13 NC
14 NC
15 NC
60
61
V
85 NC
DDA
31
100
36 NC
V
IN2
86 PXCK SEL
37 NC
62 NC
87
V
DDA
1
30
38
39
D
63
64
65
A
GND
88 COMP
GND
D
GND
V
DDA
89
90
A
GND
40 LDV
V
IN1
D
GND
16*
17 INT
18
D
41*
42*
D
66 NC
91 CLK IN
92
GND
GND
Notes:
1. NC = Do Not Connect.
V
DD
67
68
69
70
A
V
DD
GND
V
DD
43 NC
44
45 PXCK
R
T
93 CLK OUT
94 EXT PXCK
*
These pins are not connected in the
19 NC
V
DD
A
GND
TMC22071A. However, you should
connect these pins as shown for
compatibility with future genlock ICs.
20 NC
V
REF
95
96
97
98
D
GND
21 CVBS
22 CVBS
23 CVBS
24 CVBS
25 CVBS
46
47
48
49
50
D
GND
71 NC
D
GND
0
1
2
3
4
D
GND
72
73
74
75
A
D
GND
GND
V
DD
V
DDA
V
DD
V
DDA
A
GND
99 NC
100
A
GND
C
BYP
V
DD
65-22071-02B
Pin Definitions
Pin Number
68 pin 100 pin
Pin Name PLCC MQFP Pin Type
Video Input
Function
V
IN1-3
34, 31, 65, 61, 1.23Vp-p Composite Video Input. Video inputs,1.25 Volts peak-to-peak, sync
29
58
tip to peak color
Clocks
CLK IN
51
91
CMOS
CMOS
20 MHz DDS clock input. 20 MHz CMOS clock input to DDS. This
pin may also be used along with CLK OUT for directly connecting
crystals.
CLK OUT
53
93
Inverted clock output. Inverted DDS clock output. This pin may also
be used along with CLK IN for directly connecting a crystal.
PXCK
LDV
19
17
45
40
CMOS
CMOS
2x Pixel clock output. 2x oversampled line-locked clock output.
Pixel clock output. Delayed pixel clock output. LDV runs at 1/2 the
rate of PXCK and its rising edge is useful for transferring CVBS
digital video from the TMC22071A to the TMC22x9x Digital Video
Encoders.
EXT PXCK
PXCK SEL
54
46
94
86
CMOS
CMOS
External PXCK input. Input for external PXCK clock source.
PXCK source select. Select input for internal or external PXCK.
When HIGH, the internally generated line-locked PXCK is selected.
When LOW, the external PXCK source is enabled.
4
TMC22071A
PRODUCT SPECIFICATION
Pin Definitions (continued)
Pin Number
68 pin 100 pin
Pin Name PLCC
MQFP Pin Type
Function
Digital Video
GHSYNC
GVSYNC
12
13
32
33
CMOS
Horizontal sync output. When the TMC22071A is locked to
incoming video, the GHSYNC pin provides a negative-going pulse
after the falling edge of the horizontal sync pulse. There is a fixed
number of PXCK clock cycles between adjacent falling edges of
GHSYNC, except following a VCR headswitch.
CMOS
CMOS
Vertical sync output. When the TMC22071A is locked to incoming
video, the GVSYNC pin provides a negative-going edge after the
start of the first vertical sync pulse of a vertical blanking interval.
CVBS
7-0
11-9, 6- 30-28,
Composite output bus. 8-bit composite video data is output on this
bus at 1/2 the PXCK rate. During horizontal sync, field ID, subcarrier
frequency, and subcarrier phase are available on this bus.
2
25-21
mP l/O
D
66
60
9
1
TTL
TTL
Data l/O port. Microprocessor data port. All control parameters are
loaded into and read back from the Control Register over this 1-bit
bus.
0
A
0
mP port control. Microprocessor address bus. A LOW on this input
loads the l/O Port Shift Register with data from D and CS. A HIGH
0
transfers the l/O Port Shift Register contents into the Control Register
on the last falling edge of CS.
CS
62
64
5
7
TTL
TTL
Chip select. When CS is HIGH, D is in a high-impedance state and
0
ignored. When CS is LOW, the microprocessor can read or write D
data into the Control Register.
0
RESET
Master reset input. Bringing RESET LOW forces the internal state
machines to their starting states, loads the Control Register with
default values, and disables outputs. Bringing RESET HIGH restarts
the TMC22071A in its default mode.
R/W
61
4
TTL
Bus read/write control. When R/W and A are LOW, the
0
microprocessor can write to the Control Register over D . When R/W
0
is HIGH and A is LOW, the contents of the Status Register are read
0
over D .
0
INT
67
14
17
34
TTL
TTL
Interrupt output. This output is LOW if the internal horizontal phase
lock loop is unlocked with respect to incoming video for 128 or more
lines per field. After lock is established, INT goes HIGH.
VALID
HSYNC locked flag. This output, when HIGH indicates that
incoming horizontal sync has been detected within the ±16 pixel
window in time established by previous sync pulses. When LOW, it
indicates that incoming horizontal sync has not been found within the
expected time frame. VALID will toggle if the time stability of
incoming video is such that sync positioning varies more than
±16 pixels or if occasional horizontal sync pulses are missing.
5
PRODUCT SPECIFICATION
TMC22071A
Pin Definitions (continued)
Pin Number
68 pin 100 pin
Pin Name PLCC
MQFP Pin Type
Function
Analog Interface
V
REF
38
70
+1.23 V
V
input/output. +1.23 Volt reference. When the internal voltage
REF
reference is used, this pin should be decoupled to A
with a 0.1
GND
mF capacitor. An external +1.2 Volt reference may be connected
here, overriding the internal reference source.
COMP
48
88
68
0.1 mF
0.1 mF
Compensation capacitor. Compensation for DDS D/A converter
circuitry. This pin should be decoupled to V
capacitor.
with a 0.1 mF
DDA
R ,R
36, 28
A/D V decoupling. Decoupling points for A/D converter voltage
REF
T
B
references. These pins should be decoupled to A
capacitor.
with a 0.1 mF
GND
PLL Filter
DDS OUT
45
43
42
82
77
75
Internal DDS output. Analog output from the internal Direct Digital
Synthesizer D/A converter, at 1/9 the PXCK frequency.
PFD IN
Horizontal PLL input. Analog input to the Phase/Frequency
Detector of the horizontal phase-locked loop.
C
BYP
1 mF
Comparator bypass. Decoupling point for the internal comparator
reference of the Phase/Frequency Detector. This pin should be
decoupled to A
GND
with a 0.1 mF capacitor.
Power Supply
V
23, 25, 49, 51,
26, 30, 52, 60,
33, 40, 64, 73,
+5 V
+5 V
Analog power supply. Positive power supply to analog section.
Digital power supply. Positive power supply to digital section.
DDA
47
87
V
1, 7,18, 6, 18,
22, 52, 26, 42,
58,59,63 44, 48,
92, 98,
DD
100
Ground
A
24, 27, 50, 55,
32, 35, 63, 67,
37, 39, 69, 72,
41, 44, 74, 81,
0.0 V
0.0 V
Analog ground. Ground for analog section.
Digital ground. Ground for digital section.
GND
49,
89
D
8, 15,
8, 16,
GND
16, 20, 27, 38,
21, 50, 39, 41,
55-57, 46, 47,
65, 68 90, 95-
97
6
PRODUCT SPECIFICATION
TMC22071A
Table 1. Microprocessor Port Control
Control and Status Registers
A
R/W
Action
0
The TMC22071A is controlled by a single 47-bit long Con-
trol Register. Access to the Control Register is via the I/O
Port Shift Register arranged as shown in Figure 1. The Con-
trol Register can be written, with the desired programming.
The 12-bit Status Register is read-only and accessed through
the same l/O Port Shift Register. Reading the Status Register
yields information about blanking level, subcarrier presence,
and whether or not PXCK is locked or unlocked with respect
to the line rate.
0
0
Write data from D into l/O Port Shift
0
Register
0
1
1
1
0
1
Read D data from last stage of l/O
0
Port Shift Register
Transfer l/O Port Shift Register
contents to Control Register
Enables continuous update of status
bits in l/O Port Shift Register
The full sequence of 47 bits of Control Register data must be
written each time a change in that data is desired. All or a
few of the Control and Status Register bits may be read,
but the sequence always begins with bit 58 of the Status
Register.
I/O Port Shift Register
D
0
0
46
47 58
Status
Register
Control Register
CS
65-22071-03
Figure 1. Control and Shift Register Structure
R/W
The host processor writes data into the TMC22071A using
only one bit of the microprocessor’s data and address bus. As
shown in Figure 2, the user should bring A high for the CS
0
D
A
46
45
1
0
0
t
H
falling edge preceding the introduction of bit 0 to the D
0
0
port. The next rising edge of CS completes the preloading of
the control data, which transfer into the control register on
the next rising edge of the pixel clock. The I/O Port Shift
Register, Control Register and Status Register are governed
65-22071-04
t
S
Figure 2. Data Write Sequence
by CS, R/W, and A . R/W and A are latched by the
0
0
TMC22071A on the falling edge of CS and data input D is
0
CS
R/W
D
latched on the rising edge of CS. Data read from D is
0
enabled by the falling edge of CS and disabled by the rising
edge of CS. When the Control Register is read more than
once consecutively, an extra CS pulse and accompanying A
is needed to align the circulated shift register data.
0
58
57
1
0
0
A
0
65-22071A-05
Figure 3. Data Read Sequence
7
TMC22071A
PRODUCT SPECIFICATION
0
7
8
15 16
23
0
0
0
0
0
24
31 32
39 40
0
46
0
0
0
1
0
0
0
0
0 0
STATUS REGISTER
54 55
47
58
65-22071-06
Figure 4. Control Register Map
Control Register Bit Functions
Bit
Name
Function
0
SRESET
Software reset. When LOW, resets and holds internal state machines, resets Control
Register with previously written values, and disables output drivers. When HIGH,
SRESET starts and runs state machines, PXCK, and enables outputs.
1-3
FORMAT
Input signal format select.
Bit 3 is the MSB.
000 NTSC at 12.27 Mpps.
001 NTSC at 13.5 Mpps.
010 Reserved.
011 Reserved.
100 PAL at 13.5 Mpps.
101 Reserved.
11x Reserved.
4-6
7,8
TEST
Factory test control bits. These should be set LOW.
Video source select. Bit 8 is the MSB.
SOURCE
00 V
01 V
1x V
IN1
IN2
IN3
9
VGAIN
TEST
Video gain. When LOW, gain is set to unity. When HIGH, gain is set to 1.5X.
Factory test control bits. These should be set LOW.
10-11
12-16
SUBPIX
These control bits allows the HSYNC, VSYNC, and sample clock to be time-shifted by
-16/32 to +15/32 pixels. Bit 16 is the two’s complement MSB. When SUBPIX is 00 ,
h
HSYNC and incoming video are subject to LEADLAG. A value of 18 delays HSYNC
h
1/4 pixel. A value of 08 advances HSYNC 1/4 pixel.
h
17-24
LEADLAG
This control word allows the HSYNC and VSYNC to be time-shifted -122 to +132 LDV
cycles. When LEADLAG is 7B , HSYNC and incoming video are in alignment. A value of
h
83 delays HSYNC eight LDV cycles. A value of 73 advances HSYNC eight LDV
h
h
cycles. Bit 24 is the MSB.
8
PRODUCT SPECIFICATION
TMC22071A
Control Register Bit Functions (continued)
Bit
Name
Function
25
AGC
AGC operation control. After H and V sync acquisition, the A/D converter references are
adjusted to encompass the full video range. The system can initiate an A/D adjustment
sequence at any time by bringing this bit HIGH. The control bit will reset to 0 following
AGC adjustment.
26
FRERUN
When HIGH, a free-running PXCK is generated, independent of incoming video. When
LOW, PXCK is locked to incoming video.
27-29
30
TEST
Factory test control bits. These should be set LOW.
VCR/TV
Block sync enable. When HIGH the TMC22071A accepts both normal and block sync.
(In block sync, the incoming signal is at the sync tip level for 2.5 (PAL) or 3 (NTSC)
consecutive lines. Equalization pulses may be absent.) When LOW, only normal sync
may be input. For most applications, whether using a VCR or a studio video input
source, best performance will be found when this bit is HIGH.
31
CVBSEN
CVBS bus enable. When LOW, the CVBS , GHSYNC, and GVSYNC outputs are in a
7-0
high-impedance state. When HIGH, they are enabled.
32
33
TEST
Factory test control bit. This should be set LOW.
BPFOUT
Burst phase / frequency output control. When HIGH, GRS is disabled. When LOW, burst
phase and frequency information is output on CVBS
.
3-0
34
DCLAMP
Digital clamp enable. The digital clamp is enabled when DCLAMP is HIGH and disabled
when LOW.
35-39
40-43
TEST
Factory test control bits. These should be set LOW.
STVAL
Sync tip value. When DCLAMP is HIGH and STVAL is set to its default value 3 the
h
output sync level is 3 for NTSC and 7 for PAL. Bit 43 is the MSB.
h
h
44
VCR
VCR lock control. Setting this bit LOW improves the TMC22071A’s locking to VCR
signals. When only clean video input signals are used, the user may set this bit HIGH for
compatibility with existing TMC22071 firmware.
45
46
TEST
Factory test control bit. This should be set LOW.
GRSONLY
When the horizontal phase lock loop becomes unlocked (i.e. after video input is
disconnected) and this Control Bit is HIGH, all CVBS data is forced LOW except
subcarrier frequency and phase data (GRS). GHSYNC, GVSYNC, and PXCK continue
with default GRS data until video is required. The presence of GRS also depends upon
bit 33. If the GRSONLY bit is LOW, GHSYNC, GVSYNC, and PXCK continue with
default GRS data continue but video pixel data is random.
Status Bits (Read Only)
47
COLOR
Burst present status bit. This bit is HIGH when burst is present on the input video. It is
LOW, when burst is not present.
48-55
56
BLKAMP
LOCK
Blanking amplitude status bit. These eight bits report the actual blanking level.
H-lock loop status bit. When HIGH, the TMC22071A is not locked to an input signal.
When LOW, lock has been achieved.
57-58
TEST
These are read-only bits for testing puposes only.
9
TMC22071A
PRODUCT SPECIFICATION
Horizontal Timing
H
2.35 µsec PAL
2.3 µsec NTSC
Equalizing Pulse
Horizontal line rate is selectable, and is determined by the
FORMAT control bits (12.27 Mpps for NTSC, 13.5 Mpps
for NTSC and PAL). Figure 5 illustrates the horizontal
blanking interval. Figure 6 completes the definition of timing
parameters with vertical blanking interval detail.
0.5H
4.7 µsec
Serration
Video In
GVSYNC
t
VD
GHSYNC
(Odd Field)
t
DH
GHSYNC
(Even Field)
65-22071-08
Video In
Figure 6. Vertical Sync timing
Burst
Programming the TMC22071A
Upon power-up after bringing RESET LOW, the
TMC22071A Control Register is set to default values as
shown in the top entry of Table 3. These default values do
not necessarily render the TMC22071A operational in any
specific application. Before the TMC22071A is expected to
acquire input video, its Control Register must be loaded with
data that is specific to its use.
t
DH
GHSYNC
65-22071-07
Figure 5. Horizontal Sync Timing
Table 2.TMC22071A Timing Options
Field
Rate (Hz)
Line
Rate (kHz)
Pixel
Rate (Mpps)
PXCK
Frequency (MHz)
Plxels
Per Line
Standard
NTSC
59.94
59.94
50.00
15.734264
15.734264
15.625
12.2727+
13.50
24.54+
27.0
780
858
864
NTSC-601
PAL-601
13.50
27.0
Table 3. Control Register Example Data
Control Register Data (Bit 56 …… Bit 0)
46 42 38 34 30
Standard
26
22
18
14
10
6
2
DEFAULT 0000 0110 0000 1001 0000 0010 0000 0000 0000 0000 0000
001
000
010
xx0
NTSC
NTSC-601 0010 0110 0000 1001 1000 0010 0000 0000 0000
PAL-601 0010 1110 0000 1001 1000 0010 0000 0000 0000
0010 0110 0000 1001 1000 0010 0000 0000 0000
00xx
00xx
00xx
0000
0000
0001
10
PRODUCT SPECIFICATION
TMC22071A
CVBS Bus Data Formats
The CVBS bus outputs a Genlock Reference Signal (GRS)
along with the 8-bit digital composite video data. The range
of output data versus video input voltage is illustrated in
Figure 7 where sync tip and blanking levels are controlled by
the digital backporch clamp of the TMC22071A. During
horizontal sync, the TMC22071A outputs field identifica-
tion, subcarrier frequency, and subcarrier phase information
on the CVBS bus.
Field identification is output on CVBS . The LSB,
2-0
CVBS , will be LOW during odd fields and HIGH for even
0
fields. When NTSC operation is selected, CVBS count
1-0
00,01,10,11 for fields 1 through 4 respectively. When PAL
operation is selected, CVBS count 000, 001, 010, etc. to
2-0
111 for fields 1 through 8, respectively.
CVBS indicates V-component inversion in PAL. It is HIGH
3
for NTSC lines (burst 135°) and LOW for PAL lines (burst
225°)
NTSC PAL
Peak Chrominance
FE
FF
h
h
Peak Luminance
Subcarrier frequency is sent out in a 24-bit binary represen-
tation in six 4-bit nibbles on CVBS . Subcarrier frequency
3-0
D2
CF
h
h
data, f , is identical to the pre-programmed BSEED value
23-0
used in the TMC22071A to lock the subcarrier phase-locked
loop to the incoming subcarrier frequency.
Back Porch
Blanking
Subcarrier phase, F , is also sent out in a 24-bit binary
23-0
representation in six 4-bit nibbles on CVBS . Bit F is
3-0 23
the MSB.
Burst
3C
40
03
h
h
Sync Tip
03
h
h
65-22071-09
Figure 7. Output Data vs. Input Video Level
PXCK
0
1
2
3
57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
GHSYNC
CVBS
7:0
f23:20 f19:16 f15:12 f11:8 f7:4 f3:0 f23:20 f19:16 f15:12 f11:8 f7:4 f3:0
PIXEL
PIXEL
PIXEL
PIXEL
PIXEL
FREQUENCY
FIELD IDENTIFICATION
PHASE
65-22071-10
Figure 8. Genlock Reference Signal (GRS) Format
t
t
1/f
PXCK
PWHPX
PWHPX
PXCK
t
DO
GHSYNC
LDV
t
t
XV
XL
t
HO
CVBS
7:0
PIXEL 0
PIXEL 1
65-22071-11
Figure 9. CVBS Bus Video Data Format
11
TMC22071A
PRODUCT SPECIFICATION
t
t
PWHCS
PWLCS
CS
t
t
HA
SA
R/W
A
D
0
t
t
HD
SD
0
65-22071-12
Figure 10. Microprocessor Port – Write Timing
t
t
PWHCS
PWLCS
CS
t
t
HA
SA
R/W
A
D
0
t
t
HOM
DOM
0
65-22071-13
t
DOZ
Figure 11. Microprocessor Port – Read Timing
12
PRODUCT SPECIFICATION
TMC22071A
Equivalent Circuits and Transition Levels
V
V
DD
DD
n Substrate
V
n
p
DD
2k½
V
PFD IN
DD
p
p
C
BYP
DDS OUT
+
–
150½
+2.4 V
65-22071-15
65-22071-14
Figure 12. Equivalent PFD IN Circuit
Figure 13. Equivalent DDS OUT Circuit
V
V
DD
DD
n Substrate
p
n
p
Input
Output
n
65-22071-17
65-22071-16
Figure 14. Equivalent Digital Input Circuit
Figure 15. Equivalent Digital Output Circuit
t
DOM
CS
t
t
DOZ
HOM
0.5 V
Hi-Z
2.0 V
0.8 V
D
0
65-22071-18
0.5 V
Figure 16. Transition Levels for Three-State Measurements
13
TMC22071A
PRODUCT SPECIFICATION
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min.
-0.5
-0.5
Max.
Unit.
Power Supply Voltage
Input Voltage
7.0
V
V
V
+ 0.5
V
DD
Digital Outputs
Applied Voltage2
Forced Current3,4
-0.5
-6.0
+ 0.5
V
DD
6.0
mA
sec
Short Circuit Duration (single output in HIGH state to GND)
Temperature
1
Operating, Case
-60
-65
130
150
300
220
150
°C
°C
°C
°C
°C
Operating, Junction
Lead Soldering (10 seconds)
Vapor Phase Soldering (1 minute)
Storage
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current, flowing into the device.
Operating Conditions (for standard temperature range)
Parameter
Min.
Nom.
Max.
Units
V
DD
V
IH
Power Supply Voltage
Input Voltage, Logic HIGH
TTL Inputs
4.75
5.0
5.25
V
2.0
V
V
V
V
DD
CMOS Inputs
2/3V
DD
DD
V
IL
Input Voltage, Logic LOW
TTL Inputs
D
D
0.8
1/3 V
V
V
GND
CMOS Inputs
GND
DD
I
Output Current, Logic HIGH
Output Current, Logic LOW
Video Input Signal Level, Sync Tip to Peak White
External Reference Voltage
Ambient Temperature, Still Air
-2.0
4.0
mA
mA
V
OH
l
OL
V
V
1.0
IN
1.235
V
REF
A
T
0
70
°C
Microprocessor Interface
t
t
t
t
t
t
CS Pulse Width, LOW
CS Pulse Width, HIGH
Address Setup Time
Address Hold Time
Data Setup Time
50
50
ns
ns
ns
ns
ns
ns
PWHCS
PWHCS
SA
0
16
20
0
HA
SD
Data Hold Time
HD
Note:
1. Timing reference points are at the 50% level.
14
PRODUCT SPECIFICATION
TMC22071A
Electrical Characteristics (for standard temperature range)
Parameter
Conditions
Total Current
Min
Typ
Max Units
I
Power Supply Current1
190
230
mA
DD
V
= Max,
DD
f
= 30MHz
PXCK
I
I
I
Reference Inputcurrent
V
V
V
= +1.235V
100
±10
±10
mA
mA
mA
V
REF
REF
Input Current, Logic HIGH
Input Current, Logic LOW
Output Voltage, Logic HIGH
Output Voltage, Logic LOW
Hi-Z Output Leakage current, HIGH
Hi-Z Output Leakage current, LOW
Digital Input Capacitance
= Max, V = 4.0V
IN
IH
DD
DD
= Max, V = 0.4V
IN
IL
V
V
I
I
= -2.0 mA
2.4
OH
OL
OH
OL
= 4.0 mA
0.4
±10
±10
15
V
I
I
V
DD
V
DD
= Max, V = V
IN DD
mA
mA
pF
pF
pF
kW
OZH
OZL
= Max, V =GND
IN
C
C
C
R
T = 25°C, f = 1 Mhz
A
4
l
Digital Output Capacitance
T - 25°C, f = 1 Mhz
A
10
O
V
V
Input Capacitance, V
IN1-3
T = 25°C, f = 3.58 Mhz
A
15
Input Resistance, V
IN1-3
50
Note:
1. Typical I
with V
DD
= +5.0 Volts and T = 25°C, Maximum I
DD
with V = +5.25 Volts and T = 0°C.
DD A
DD
A
Switching Characteristics (for standard temperature range)
Parameter
Conditlons
= 35 pF
Min
2
Typ
Max
Units
ns
t
t
f
f
t
t
t
t
t
t
t
t
t
Output Delay Time
C
15
8
DO
LOAD
Output Hold Time
3
ns
HO
Pixel Rate
12
24
12
12
15.3
30.6
MHz
MHz
ns
PCK
PXCK
PWHPX
PWHPX
DH
Master Clock Rate
PXCK Pulse Width, LOW
PXCK Pulse Width, HIGH
Horizontal Sync to GHSYNC
Vertical Sync to GVSYNC
PXCK LOW to LDV HIGH
PXCK LOW to LDV LOW
ns
14
14
pixels
pixels
ns
VD
8
8
XL
ns
XV
D enable time
0
20
15
5
ns
DOM
HOM
DOZ
D disable time
0
10
ns
CS LOW to D output driven
ns
0
15
TMC22071A
PRODUCT SPECIFICATION
System Performance Characterlstics
Parameter
Min
Type
Max
±3
Units
ns
E
SCH
E
SCP
Sync time-base variation1
Subcarrier Phase Error1
±2
degrees
frames
dB
t
AL
Line-lock Acquisition Time
2
V
Channel-to-Channel Crosstalk @3.58 Mhz
-35
XT
Note:
1. NTSC/PAL compliant black burst at nominal input level ±10%, frequencies nominal ±10 ppm.
+5V
Ferrite Bead
6.8 pF
Analog Supply Plane*
Digital Supply Plane
10µH
150 pF
390
pF
0.01 µF
10µF
0.1µF
10µF
0.1µF
+5V
D
V
V
A
GND
DDS OUT
PFD IN
COMP
GND
DD DDA
0.1µF
3.3 µF
LPF
LPF
3.3K½
0.1µF
Video A
Video B
Video C
V
V
V
IN1
IN2
IN3
V
REF
75½
75½
75½
3.3 µF
3.3 µF
LM385-1.2
TMC22071A
Genlocking
Video Digitizer
R
T
LPF
0.1µF
R
B
0.1µF
8
CVBS
7:0
EXT PXCK
GHSYNC
GVSYNC
PXCK
20 MHz, TTL
CLK IN
CLK OUT
PXCK SEL
C
LDV
BYP
0.1µF
65-22071A-19
MICROPROCESSOR
INTERFACE
and
must be connected
*section of supply plane beneath
analog interface circuitry
via low-impedance path
Figure 17. Typical Interface Circuit
Chebyshev response with-3dB bandwidth of 6.7MHz and a
group delay of 140 nanoseconds at 5MHz. The filter of Figure
19 has been equalized for group delay in the video signal
band. Its -3dB passband is 5.5MHz while the group delay is
constant at 220 nanoseconds through the DC to 5MHz
frequency band.
Application Notes
The TMC22071A is a complex mixed-signal VLSI circuit.
It produces CMOS digital signals at clock rates of up to 15
MHz while processing analog video inputs with a resolu-
tion of less than a few millivolts. To maximize performance
it is important to provide an electrically quiet operating
environment. The circuit shown in Figure 17 provides an
2.2µH
2.2µH
optional external 1.2V reference to the V
input of the
source is adequate for
REF
TMC22071A. The internal V
most applications.
REF
470 pF
1000 pF
470 pF
Flltering
Inexpensive low-pass anti-aliasing filters are shown in Fig-
ures 18 and 20. These filters would normally be inserted in
the video signal path just before the 75W terminating resis-
tor and AC-coupling capacitor for each of the three video
65-22071-20
Figure 18. Simple Anti-aliasing Filter
inputs, V . The filter of Figure 18 exhibits a 5th-order
IN1-3
16
PRODUCT SPECIFICATION
TMC22071A
3.3 µH
3.3 µH
4.7 µH
4.7 µH
Grounding
The TMC22071A has separate analog and digital circuits. To
minimize digital crosstalk into the analog signals, the power
supplies and ground connections are provided over separate
470 pF
470 pF
430 pF
750 pF
430 pF
910 µH
pins (V
pins; D
and V
DDA
are digital and analog power supply
are digital and analog ground pins).
DD
2.2 µH
and A
GND
GND
In general, the best results are obtained by tying all grounds
to a solid, low-impedance ground plane. Power supply pins
should be individually decoupled at the pin. Power supply
noise isolation should be provided between analog and digi-
tal supplies via a ferrite bead inductor on the analog lead.
Ultimately all +5 Volt power to the TMC22071A should
come from the same power source.
65-22071-21
Figure 19. Group Delay Equalizer Filter
Using a 20 MHz Crystal
In systems where a 20 MHz clock is not available, a crystal
may be used to generate the clock to the TMC22071A. The
crystal must be a 20 MHz “fundamental” type, not overtone.
Specific crystal characteristics are listed in Table 4 and the
connections are shown in Figure 20.
Another approach calls for separating analog and digital
ground. While some systems may benefit from this strategy,
analog and digital grounds must be kept within 0.1V of each
other at all times.
Table 4. Crystal Parameters
Parameter
Value
Interface to the TMC22x9x Encoder
Fundamental frequency 20 MHz
The TMC22x9x Digital Video Encoders have been designed
to directly interface to the TMC22071A Digital Video
Genlock. The TMC22071A is the source for TMC22x9x
Tolerance
Stability
±30 ppm @ 25°C
±50 ppm, 0°C to 70°C
20 pF
input signals CVBS , GHSYNC, GVSYNC, LDV, and
7-0
Load Capacitance
Shunt Capacitance
ESR
PXCK as shown in Figure 21. These signals directly connect
to the TMC22x9x. The microprocessor interface for
TMC22x9x and TMC22071A are identical. All R/W,
RESET, data and address bus signals from the host micro-
processor are shared by the TMC22x9x and TMC22071A.
Only CS, VALID, and INT signals are separate from the
microprocessor bus.
7 pF Max.
50 W, Max.
TMC22071A
33 pF
CLK IN
1M½
20 MHz
Crystal
300½
CLK OUT
33 pF
65-22071A-22
Figure 20. Direct Crystal Connections
8
CVBS
CVBS
7:0
7:0
GHSYNC
GVSYNC
PXCK
GHSYNC
GVSYNC
PXCK
TMC22071A
TMC22x9x
DIGITAL VIDEO ENCODER
LDV
LDV
GENLOCKING VIDEO DIGITIZER
2
8
65-22071A-23
MICROPROCESSOR INTERFACE
Figure 21. TMC22x9x Interface Circuit
17
TMC22071A
PRODUCT SPECIFICATION
4. Decoupling capacitors should be applied liberally to
Printed Circuit Board Layout
V
DD
pins. Remember that not all power supply pins are
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Wire-wrap is
not an option. Overall system performance is strongly influ-
enced by the board layout. Capacitive coupling from digital
to analog circuits may result in poor picture quality. Con-
sider the following suggestions when doing the layout:
created equal. They typically supply adjacent circuits on
the device, which generate varying amounts of noise.
For best results, use 0.1mF capacitors in parallel with
10mF capacitors. Lead lengths should be minimized.
Ceramic chip capacitors are the best choice.
5. If the digital power supply has a dedicated power plane
layer, it should not overlap the TMC22071A, the voltage
reference or the analog outputs. Capacitive coupling of
digital power supply noise from this layer to the
TMC22071A and its related analog circuitry can
degrade performance.
1. Keep the critical analog traces (COMP,V
, R , R ,
T B
REF
DDS OUT, PFD IN, C
, and V
) as short as pos-
IN1-3
BYP
sible and as far as possible from all digital signals. The
TMC22071A should be located near the board edge,
close to the analog output connectors.
2. The digital power plane for the TMC22071A should be
that which supplies the rest of the digital circuitry. A sin-
6. CLK should be handled carefully. Jitter and noise on
this clock or its ground reference may degrade perfor-
mance. Terminate the clock line carefully to eliminate
overshoot and ringing.
gle power plane should be used for all of the V
DD
pins.
If the analog power supply for the TMC22071A is the
same as that of the system’s digital circuitry, power to
the TMC22071A V
DDA
ferrite beads and 0.1 mF capacitors to reduce noise.
pins should be decoupled with
Related Products
• TMC22x9x Digital Video Encoders
• TMC2242/TMC2243/TMC2246 Video Filters
• TMC2081 Digital Video Mixer
3. The ground plane should be solid, nor cross-hatched.
Connections to the ground plane should have very short
leads.
• TMC22x5y Digital Decoders
• TMC2302 Image Manipulation Sequencer
18
PRODUCT SPECIFICATION
TMC22071A
Notes:
19
TMC22071A
PRODUCT SPECIFICATION
Notes:
20
PRODUCT SPECIFICATION
TMC22071A
Notes:
21
TMC22071A
PRODUCT SPECIFICATION
Mechanical Dimensions
68 Lead PLCC Package
Notes:
Inches
Millimeters
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982
Min.
Max.
Min.
Max.
2. Corner and edge chamfer (J) = 45¡
A
.165
.090
.020
.013
.026
.985
.950
.200
.130
—
4.19
2.29
.51
5.08
3.30
—
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)
A1
A2
B
.021
.032
.995
.958
.33
.53
B1
.66
.81
D/E
D1/E1
D3/E3
e
25.02
24.13
25.27
24.33
3
2
.800 BSC
.050 BSC
.042 .056
20.32 BSC
1.27 BSC
1.07 1.42
J
ND/NE
N
17
68
17
68
ccc
—
.004
—
0.10
E
E1
J
D
D1
D3/E3
B1
e
J
A
A1
-C-
B
A2
LEAD COPLANARITY
ccc
C
22
PRODUCT SPECIFICATION
TMC22071A
Mechanical Dimensions (continued)
100 Lead MQFP Package – 3.2mm Footprint
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
2. Controlling dimension is millimeters.
Min.
Max.
A
—
.134
—
—
3.40
—
3. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall be .08mm (.003in.) maximum in excess of
the "B" dimension. Dambar cannot be located on the lower radius
or the foot.
A1
A2
B
.010
.100
.008
.005
.904
.783
.667
.547
.25
.120
.015
.009
.923
.791
.687
.555
2.55
.22
3.05
.38
3, 5
5
4. "L" is the length of terminal for soldering to a substrate.
5. "B" & "C" includes lead finish thickness.
C
.13
.23
D
22.95
19.90
16.95
13.90
23.45
20.10
17.45
14.10
D1
E
E1
e
.0256 BSC
.65 BSC
4
L
.028
.040
.73
1.03
N
100
30
100
30
ND
NE
20
20
a
0¡
7¡
0¡
7¡
ccc
—
.004
—
.12
D
.20 (.008) Min.
D1
0¡ Min.
.13 (.30)
.005 (.012)
Datum Plane
R
C
B
e
E1
a
.13 (.005) R Min.
Pin 1 Indentifier
E
L
0.076" (1.95mm) Ref
Lead Detail
See Lead Detail
Base Plane
A
A2
-C-
Lead Coplanarity
ccc
B
Seating Plane
A1
C
23
TMC22071A
PRODUCT SPECIFICATION
Ordering Information
Product Number
Temperature Range
T = 0°C to 70°C
Screening
Commercial
Commercial
Package
Package Marking
22071AR1C
TMC22071AR1C
68-Lead PLCC
100-Lead MQFP
A
1
TMC22071AKHC
Note:
1. 100 Lead MQFP is strongly recommended for all new board designs.
T = 0°C to 70°C
A
22071AKHC
7/24/98 0.0m 002
Stock#DS7022071A
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