TMC22091 [FAIRCHILD]
Digital Video Encoders/Layering Engine; 数字视频编码器/分层引擎
| 型号： | TMC22091 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Digital Video Encoders/Layering Engine |
| 文件： | 总60页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
TMC2 2 0 9 1 /TMC2 2 1 9 1
Dig it a l Vid e o En c o d e rs /La ye rin g En g in e
• Controlled edge rates
• 3 power-down modes
• Built-in color bars and modulated ramp test signals
• JTAG (IEEE Std 1149.1-1990) test interface
• Single +5V power supply
Features
• All-digital video encoding
• Internal digital oscillators, no crystals required
• Multiple input formats supported
– 24-bit and 15-bit GBR/RGB
• 84 lead PLCC package
• 100 lead MQFP package
– YC C 422 or 444
B R
– Color indexed
• 30 overlay colors (TMC22191)
• Fully programmable timing
• Supports input pixel rates of 10 to 15 Mpps
• 256 x 8 x 3 color look-up tables (bypassable on
TMC22191)
Description
The TMC22x91 digital video encoders convert digital com-
puter image or graphics data (in RGB, YCBCR, or color
indexed format) or a CCIR-601 signal into a standard analog
baseband television (NTSC or PAL) signal with a modulated
color subcarrier.
• 8-bit mask register
• 8-bit composite digital video input
• Hardware and 24-bit data keying
• Synchronizes with TMC22071 Genlocking Video
Digitizer
• 8:8:8 video reconstruction
• SMPTE 170M NTSC or CCIR Report 624 PAL
compatible
• Supports PAL-M and NTSC without pedestal
• Simultaneous S-VIDEO (Y/C) NTSC/PAL output
• 10-bit D/A conversion (three channels)
Both composite (single lead) and S-VIDEO (separate
chroma and luma) formats are active simultaneously at the
three analog output pins, each of which generates a standard
video-level signal into doubly-terminated 75Ω load.
The TMC22x91 accepts digitized video from the companion
TMC22071 Genlocking Video Digitizer. Soft switching
between video sources is done under either hardware or
programmable data control.
The TMC22191 offers 4-layer keying capability, bypassable
CLUT, and 30 Overlay colors.
Logic Symbol
The TMC22x91 is fabricated in a submicron CMOS process
and packaged in an 84 Lead Plastic Leadless Chip Carrier, or
in a 100 Lead Metric Quad Flat Pack. Performance is guar-
anteed from 0°C to 70°C.
BYPASS and OL
on TMC22191 only.
4:0
24
PD
23-0
6
CHROMA
LUNA
COMPOSITE
OL
4-0
PDC
VHSYNC
VVSYNC
KEY
V
REF
COMP
BYPASS
R
REF
8
TMC22x91
DIGITAL
VIDEO
CVBS
7-0
GHSYNC
GVSYNC
ENCODER
TDI
TMS
TCK
TDO
RESET
8
2
D
7-0
A
LDV
1-0
PXCK
CS
R/W
27008A
Rev. 1.1.0
TMC22091/TMC22191
PRODUCT SPECIFICATION
Block Diagram
OL
4-0
BYPASS and OL
4:0
on TMC22191 only.
BYPASS
LPF
INT
G/R/Y MAP
R/R-Y
R-Y
B-Y
256 x 8 x 3
COLOR
LOOK-UP
TABLE
10-bit
INTER-
POLATOR
4:2:2/4:4:4
CHROMA
D/A
CHROMA
MODULATOR
B/G/C
B
FORMATTER
MASK, KEY
COMPARATOR
B/B-Y
G/Y
PD
MATRIX
23-0
R/B/C
R
LPF
INT
Data Key
SYNC,
10-bit
LUMA
D/A
KEY
PDC
BLANK
INSERT
VVSYNC
VHSYNC
GHSYNC
GVSYNC
DIGITAL
SYNC.
GEN.
VIDEO
SWITCH
10-bit
D/A
COMPOSITE
SUBCARRIER
SYNTHESIZER
INT
CVBS
7-0
D/A
REF.
INTERPOLATION
FILTERS
CLOCK
CONTROL
JTAG
V
REF
COMP
R
REF
CLOCKS
MICROPROCESSOR
INTERFACE
JTAG TEST
INTERFACE
27006A
Timing
Functional Description
The encoder operates from a single clock at twice the system
pixel rate. This frequency may be set between 20 MHz and
36 MHz (pixel rates of 10 Mpps to 18 Mpps). Within this
range are included CCIR-601, D2, and square-pixel formats,
as well as a variety of computer-specific pixel rates. An array
of programmable timing registers allows the software selec-
tion of all pertinent signal parameters to produce NTSC
(with or without 7.5 IRE pedestal) and PAL, and PAL-M
outputs.
The TMC22091 and TMC22191 are totally integrated, fully-
programmable digital video encoders with simultaneous
composite and Y/C (S-VIDEO) outputs. The TMC22x91
video outputs are compatible with SMPTE 170M NTSC,
CCIR Report 624 PAL, PAL-M, and NTSC without pedestal
television standards. No external component selection or
tuning is required.
The encoders accept digital image data at the PD port in one
of several formats, which are matrixed into luminance and
chrominance components. The chrominance signals are
modulated onto a digitally synthesized subcarrier. The lumi-
nance and chrominance signals are separately interpolated to
twice the pixel rate, and converted to analog levels by 10-bit
D/A converters. They are also digitally combined and the
resulting composite signal is output by a third 10-bit D/A
converter. This composite signal may be keyed (pixel rate
switching) with a second composite digital video signal pre-
sented to the encoder.
Table 1. Comparing the TMC22x91 Encoders
Feature
TMC22091 TMC22191
OL pixel inputs for 30
No
Yes
4-0
overlay colors
Number of video layers
supported
2
4
BYPASS input for
bypassing CLUTs
No
Yes
The output video frames may be internally timed by the
TMC22x91, synchronized with the external frame buffer, or
slaved to the companion Genlocking Video Digitizer
(TMC22071). All operational parameters are fully program-
mable over a standard microprocessor port.
Input Formatting
The input section accepts a variety of video and graphics for-
mats, including 24-bit GBR and RGB, 15-bit GBR and
RGB,YCBCR422,YCBCR444, and 8-bit color-indexed data
(Figure 1a and 1b).
Table 1 shows the key features that distinguish between the
TMC22091 and TMC22191. All of the information pre-
sented in this data sheet applies to both products unless oth-
erwise noted. Statements, paragraphs, tables, and figures that
apply to only one or two of the encoders have notation speci-
fying the applicable part number.
The input section of the TMC22x91 includes a key compara-
tor which monitors the pixel data port with three independent
8-bit comparators, and invokes a video key when the selected
registers match the incoming data.
2
PRODUCT SPECIFICATION
TMC22091/TMC22191
Mask Register
Colorspace Conversion Matrix and
Interpolator
A Mask Register is provided which is logically ANDed with
incoming color-index data to facilitate pixel animation and
other special graphics effects. The Mask Register is ahead of
the Data Key comparators and is enabled only when color-
index input is selected. Mask Register programming and
operation are similar to that of the 171/176 family of graph-
ics RAMDACS.
The matrix converts RGB data (whether from RGB inputs or
color-indexed CLUT data) into Y, B-Y, R-Y format for
encoding. In input configurations where the pixel input is
already inY, B-Y, R-Y format, the matrix is bypassed. When
pixel data is input inYC C 422 format, the interpolation fil-
ters produce YC C 444 for encoding.
B R
B R
Color Lookup Table
Sync Generator
The Color Lookup Table (CLUT) is a 256 x 8 x 3 random-
access memory. It provides means for offset, gain, gamma,
The TMC22x91 can operate in Master, Genlock, or Slave
modes. In Master and Genlock modes, the encoder internally
generates all timing and sync signals, and provides Horizon-
tal Sync, Vertical Sync, and Pixel Data Control (PDC) to the
external frame buffer circuitry. PDC is independently select-
able to function as an input or an output. In Genlock mode,
the TMC22x91 timing is controlled by the TMC22071 Gen-
and color correction in RGB andYC C operating modes. It
B R
provides a full 24-bit color lookup function for color-index
mode. It can be loaded in the same manner as a standard
VGA RAMDAC.
locking Video Digitizer over the CVBS bus, GVSYNC,
7-0
and GHSYNC. The encoder, in turn, produces VHSYNC,
VVSYNC, and PDC for the frame buffer interface.
MODE
Format Control Register
MSB LSB
MSB
23
LSB
0
16 15
G0
8
7
GBR444
00011000
00010000
00011100
00011101
0001X011
G
R
Y
Y
B
R
B
G7
R7
Y7
B
B0 R7
R0
7
RGB444
G
R0 G7
G0 B7
B0
YC C 444
B R
C
C
R
Y0 CB7
CB7
CB0RR7
RR0
B
CB0
CR0
YC C 422
B R
C /C
CR7
Y7
Y0
B R
COLOR INDEX
GBR15
Pixel
P7
B
G
P0
R0
00011010
00010010
G
R
R
G4
G0 B4
R0 G4
B0 R4
RGB15
B
R4
G0 B4
B0
24300A
Figure 1a. Pixel Data Format
3
TMC22091/TMC22191
PRODUCT SPECIFICATION
MODE
Format Control Register
MSB
23
LSB
0
16 15
G0
8
7
MSB
LSB
GBR444
01011000
G
R
B
R
B
G7
R7
Y7
Y7
P7
R4
G4
B
B0 R7
G0 B7
CB0CR7
CB0 CR7
P0 P7
B4
R0
7
RGB444
01010000
G
R0 G7
B0
YC C 444
B R
0101X000
0101X001
0101X011
01010010
01011010
Y
C
C
R
Y0 CB7
CR0
CR0
P0
B
YC C 422
B R
Y
C *
B
C *
R
CB7
Y0
COLOR INDEX
RGB15
Pixel
Pixel
Pixel
P0 P7
R
G
B
R0
G4
G0
B0
GBR15
G
B
R
G0
B4
B0
R4
R0
24393A
*CB and CR are loaded on alternate LDV cycles
Figure 1b. Pixel Data Format (TMC22191 when CLUTs are Bypassed)
In Slave mode, VHSYNC, VVSYNC, and PDC (optional)
are inputs to the TMC22x91. These inputs determine when
new lines, frames, and active picture areas begin. The exter-
nal controlling circuitry needs to establish the correct timing
for these signals.
An interpolation filter on the CVBS data similarly raises the
sample rate of the video signal, for mixing with the encoded
pixel data.
Composite Video Switch
The Composite Video Switch selects between the composite
video input (CVBS) and the composite encoded pixel data
on a pixel-by-pixel basis, under the control of a key function.
Horizontal and vertical synchronization signals are digitally
generated by the TMC22x91 with controlled rise and fall
times on all sync edges, the beginning and end of active
video, and the burst envelope. All elements of horizontal
sync timing are programmable, as are the frequency, phase,
and duration of color burst.
Keying may be managed by hardware or software. The hard-
ware key input (KEY pin) directly controls the video switch.
The encoder may be programmed to operate with a data key,
represented by three 8-bit registers that compare with the 24
input bits. They operate in all input modes and may be indi-
vidually enabled or disabled.
Video Input
The TMC22x91 accepts genlocked synchronization data and
digital composite video signals from the TMC22071 Gen-
locking Video Digitizer over the 8-bit CVBS bus. The
encoder synchronizes its digital subcarrier oscillator to the
video input from the TMC22071 with this data. The compos-
ite video data output from the TMC22071 is passed to the
internal video switch for keying with the encoded pixel data.
D/A Converters
The analog outputs of the TMC22x91 are the outputs of
three 10-bit D/A converters, operating at twice the pixel
clock rate. The outputs are capable of driving standard video
levels into a doubly-terminated 75Ω coaxial video cable
(37.5Ω total load). An internal voltage reference is provided
which can be used to provide reference current for the three
D/A converters. For accurate video levels, an external fixed
or variable voltage reference source is recommended. The
video signal levels from the TMC22x91 may be adjusted to
overcome the insertion loss of analog low-pass output filters.
Chroma Modulator
A 32-bit digital subcarrier synthesizer feeds a quadrature
modulator, producing a digital chrominance signal. The rela-
tive phases of the burst and active video portions of the sub-
carrier can be individually adjusted to compensate for
external phase errors and to effect a hue control.
The D/A converters on the TMC22x91 may be powered-
down via Control Register 0E bits 5 and 6. The
COMPOSITE D/A is controlled by bit 6 and the LUMA and
CHROMA D/A converters are controlled by bit 5.
Interpolation Filters
Interpolation filters on the luminance and chrominance sig-
nals double the pixel rate in preparation for D/A conversion.
This band-limited process greatly simplifies the output filter-
ing required following the D/A converters and dramatically
reduces sin(x)/x distortion.
4
PRODUCT SPECIFICATION
TMC22091/TMC22191
bars are useful as an idle system output signal. The test sig-
nals may be used to verify proper operation of the analog
video signal chain.
Microprocessor Interface
The microprocessor interface employs a 13 line format. The
RESET pin sets all internal state machines to their initialized
conditions, disables the analog outputs, sets the internal
SRESET bit LOW (reset condition), and places the encoder
in a power-down mode. All register and CLUT data are
maintained in power-down mode. If the HRESET bit is set
HIGH, line 1 field 1 is started when RESET goes HIGH, and
SRESET is ignored. If HRESET is LOW, the encoder
remains idle after RESET goes HIGH until Control Register
bit SRESET is set HIGH, which initiates line 1 field 1.
TMC22090/TMC22190 Compatibility
The TMC22090 and TMC22190 are earlier versions of the
TMC22091 and TMC22191, respectively. They lack the fol-
lowing features of the newer versions:
1. Selectable Setup (to support NTSC EIA-J video output
for Japan)
2. PAL-M format (for South American applications)
Two address lines are provided and decoded for access to the
internal Control Registers and CLUT. Control Registers and
CLUT are accessed by loading a desired address through the
3. Extended EH and SL intervals (to support pixel rates
above 15 Mpps)
8-bit D port, followed by the desired data read or write for
7-0
4. Individual D/A power-down (to reduce total dissipation
when some outputs are not required)
that address. Both the CLUT and the Control Registers are
self-indexing, allowing continuous reads or writes to succes-
sive addresses.
5. Luminance I/O processing (to reduce flicker in graphics
applications)
JTAG Test Interface
These features are controlled by registers 0E and 0F, and
enabled by setting Register OE bit 7 to ONE. If an applica-
tion of the TMC22x90 is programmed with this bit set to
ZERO (as recommended in the product documentation) then
the corresponding TMC22x91 will perform identically.
Though the earlier parts continue to be available, it is recom-
mended that the newer devices be used in new designs for
the additional flexibility. Older designs may be readily
converted to the newer versions to take advantage of the
added features and lower cost of the later technology.
The TMC22x91 includes a standard 4-line JTAG (IEEE Std
1149.1-1990) test interface port, providing access to all digi-
tal input/output data pins. This is provided to facilitate com-
ponent and board-level testing.
Test/Validation Mode
The TMC22x91 may be configured to produce standard
color bars or a 40 IRE modulated (or unmodulated) video
ramp, independent of any pixel or video data input. Color
5
TMC22091/TMC22191
PRODUCT SPECIFICATION
Pin Assignments
84 Lead PLCC
1 84
Pin
1
Name
Pin Name
22 TDO
23 TCK
24 TMS
25 TDI
Pin Name
43
Pin Name
CVBS
V
DDA
64
65
V
DD
2
1
0
2
CVBS
CVBS
KEY
44 CVBS
45 CVBS
46 CVBS
47 CVBS
D
GND
7
6
5
4
3
66 PD
11
4
67 PD
10
5
RESET
CS
26
27
D
68 PD
9
GND
6
V
DD
48 OL (TEST) 69 PD
3 8
7
R/W
28 BYPASS (TEST) 49 OL (TEST) 70 PD
2 7
8
A
1
29 OL (TEST)
50 OL (TEST) 71 PD
1 6
4
9
A
30
31
32
V
51 OL (TEST) 72 PD
0 5
0
REF
10
D
GND
R
REF
52 PD
23
73 PD
4
11 PDC
A
GND
53 PD
22
74 PD
3
12 VHSYNC 33 COMPOSITE
13 VVSYNC 34
54 PD
21
75 PD
2
A
55 PD
20
76 PD
1
GND
35 LUMA
36
37 CHROMA
38
39 COMP
14
15
16
17
18
19
20
21
D
56 PD
19
77 PD
0
7
D
6
A
57 PD
18
78 LDV
GND
D
5
58 PD
17
79 PXCK
D
4
A
GND
59 PD
16
80
81
D
GND
65-3751-01
D
3
60 PD
15
V
DD
D
2
40
41
42
V
DDA
61 PD
14
82 GVSYNC
83 GHSYNC
D
1
V
DDA
62 PD
13
D
0
V
DDA
63 PD
12
84 CVBS
3
Note: Pin names in parentheses apply to TMC22091.
100 Lead MQFP
Pin
1
Name
NC
Pin Name
Pin Name
51 PD
Pin Name
76
26 PD
D
GND
23
3
2
COMPOSITE
27 PD
52 NC
53 NC
54 NC
55 NC
77 PDC
22
3
NC
28 NC
29 NC
30 NC
78 NC
4
A
GND
79 NC
5
LUMA
80 VHSYNC
81 VVSYNC
6
A
GND
31 PD
21
56 PD
2
7
NC
32 PD
20
57 PD
82
83
84
85
86
87
88
89
D
7
1
8
CHROMA
33 PD
19
58 PD
D
6
0
9
A
GND
34 PD
18
59 LDV
D
5
100
10 COMP
11 NC
35 PD
17
60 PXCK
D
4
36 PD
16
61
62
D
D
3
GND
1
12 NC
37 PD
15
V
DD
D
2
65-3751-02
13
14
15
16
17
V
DDA
38 PD
14
63 GVSYNC
64 GHSYNC
D
1
V
DDA
39 PD
13
D
0
V
DDA
40 PD
12
65 CVBS
66 CVBS
67 CVBS
68 CVBS
69 NC
90 TDO
91 TCK
92 TMS
93 TDI
3
2
1
0
V
DDA
41
42
V
DD
V
DDA
D
GND
18 CVBS
19 CVBS
20 CVBS
21 CVBS
43 PD
11
7
6
5
4
44 PD
10
94
95
D
GND
45 PD
70 KEY
V
DD
9
46 PD
71 RESET
72 CS
96 BYPASS (TEST)
8
22 OL (TEST) 47 PD
97 OL (TEST)
4
3
7
23 OL (TEST) 48 PD
73 R/W
98
V
REF
2
6
24 OL (TEST) 49 PD
74
75
A
99
R
REF
1
5
1
25 OL (TEST) 50 PD
A
0
100 A
GND
0
4
Note: Pin names in parentheses apply to TMC22091.
6
PRODUCT SPECIFICATION
TMC22091/TMC22191
Pin Descriptions
Pin Number
84-Lead 100-Lead
Pin Name
Clocks
PXCK
PLCC
MQFP
Value
Pin Function Description
79
60
TTL
Master Clock Input. This 20 to 30 MHz clock is internally
divided by 2 to generate the internal pixel clock, PCK, which a
LOW on RESET forces LOW. PXCK drives the entire
TMC22x91, except the asynchronous microprocessor interface
and the semi-synchronous LDV data input clock. All internal
registers are strobed on the rising edge of PXCK.
LDV
78
59
TTL
Pixel Data Load Clock. On each rising edge of LDV, data on
PD
are latched into the input preload register, for transfer
23-0
into the input demultiplexer on the next rising edge of PCK.
Frame Buffer Interface
PD
23-0
52-63,
66-77
26, 27,
31-40,
43-51,
56-58
TTL
TTL
Pixel Data Inputs. In YC C , GBR, RGB, and color-indexed
B R
mode, pixel data enter the TMC22x91 on PD . The specific
23-0
format is found in Figures 1a and 1b. LDV is the clock that
controls the loading of pixel data.
VHSYNC
VVSYNC
12
13
80
Horizontal Sync I/O. In Master and Genlock modes, the
TMC22x91 outputs horizontal sync on this pin. In Slave modes,
the TMC22x91 accepts and locks to horizontal sync input on
this pin (with vertical sync on VVSYNC). VHSYNC and
VVSYNC must be coincident since they are clocked into the
TMC22x91 on the same rising edge of PXCK.
81
TTL
Vertical Sync I/O. In separate V and H sync Master and
Genlock modes, the TMC22x91 outputs vertical block sync
(VVSYNC LOW for the 2.5 (PAL) or 3 (NTSC) lines on which
vertical sync pulses occur). In composite sync (H and V sync
on same signal) Master and Genlock modes, the TMC22x91
outputs horizontal sync, vertical sync, and equalization over
this pin. In Slave mode, the TMC22x91 accepts and locks to
vertical sync input on this pin (with horizontal sync on
VHSYNC). VHSYNC and VVSYNC must be coincident such
that they are clocked into the TMC22x91 on the same rising
edge of PXCK.
PDC
KEY
11
77
70
TTL
TTL
Pixel Data Control. In Master mode, the TMC22x91 forces
PDC HIGH when and only when it wants active video from the
frame buffer. During blanking (syncs, equalization, burst, and
porches), it forces PDC LOW, signaling that it will ignore any
data presented over PD . When PDC is used as an input,
23-0
forcing it HIGH allows the TMC22x91 to receive PD during the
active video state.
4
Hardware Key Input. When the HKEN control bit is set HIGH
and hardware key pin, KEY, is HIGH, video data entering on
CVBS
are routed to the COMPOSITE output. This control
7-0
signal is pipelined so the pixel that is presented to the PD port
when the KEY signal is invoked is at the midpoint of the soft
key transition. When HKEN is LOW, KEY is ignored. Like PD
data, KEY is clocked into the TMC22x91 on the rising edge of
LDV.
7
TMC22091/TMC22191
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Number
84-Lead 100-Lead
Pin Name
OL
PLCC
MQFP
Value
Pin Function Description
29, 48-51 97, 22-25
TTL
Overlay Data Inputs (TMC22191 only). 30 of the 256
locations of the CLUT may be reserved for overlay operation.
These CLUT locations are directly accessed by five input pins,
4-0
OL . OL
are entered into the TMC22191 on a pixel-by-
pixel basis and select which of the 30 overlay colors is to be
4-0 4-0
encoded. When all five OL
occurs.
inputs are LOW, no overlay
4-0
BYPASS
28
96
TTL
CLUT Bypass Control (TMC22191 only). When BYPASS is
HIGH, the CLUT is in the pixel data path within the TMC22191.
When BYPASS is LOW, pixel data bypasses the CLUT.
BYPASS is active only for certain modes of the Layering
Control Register (LCR) when the Format Control Register bit 6
is HIGH.
Genlock Interface
GHSYNC
83
82
64
63
CMOS Genlock Horizontal Sync. In Genlock mode, the TMC22x91
will start a new horizontal line (blank-to-sync-edge transition)
with each falling edge of GHSYNC. In non-genlock modes, the
TMC22x91 ignores GHSYNC. The internal pixel clock, PCK, is
aligned with the falling edge of VHSYNC or GHSYNC (Genlock
mode).
GVSYNC
CMOS Genlock Vertical Sync. In Genlock mode, the TMC22x91 will
start a new vertical sync sequence at line 1 field 1 whenever
GVSYNC and GHSYNC are coincident such that they are
clocked into the TMC22x91 on the same rising edge of PXCK.
If GVSYNC falls at any other time, the TMC22x91 will assume
that this marks the start of field 2, and will ignore it (in odd-field
sync mode) or (in all-field sync mode) respond by generating a
single vertical sync pulse, followed by 2 (PAL) or 2.5 (NTSC)
lines of vertical sync, keyed to the next falling edge on
GHSYNC. See Interface Control Register bit 0 for odd-field and
all-field operation.
CVBS
44-47,84, 18-21,
TTL
Composite Video Inputs. The encoder receives digitized
video, subcarrier phase, and subcarrier frequency over this 8-
bit bus at the PCK rate. This data may be provided by the
companion TMC22071 Genlocking Video Digitizer. In Genlock
mode, the TMC22x91 expects subcarrier phase and frequency
data during each line’s horizontal sync interval, as well as video
data when keying is engaged, transferred at the PCK rate.
7-0
1-3
65-68
Microprocessor Interface
D
14-21
82-89
74-75
TTL
TTL
Data I/O Port. All control parameters are loaded into and read
back over this 8-bit port. For digital testing, the five lower bits
can also serve as a two-cycle 10-bit data output port. For D/A
converter testing, it can be used as a 10-bit two-cycle input
port, facilitating, for example, ramp-based D/A converter
linearity tests.
7-0
A
1-0
8-9
µProc Port Controls. As in a RAMDAC, this control governs
whether the microprocessor interface selects a table address
or reads/writes table contents. It also governs setting and
verification of the TMC22x91’s internal operating modes, also
over port D
.
7-0
8
PRODUCT SPECIFICATION
TMC22091/TMC22191
Pin Descriptions (continued)
Pin Number
84-Lead 100-Lead
Pin Name
PLCC
MQFP
Value
Pin Function Description
Chip Select. When CS is HIGH, the microprocessor interface
CS
6
72
TTL
port, D , is set to HIGH impedance and ignored. When CS is
7-0
LOW, the microprocessor can read or write parameters over
D . One additional falling edge of CS is needed to move input
7-0
data to its assigned working registers.
R/W
7
5
73
71
TTL
TTL
Bus Read/Write Control. When R/W and CS are LOW, the
microprocessor can write to the control registers or CLUT over
D . When R/W is HIGH and CS is LOW, it can read the
7-0
contents of any CLUT address or control register over D
.
7-0
RESET
Master Reset Input. Bringing RESET LOW sets the software
reset control bit, SRESET, LOW, forcing the internal state
machines to their starting states and disabling all outputs.
Bringing RESET HIGH synchronizes the internal pixel clock
(PCK = PXCK / 2) to maintain a defined pipeline delay through
the TMC22x91. If HRESET is set HIGH, the encoder is enabled
when RESET goes HIGH. If HRESET is LOW, the host restarts
the TMC22x91 by setting SRESET HIGH. RESET does not
affect the CLUT or the control registers, except SRESET.
Video Output
COMPOSITE
33
35
37
2
5
8
1 V
1 V
1 V
NTSC/PAL Video. Analog output of composite D/A converter,
nominally 1.35 volt peak-to-peak into a 37.5Ω load.
P-P
P-P
P-P
LUMA
Luminance-only Video. Analog output of luminance D/A
converter, nominally 1.35 volt peak-to-peak into a 37.5Ω load.
CHROMA
Chrominance-only Video. Analog output of chrominance D/A
converter, nominally 1.35 volt peak-to-peak into a 37.5Ω load.
Analog Interface
V
30
39
31
98
10
99
+1.23 V Voltage Reference Input. External voltage reference input,
REF
internal voltage reference output, nominally 1.235 V.
COMP
0.1 µF Compensation Capacitor. Connection point for 0.1µf
decoupling capacitor.
R
392Ω
Current-setting Resistor. Connection point for external
REF
current-setting resistor for D/A converters. The resistor (392Ω)
is connected between R
and A . Output video levels
REF
GND
are inversely proportional to the value of R
REF
.
JTAG Test Interface
TDI
25
93
92
TTL
TTL
Data Input Port. Boundary scan data input port.
TMS
24
Scan Select Input. Boundary scan (HIGH)/normal operation
(LOW) selector.
TCK
23
22
91
90
TTL
TTL
Scan Clock Input. Boundary scan clock.
TDO
Data Output Port. Boundary scan data output port.
Power Supply
V
V
27, 64, 81 41, 62, 95
40-43 13-17
+5 V
+5 V
Positive digital power supply.
Positive analog power supply.
Digital Ground.
DD
DDA
D
10, 26, 65, 42, 61, 76, 0.0 V
80 94
GND
A
GND
32, 34, 36, 4, 6, 9,
38 100
0.0 V
Analog Ground.
9
PRODUCT SPECIFICATION
TMC22091/TMC22191
Pin Descriptions (continued)
Pin Number
84-Lead 100-Lead
Pin Name
Test
PLCC
MQFP
Value
Pin Function Description
TEST
28, 29,
48-51
22-25,
96-97
0.0 V
Factory testing (TMC22091 only). Reserved for factory
testing. These pins have no effect on the operation but do
function as JTAG registers. They should be grounded directly
or pulled down to ground with 1kΩ or smaller resistors.
NC
N/A
1, 3, 7,
11-12,
No Connect
28-30,
52-55,
69, 78-79
Control Registers
The TMC22x91 is initialized and controlled by a set of regis-
ters. The registers are organized into 13 categories:
contents or those of the Control Registers. The port is
governed by pins CS, R/W, and A
.
1-0
1. Global Control
2. Format Control
3. Interface Control
4. Test Control
The Address Register for the CLUT and the Control Register
pointer automatically increment to allow successive writes to
sequential addresses. In the CLUT, the Address Register has
two additional bits which increment in modulo-three to
sequentially access the red, green, and blue portions. All
three colors must be written when any CLUT address is
changed.
5. Key Control
6. Misc. Control
7. Standards Control
8. Layering Control (TMC22191)
9. Key Value
The control register autoincrement follows the sequence
indicated in the Control Register Map. When it reaches
address 40, it stops incrementing, allowing multiple reads or
writes of test data from/to the TESTDAT register. To exit the
test mode, reset the Control Register pointer by setting A
,
10. Timing
1-0
D , and R/W LOW and then bring CS LOW. Address 1F is
7-0
11. Subcarrier
a read-only status register. It is addressed by the autoincre-
ment sequencer. Any data may be written into this port at
that time but it will not be stored. When address 50 is
accessed, no autoincrement takes place, allowing multiple
writes to the Mask Register.
12. Test I/O
13. Mask Register
An external controller loads the Control Registers through a
standard interface port. It also loads the CLUT and reads its
10
PRODUCT SPECIFICATION
TMC22091/TMC22191
Table 2. Microprocessor Port Control
Table 3. Control Register Map (continued)
Reg Bit Name Function
A
1-0
R/W
Action
00
00
01
01
10
10
11
11
0
Write D
pointer
into Control Register
7-0
02
02
02
2
1
0
FBDIS
Frame buffer signals
disable
1
0
1
0
1
0
1
Read Control Register pointer
on D
PDCDIR
FLDLK
PDC master, slave
select
7-0
Write D
Pointer
into CLUT Address
7-0
Field lock select
Test Control Register
Read CLUT Address Pointer on
03
03
7
6
Reserved
D
7-0
LIMEN
Luminance limiter
enable
Write D
7-0
Register
to addressed Control
03
03
03
5
4
3
TESTEN
HOLDEN
TSTMSB
Test enable
Read addressed Control
Register on D
7-0
to addressed CLUT
MSBs/LSBs hold select
Write D
7-0
LSBs, MSBs in/out
select
location
Read addressed CLUT location
on D
03
03
2
1
LUMTST
8FSUBR
LUMA channel test
7-0
8-field subcarrier reset
enable
03
0
CHRTST
CHROMA channel test
Table 3. Control Register Map
Key Control Register
04
04
04
04
7
6
5
4
Reserved
Reg Bit Name
Function
HKEN
Hardware key enable
Burst key enable
Global Control Register
BUKEN
SKEXT
00
00
00
7-5
4
Reserved
Data key operation
select
SRESET
PAL
Software reset
3
Standard select, NTSC
or PAL
04
04
04
04
3
2
1
0
DKDIS
EKDIS
FKDIS
SKEN
Green/red/Y data key
disable
00
00
2
1
LUMDIS
CHRDIS
Luminance input disable
Blue/green/C data key
B
disable
Chrominance input
disable
Red/blue/C data key
R
disable
00
0
HRESET
Software reset disable
Format Control Register
Data key enable
01
01
7
6
Reserved
Layering Control Register (TMC22191)
LCREN
Layering Control
Register enable
(TMC22191)
04
7
LAYMODE MSB of Layer
Assignments select
04
04
04
6
5
4
HKEN
Hardware key enable
Burst key enable
01
01
01
5
4
RAMPEN
CB
Modulated ramp test
Color bar test
BUKEN
SKEXT
Data key operation
select
3-2 FORMAT
PD
23-0
input format
select
04
04
3-1 LAYMODE LSBs of Layer
Assignments select
01
1-0 INMODE
PD
23-0
select
input mode
0
SKEN
Data key enable
Interface Control Register
Key Value Registers
02
02
02
02
7
6
VITSEN
SHCY
VITS lines enable
05
7-0 DKEY
Green/red/Y data key
value
Short-cycle test mode
Time-base source select
Sync output mode select
5-4 TBASE
SOUT
06
7-0 EKEY
Blue/green/C data key
B
value
3
11
TMC22091/TMC22191
PRODUCT SPECIFICATION
Table 3. Control Register Map (continued)
Table 3. Control Register Map (continued)
Reg Bit Name Function
Reg Bit Name
Function
07
7-0 FKEY
Red/blue/C data key
R
value
19
1A
7-0 FP
7-0 EL
Front porch length
Equalization pulse LOW
length
08-0D
Reserved
Misc. Control Register
1B
1C
1D
7-0 EH
7-0 SL
7-0 SH
Equalization pulse HIGH
length
0E
0E
0E
0E
7
6
5
4
EFEN
Register 0E and 0F
enable
Vertical sync LOW
length
COMPD/A
SVIDD/A
FKREN
COMPOSITE D/A
disable
Vertical sync HIGH
length
LUMA/CHROMA D/A
disable
1E
1F
1F
7-0 CBL
Color bar length
Luminance processing
enabled
7-5 FIELD
4-0 LTYPE
Field identification
Line type identification
0E
0E
3
2
RATIO
TFLK
Luminance ratio select
Subcarrier Registers
Luminance pass
threshold select
20
21
22
23
7-0 FREQL
7-0 FREQ3
7-0 FREQ2
7-0 FREQM
Subcarrier frequency 4th
byte (LSBs)
0E
0E
1
0
T512
EH/SL offset select
Subcarrier frequency 3rd
byte
CB100
NTSC/PAL Color Bars
Standards Control Register
Subcarrier frequency
2nd byte
0F
0F
0F
7
6
5
4
EFEN
SIX25
PALID
SETUP
Same as Reg 0E bit 7
but read-only
Subcarrier frequency 1st
byte (MSBs)
625/525 line per frame
select
24
25
7-0 SYSPHL
7-0 SYSPHM
Video phase offset LSBs
Phase alternate line
select
Video phase offset
MSBs
0F
0F
0F
7.5 IRE Pedestal Enable
Luminance gain settings
26
27
7-0 BURPHL
7-0 BURPHM
Burst phase offset LSBs
Burst phase offset MSBs
Reserved
3-2 YGAIN
1-0 CGAIN
Chrominance gain
settings
28-3F
Test I/O Register
Timing Registers
40
7-0 TESTDAT
Test data input/output
Mask register
10
7-0 SY
Horizontal sync tip
length
Mask Register
50
7-0 MASK
11
12
13
14
7-0 BR
7-0 BU
7-0 CBP
7-0 XBP
Breezeway length
Burst length
Y-Component Register
60
7-0
Y
Y-component input/
output
Color back porch length
Extended color back
porch 8 LSB
Notes:
1. Functions are listed in the order used for reading and
writing.
2. For each register listed above, all bits not listed are
reserved and should be set to zero to ensure proper
operation.
3. The meaning of Register 04 (Key Control Register/Layer-
ing Control Register) is determined by Format Control
Register bit 6 (TMC22191).
15
16
17
18
7-0 VA
7-0 VC
7-0 VB
7-6 XBP
Active video 8 LSB
Active video start 8 LSB
Active video end 8 LSB
Extended color back
porch 2 MSB
18
18
18
5-4 VA
3-2 VC
1-0 VB
Active video 2 MSB
Active video start 2 MSB
Active video end 2 MSB
12
PRODUCT SPECIFICATION
TMC22091/TMC22191
Control Register Definitions
Global Control Register (00)
7
6
5
4
3
2
1
0
Reserved
SRESET
PAL
LUMDIS
CHRDIS
HRESET
Reg
00
Bit
7-5
4
Name
Function
Reserved.
00
SRESET
Software reset. When LOW, resets and holds internal state machines and
disables outputs. When HIGH (normal), starts and runs state machines and
enables outputs.
00
00
00
00
3
2
1
0
PAL
Video standard select. When LOW, the NTSC standard is generated with 7.5
IRE pedestal. When HIGH, PAL standard video is generated. This bit is ignored
if Register 0E bit 7 is HIGH, enabling the 0E and 0F registers.
LUMDIS
CHRDIS
HRESET
Luminance input disable. When LOW (normal), luminance (Y) data from
external frame buffer is enabled. When HIGH, luminance (Y) data into the
TMC22x91 is forced to 0 IRE but sync pulses continue from the LUMA output.
Chrominance input disable. When LOW (normal), burst and frame buffer data
into the TMC22x91 are enabled. when HIGH, burst and frame buffer data are
suppressed, enabling monochrome operation.
Software reset enable. SRESET is forced LOW when the RESET pin is taken
LOW. State machines are reset and held. When HRESET is LOW, RESET may
be taken HIGH at any time. The TMC22x91 is enabled and a new frame is
begun with line 1, field 1 on the next PXCK after SRESET is set HIGH. The D/A
converters are powered down while RESET is LOW. When HRESET is HIGH,
a new frame is begun with line 1, field 1 on the next PXCK after RESET is taken
HIGH. SRESET is ignored. The D/A converters remain active during the reset
sequence.
13
TMC22091/TMC22191
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Format Control Register (01)
7
6
5
4
3
2
1
0
Reserved
LCREN
RAMPEN
CB
FORMAT
INMODE
Reg
Bit
Name
Function
Reserved.
01
01
7
6
LCREN
(TMC22191) Layering Control Register enable. When LOW, the Layering
Control Register is not available and Key Control Register functions are
enabled. In this mode, the TMC22191 functions like the TMC22091. When
HIGH, the Layering Control Register takes the place of the Key Control
Register and enables the layering functions. Data loaded into the Key or
Layering Control Registers will remain but have a different meaning if this bit is
changed.
01
01
01
5
RAMPEN
CB
Modulated ramp test. When LOW (normal), the TMC22x91 encodes and
outputs video corresponding to input data. When RAMPEN and CB are both
HIGH, an internally generated 40 IRE modulated ramp is produced, preempting
input data.
4
Color bar test. When HIGH (normal), the TMC22x91 encodes and outputs
video corresponding to input data. When CB, RAMPEN, and Format Control
Register bit 0 are LOW, internally generated color bars are produced,
preempting input data.
3-2
FORMAT
PD
23-0
input format select. Two bits select RGB, GBR, or YC C input data.
B R
When bits 3 and 2 are:
0 0 the CLUT output is interpreted as RGB and is converted to YC C .
B R
0 1 is reserved. Bits 3 and 2 must be 00 or 10 when the Layering Control
Register is enabled (TMC22191).
1 0 the CLUT output is interpreted as GBR, and is converted to YC C .
B R
1 1 the CLUT output is interpreted as YC C .
B R
01
1-0
INMODE
PD
input mode select. These two bits set up the TMC22x91 for either 444,
422, 15-bit, or 8-bit input modes.
23-0
0 0 24-bit/pixel GBR, RGB, or YC C 444 data enters from PD
B R 23-0
0 1 YC C 422 data enters from PD
; C and C alternate from PD
B R 23-8
R
B
15-8
1 0 15-bit/pixel GBR or RGB data from PD
14-0
1 1 8-bit/pixel color indexed data enters from PD
.
7-0
Bits 1 and 0 must be 00, 01, or 11 when the Layering Control Register is
enabled (TMC22191).
14
PRODUCT SPECIFICATION
TMC22091/TMC22191
Control Register Definitions (continued)
Interface Control Register (02)
7
6
5
4
3
2
1
0
VITSEN
SHCY
TBASE
SOUT
FBDIS
PDCDIR
FLDLK
Reg
Bit
Name
Function
02
02
02
7
VITSEN
VITS lines enable. When LOW, all UBB lines in the vertical interval are black
burst regardless of input data. When HIGH, all UBB lines in the vertical interval
become UVV active video and are dependent upon input data.
6
SHCY
Short-cycle test mode. When LOW, normal operation is enabled. when HIGH,
EH (equalization pulse HIGH length) and SL (vertical sync LOW length) are
shortened by 256.
5-4
TBASE
Time-base source select. These two bits set up the TMC22x91 for either
genlock or frame buffer control of timing. When bits 5 and 4 are:
0 0 the encoder counts out its own time-base from input clock PXCK.
0 1 the encoder locks to synchronizing signals from external genlock.
1 0 the encoder locks to synchronizing signals from frame buffer controller.
02
02
02
02
3
2
1
0
SOUT
Sync output mode select. When LOW, VHSYNC and VVSYNC output separate
horizontal and vertical sync pulses. When HIGH, composite sync (H and V) is
output on VVSYNC while horizontal sync is output on VHSYNC.
FBDIS
PDCDIR
FLDLK
Frame buffer signals enable. When LOW, VVSYNC and VHSYNC outputs to
frame buffer are enabled. When HIGH, VVSYNC and VHSYNC outputs to
frame buffer are disabled.
PDC master/slave select. When LOW, PDC is an output where the encoder is
requesting data from the frame buffer. When HIGH, PDC is an input, and
directs the encoder to accept data from the frame buffer.
Field lock select. When LOW, (in Slave mode) the encoder locks to each new
field. When HIGH, the encoder locks to field 1 only.
15
TMC22091/TMC22191
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Test Control Register (03)
7
6
5
4
3
2
1
0
Reserved
LIMEN
TESTEN
HOLDEN
TSTMSB
LUMTST
8FSUBR
CHRTST
Reg
Bit
Name
Function
Reserved.
03
03
7
6
LIMEN
Luminance limiter enable. When LOW, all luminance values are passed to
modulator. when HIGH, luminance values are limited to 101 IRE.
03
03
03
03
03
5
4
3
2
1
TESTEN
Test enable. When LOW, normal operation is enabled. When HIGH,
TESTDAT
(Register 40) is connected to the composite output (READ) and
7-0
D/A converters (WRITE) for test.
HOLDEN
TSTMSB
LUMTST
8FSUBR
MSBs/LSBs hold select. When LOW, alternates MSBs and LSBs in test, at
PXCK rate. When HIGH, reads/writes only MSBS or LSBS in test (per
TSTMSB, bit 3)
LSBS,MSBS hold select. When LOW, connects 2 LSBs to TESTDAT
for testing when TESTEN is HIGH. When HIGH, connects 8 MSBs to
1-0
TESTDAT
for testing when TESTEN is HIGH.
7-0
LUMA channel test. When LOW (normal), the luminance D/A converter is
driven from luminance channel. When HIGH, the luminance D/A converter is
driven from TESTDAT for testing when TESTEN is HIGH.
8-field subcarrier reset enable. When LOW, the internal subcarrier generator is
reset with frequency and phase data from FREQ, SYSPH, and BURPH
registers every eight fields. When HIGH, the internal subcarrier generator free-
runs on the basis of frequency and phase data from the last time it was reset.
When RESET goes LOW, the subcarrier frequency and phase will be reset
from FREQ, SYSPH, and BURPH after field 8.
03
0
CHRTST
CHROMA channel test. When LOW (normal), the chrominance D/A converter is
driven from chrominance channel. When HIGH, the chrominance D/A converter
is driven from TESTDAT when TESTEN is HIGH.
16
PRODUCT SPECIFICATION
TMC22091/TMC22191
Control Register Definitions (continued)
Key Control Register (04)
7
6
5
4
3
2
1
0
Reserved
HKEN
BUKEN
SKEXT
DKDIS
EKDIS
FKDIS
SKEN
Reg
Bit
Name
Function
04
04
7
6
Reserved.
HKEN
Hardware key enable. When LOW, the KEY input pin ignored. When HIGH, the
KEY input pin is enabled.
04
04
04
5
4
3
BUKEN
SKEXT
DKDIS
Burst key enable. When LOW, output video burst is generated on TMC22x91.
When HIGH, output burst is taken from genlock input data.
Data key operation select. When LOW, data keying is allowed only during
active video. When HIGH, keying is allowed during active video and blanking.
Green/red/Y data key disable. When LOW, green/red/Y input data is enabled
for data keying. When HIGH, green/red/Y input data is ignored for data keying.
This function is enabled when Layering Control Register is enabled
(TMC22191).
04
04
04
2
1
0
EKDIS
FKDIS
SKEN
Blue/green/C data key disable. When LOW, Blue/green/C input data is
B B
enabled for data keying. When HIGH, Blue/green/C input data is ignored for
B
data keying. This function is enabled when Layering Control Register is
enabled (TMC22191).
Red/blue/C data key disable. When LOW, red/blue/C input data is enabled
R
R
for data keying. When HIGH, red/blue/C input data is ignored for data keying.
R
This function is enabled when Layering Control Register is enabled
(TMC22191).
Data key enable. When LOW, data keying is disabled. When HIGH, data keying
is enabled.
17
TMC22091/TMC22191
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Layering Control Register (04) (TMC22191)
7
6
5
4
3
2
1
0
LAYMODE
HKEN
BUKEN
SKEXT
LAYMODE
SKEN
Reg
Bit
7
Name
Function
04
04
LAYMODE
HKEN
MSB of Layer Assignments select.
6
Hardware key enable. When LOW, the KEY input pin ignored. When HIGH, the
KEY input pin is enabled.
04
04
5
4
BUKEN
SKEXT
Burst key enable. When LOW, output video burst is generated on TMC22191.
When HIGH, output burst is taken from genlock input data.
Data key operation select. When LOW, data keying is allowed only during
active video. When HIGH, data keying is allowed during active video and
blanking.
04
04
3-1
0
LAYMODE
SKEN
Three LSBs of Layer Assignments select.
Data key enable. When LOW, data keying is disabled. When HIGH, data keying
is enabled.
Key Value Registers (05-07)
Reg
Bit
Name
Function
05
7-0
DKEY
Green/red/Y data key value. Eight bits hold the match value which triggers
keying on red/Y.
06
07
7-0
7-0
EKEY
FKEY
Blue/green/U data key value. Eight bits hold the match value which triggers
keying on green/U.
Red/blue/V key value. Eight bits hold the match value which triggers keying on
blue/V.
18
PRODUCT SPECIFICATION
TMC22091/TMC22191
Control Register Definitions (continued)
Miscellaneous Control Register (0E)
7
6
5
4
3
2
1
0
EFEN
COMPD/A
SVIDD/A
FKREN
RATIO
TFLK
T512
CB100
Reg
Bit
Name
Function
0E
7
EFEN
Register 0E and 0F enable. When LOW, the functions of Register 0E and 0F
are disabled. When HIGH, Registers 0E and 0F are active. When Registers 0E
and 0F are enabled, Register 00 bit 3 is ignored. Register 0E bit 7 will read back
whatever value was written.
0E
0E
0E
6
5
4
COMPD/A
SVIDD/A
FKREN
COMPOSITE D/A disable. When HIGH, the COMPOSITE D/A converter is
powered-down. When LOW, the D/A is enabled.
LUMA/CHROMA D/A disable. When HIGH, the LUMA and CHROMA D/A
converters are powered-down. When LOW, they are enabled.
Luminance processing enable. When FKREN is HIGH, the KEY input defines
the function of CVBS input data. When the KEY input is HIGH, CVBS data is
keyed over PD input data. When KEY is LOW, CVBS data is assumed to be
luminance data delayed by one When FKREN is LOW, the KEY input operates
normally, switching between CVBS and PD data.
0E
0E
3
2
RATIO
TFLK
Luminance ratio control bit. When LOW, 1/2 of current luminance and 1/2 of
field delayed luminance from the CVBS input are added to yield a new
combined luminance value. When RATIO is HIGH, 3/4 of current luminance is
added to 1/4 of the delayed luminance to produce a new luminance value.
Luminance-pass threshold. The difference between current luminance and
delayed luminance (from the CVBS inputs) is compared against a preset
threshold set by TFLK. When TFLK is LOW, the high threshold must be
exceeded to trigger the combining of current and delayed luminance (according
to RATIO). If the higher threshold is not exceeded, current luminance is passed
without modification. When TFLK is HIGH, a lower threshold is used to trigger
the combining of current and delayed luminance.
0E
0E
1
0
T512
EH/SL offset control bit. When LOW, the true value of EH and SL is offset by
256. When HIGH, the true value for EH and SL is offset by 512.
CB100
NTSC/PAL color bars select. When HIGH, color bars with 100% white level are
selected. When LOW, color bars will have 75% white level.
19
TMC22091/TMC22191
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Standards Control Register (0F)
7
6
5
4
3
2
1
0
EFEN
SIX25
PALID
SETUP
YGAIN
CGAIN
Reg
Bit
7
Name
EFEN
SIX25
Function
0F
0F
Same as Register 0E bit 7, but read-only.
6
Select 625 lines per frame. When HIGH, the encoder assumes 625 line per
frame. When LOW, 525 lines per frame are assumed.
0F
0F
0F
5
PALID
SETUP
YGAIN
PAL select. When HIGH, Phase alternate line (PAL) operation is selected.
When LOW, operation conforms to NTSC standards.
4
Setup enable. When HIGH, a 7.5 IRE Pedestal is added to the output video.
when LOW, no pedestal is added.
3-2
Luminance gain settings are adjusted to conform to the following NTSC and
PAL standards:
0 0 NTSC without SETUP
0 1 NTSC-A and PAL-M
1 0 PAL-I and PAL-N
1 1 Reserved
0F
1-0
CGAIN
Chrominance gain settings are adjusted to conform to the following NTSC and
PAL standards:
0 0 NTSC without SETUP
0 1 NTSC-A and PAL-M
1 0 PAL-I and PAL-N
1 1 Reserved
Timing Registers (10-17)
Reg
Bit
Name
Function
10
7-0
SY
Horizontal sync tip length. This 8-bit register holds a value extending from 0 to
255 PCK cycles.
11
12
13
14
7-0
7-0
7-0
7-0
BR
Breezeway length. This 8-bit register holds a value extending from 0 to 255
PCK cycles.
BU
Burst length. This 8-bit register holds a value extending from 0 to 255 PCK
cycles.
CBP
XBP
Color back porch length. This 8-bit register holds a value extending from 0 to
255 PCK cycles.
Extended color back porch 8 LSBs. This 8-bit register holds the LSBs of a
10-bit value extending from 0 to 1023 PCK cycles. The two MSBs are located in
control register 18.
15
16
17
7-0
7-0
7-0
VA
VC
VB
Active video 8 LSBs. This 8-bit register holds the LSBs of a 10-bit value
extending from 0 to 1023 PCK cycles. The two MSBs are located in control
register 18.
Active video start 8 LSBs. This 8-bit register holds the LSBs of a 10-bit value
which is the initial half active video length extending from 0 to 1023 PCK cycles.
The two MSBs are located in control register 18.
Active video end 8 LSBs This 8-bit register holds the LSBs of a 10-bit value
which is the end half active video length extending from 0 to 1023 PCK cycles.
The two MSBs are located in control register 18.
20
PRODUCT SPECIFICATION
TMC22091/TMC22191
Control Register Definitions (continued)
Timing Register (18)
7
6
5
4
3
2
1
0
XBP
Bit
VA
VC
VB
Reg
Name
Function
18
7-6
XBP
Extended color back porch 2 MSBs. These two bits hold the MSBs of a 10-bit
value extending from 0 to 1023 PCK cycles. The LSBs are located in control
register 14.
18
18
5-4
3-2
VA
VC
Active video 2 MSB. These two bits hold the MSBs of a 10-bit value extending
from 0 to 1023 PCK cycles. The LSBs are located in control register 15.
Active video start 2 MSBs. These two bits hold the MSBs of a 10-bit value which
is the initial half active video length extending from 0 to 1023 PCK cycles. The
LSBs are located in control register 16.
18
1-0
VB
Active video end 2 MSBs. These two bits hold the MSBs of a 10-bit value which
is the end half active video length extending from 0 to 1023 PCK cycles. The
LSBs are located in control register 17.
Timing Registers (19-1E)
Reg
Bit
Name
Function
19
7-0
FP
Front porch length. This 8-bit register holds a value extending from 0 to 255
PCK cycles.
1A
1B
7-0
7-0
EL
Equalization pulse LOW length. This 8-bit register holds a value from 0 to 255
PCK cycles.
EH
Equalization pulse HIGH length. This 8-bit register holds a value extending from
0 to 255 PCK cycles. This value, when added to 256 (or 512), determines the
final pulse length in the range of 256 to 511 (or 767) PCK cycles.
1C
7-0
SL
Vertical sync LOW length. This 8-bit register holds a value from 0 to 255 PCK
cycles. This value, when added to 256 (or 512), determines the final pulse
length in the range of 256 to 511 (or 767) PCK cycles.
1D
1E
7-0
7-0
SH
Vertical sync HIGH length. This 8-bit register holds a value extending from 0 to
255 PCK cycles.
CBL
Color bar length. This 8-bit register holds a value which is the length of each
color bar displayed extending from 0 to 255 PCK cycles.
Timing Register (1F)
7
6
5
4
3
2
1
0
FIELD
LTYPE
Reg
Bit
Name
Function
1F
7-5
FIELD
Field identification (read only). These three bits are updated 12 PXCK periods
after each VHSYNC. They allow the user to determine field type on a
continuous basis.
1F
4-0
LTYPE
Line type identification (read only). These five bits are updates 5 PXCK periods
after each VHSYNC. They allow the user to determine line type on a continuous
basis.
21
TMC22091/TMC22191
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Subcarrier Registers (20-27)
Reg
Bit
Name
Function
20
7-0
FREQL
Subcarrier frequency 4th byte (LSBs). This 8-bit register holds the LSB (bits
7-0) of the 32-bit subcarrier frequency value (non-genlock modes). The next
eight most significant bits are held in Register 21.
21
22
7-0
7-0
FREQ3
FREQ2
Subcarrier frequency 3rd byte. This 8-bit register holds bits 15:8 of the
subcarrier frequency value (non-genlock modes). The next eight most
significant bits are held in Register 22.
Subcarrier frequency 2nd byte. This 8-bit register holds bits 23-16 of the
subcarrier frequency value (non-genlock modes). The eight MSBs are held in
Register 23.
23
24
25
26
27
7-0
7-0
7-0
7-0
7-0
FREQM
Subcarrier frequency 1st byte (MSBs). This 8-bit register holds the MSBs (bits
31-24) of the 32-bit subcarrier frequency value (non-genlock modes).
SYSPHL
SYSPHM
BURPHL
BURPHM
Video phase offset LSBs. This 8-bit register holds the 8 LSBs of color subcarrier
phase offset during active video.
Video phase offset MSBs. This 8-bit register holds the 8 MSBs of color
subcarrier phase offset during active video.
Burst phase offset LSBs. This 8-bit register holds the 8 LSBs of burst phase
offset for color adjustment.
Burst phase offset MSBs. This 8-bit register holds the 8 MSBs of burst phase
for color adjustment.
Test I/O Register (40)
Reg
Bit
Name
Function
40
7-0
TESTDAT
Test data input/output. This 8-bit register holds MSBs or LSBs, as determined
by the Test Control Register. This control address does not auto-increment
during read or write operations. To exit the test mode, reset the Control
Register pointer by setting A
and R/W LOW and then bring CS LOW.
1-0
Mask Register (50)
Reg
Bit
Name
Function
50
7-0
MASK
Mask register. This 8-bit register holds an 8-bit word that is logically ANDed with
the incoming data presented to the three CLUTs in color-index mode. This
register is a write-only register.
Y-Component Register (60)
Reg
Bit
Name
Function
60
7-0
Y
Y-component register. This register holds the contents of the luminance value
before the Sync and Blank Insert circuitry of the encoder. Loading the Control
Register pointer with 60 brings 8-bit Y values out on the D
port.
h
7-0
22
PRODUCT SPECIFICATION
TMC22091/TMC22191
Color Lookup Table
The CLUT can be used in a variety of ways, depending on
the data format and source presented to the PD port.
gamma correction, are easily loaded. The color data is
loaded into the tables in G-B-R sequence in GBR mode, and
R-G-B sequence in RGB mode.
The CLUT is loaded like a RAMDAC, sequentially writing
one byte to each of the three locations associated with the
selected CLUT address. These three locations are referred to
as Tables D, E, and F as shown in table 16 (not R,G, and B
because they may or may not contain RGB information). and
are loaded in that sequence. The address will increment auto-
matically after the three values at one address are written or
read.
Luminance/Color Difference Modes
The TMC22x91 expects Y, B-Y, and R-Y signals at the input
to its modulator section. When presenting CCIR-601YC C
or digitizedY, B-Y, R-Y data to the CLUT, gain and offset fac-
tors are needed. Table 4 specifies the recommended transfer
B R
functions. The CLUT is loaded inY-C -C sequence.
B
R
Overlay Operation
For the TMC22091 and TMC22191 (when Format Control
Color-index Modes
In color-index (CI) mode, the CLUT is used to store the
color look-up data, translating the 8-bit source pixel data into
24-bit RGB colors. Table D holds red data, Table E is green
data, and Table F holds blue Data. The incoming data are
presented to the three tables in parallel, and a 24-bit output is
produced.
Register Bit 6 = LOW), the OL inputs are inactive. In
4-0
CCIR-601 operation, the nominal data range forY is from 16
to 235 and for C and C is from 16 to 240. This means that
B
R
CLUT locations 0 to 15 and 241 to 255 are available for
overlay colors. When the overlay locations are addressed (by
forcing CLUT addresses outside the normal CCIR-601 data
range), the addressed CLUT data is encoded resulting in the
specific color found in that CLUT location. Overlay colors
information stored in the unused CLUT locations must be Y,
B-Y, R-Y values. Y, B-Y, and R-Y values are found from
RGB values by:
When the encoder is connected in parallel with a RAMDAC
in a VGA system, the CLUT can be loaded simultaneously
with the CLUT in the output RAMDAC. If a 6-bit RAMDAC
is employed, 6 bits can be loaded via data pins D (MSB
7-2
justified). The two LSBs should be set to 00 for optimal
black level representation, but the largest error introduced by
extraneous data in the LSBs is 3/4 LSB (at 6 bits). The
encoder will produce the closest possible translation of the
VGA colors in the encoded video environment.
Y = 0.299 R + 0.587 G + 0.114 B
B-Y = -0.299 R – 0.587 G + 0.886 B
R-Y = 0.701 R – 0.587 G – 0.114 B
For the TMC22191, when the Format Control Register
GBR/RGB Modes
Bit 6 = HIGH, Overlay is controlled by the OL inputs
4-0
The nominal configuration for GBR/RGB modes is unity
gain (CLUT data = CLUT address) for PAL and NTSC.
Other transfer functions, such as gain adjustment, offset, and
which directly access CLUT locations, 01 thru 0F and F1
thru FF, as shown in Table 5. The values stored in these
CLUT locations must be in RGB format.
Table 4. CLUT Transfer Functions for NTSC and PAL
Input Format (CLUT Address)
Output Format (CLUT Data)
Component
Data Range
0 to 255
0 to 255
0 to 255
16 to 235
±112
Transfer Equations
R =R
Component
Data Range
0 to 255
0 to 255
0 to 255
0 to 255
±113
R
G
B
Y
R
O
0
G =G
0
G
O
O
B =B
0
B
Y = Y * 1.1644 – 18.63
O
Y
O
C
B
C
R
(B-Y) = C * 1.0126
(B-Y)
(R-Y)
O
B
O
±112
(R-Y) = C * 0.8011
±90
O
R
O
Y
0 to 255
±127
Y =Y
Y
0 to 255
±113
0
O
B-Y
R-Y
(B-Y) = (B-Y) * 0.893
(B-Y)
O
O
±127
(R-Y) = (R-Y) * 0.7065
(R-Y)
±90
O
O
23
TMC22091/TMC22191
PRODUCT SPECIFICATION
Table 5. CLUT Locations Addressed by
Overlay Inputs (TMC22191)
Table 5. CLUT Locations Addressed by
Overlay Inputs (TMC22191) (continued)
OL4-0
00
CLUT location
OL4-0
1E
CLUT location
No Overlay
FE
FF
01
01
02
1F
02
Color-space Conversion in the Matrix
•
•
•
•
When the input pixels are in RGB, GBR, or color-index for-
mat and the CLUT is bypassed (TMC22191), the Matrix
remains enabled, converting RGB data to color-difference
format. When the input pixels are in 444 format
(YC C 444, RGB, GBR, CI), the Interpolator (which con-
verts 422 to 444) is not active. When the input pixels are in
0E
0F
10
11
12
0E
0F
No Overlay
F1
B R
YC C format, the CLUT is enabled to scale the data to
B R
color-difference values and the Matrix is inactive. In color-
index mode, the Matrix is active, converting the RGB CLUT
output data to color-difference values.
F2
•
•
•
•
Table 6. Pixel Input Operation for Format Control Register bit 6 = HIGH (TMC22191)
Format Control Register Pixel Data Format
FORMAT
INMODE
BYPASS = LOW
BYPASS = HIGH
Bit 3,2
Bit 1,0
CLUT bypassed
CLUT enabled
00 (RGB)
00 (444)
01 (422)
10 (15-bit)
11 (CI)
xx
RGB
YC C 444
B R
00
00
RGB
YC C 422
B R
RGB
RGB15
CI
00
RGB
01
reserved
GBR
reserved
10 (GBR)
10
00 (444)
01 (422)
10 (15-bit)
11 (CI)
xx
YC C 444
B R
GBR
YC C 422
B R
10
GBR
GBR15
CI
10
GBR
11
not allowed
not allowed
Format Control Register Bit 6 = HIGH
Format Control Register Bit 6 = LOW
MSB
LSB
0
MSB
LSB
0
16 15
8 7
16 15
8 7
23
23
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Y1
Y2
Y3
Y4
CB1
CB1
CB3
CB3
CR1
CR1
CR3
CR3
Y1
Y2
Y3
Y4
CB1
CR1
CB3
CR3
Pixel n
Pixel n
Yn
Yn+1
CBn
CBn
CRn
CRn
Yn
Yn+1
CBn
CRn
Pixel n+1
Pixel n+1
27003A
Note: The pixel input sequence begins on the first LDV pulse after PDC goes HIGH. n = Odd number
Figure 2. Pixel Data (PD ) Sequence for YC C 422
23-0
B R
24
PRODUCT SPECIFICATION
TMC22091/TMC22191
Table 7. Horizontal Timing Specifications
Gamma Correction
NTSC-M
(µs)
PAL-I
(µs)
PAL-M
(µs)
Gamma is built into broadcast television systems as a correc-
tion factor for nonlinearity in image acquisition (nonlinear
conversion of light into current in a vidicon) and at the dis-
play (phosphor nonlinearity in converting current into light).
Parameter
FP
SY
BR
BU
CBP
VA
1.5
4.7
1.65
4.7
1.9
4.95
0.6
0.9
0.9
A Gamma corrector transfer function takes the form of
Output = k ( Input )1/γ
2.5
2.25
2.55
51.95
64.0
2.25
1.6
1.8
where a typical Gamma is 2.2 for NTSC, 2.8 for PAL.
52.6556
63.5556
51.692
63.492
H
Computer systems usually ignore Gamma in driving a dis-
play monitor. Each R, G, and B channel is treated as linear.
When encoding a computer display output to video, the user
must decide whether to apply a gamma correction factor and,
if so, what value. It is a good assumption that, since the digi-
tal video input over the CVBS bus is in composite form, it
has been Gamma corrected.
Vertical Programming
Vertical interval timing is also fully programmable, and is
established by loading the timing registers with the durations
of each vertical timing element, the duration expressed in
PCK clock cycles. In this way as with horizontal program-
ming, any pixel rate between 10 and 15 Mpps can be accom-
modated, and any desired standard or non-standard vertical
video timing may be produced.
Gamma correction is applied in the RGB domain. When
operating in YC C , for example when encoding a CCIR-
B R
601 signal, Gamma should have already been applied.
Gamma correction is readily added to the RGB transfer
equations shown in Table 4.
Like horizontal timing parameters, vertical timing parame-
ters are calculated as follows:
t = N x (PCK period)
= N x (2 x PXCK period)
Video Timing
The TMC22x91 can be programmed to accommodate a wide
range of system timing requirements. With a line locked
pixel rate of 10 to 15 Mpps, the digitally synthesized hori-
zontal waveforms and subcarrier frequency and phase are
determined from 24 registers that are loaded by a controller.
where N is the value loaded into the appropriate timing reg-
ister, and PCK is the pixel clock period.
The Vertical Interval comprises several different line types
based upon H, the Horizontal line time.
Horizontal Programming
H = (2 x SL) + (2 x SH) [Vertical sync pulses]
= (2 x EL) + (2 x EH) [Equalization pulses]
Horizontal interval timing is fully programmable, and is
established by loading the timing registers with the durations
of each horizontal element. The duration is expressed in
PCK clock cycles. In this way, any pixel clock rate between
10 MHz and 15 MHz can be accommodated, and any desired
standard or non-standard horizontal video timing may be
produced. Figure 3 illustrates the horizontal blanking inter-
val with timing register identification.
The VB and VC lines are added to produce the half-lines
needed in the vertical interval at the beginning and end of
some fields. These must properly mate with components of
the normal lines.
VB = CBP + VA - XBP = H/2 – CBPVC
= VA – (EL + EH) = VA – H/2
Horizontal timing parameters can be calculated as follows:
where Equalization HIGH and LOW pulses (EL + EH) = H/2
and the Extended Color Back Porch, XBP = VA + CBP –VB.
XBP begins after the end of burst, BU, taking the place of
CBP in vertical interval UBV lines. Figure 5 shows the verti-
cal sync and equalization pulse detail
t = N x (PCK period)
= N x (2 x PXCK period)
where N is the value loaded into the appropriate timing reg-
ister, and PCK is the pixel clock period.
Table 8. Vertical Timing Specifications
Horizontal timing resolution is two PXCK periods. PXCK
must be chosen such that it is an even integer multiple of the
horizontal line frequency. This ensures that the horizontal
line period, H, contains an integer number of pixels. The hor-
izontal line comprises the sum of appropriate elements.
Parameter
NTSC-M
PAL-I
PAL-M
(µs)
(µs)
(µs)
(µs)
H
63.5556
29.4778
2.3
64
29.65
2.35
4.7
63.492
29.45
2.3
EH
EL
SH
SL
H = FP + SY + BR + BU + CBP + VA
When programming horizontal timing, subtract 5 PCK
periods from the calculated values of CBP and add 5 PCK
periods to the calculated value for VA.
4.7
4.65
27.1
27.3
27.1
25
TMC22091/TMC22191
PRODUCT SPECIFICATION
H
H/2
SL
Burst
BU
EH
VA
FP
SY
FP
VA
EL
SH
24319A
FP
24318B
Figure 3. Horizontal Blanking Interval Timing
Figure 4. Sync and Equalization Pulse Detail Timing
FIELDS 1 AND 3
VERTICAL BLANKING
21
22
524
523
PRE-EQUALIZATION
3H
VERTICAL SYNC
3H
POST-EQUALIZATION
3H
1
2
3
4
5
6
7
8
9
10
19
20
UBB
UBB
UVV
UVV
UVV
UVV
EE
EE
EE
SS
SS
SS
EE
EE
EE
UBB
VHSYNC
VVSYNC
COMPOSITE
SYNC
283
284
285
262
263
FIELDS 2 AND 4
264
EE
265
266
267
SS
268
SS
269
SE
270
EE
271
EE
272
EB
273
282
UBB
UBV
UVV
UVV
UVV
UVE
EE
ES
UBB
VHSYNC
VVSYNC
COMPOSITE
SYNC
27000A
Figure 5. NTSC Vertical Interval
26
PRODUCT SPECIFICATION
TMC22091/TMC22191
Table 9. NTSC Field/Line Sequence and Identification
Field 1
Field 2
Field 3
Field 4
FIELD ID = x00
FIELD ID = x01
FIELD ID = x10
FIELD ID = x11
Line
ID
EE
LTYPE
Line
ID
EE
LTYPE
Line
ID
EE
LTYPE
Line
264
265
266
267
268
269
270
271
272
273
•••
ID
EE
LTYPE
00
1
2
00
00
00
03
03
03
00
00
00
0D
•••
0D
0F
0F
•••
0F
0C
264
265
266
267
268
269
270
271
272
273
•••
00
00
01
03
03
02
00
00
10
0D
•••
0D
0E
0F
•••
0F.
0F
1
2
00
00
00
03
03
03
00
00
00
0D
•••
0D
0F
0F
•••
0F
0C
EE
EE
EE
EE
00
3
EE
ES
3
EE
ES
01
4
SS
SS
4
SS
SS
03
5
SS
SS
5
SS
SS
03
6
SS
SE
6
SS
SE
02
7
EE
EE
7
EE
EE
00
8
EE
EE
8
EE
EE
00
9
EE
EB
9
EE
EB
10
10
•••
20
21
22
•••
262
263
UBB
•••
UBB
•••
10
•••
20
21
22
•••
262
263
UBB
•••
UBB
•••
0D
•••
UBB
UVV
UVV
•••
282
283
284
•••
UBB
UBV
UVV
•••
UBB
UVV
UVV
•••
282
283
284
•••
UBB
UBV
UVV
•••
0D
0E
0F
•••
UVV
UVE
524
525
UVV
UVV
UVV
UVE
524
525
UVV
UVV
0F
0F
EE
SS
EB
UVV
UBV
Equalization pulse
Vertical sync pulse
Equalization broad pulse
Active video
SE
ES
UBB
UVE
Half-line vertical sync pulse, half-line equalization pulse
Half-line equalization pulse, half-line vertical sync pulse
Black burst
Half-line video, half-line equalization pulse
Half-line black, half-line video
Master and Genlock mode details of VHSYNC, VVSYNC,
and composite VVSYNC (SOUT = HIGH) outputs are
shown in Figures 5 and 6. When VHSYNC and VVSYNC
are used as inputs (Slave mode), their falling edges mark the
beginning of the sync interval and the width of the input
pulse is specified under Operating Conditions.
27
TMC22091/TMC22191
PRODUCT SPECIFICATION
1247
1248
VE
FIELDS 1 AND 5
24
25
26
1249
1250
EE
1
2
3
4
5
6
7
22
23
UBB
UBV
UVV
UVV
UVV
EE
SS
SS
SE
EE
EE
BB
UBB
UBB
VHSYNC
VVSYNC
COMPOSITE
SYNC
336
337
309
310
VV
FIELDS 2 AND 6
311
EE
312
313
314
SS
315
SS
316
EE
317
EE
318
EB
319
320
334
335
UBB
UBV
UVV
UVV
UVV
EE
ES
UBB
UBB
VHSYNC
VVSYNC
COMPOSITE
SYNC
622
623
VE
FIELDS 3 AND 7
649
650
651
624
EE
625
EE
626
627
SS
628
SE
629
EE
630
EE
631
632
647
648
UBB
UBV
UVV
UVV
UVV
SS
UBB
UBB
UBB
VHSYNC
VVSYNC
COMPOSITE
SYNC
961
962
934
935
UV
FIELDS 4 AND 8
936
EE
937
938
939
SS
940
SS
941
EE
942
EE
943
EB
944
BB
945
959
960
UBB
UBV
UVV
UVV
UVV
EE
ES
UBB
VHSYNC
VVSYNC
COMPOSITE
SYNC
27001A
Figure 6. PAL Vertical Interval
28
PRODUCT SPECIFICATION
TMC22091/TMC22191
Table 10. PAL Field/Line Sequence and Identification
Field 1
Field 2
Field 3
Field 4
FIELD ID = 000, 100
FIELD ID = 001, 101
FIELD ID = 010, 110
FIELD ID = 011, 111
Line
ID
SS
LTYPE
Line
ID
ES
LTYPE
Line
ID
SS
LTYPE
Line
938
939
940
941
942
943
944
945
•••
ID
ES
LTYPE
01
1
2
03
03
02
00
00
05
0D
0D
•••
0D
0E
0F
•••
0F
0F
07
00
00
313
314
315
316
317
318
319
320
•••
01
03
03
00
00
10
0D
0D
•••
0D
0F
0F
•••
0F
07
04
00
00
626
627
628
629
630
631
632
633
•••
03
03
02
00
00
0D
0D
0D
•••
SS
SS
SS
SS
03
3
SE
SS
SE
SS
03
4
EE
EE
EE
EE
00
5
EE
EE
EE
EE
00
6
-BB
UBB
UBB
•••
EB
UBB
UBB
UBB
•••
EB
10
7
UBB
UBB
•••
-BB
UBB
•••
05
8
0D
•••
•••
22
23
24
•••
308
309
310
311
312
UBB
UBV
UVV
•••
335
336
337
•••
UBB
UVV
UVV
•••
647
648
649
•••
UBB
UBV
UVV
•••
0D
0E
0F
•••
960
961
962
•••
UBB
UVV
UVV
•••
0D
0F.
0F
•••
UVV
UVV
-VV
EE
621
622
623
624
625
UVV
-VV
-VE
EE
933
934
935
936
937
UVV
UVV
UVV
EE
0F
0F
0F
00
00
1246
1247
1248
1249
1250
UVV
UVV
-VE
EE
0F
0F
04
00
EE
EE
EE
EE
00
EE
SS
EB
-BB
-VV
-VE
Equalization pulse
Vertical sync pulse
Equalization broad pulse
Black burst with color burst suppressed
Active video with color burst suppressed
Half-line video, half-line equalization
pulse, color burst suppressed.
SE
ES
UBB
UVV
UVE
UBV
Half-line vertical sync pulse, half-line equalization pulse
Half-line equalization pulse, half-line vertical sync pulse
Black burst
Active video
Half-line video, half-line equalization pulse
half-line black, half-line video
29
TMC22091/TMC22191
PRODUCT SPECIFICATION
521
522
18
FIELDS 1 AND 5
2
17
523
EE
524
EE
525
EE
1
3
4
5
6
7
8
9
UBB
UBB
UVV
UVV
UVV
SS
SE
SS
EE
EE
EE
BB
BB
VHSYNC
VVSYNC
COMPOSITE
SYNC
259
260
280
281
FIELDS 2 AND 6
261
262
263
264
265
266
267
268
269
270
271
279
UBB
UBV
UVV
UVV
UVV
VE
EE
EE
ES
SS
SS
SE
EE
EE
EB
BB
VHSYNC
VVSYNC
COMPOSITE
SYNC
18
521
522
VV
FIELDS 3 AND 7
17
523
EE
524
EE
525
EE
1
2
3
4
5
6
7
8
9
UBB
UBB
UBB
UVV
UVV
SS
SS
SS
EE
EE
EE
BB
VHSYNC
VVSYNC
COMPOSITE
SYNC
280
281
258
259
260
VE
FIELDS 4 AND 8
279
261
EE
262
EE
263
ES
264
265
266
SE
267
EE
268
EE
269
EB
270
BB
271
UBB
UBB
UBV
UVV
UVV
UV
SS
SS
VHSYNC
VVSYNC
COMPOSITE
SYNC
27082A
Figure 7. PAL-M Vertical Interval
30
PRODUCT SPECIFICATION
TMC22091/TMC22191
Table 11. PAL-M Field/Line Sequence and Identification
Field 1
Field 2
Field 3
Field 4
FIELD ID = 000, 100
FIELD ID = 001, 111
FIELD ID = 010, 110
FIELD ID = 011, 111
Line
ID
SS
LTYPE
Line
ID
ES
LTYPE
Line
ID
SS
LTYPE
Line
263
264
265
266
267
268
269
270
271
•••
ID
ES
LTYPE
01
1
2
03
03
03
00
00
00
05
05
0D
•••
0D
0F
···
263
264
265
266
267
268
269
270
271
•••
01
03
03
02
00
00
10
05
1D
•••
1
2
03
03
03
00
00
00
05
05
•••
0D.
0F
•••
0F
07
04
00
00
SS
SS
SS
SS
03
3
SS
SS
3
SS
SS
03
4
EE
SE
4
EE
SE
02
5
EE
EE
5
EE
EE
00
6
EE
EE
6
EE
EE
00
7
-BB
-BB
UBB
•••
EB
7
-BB
UBB
•••
EB
10
8
-BB
UBB
•••
8
-BB
UBB
•••
05
9
•••
17
18
•••
258
259
260
261
262
1D
•••
•••
17
18
···
259
260
261
262
UBB
UVV
•••
UBB
UVV
···
279
280
281
•••
UBB
UBV
UVV
•••
0D
0E.
0F
•••
279
280
281
•••
UBB
UBV
UVV
•••
0D
0E.
0F
•••
UVV
-VV
-VE
EE
UVV
-VE
EE
0F
04
00
00
521
522
523
524
525
UVV
-VV
EE
0F
07
00.
00
00
521
522
523
524
525
UVV
UVV
EE
0F
0F
00
EE
EE
EE
EE
00
EE
EE
00
EE
SS
EB
-BB
-VV
-VE
Equalization pulse
Vertical sync pulse
Equalization broad pulse
Black burst with color burst suppressed
Active video with color burst suppressed
Half-line video, half-line equalization
pulse, color burst suppressed.
SE
ES
UBB
UVV
UVE
UBV
Half-line vertical sync pulse, half-line equalization pulse
Half-line equalization pulse, half-line vertical sync pulse
Black burst
Active video
Half-line video, half-line equalization pulse
half-line black, half-line video
31
TMC22091/TMC22191
PRODUCT SPECIFICATION
Table 12. Standard Timing Parameters
Timing Register (hex)
Field Horizontal Pixel PXCK
2
2
Rate
(Hz)
Freq.
(kHz)
Rate
Freq. SY BR BU CBP XBP VA VC VB Note 1 FP EL EH SL SH CBL
Standard
(Mpps) (MHz) 10 11 12
13
14
15 16 17
18
19 1A 1B 1C 1D
1E
NTSC sqr. 59.94 15.734266 12.27 24.54 3A 07 1F
pixel
0F
23
8B 05 77
65
12 1C 6A 4C 3A
52
NTSC
CCIR-601
59.94 15.734266 13.50 27.00 40 08 22
13
12
21
22
21
13
13
15
3F CA 1D 9D
54 F7 30 B5
65
65
75
65
75
61
65
65
13 1F 8E 6E 3F
15 21 A6 84 43
19 23 B5 93 45
16 20 90 71 3F
19 23 BD 9A 47
18 1D 70 53 3A
1A 1F 8E 6E 3F
1B 21 A5 84 42
59
5F
61
58
62
52
57
5D
NTSC 4x 59.94 15.734266 14.32 28.64 43 09 24
F
SC
PAL sqr.
pixel
50.00 15.625000 14.75 29.50 45 0D 21
50.00 15.625000 13.50 27.00 40 0C 1E
50.00 15.625000 15.00 30.00 46 0D 22
60.00 15.750000 12.50 25.01 3E 0B 1C
60.00 15,750000 13.50 27.00 44 0C 1E
6D 03 2B B7
4D BE 0E 93
PAL
CCIR-601
PAL 15
Mpps
73
26
26
11 31 BF
86 FE 8B
PAL-M
sqr.pixel
PAL-M
CCIR-601
Bf
12 99
PAL-M 4x 60.00 15,750000 14.30 28.60 47 0D 20
4C E8 22 AC
F
SC
Notes:
1. XBP, VA, VC, and VB are 10-bit values. The 2 MSBs for these four variables are in Timing Register 18. See Table 3.
2. EH and SL are 9-bit values. A most significant "1" is forced by the TMC22x91 since EH and SL must range from 256 to 511.
EH and SL may be extended to 767. Only the eight LSBs are stored in Timing Registers 1B and 1C.
3. Every calculated timing parameter has a minimum value of 5 except EH and SL which have minimum values of 256.
VITS Insertion
Subcarrier Programming
In both NTSC and PAL, the TMC22x91 can be set up to
allow Vertical Interval Test Signals (VITS) in the vertical
interval in place of normal black burst lines (UBB). This is
controlled by Interface Control Register bit 7. If this bit is
LOW, UBB lines are black burst and are independent of
TMC22x91 input data. If the bit is HIGH, all vertical interval
UBB lines become UVV. UVV lines are active video and
depend upon data input to the TMC22x91. VITS lines may
carry special test signals or pass captioning data through the
encoder.
The color subcarrier is produced by an internal 32-bit digital
frequency synthesizer which is completely programmable in
frequency and phase. Separate registers are provided for phase
adjustment of the color burst and of the active video, permit-
ting external delay compensation and color adjustment.
In Master or Slave mode, the subcarrier is internally syn-
chronized to establish and maintain a specified relationship
between the falling edge of horizontal sync and color burst
phase (SCH). In NTSC and PAL, SCH synchronization is
performed every eight fields, on field 1 of the eight-field
sequence. Proper subcarrier phase is maintained through the
entire eight fields, including the 25 Hz offset in PAL
systems. See the description of 8FSUBR under Test Control
Register bit 1 for the subcarrier reset function.
Edge Control
SMPTE 170M NTSC and Report 624 PAL video standards
call for specific rise and fall times on critical portions of the
video waveform. The TMC22x91 does this automatically.
The TMC22x91 digitally defines slopes compatible with
SMPTE 170M NTSC or CCIR Report 624 PAL on:
In Genlock mode, the phase and relative frequency of the
incoming video are transmitted by the TMC22071 Genlock-
ing Video Digitizer over the CVBS bus at the beginning of
each line, which synchronize the digital subcarrier synthe-
sizer. When key control register bit BUKEN is HIGH and
digitized burst from the TMC22071 is passed through to the
reconstruction D/A converter, the reference subcarrier for the
chrominance modulator is still synthesized within the
encoder.
1. H and V Sync leading and trailing edges.
2. Burst envelope.
3. Active video leading and trailing edges.
32
PRODUCT SPECIFICATION
TMC22091/TMC22191
NTSC Subcarrier
PAL Subcarrier
For NTSC encoding, the subcarrier synthesizer frequency
has a simple relationship to the pixel clock period, repeating
over 2 lines: The decimal value is:
The PAL relationship is more complex, repeating only once
in 8 fields (the well-known 25 Hz offset):
(1135 ⁄ 4) + (1 ⁄ 625)
--------------------------------------------------
(pixels/line)
32
FREQ =
× 2
(455 ⁄ 2)
32
-----------------------------
(pixels/line)
FREQ =
× 2
This value must be converted to binary and split as described
previously for NTSC.
This value must be converted to binary and split into four
8-bit registers, FREQM, FREQ2, FREQ3, and FREQL. The
number of pixels/line is:
For PAL, the decimal value for SYSPH is found from:
FREQ
217
Pixels/line = (2/PXCK frequency) (H period)
SYSPH = --------------- = BURPH
SYSPH establishes the appropriate phase relationship
between the internal synthesizer and the chroma modulator.
The nominal value for SYSPH is zero.
This value must be converted to binary and split into two
8-bit registers, SYSPHM and SYSPHL. Burst Phase in PAL
is identical to SYSPH. Therefore, the same values for
SYSPHM and SYSPHL must be used for BURPHM and
BURPHL.
Other values for SYSPH must be converted to binary and
split into two 8-bit registers, SYSPHM and SYSPHL.
PAL-M Subcarrier
Burst Phase (BURPH) sets up the correct relative NTSC
modulation angle. The value for BURPH is:
(909 ⁄ 4)
32
-----------------------------
(pixels/line)
FREQ =
× 2
BURPH = SYSPH + 8,192
FREQ
SYSPH = --------------- = BURPH
217
This value must be converted to binary and split into two
8-bit registers, BURPHM and BURPHL. The decimal num-
ber 8,192 advances the burst phase by 45°.
Table 13. Standard Subcarrier Parameters
Subcarrier Register (hex)
Field
Rate
(Hz)
Horizontal
Freq.
(kHz)
Pixel
Rate
(MHz)
PXCK
Freq.
(MHz)
Sub-carrier
Freq.
(MHz)
BURPHM BURPHL SYSPHM SYSPHL FREQM FREQ2 FREQ3 FREQL
Standard
27
26
25
24
23
22
21
20
NTSC sqr.
pixel
59.94
59.94
59.94
50.00
50.00
50.00
60
15.734266
15.734266
15.734266
15.625000
15.625000
15.625000
15.750
12.27
13.50
14.32
14.75
13.50
15.00
12.50
13.50
14.30
24.54
27.00
28.64
29.50
27.00
30.00
25.01
27.00
28.60
3.57954500
3.57954500
3.57954500
4.43361875
4.43361875
4.43361875
3.57561149
3.57561149
3.57561149
20
00
00
00
4A
AA
AA
AB
NTSC
CCIR-601
20
20
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
43
40
4C
54
4B
49
43
40
E0
00
F3
13
AA
45
DF
10
F8
00
18
15
C6
00
3F
66
3E
00
19
96
A1
51
D7
F5
NTSC 4x
fSC
PAL sq.
pixel
PAL
CCIR-601
PAL 15
Mpps
PAL-M sq.
pixel
PAL-M
CCIR-601
60
15,750
PAL-M 4x
fSC
60
15,750
33
TMC22091/TMC22191
PRODUCT SPECIFICATION
(Figure 11), the luminance component stair-step signal at the
LUMA output, and the chrominance component on the
CHROMA output. The six colors are 100% saturated PAL
and 75% saturated for NTSC.
SCH Phase Error Correction
SCH refers to the timing relationship between the 50% point
of the leading edge of horizontal sync and the positive or
negative zero-crossing of the color burst subcarrier refer-
ence. SCH error is usually expressed in degrees of subcarrier
phase. In PAL, SCH is defined for line 1 of field 1, but since
there is no color burst on line 1, SCH is usually measured at
line 7 of field 1. The need to specify SCH relative to a partic-
ular line in PAL is due to the 25 Hz offset of PAL subcarrier
frequency. Since NTSC has no such 25 Hz offset, SCH
applies to all lines.
The percentage color saturation is selectable via Misc.
Control Register 0E, bit 0.
The color bar test pattern comprises eight equal-width bars
during VA, the active video period. The Timing Register
value for CBL is found from:
VA + 7
CBL = -----------------
8
The SCH relationship is only important in the TMC22x91
when two video sources are being combined or if the com-
posite video output is externally combined with another
video source. In these cases, improper SCH phasing will
result in a noticeable horizontal jump of one image with
respect to another and/or a change in hue proportional to the
SCH error between the two sources.
If CBL is larger than this, the color bars are truncated at the
end of VA. If CBL is smaller than VA/8, the color bar
sequence will repeat, starting with another white bar. From
left to right color bars 1 to 8 should be white, yellow, cyan,
green, magenta, red, blue, and black.
SCH phasing can be adjusted by modifying BURPH and
SYSPH values by equal amounts. SCH is advanced/delayed
by one degree by increasing/decreasing the value of BURPH
The modulated ramp waveform is enabled by setting the For-
mat Control Register to 30 . It comprises constant-amplitude
h
and constant-phase subcarrier modulation superimposed on a
linear ramp which slews from black to white during the
active video portion of each horizontal line (Figure 12). This
waveform is useful in making differential gain and differen-
tial phase measurements. Differential gain is a measure of
the variation in saturation of a color as the luminance com-
ponent is varied from black to white. Differential phase is a
measure of the variation in hue of a color as the luminance
component is varied from black to white.
and SYSPH by approximately B6 . An SCH error of 15° is
h
corrected with SYSPH and BURPH offsets of AAA .
h
Video Test Signals
The TMC22x91 has two standard video test waveforms for
evaluating video signal integrity. They are selected and
controlled by the Format Control Register.
Setting the Format Control Register bits 0, 4, and 5 LOW
generates standard color bars at the COMPOSITE output
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
24387A
Figure 8. 100% Color Bars With 100% and 75% Chrominance Saturation
34
PRODUCT SPECIFICATION
TMC22091/TMC22191
Microprocessor Interface
The microprocessor interface comprises 13-lines. Two
address bits provide four addresses for device programming
and CLUT/register management. Address bit 0 selects
between control registers and CLUT memory. Address bit 1
selects between reading/writing the register addresses and
reading/writing register or CLUT data.
When writing, the address is presented along with a LOW on
the R/W pin during the falling edge of CS. Eight bits of data
are presented on D during the subsequent rising edge of
7-0
CS.
24388A
One additional falling edge of CS is needed to move input
data to the assigned working registers.
Figure 7. Modulated Ramp Waveform
t
t
PWHCS
PWLCS
CS
t
t
HA
SA
R/W
A -A
1
0
0
t
t
HD
SD
D -D
7
24323A
Figure 10. Microprocessor Port – Write Timing
t
t
PWHCS
PWLCS
CS
t
t
HA
SA
R/W
A -A
1
0
0
t
t
HOM
DOM
D -D
7
24324A
t
DOZ
Figure 11. Microprocessor Port – Read Timing
35
TMC22091/TMC22191
PRODUCT SPECIFICATION
In read mode, the address is accompanied by a HIGH on the
R/W pin during a falling edge of CS. The data output pins go
and Blank Insert block are monitored. When the Control
Register pointer is loaded with 60 , the D port will output
h
7-0
to a low-impedance state t
ns after CS falls. Valid data is
after the falling edge of CS. Because
8-bit luminance pixels synchronous with respect to PXCK.
DOZ
present on D
t
To halt the pixel flow from D , bring CS HIGH.
7-0 DOM
7-0
this port operates asynchronously with the pixel timing,
there is an uncertainty in this data valid output delay of one
Operational Timing
PXCK period. This uncertainty does not apply to t
.
DOZ
The TMC22x91 operates in three distinct modes:
The RESET pin restores the TMC22x91 to field 1 line 1 and
places the encoder in a power-down state (if HRESET is
LOW). Bit 4 of the Global Control Register (SRESET) is set
LOW. All other control words and CLUT contents are left
unchanged. Returning RESET HIGH synchronizes the inter-
nal clock with PXCK and restores the device outputs to
active states.
1. Master mode. The encoder independently produces all
internal timing and provides digital sync to the host
controller.
2. Slave mode. The encoder accepts horizontal and vertical
sync from the controller and synchronizes the video out-
put accordingly.
3. Genlock mode. The encoder accepts horizontal and ver-
tical sync from the companion TMC22071 Genlocking
Video Digitizer, synchronizes itself to the incoming
video, and provides appropriate H Sync and V Sync to
the host. It synchronizes Pixel Data input in two ways:
Reading Pixel Data from the D
Port
7-0
The microprocessor port of the TMC22x91 may be used to
monitor digital video outputs. The eight MSBs of the up-
sampled and interpolated pixel data that go to the
COMPOSITE D/A converter can also be accessed via the
D
port. When the Test Control Register is loaded with 28
7-0
and the Control Register pointer is loaded with 40 , the D
h
a. Internal PDC. The encoder internally generates the
Pixel Data Control (PDC) signal which calls for
data input from the external pixel source.
h
7-0
port will output the 8-bit composite pixels synchronous with
PXCK. To halt the pixel flow from D , simply bring CS
HIGH.
7-0
b. External PDC. The encoder receives a PDC signal
from the host and accepts Pixel Data based on that
input.
Luminance pixel data may also be read from D . In this
7-0
case, the eight MSBs of luminance at the input of the Sync
1
2
3
PXCK
t
t
t
SR
SR
HR
RESET
24330A
Figure 12. Reset Timing – PCK Synchronization
does not refer to 2N, timing is relative to signals shown in
the diagram only.
Reset Timing
The TMC22x91 operates from a master clock (PXCK) at
twice the pixel rate. In Master mode, the PCK to PXCK tim-
ing relationship is set on the rising edge of RESET. In Figure
12, PCK is denoted by odd PXCK counts.
Pixel Data Input Timing
PXCK is internally divided by 2 to generate an internal pixel
clock, PCK which is not accessible from the pins of the
TMC22x91. To ensure the correct phase relationship
When RESET is taken LOW with sufficient setup time (t
)
SR
before a rising edge of PXCK, the internal state machines are
reset and the device is put into a mode as dictated by the Glo-
bal Control Register bits 0 and 4. In Master mode, when the
RESET pin is taken HIGH, the internal clock timing is estab-
lished. In Slave and Genlock mode, this timing is established
by VHSYNC and GHSYNC respectively. The first PXCK
following this RESET rising edge is designated as PXCK 1.
Where it is significant, reference PXCK timing will be
shown with numbered rising edges. A designation of 2N
clocks refers to an even number of PXCK rising edges from
device reset. If RESET is not shown and clock numbering
between PCK and pixel data, PCK is locked to VHSYNC or
GHSYNC (Slave or Genlock mode, respectively). In Master
mode, VHSYNC is produced on the rising edge of PCK
allowing external circuitry to synchronize the generation of
pixel data and LDV which also operates at the rate of PCK.
The rising edge of LDV clocks the 24-bit pixel data into
three 8-bit registers while PCK clocks that data through the
pixel data path within the TMC22x91. It is therefore neces-
sary to meet the set-up and hold timing between pixel data
and LDV as well as LDV and PCK as shown in Figure 13.
36
PRODUCT SPECIFICATION
TMC22091/TMC22191
t
t
PWLPX
PWHPX
2N+1
2N+2
2N+3
PXCK
t
SP
t
PWLVH
VHSYNC
(GHSYNC)
PCK
LDV
t
t
PWHLDV
XL
t
PWLLDV
t
t
HP
SP
PD
KEY
24340A
Figure 13. Slave Mode PD Port Interface Timing (Genlock Mode)
0
1
2
3
4
16 17 18 19 20 21
51 52 53 54 55 56 57 58 59 60
PXCK
RESET
VHSYNC
COMPOSITE
OUTPUT
50% Sync Amplitude
24353A
Figure 14. Master Mode Timing
Master Mode
Slave Mode
In Master mode, initial timing is determined from the
RESET input, and subsequent cycles result from pro-
grammed values in the Timing Control Registers. The Hori-
zontal Sync output, VHSYNC, goes LOW 18 PXCK clock
cycles after the device is reset. The 50% point of the falling
edge of sync LOW on line 4 of field 1 (NTSC) or line 1 of
field 1 (PAL) occurs at the COMPOSITE and LUMA out-
puts 56 clocks after reset, or 38 clocks after VHSYNC. See
Figure 14, Master Mode Timing.
In Slave mode, the 50% point of the falling edge of sync
occurs 46 PXCK clocks after the falling edge of VHSYNC,
which is an input signal to the TMC22x91. This must be pro-
vided by the host to begin every line. If it is early, the line
will be started early, maintaining the 52 clock delay to out-
put. If it comes late, the front porch portion of the output
waveform will be extended as necessary. See Figure 15,
Slave Mode Timing.
37
TMC22091/TMC22191
PRODUCT SPECIFICATION
PXCK
VHSYNC
VVSYNC
1
1
for field 1
COMPOSITE
OUTPUT
50% Sync Amplitude
Figure 15. Slave Mode Timing
24355A
PXCK
GHSYNC
VHSYNC
COMPOSITE
OUTPUT
24356A
50% Sync Amplitude
Figure 16. Genlocked Mode Timing
The position (number of PCK cycles) of the rising edge of
PDC relative to the falling edge of VHSYNC can be found
by summing SY, BU, BR, and CBP. See Figure 17.
Genlocked Mode
In Genlocked mode, the encoder receives sync signals over
the GHSYNC and GVSYNC inputs, and provides VHSYNC
and VVSYNC to the host. The 50% sync amplitude point
occurs 50 PXCK clocks after GHSYNC goes LOW, while
VHSYNC is produced at clock 13. If GHSYNC is late, the
front porch is lengthened, if is is early, front porch is
shortened. See Figure 16, Genlock Mode Timing.
External Pixel Data Control
When used as an input, PDC goes HIGH four PXCK cycles
before the first valid pixel of a line is presented to the PD
input port. If this signal is late (with respect to the horizontal
blanking interval programmed in the timing control regis-
ters), the Color Back Porch (CBP) will be extended. If it is
early, incoming pixel data will be ignored until the end of the
CBP.
Pixel Data Control
The Pixel Data Control (PDC) signal determines the active
picture area. It may be an input or an output, as determined
by the Interface Control Register bit 1.
38
PRODUCT SPECIFICATION
TMC22091/TMC22191
PXCK
PDC
PD
P
P
P
P
P
P
P
P
P
P
1
2
3
4
19
20
21
22
23
24
COMPOSITE
OUTPUT
P
PI
P
PI
P
2 3
1
1
2
POST-FILTER
OUTPUT
24358A
Figure 17. External Pixel Data Control
Pixels produced by the encoder appear at the analog outputs
(COMPOSITE, LUMA, CHROMA) 40 clocks after they are
registered into the PD port. Note that the pixels enter at one-
half the PXCK rate. The encoded signal passes through
interpolation filters which generate intermediate output val-
ues, improving the output frequency response and greatly
simplifying the external reconstruction filter. The interpo-
lated pixels are designated PI in the diagram.
Internal Pixel Data Control
When programmed as an output, PDC goes HIGH four
PXCK periods prior to the end of CBP (as programmed in
the horizontal timing registers) which is also four PXCK
cycles prior to required input of the first pixel of a line.
PXCK
PDC
t
DO
P
P
P
P
P
P
P
P
P
P
24
PD
1
2
3
4
19
20
21
22
23
COMPOSITE
OUTPUT
P
PI
P
PI
P
2 3
1
1
2
POST-FILTER
OUTPUT
24357A
Figure 18. Internal Pixel Data Control
39
TMC22091/TMC22191
PRODUCT SPECIFICATION
A 4-Layer Example
Layering with the TMC22191
For this layering example, a BACKGROUND image is
generated. This image comprises shaded matte levels varying
from black at the top of the screen to white at the bottom.
This could just as well be a color image which will be seen
wherever no other image appears through the layering
process.
Layering is a video production process where various images
or patterns are superimposed (keyed) over each other to form
a layered composite of the input images. Four layers with the
following priority are provided by the TMC22191:
1. The DOWNSTREAM KEY layer keys over all other
layers.
The MIDGROUND image comprises a happy face superim-
posed over a white rectangle. Only the happy face and the
white rectangle are of interest for this image and therefore,
the portion of the image outside that area will be replaced by
the BACKGROUND image when MIDGROUND is keyed
over BACKGROUND. A key signal is generated on a pixel-
by-pixel basis. It indicates which image is active. The key
signal for keying MIDGROUND over BACKGROUND is
shown to the right of the MIDGROUND image. This repre-
sents a single bit signal mapped over the image. When the
signal is black (logic LOW), the MIDGROUND image is
active, when it is white (logic HIGH), the BACKGROUND
is active.
2. The FOREGROUND layer keys over MIDGROUND
and BACKGROUND, but not over DOWNSTREAM
KEY.
3. The MIDGROUND layer keys over BACKGROUND,
but not over FOREGROUND or DOWNSTREAM
KEY.
4. The BACKGROUND layer never keys over any other
layer.
It is important not to confuse layers with sources. The
TMC22191 can be programmed to assign any of its input
sources (RGB, YC C , CVBS bus, Overlay bits) to any of
R B
the four layers.
The results of layering MIDGROUND over BACK-
GROUND images are shown in the 2-layer composite image
Figure 19.
The ability to combine various video sources into a 4-layer
composite image is a very powerful tool in the production of
live video. The TMC22191 performs layering operations
entirely in the digital domain, enabling precise digital
control.
BACKGROUND
KEY
2-LAYER COMPOSITE
MIDGROUND
27036A
Figure 19. 2-Layer Image Construction
A FOREGROUND image comprises a shaded matte rectan-
FOREGROUND image is active, when it is white (logic
HIGH), the composite image is active.
gle with "HI KIDS !" alpha characters in its center. This is to
be superimposed over the previous 2-layer composite image.
The key signal needed for superimposing FOREGROUND
over other images is shown to the right of the FORE-
GROUND image. This represents a single bit signal mapped
over the image. When the signal is black (logic LOW), the
A new 3-layer composite image, FOREGROUND over
MIDGROUND over BACKGROUND, is shown in Figure
20.
40
PRODUCT SPECIFICATION
TMC22091/TMC22191
2-LAYER COMPOSITE
KEY
3-LAYER COMPOSITE
HI KIDS !
HI KIDS !
FOREGROUND
HI KIDS !
27037A
Figure 20. Adding a 3rd Layer
A DOWNSTREAM KEY image comprises the white alpha
characters "HAPPY FACE", and black alpha characters
"Time". This is to be superimposed over the previous 3-layer
composite image. The key signal needed for superimposing
DOWNSTREAM KEY image over the other composite
images is shown to the right. This represents a single bit sig-
nal mapped over the image. When the signal is black (logic
LOW), the DOWNSTREAM KEY image is active, when it
is white (logic HIGH), the previous composite image is
active.
In this illustration, all four source images are static (not mov-
ing). The images input to the TMC22191 can just as well be
"live" (from video camera or VCR sources) as long as:
• Data from those sources is in an input format that the
TMC22191 can accept, and
• The sources either synchronize the TMC22191
(Genlock mode) or are synchronized by the TMC22191
(Master or Slave mode).
Key signals may be generated external to the TMC22191
(Hardware Keying) and use the KEY input pin for control.
Key signals may also be generated within the TMC22191
(Data Keying) by the comparison of input color data with
color data stored in the TMC22191.
The final 4-layer composite image, DOWNSTREAM KEY
over FOREGROUND over MIDGROUND over BACK-
GROUND, is shown in Figure 21.
3-LAYER COMPOSITE
HI KIDS !
KEY
4-LAYER COMPOSITE
HI KIDS !
DOWNSTREAM KEY
HAPPY
FACE
TIME
HAPPY
FACE
TIME
HAPPY
FACE
TIME
27038A
Figure 21. Adding a 4th Layer
41
TMC22091/TMC22191
PRODUCT SPECIFICATION
2-Layer Keying with the TMC22091
Assigning Video Sources to Layers with the
TMC22191
The TMC22091 facilitates the keying of PD port input data
over the CVBS bus input data. Keying is controlled on a
pixel-by-pixel basis by either the KEY input pin or the inter-
nal Data Key. The first two layers in the previous 4-Layer
Example apply to the TMC22091. The result of keying is an
effect where a MIDGROUND source image (i.e. Happy Face
from PD data) is superimposed over a BACKGROUND
source image (i.e. variable matte color from CVBS data).
Digital video inputs to the TMC22191 (PD, CVBS, Overlay)
are assigned to the four layers by choosing one of the 16
modes of the Layering Control Register. OVERLAY is
always keyed (switched on a pixel-by-pixel basis from active
to transparent) by the OL inputs. OVERLAY can not be
4-0
programmed to the BACKGROUND layer. The CVBS digi-
tal video bus can be assigned to any of the four layers and is
keyed by the KEY input signal or internal Data Key. In
modes 0 thru 7, the CLUTs are not bypassed and the
BYPASS input is ignored.
Table 14. Layer Assignments, Image Sources, and Keying Controls (TMC22191)
LCR 04
Background
Midground
Foreground
Downstream Key
Keying
Keying
Control
Keying
Control
LAYMODE
Image Source
Image Source
Image Source:
Image Source:
Control
0
PD(YC C , RGB, CI)
CVBS
KEY or
—
—
—
—
B
R
Data Key
1
PD(YC C , RGB, CI)
CVBS
KEY or
OVERLAY
OL
4-0
—
—
B
R
Data Key
2
3
4
PD(YC C , RGB, CI)
CVBS
CVBS
KEY
KEY
PD(YC C , RGB, CI) Data Key
OVERLAY
OVERLAY
—
OL
OL
B
R
B
R
4-0
PD(YC C , RGB, CI)
PD(YC C , RGB, CI) Data Key
B R
B
R
4-0
CVBS
OVERLAY
OL
4-0
PD(YC C , RGB, CI) KEY or
—
B
R
Data Key
5
CVBS
PD(YC C , RGB, CI) KEY or
OVERLAY
OL
—
—
B
R
4-0
Data Key
6
7
8
PD(YC C , RGB, CI)
CVBS
CVBS
CVBS
KEY
OVERLAY
OVERLAY
OL
OL
PD(YC C , RGB, CI) Data Key
B R
B
R
4-0
PD(YC C , RGB, CI)
KEY
PD(YC C , RGB, CI) Data Key
B
R
4-0
B
R
PD(YC C , CI)
KEY or
—
—
—
B
R
Data Key
9
A
B
C
PD(RGB)
PD(RGB)
PD(RGB)
PD(RGB)
PD(YC C , CI)
BYPASS
CVBS
KEY or
Data Key
OVERLAY
OVERLAY
OL
B
R
4-0
4-0
CVBS
CVBS
KEY or
Data Key
PD(YC C , CI)
BYPASS
OL
B
R
KEY or
Data Key
OVERLAY
OVERLAY
OL
OL
PD(YC C , CI)
BYPASS
4-0
B R
PD(YC C , CI)
BYPASS
CVBS
KEY or
B
R
4-0
Data Key
D
E
F
CVBS
CVBS
PD(RGB)
OVERLAY
OVERLAY
KEY
PD(YC C , CI)
BYPASS
KEY
OVERLAY
OL
4-0
B
R
OL
OL
PD(RGB)
CVBS
PD(YC C , CI)
BYPASS
BYPASS
4-0
B R
PD(RGB)
KEY or
PD(YC C , CI)
B R
4-0
Data Key
Notes:
1. For LAYMODE = 0 to 7, Pixel Data always passes through the CLUTs. FORMAT, INMODE, and the BYPASS pin selects the
input format for PD according to Table 6.
23-0
2. For LAYMODE = 8 to F and BYPASS = HIGH, Data Key is disabled.
3. Asserting the signal listed under "Keying Control:" enables the corresponding "Signal Source:". Signals with " " are asserted
by a logic LOW.
42
PRODUCT SPECIFICATION
TMC22091/TMC22191
Key Control Register bit 5 HIGH. In this mode, KEY is
always active, and may be exercised at will.
Hardware Keying
The KEY input switches the COMPOSITE D/A converter
input from the luminance and chrominance combiner output
to the CVBS data bus on a pixel-by-pixel basis. This is a
"soft" switch, executed over four PXCK periods to minimize
out-of-band spurious signals. The video signal from the
CVBS bus can only present on the COMPOSITE output. The
CHROMA and LUMA outputs continue to present encoded
PD port data when CVBS is active.
The KEY input is registered into the encoder just like Pixel
Data is clocked into the PD port. It may be considered a 25th
Pixel Data bit. It is internally pipelined, so the midpoint of
the key transition occurs at the output of the pixel that was
input at the same time as the KEY signal.
Data Keying
Data Keying internally generates a Key signal that acts
exactly as the external KEY signal. There are three Key
Value Registers 05, 06, and 07 that are matched against the
input data to the three tables in the CLUT. These tables are
designated D, E, and F. They contain different information
depending on the input mode selected as shown in Table 16.
Hardware keying is enabled by the Key Control Register bit
6. Normally, keying is only effective during the Active Video
portion of the waveform as determined by the VA registers
15 and 18. The Horizontal Blanking interval is generated by
the encoder state machine even if the KEY signal is held
HIGH through Horizontal Blanking. However, it is possible
to allow digital Horizontal Blanking to be passed through
from the CVBS bus to the COMPOSITE output by setting
0
1
2
3
4
5
6
7
8
9
38 39 40 41 42 43 44 45 46 47 48 49
PXCK
CVBS
V
V
V
V
V
V
P
V
V
V
V
V
N+2
N+3
N+4
N+5
N+6
N+25
N+26
N+24
N+27
N+25
N+28
N+29
N+30
N+28
*
KEY
PD
P
P
P
P
P
P
P
P
P
P
N
N+1
N+2
N+3
N+4
N+23
N+26
N+27
KEY MIDPOINT
COMPOSITE
OUTPUT
KEY is advanced five PXCK cycles when
Control Register OE bit 4 is HIGH (TMC22191).
*
24359A
Figure 22. Hardware Keying
The key registers may be individually enabled using bits
3,2,1 of the Key Control Register. Bit 4 of the same register
enables/disables Data Keying in its entirety. Data Keying and
Hardware Keying are logically ORed: when both are
enabled, either one will result in a key switch to the CVBS
channel.
Table 16.Table D, E, F Contents
Mode
GBR
RGB
Table D
Green
Red
Y
Table E
Blue
Table F
Red
Green
Blue
YC C
B R
C
C
R
B
The key comparison is based on the input data to the tables
in the CLUT. When operating in color-index mode, all three
tables receive the same input value, so any one of the three
registers is sufficient to identify a key value. The outputs of
all enabled key registers are ANDed to produce the KEY sig-
nal. If more than one key register are enabled and their key
values are not identical, no key will be generated.
CI
CI
CI
CI
43
TMC22091/TMC22191
PRODUCT SPECIFICATION
Genlock Interface
The TMC22x91 can process digital composite video
connected to its CVBS port. It has been designed to couple
tightly with the companion TMC22071 Genlocking Video
Digitizer, but it will work with other sources as well.
Subcarrier frequency and phase data are transmitted to the
encoder over the CVBS bus as 4-bit nibbles on CVBS
3-0
during the horizontal sync period. Field identification is also
required for the TMC22x91 internal sync generator. The
14th nibble of the sequence contains no relevant data.
The digital composite video has to be in standard 8-bit
binary format at a PXCK/2 rate. Synchronization with the
internal PXCK/2 is established by the phasing of the
GHSYNC input, as shown in Figures 24 and 25.
0
1
2
3
4
5
6
7
8
9
38 39 40 41 42 43 44 45 46 47 48 49
PXCK
CVBS
PD
V
V
V
V
V
V
P
V
P
V
P
V
P
V
P
V
P
N+2
N+3
N+4
N+5
N+6
N+4
N+25
N+26
N+27
N+28
N+29
N+30
P
P
P
P
P
N
N+1
N+2
N+3
N+23
N+24
N+25
N+26
N+27
N+28
KEY MIDPOINT
FIRST KEY WORD
COMPOSITE
OUTPUT
24360A
Figure 23. Data Keying
2N+1
2N+2
2N+3
PXCK
t
t
HGI
SGI
GHSYNC
t
t
HGI
SGI
CVBS
7-0
24341A
Figure 24. Genlock Interface Timing
44
PRODUCT SPECIFICATION
TMC22091/TMC22191
PXCK
0
1
2
3
4
57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
GHSYNC
CVBS
7-0
f23:20 f19:16 f15:12 f11:8 f7:4 f3:0 φ23:20 φ19:16 φ15:12 φ11:8 φ7:4 φ3:0
PIXEL
PIXEL
PIXEL FID
PIXEL
PIXEL
FREQUENCY
PHASE
24383A
FIELD IDENTIFICATION
Figure 25. Frequency/Phase Data Transfer
Since these are fixed-coefficient digital filters, their filter
characteristics depend upon clock rate. Figures 26 and 27
show the frequency response for two pixel rates, 12.27 MHz
and 14.75 MHz.
Filtering
The TMC22x91 incorporates internal digital filters to estab-
lish appropriate bandwidths and simplify external analog fil-
ter designs.
0
Color-Difference Low-Pass Filters
-10
f = 14.75 Mpps
The color-difference low-pass filters in the TMC22x91
establish chrominance bandwidths which meet the specifica-
tions outlined in CCIR Report 624-3, Table II, Item 2.6, for
system I over a range of pixel rates from 12.27 Mpps to
14.75 Mpps. Equal bandwidth is established for both color-
difference channels.
-20
-30
-40
f = 12.27 Mpps
-50
-60
-70
-80
-90
0
0
3
6
9
12
15
CCIR Rep 624 Specification
-10
Frequency (MHz)
24394A
-20
Figure 27. Chroma Modulator and Luminance
Interpolation Filter Full Spectrum Response
f = 14.27 Mpps
-30
-40
-50
-60
-70
-80
-90
f = 12.27 Mpps
f = 14.75 Mpps
0
-1
-2
-3
-4
0
1
2
3
4
5
6
7
8
f = 12.27 Mpps
Frequency (MHz)
24363A
Figure 26. Color-Difference Low-Pass Filter Response
Interpolation Filters
0
1
2
3
4
5
6
7
Frequency (MHz)
24365A
The Chroma Modulator output and the luminance data path
are digitally filtered with sharp-cutoff low-pass interpolation
filters. These filters ensure that aliased subcarrier, chromi-
nance, and luminance frequencies are sufficiently suppressed
in the frequency band above base-band video and below the
Figure 28. Chroma Modulator and Luminance
Interpolation Filter Passband Detail
All digital-to-analog reconstruction systems exhibit a high
frequency roll-off as a result of the zero-order hold charac-
teristic of D/A converters. This response is commonly
referred to as a sin(x)/x response. It is a function of the sam-
pling rate of the output D/A.
pixel frequency (f /4 to 3f /4, where f is the PXCK
S
S
S
frequency).
45
TMC22091/TMC22191
PRODUCT SPECIFICATION
The digital interpolation filters in TMC22x91 convert the
data stream to a sample rate of twice the pixel rate. As shown
in Figures 27 and 28, the filters decrease the sin(x)/x rolloff
JTAG Test Interface
The JTAG test port accesses registers at every digital I/O pin
except the JTAG test port pins. Table 16 shows the sequence
of the test registers. The register number (Reg) indicates the
order in which the register data is loaded and read (Reg 1 is
loaded and read first, therefore it is at the end of the serial
path). The scan path is 59 registers long. The six TEST pins
of the TMC22091 function as JTAG registers.
and the output spectrum between f /4 and 3f /4 contains
S
S
very little energy. Since there is so little signal energy in this
frequency band, the demands placed on the output recon-
struction filter are greatly reduced. The output filter needs to
be flat to f /4 and have good rejection at 3f /4. The relaxed
S
S
requirements greatly simplify the design of a filter with good
phase response and low group delay distortion. A small
amount of peaking may be used to compensate residual
sin(x)/x rolloff.
The JTAG port is a 4-line interface, following IEEE Std.
1149.1-1990 specifications. The Test Data Input (TDI) and
Test Mode Select (TMS) inputs are referred to the rising
edge of the Test ClocK (TCK) input. The Test Data Output
(TDO) is referred to the falling edge of TCK.
Table 16. JTAG Interface Connections
Reg Pin
Signal
Reg Pin
Signal
Reg Pin
Signal
1
28
29
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
BYPASS (TEST)
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
62
63
66
67
68
69
70
71
72
73
74
75
76
77
78
79
82
83
84
1
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
2
CVBS
CVBS
KEY
13
12
11
10
9
1
0
2
OL (TEST)
3
4
3
CVBS
CVBS
CVBS
CVBS
4
7
6
5
4
4
5
RESET
CS
5
6
6
7
R/W
8
7
OL (TEST)
8
A
1
A
0
3
7
8
OL (TEST)
9
2
6
9
OL (TEST)
11
12
13
14
15
16
17
18
19
20
21
PDC
1
5
10
11
12
13
14
15
16
17
18
19
20
OL (TEST)
VHSYNC
VVSYNC
0
4
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
23
22
21
20
19
18
17
16
15
14
3
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
2
1
0
LDV
PXCK
GVSYNC
GHSYNC
CVBS
CVBS
3
2
46
PRODUCT SPECIFICATION
TMC22091/TMC22191
t
t
PWHTCK
PWLTCK
TCK
t
STP
t
HTP
TDI
TMS
t
DOTP
t
HOTP
TDO
24333A
Figure 29. JTAG Test Port Timing
Equivalent Circuits
V
DD
V
DD
n Substrate
n
p
R
REF
V
DD
V
REF
COMPOSITE
LUMA
CHROMA
27012A
27013A
Figure 30. Equivalent Analog Input Circuit
Figure 31. Equivalent Analog Output Circuit
V
V
DD
DD
n Substrate
p
p
Input
Output
n
n
27011A
27014A
Figure 32. Equivalent Digital Input Circuit
Figure 33. Equivalent Digital Output Circuit
47
TMC22091/TMC22191
PRODUCT SPECIFICATION
t
DOM
CS
t
t
DOZ
HOM
0.5V
2.0V
0.8V
Hi-Z
D
7-0
27029A
0.5V
Figure 34. Transition Levels for Three-State Measurements
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min.
Max.
7.0
Unit
Power Supply Voltage
Digital Inputs
-0.5
V
Applied Voltage2
-0.5
V +0.5
DD
V
Forced Current3,4
-20.0
20.0
mA
Digital Outputs
Applied Voltage2
-0.5
V +0.5
DD
V
Forced Current3,4
-20.0
20.0
1
mA
Short Circuit Duration (Single output in HIGH state to GND)
Analog Output Short Circuit Duration (Single output to GND)
Temperature
second
Infinite
Operating, ambient
-20
-65
110
140
300
220
150
°C
°C
°C
°C
°C
Operating, junction, plastic package
Lead, soldering (10 seconds)
Vapor phase soldering (1 minute)
Storage
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current, flowing into the device.
48
PRODUCT SPECIFICATION
TMC22091/TMC22191
Operating Conditions
Parameter
Min.
Nom.
Max.
Units
V
V
Power Supply Voltage
4.75
5.0
5.25
V
DD
IH
Input Voltage, Logic HIGH
TTL Compatible Inputs, all but TCK
TTL Compatible Input TCK
CMOS Compatible Inputs
Input Voltage, Logic LOW
TTL Compatible Inputs
2.0
2.5
V
DD
V
V
V
V
DD
DD
(2/3)V
DD
V
V
IL
GND
GND
0.8
(1/3)V
-2.0
V
V
CMOS Compatible Inputs
Output Current, Logic HIGH
Output Current, Logic LOW
External Reference Voltage
DD
I
I
mA
mA
V
OH
4.0
OL
V
1.235
3.15
REF
REF
I
D/A Converter Reference Current, V
REF
= Nom.
pin)
2.1
281
0
4.4
588
70
mA
(I
REF
= V
REF
/ R , flowing out of the R
REF REF
R
R
Reference Resistor, V
REF
= Nom.
392
Ω
Ω
REF
OUT
A
Total Output Load Resistance
Ambient Temperature, Still Air
37.5
T
°C
Pixel Interface
f
f
t
t
Pixel Rate
12.27
24.54
10
15
30
Mpps
MHz
ns
PXL
Master Clock Rate, 2x pixel rate
PXCK Pulse Width, HIGH
PXCK Pulse Width, LOW
PXCK
PWHPX
PWLPX
10
ns
For PD, VVSYNC, VHSYNC, PDC, KEY
t
t
t
t
t
t
t
Setup Time
12
0
ns
ns
ns
ns
ns
ns
SP
Hold Time, PD and KEY
Hold Time, PDC, VHSYNC, VVSYNC
Delay Time, LDV
HP
5
HP
10
15
10
6
XL
LDV Pulse Width, HIGH
LDV Pulse Width, LOW
VHSYNC Pulse Width, LOW
PWHLDV
PWLLDV
PWLVH
15
3
PXCK
periods
t
VVSYNC Pulse Width, LOW
0.5
H
PWHVV
Genlock Interface
t
Setup Time, GHSYNC, GVSYNC, CVBS
Hold Time, GHSYNC, GVSYNC, CVBS
10
0
ns
ns
SGI
HGI
t
Microprocessor Interface
t
t
t
t
t
t
CS Pulse Width, LOW
CS Pulse Width, HIGH
Address Setup Time
Address Hold Time
55
30
10
0
ns
ns
ns
ns
ns
ns
PWLCS
PWHCS
SA
HA
Data Setup Time (write)
Data Hold Time (write)
15
0
SD
HD
49
TMC22091/TMC22191
PRODUCT SPECIFICATION
Operating Conditions (continued)
Parameter
Min.
24
2
Nom.
Max.
Units
ns
t
t
Reset Setup Time
Reset Hold Time
SR
HR
ns
JTAG Interface
f
t
t
t
t
Test Clock (TCK) Rate
20
MHz
ns
TCK
TCK Pulse Width, LOW
10
25
10
3
PWLTCK
PWHTCK
STP
TCK Pulse Width, HIGH
ns
Test Port Setup Time, TDI, TMS
Test Port Hold Time, TDI, TMS
ns
ns
HTP
Note:
1. Timing reference points are at the 50% level.
Electrical Characteristics
Parameter
Conditions
Min.
Typ.
Max. Units
I
I
Power Supply Current1
Power Supply Current1
(D/A disabled)
V
= Max, f
= 30MHz
= 30MHz
250
300
60
mA
mA
DD
DD
DD
PXCK
PXCK
V
= Max, f
DDQ
V
Voltage Reference Output
0.988 1.235 1.482
V
RO
I
I
I
Input Bias Current, V
REF
V
V
V
= Nom
100
µA
µA
µA
V
BR
REF
Input Current, Logic HIGH
Input Current, Logic LOW
Output Voltage, Logic HIGH
Output Voltage, Logic LOW
Hi-Z Leakage current, HIGH
Hi-Z Leakage current, LOW
Digital Input Capacitance
Digital Output Capacitance
Video Output Compliance Voltage
Video Output Resistance
Video Output Capacitance
= Max, V = V
IN DD
10
IH
IL
DD
DD
= Max, V = 0V
IN
-10
V
V
I
I
= Max
2.4
0.4
10
OH
OH
OL
= Max
V
OL
I
I
V
= Max, V = V
IN DD
µA
µA
pF
pF
V
OZH
OZL
DD
DD
V
= Max, V = GND
IN
-10
C
C
T = 25°C, f = 1MHz
A
4
10
2.0
25
I
T = 25°C, f = 1MHz
A
10
O
V
-0.3
OC
R
C
15
15
kΩ
pF
OUT
OUT
I
= 0 mA, f = 1 MHz
OUT
Note:
1. Typical I
with V
DD
= +5.0 Volts and T = 25°C, Maximum I
DD
with V = +5.25 Volts and T = 0°C.
DD A
DD
A
50
PRODUCT SPECIFICATION
TMC22091/TMC22191
Switching Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
PIPES
Pipeline Delay3
PD to Analog Out
44
44
44
PXCK
periods
t
t
t
t
t
Output Delay, CS to low-Z
6
23
ns
ns
ns
ns
ns
DOZ
Output Delay, CS to Data Valid4
Output Hold Time, CS to hi-Z
Output Delay, TCK to TDO Valid
100
DOM
HOM
DOTP
HOTP
10
30
25
Output Hold Time, TCK to TDO
Valid
5
t
Output Delay
PXCK to VHSYNC,
VVSYNC, PDC
ns
DOS
t
t
t
D/A Output Current Risetime
D/A Output Current Falltime
Analog Output Delay
10% to 90% of full-scale
90% to 10% of full-scale
2
ns
ns
ns
R
2
F
20
DOV
Notes:
1. Timing reference points are at the 50% level.
2. Analog C < 10 pF, D load < 40 pF.
LOAD 7-0
3. Pipeline delay, with respect to PXCK, is a function of the phase relationship between the internally generated PCK (PXCK/2)
and PXCK, as established by the hardware reset.
4. t
DOM
= 1 PXCK + 54 ns = 100 ns worst-case at PXCK = 24.54 MHz.
System Performance Characteristics
Parameter
Conditions
Min.
Typ.
Max.
10
Units
Bits
RES
ELI
ELD
EG
D/A Converter Resolution
10
10
Integral Linearity Error
Differential Linearity Error
Gain Error
0.25
0.20
±10
%
%
% FS
degree
dp
Differential Phase
PXCK = 24.54 MHz,
40 IRE Ramp3
0.5
0.9
dg
Differential Gain
PXCK = 24.54 MHz,
40 IRE Ramp3
%
SKEW
PSRR
CHROMA to LUMA Output Skew
Power Supply Rejection Ratio
0
2
ns
CCOMP = 0.1 µF, f = 1kHz
0.5
%/
%VDD
Notes:
1. TTL input levels are 0.0 and 3.0 Volts, 10%-90% rise and fall times <3 ns.
2. Analog C
3. NTSC
< 10 pF, D load < 40 pF.
7-0
LOAD
51
TMC22091/TMC22191
PRODUCT SPECIFICATION
Video
from
Encoder
Video
Output
1.8µH
75Ω
IN5818
+5V
75Ω
27pF
+5V
+5V
100
pF
75
Ω
47 µF
47 µF
1.0µH
330pF
330pF
0.1 µF
0.1 µF
BYPASS and OL
4-0
on TMC22191 only.
5
OL
4-0
V
D
GND
A
V
DDA
DO
GND
BYPASS
PD
23-0
VHSYNC
VVSYNC
PDC
LPF
LPF
LPF
CHROMA
LUMA
24
S-VIDEO OUTPUT
COMPOSITE
COMPOSITE VIDEO
OUTPUT
TMC22x91
DIGITAL VIDEO
ENCODER
KEY
V
DD
0.1 µF
COMP
LDV
PXCK
3.3KΩ
V
R
REF
LM185-1.2
8
CVBS
7-0
REF
392Ω
0.1µF
GHSYNC
GVSYNC
8
2
27007A
MICROPROCESSOR
INTERFACE
JTAG TEST
INTERFACE
Figure 35. Recommended Interface Circuit
Applications Discussion
The TMC22x91 is a complex mixed-signal VLSI circuit. It
converts digital video signals at clock rates of up to 30 MHz
to analog video outputs. A recommended circuit connection
is shown in Figure 35.
Interface to the TMC22071 Genlocking Video
Digitizer
The TMC22x91 Digital Video Encoder has been designed to
directly interface to the TMC22071 Genlocking Video Digi-
tizer. An interface circuit is shown in Figure 37. The micro-
processor interface for TMC22x91 and TMC22071 are
References
The circuit shown in Figure 35 uses a stable external 1.235V
voltage reference. To use the internal voltage reference, sim-
ply delete the 3.3kΩ resistor and the LM185-12. A simple
voltage divider from the power supply should NOT be used,
as any variations in power supply voltage would appear
directly on the video outputs.
similar. The R/W, RESET, D and A signals from the host
0
0
microprocessor are shared by the TMC22x91 and
TMC22071. The CS signals are separately driven from the
microprocessor bus.
Grounding Strategy
The TMC22x91 has distinctly separate analog and digital
circuits. To minimize digital crosstalk into the analog sig-
nals, the power supplies and grounds are provided over sepa-
rate pins. In general, the best results are obtained by
connecting all grounds to a ground plane. Power supply pins
should be individually decoupled at the pin.
Filtering
An simple low-pass output reconstruction filter is shown in
Figure 36. This filter is located in the video signal path after
the COMPOSITE, LUMA, and CHROMA outputs. The
value of R
may be varied to make up for the filter loss.
REF
Video
from
Encoder
Video
Output
1.8µH
75Ω
75Ω
27pF
75
Ω
1.0µH
330pF
330pF
100
pF
27025A
Figure 36. Recommended Output Reconstruction Filter
52
PRODUCT SPECIFICATION
TMC22091/TMC22191
8
CVBS
CVBS
7-0
7-0
GHSYNC
GVSYNC
PXCK
GHSYNC
GVSYNC
PXCK
TMC22071
TMC22x91
LDV
LDV
GENLOCKING VIDEO DIGITIZER
DIGITAL VIDEO ENCODER
2
8
MICROPROCESSOR
INTERFACE
27009A
Figure 37. TMC22x91-to-TMC22071 Interface Circuit
Printed Circuit Board Layout
Microprocessor I/O Operations
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor picture quality. Consider the following sugges-
tions when doing the layout:
Various CLUT Read/Write operations are shown in Table 17.
Each step in the table requires a CS pulse (falling edge fol-
lowed by a rising edge) to execute.
For Write operations, R/W and A must conform to setup
1-0
and hold timing with respect to the falling edge of CS. D
7-0
must meet setup and hold timing with respect to the rising
edge of CS. These timing relationships are illustrated in Fig-
ure 10. When writing data into an internal register (i.e.
CLUT Address Register) an extra CS falling edge is required
to transfer the input data to that register. This requirement is
usually accomplished by executing the next step in the
sequence. If there is no planned next step in the sequence,
executing a Control Register Read step will meet the require-
ment and terminate the sequence.
• Keep analog traces (COMP, V ) as short and as
, R
far from all digital signals as possible.
REF REF
• The power plane for the TMC22x91 should be separate
from that which supplies other digital circuitry. A single
power plane should be used for all of the V
DD
pins. If the
power supply for the TMC22x91 is the same for the
system’s digital circuitry, power to the TMC22x91 should
be filtered with ferrite beads and 0.1µF capacitors to
reduce noise.
For Read operations, R/W and A must conform to setup
1-0
and hold timing with respect to the falling edge of CS. Read
• The ground plane should be solid, not cross-hatched.
Connections to the ground plane should be very short.
data on D is initiated by the falling edge of CS\ and termi-
7-0
• Decoupling capacitors should be applied liberally to V
pins. For best results, use 0.1µF capacitor in
DD
nated by the rising edge of CS as shown in Figure 11. When
reading Control Registers, valid data appears t
after the
DOM
parallel with 47µF capacitors. Lead lengths should be
falling edge of CS. When reading CLUT locations, an extra
CLUT Read step is needed to set up the CLUT Read
sequence. This is accomplished in the table by executing an
extra CLUT Read step just before the CLUT Read sequence
which returns successive d, e, and f data. CLUT Read
sequences must be terminated an extra CS falling edge. This
requirement is usually accomplished by executing the next
I/O step. If there is no planned next step in the sequence,
executing a Control Register Read step will meet the require-
ment and terminate the sequence.
minimized. Ceramic chip capacitors are the best choice.
• The PXCK should be handled carefully. Jitter and noise
on this clock or its ground reference will translate to noise
on the video outputs. Terminate the clock line carefully to
eliminate overshoot and ringing.
53
TMC22091/TMC22191
PRODUCT SPECIFICATION
Table 17. CLUT Read/Write Sequences
Step
R/W\
A
1-0
D
7-0
Function
Write Entire CLUT Starting at Address 00
1
1
0
0
01
01
11
11
11
•••
11
11
11
00
00
00
Write 00 into CLUT Address Register.
Write 00 into CLUT Address Register.
d1 written into D, CLUT address 00.
e1 written into E, CLUT address 00.
f1 written into F, CLUT address 00.
repeat steps 3, 4, 5 until CLUT is full.
d256 written into D, CLUT address FF.
e256 written into E, CLUT address FF.
f256 written into F, CLUT address FF.
Sequence termination.
2
0
d1
3
0
e1
4
0
f1
•••
767
768
769
770
•••
0
•••
d256
e256
f256
xx
0
0
1
Write CLUT Location address
1
2
3
4
5
0
0
0
0
1
01
11
11
11
00
addr
d1
e1
f1
Write addr into the CLUT Address Register.
d1 written into D, CLUT address addr.
e1 written into E, CLUT address addr.
f1 written into F, CLUT address addr.
Sequence termination.
xx
Read CLUT Location address
1
2
3
4
5
6
0
1
1
1
1
1
01
11
11
11
11
00
addr
xx
Write addr into the CLUT Address Register.
Set up for CLUT Read sequence.
d1 read from D, CLUT address addr.
e1 read from E, CLUT address addr.
f1 read from F, CLUT address addr.
Sequence termination.
d1
e1
f1
xx
Read CLUT Address Register Then Write
1
2
3
4
5
6
7
8
9
1
0
0
0
1
0
0
0
1
01
11
11
11
01
11
11
11
00
addr
d1
Read CLUT Address Register.
d1 written into D, CLUT address addr.
e1 written into E, CLUT address addr.
f1 written into F, CLUT address addr.
Read CLUT Address Register. (terminates Write sequence)
d2 written into D, CLUT address addr+1.
e2 written into E, CLUT address addr+1.
f2 written into F, CLUT address addr+1.
Sequence termination.
e1
f1
addr+1
d2
e2
f2
xx
54
PRODUCT SPECIFICATION
TMC22091/TMC22191
Table 17. CLUT Read/Write Sequences (continued)
Step
R/W\
A
1-0
D
7-0
Function
Read/Modify/Write CLUT Location address
1
2
0
1
01
11
11
11
11
•••
01
addr
xx
Write addr into the CLUT Address Register.
Set up for CLUT Read.
3
1
d1
d1 read from D, CLUT address addr.
e1 read from E, CLUT address addr.
f1 read from F, CLUT address addr.
System Modifies d1, e1, f1 to d1', e1', f1'.
4
1
e1
5
1
f1
•••
6
•••
0
•••
addr
Write addr into the CLUT Address Register. (terminates Read
sequence)
7
8
0
0
0
1
11
11
11
00
d1’
e1’
f1’
d1' written into D, CLUT address addr.
e1' written into E, CLUT address addr.
f1' written into F, CLUT address addr.
Sequence termination.
9
10
xx
Related Products
• TMC22071 Genlocking Video Digitizer
• TMC2242/2243/2246 Video Filters
• TMC2249 Video Mixer
• TMC2255 Convolver
• TMC2272 Colorspace Converter
• TMC2302 Image Manipulation Sequencer
55
TMC22091/TMC22191
PRODUCT SPECIFICATION
Notes:
56
PRODUCT SPECIFICATION
TMC22091/TMC22191
Notes:
57
TMC22091/TMC22191
PRODUCT SPECIFICATION
Mechanical Dimensions – 84-Lead PLCC Package
Notes:
Inches
Millimeters
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Min.
Max.
Min.
Max.
2. Corner and edge chamfer = 45°.
A
.165
.090
.200
.130
—
4.19
2.29
.51
5.08
3.30
—
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm).
A1
A2
.020
B
.013
.021
.032
1.195
1.158
.33
.53
B1
.026
.66
.81
D/E
D1/E1
D3/E3
e
1.185
1.150
30.10
29.21
30.35
29.41
3
2
1.000 BSC
.050 BSC
.042 .056
25.40 BSC
1.27 BSC
1.07 1.42
J
ND/NE
N
21
84
21
84
ccc
—
.004
—
0.10
E
E1
J
D
D1
D3/E3
B1
J
e
A
A1
-C-
B
A2
LEAD COPLANARITY
ccc
C
58
PRODUCT SPECIFICATION
TMC22091/TMC22191
Mechanical Dimensions
100 Lead MQFP Package – 3.2mm Footprint
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
2. Controlling dimension is millimeters.
Min.
Max.
A
—
.134
—
—
3.40
—
3. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall be .08mm (.003in.) maximum in excess of
the "B" dimension. Dambar cannot be located on the lower radius
or the foot.
A1
A2
B
.010
.100
.008
.005
.904
.783
.667
.547
.25
.120
.015
.009
.923
.791
.687
.555
2.55
.22
3.05
.38
3, 5
5
4. "L" is the length of terminal for soldering to a substrate.
5. "B" & "C" includes lead finish thickness.
C
.13
.23
D
22.95
19.90
16.95
13.90
23.45
20.10
17.45
14.10
D1
E
E1
e
.0256 BSC
.65 BSC
4
L
.028
.040
.73
1.03
N
100
30
100
30
ND
NE
20
20
α
0°
7°
0°
7°
ccc
—
.004
—
.12
D
.20 (.008) Min.
D1
0° Min.
.13 (.30)
.005 (.012)
Datum Plane
R
B
e
C
E1
α
.13 (.005) R Min.
Pin 1 Indentifier
E
L
0.076" (1.95mm) Ref
Lead Detail
See Lead Detail
Base Plane
A
A2
-C-
Lead Coplanarity
ccc
B
Seating Plane
A1
C
59
TMC22091/TMC22191
PRODUCT SPECIFICATION
Ordering Information
Product Number
TMC22091KHC
TMC22091R0C
TMC22191KHC
TMC22191R0C
Temperature Range
T = 0°C to 70°C
Screening
Commercial
Commercial
Commercial
Commercial
Package
Package Marking
22091KHC
100-Lead MQFP
84-Lead PLCC
100-Lead MQFP
84-Lead PLCC
A
T = 0°C to 70°C
A
22091R0C
T = 0°C to 70°C
A
22191KHC
T = 0°C to 70°C
A
22191R0C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
6/12/98 0.0m 002
Stock# DS70022091
1998 Fairchild Semiconductor Corporation
相关型号：
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