TMC22051AKHC [CADEKA]
Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit; 多标准数字视频解码器三线自适应梳状解码器系列， 8和10位
| 型号： | TMC22051AKHC |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| 文件： | 总84页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.cadeka.com
TMC2 2 x 5 yA
Mu lt is t a n d a rd Dig it a l Vid e o De c o d e r
Th re e -Lin e Ad a p t ive Co m b De c o d e r Fa m ily, 8 & 1 0 b it
Features
Description
The TMC22x5yA family of Digital Video Decoders offers
unprecedented, broadcast-quality video processing perfor-
mance in a single chip. It accepts line-locked or subcarrier-
locked composite, YC, or D1 digital video and produces dig-
ital components in a variety of formats.
• Very high performance, low cost
• Adaptive comb-based decoding
• Multiple pin-compatible versions
- 3-line, 2-line, and band-split
- 8- and 10-bit processing
• Internal digital linestores
• Supports NTSC/PAL field and NTSC frame based
decoding
• Multiple input formats
- CCIR-601/624 (D1), D2, CVBS, YC
• Multiple output formats
An internal three-line adaptive comb decoder structure pro-
duces optimal picture quality with a wide range of source
material. NTSC/PAL field and NTSC frame based decoding
is supported with external memory. Full comb programma-
bility allows the user to tailor the decoder’s response to a
particular systems goals.
- CCIR-601/624 (D1), RGB, YC C
• 10-18 Mpps data rate
• Parallel and serial control interface
• Single +5V power supply
B R
A family of products offers 3-line, 2-line, and simple decod-
ers in 8-bit and 10-bit versions—all in a pin and software-
compatible format. Serial and parallel control ports are pro-
vided. These submicron CMOS devices are packaged in a
100-lead Metric Quad Flat Pack (MQFP).
Applications
• Studio television equipment
• Personal computer video input
• MPEG and JPEG compression inputs
Related Products
• TMC22071 Genlocking Video Digitizer
• TMC22x9x 8 bit Digital Video Encoders
• TMC2081 Digital Video Mixer
• TMC3003 Triple 10-bit D/A Converter
• TMC1185 10 bit A/D converter
• TMC2192 10 bit video encoder
• TMC2072 Enhanced Genlocking Video Digitizer
Block Diagram
BUFFER
MASTER
1-0
Y/C Split0
Y/C Split1
G/Y
9-0
VIDEOA
VIDEOB
9-0
Chroma
Demod
Output
Processor
Input
Processor
Adaptive
Comb
Filter
B/Cb
9-0
9-0
Linestore1
Linestore2
R/Cr
9-0
Burst
Locked
Loop
Comb
Fail
Y/C Split2
FID
2-0
DREF
DHSYNC
DVSYNC
CLOCK
LDV
HSYNC
VSYNC
Internal
Sync Pulse
Generator
Global Control
Parallel Control
Serial Control
65-22x5y-01
A
1-0
R/W
CS
D
SET RESET SER
SA
SDA SCL
2-0
7-0
REV. 1.0.0 2/4/03
TMC22x5yA
PRODUCT SPECIFICATION
Table of Contents
Features......................................................................1
Applications ...............................................................1
Description .................................................................1
Block Diagram............................................................1
Contents .....................................................................2
List of Tables and Figures ........................................3
General Description...................................................4
Input Processor...............................................................4
Adaptive Comb Filter.....................................................4
Output Processor............................................................5
Parallel and Serial Microprocessor Interfaces................5
Pin Assignments........................................................5
Pin Descriptions.........................................................6
Control Register Map.................................................8
Control Register Definitions ...................................11
Decoder Introduction...............................................40
YC Separation..............................................................40
Comb Filter Architecture for YC Separation...............41
YC Line-Based Comb Filters.......................................42
D1 Line-Based Comb Filters .......................................42
NTSC Frame and Field Based Decoders ...............42
Composite Frame-Based Comb Filters........................42
Composite Field-Based Comb Filters..........................42
PAL Field Comb Decoders......................................42
Composite PAL Field Comb Filters.............................42
The TMC22x5yA Comb Filter Architecture............43
TMC22x5yA Functional Description.......................44
Input Processor.............................................................44
Bandsplit Filter (BSF)..................................................44
Comb Filter Input.........................................................45
Adaptive Comb Filter...................................................47
Comb Fails................................................................49
Comb Fail Detection ....................................................49
Generation of the Comb Fail Signals.....................50
Luma Error Signals ......................................................50
Hue and Saturation Error Signals.................................50
Picture Correlation .......................................................50
Adapting the Comb Filter ............................................50
XLUT...........................................................................51
Digital Burst Locked Loop ..........................................53
Color Kill Counter .......................................................53
PAL Color Frame Bit...................................................55
Hue Control..................................................................55
System Monitoring of the Burst Loop Error................55
Clamp Circuit .............................................................. 55
Pedestal Removal ........................................................ 55
Clamp Generator ......................................................... 55
Luma Notch Filter ....................................................... 56
Matrix .......................................................................... 56
Programmable U Scalar............................................... 56
Programmable V Scalar............................................... 56
Programmable Y Scalar............................................... 56
Programmable MS Scalar............................................ 56
Fixed (B-Y) and (R-Y) Scalars ................................... 56
Y Offset ....................................................................... 57
Matrix Limiters............................................................ 57
Examples of Output Matrix Operation........................ 57
Simple Luma Color Correction ................................... 58
C C MSB Inversion ................................................. 58
B R
Output Rounding ......................................................... 58
Output Formats............................................................ 58
Decimating C C Data............................................... 58
B R
Multiplexed YC C Output (TRS Words Inserted)... 58
B R
YC Outputs.................................................................. 58
The LDV Clock........................................................... 58
Sync Pulse Generator .............................................59
Internal Field and Line Numbering Scheme ............... 59
Timing Parameters ..................................................61
Subcarrier Programming ............................................. 61
Horizontal Timing ....................................................... 61
Horizontal and Vertical Timing Parameters................ 61
Vertical Blanking ........................................................ 62
VINDO Operation ....................................................... 65
Video Measurement.................................................65
Pixel Grab.................................................................... 65
Composite Line Grab .................................................. 67
Parallel Microprocessor Interface ............................... 67
Serial Control Port (R-Bus)......................................... 68
Equivalent Circuits and Threshold Levels ............71
Absolute Maximum Ratings....................................72
Operating Conditions..............................................73
Electrical Characteristics........................................75
Switching Characteristics.......................................76
System Performance Characteristics....................76
Programming Examples..........................................77
Programming Worksheet........................................81
Related Products .....................................................82
Ordering Information...............................................84
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PRODUCT SPECIFICATION
TMC22x5yA
List of Tables and Figures
Table 1. TMC22x5yA Decoder Family ................. 4
Table 2. Normalized Subcarrier Frequency
as a Function of Pixel Data Rates....... 45
Table 3. Comb Filter Architecture ..................... 48
Table 4. Simple Example of an Adaptive
Figure 11. Input Processor.................................... 44
Figure 12. Complementary Bandsplit Filter......... 44
Figure 13. Bandsplit Filter, Full Frequency
Response .............................................. 45
Figure 14. Bandsplit Filter, Passband
Comb Filter Architecture ..................... 48
Response .............................................. 45
Table 5. Adaption Modes ................................... 51
Table 6. XLUT Input Selection ........................... 52
Table 7. XLUT Output Function......................... 52
Table 8. XLUT Special Function Definitions..... 52
Table 9. PAL-B,G,H,I Bruch
Figure 15. Block Diagram of Comb Filter Input... 46
Figure 16. Signal Flow Around the Adaptive
Comb Filter ........................................... 47
Figure 17. Example of a Comb Fail Using a NTSC
Two Line Comb Filter........................... 49
Blanking Sequence .............................. 53
Figure 18. Generation of Upper and Lower Comb
Fail Signals ........................................... 50
Figure 19. Comb Filter Selection .......................... 51
Figure 20. XLUT Input Selection ........................... 52
Figure 21. Block Diagram of Digital Burst
Table 10. PAL-M Bruch Blanking Sequence ...... 54
Table 11. Blanking Level Selection..................... 55
Table 12. Adaptive Notch Threshold Control..... 55
Table 13. Matrix Limiters...................................... 57
Table 14. Output Format ...................................... 58
Table 15. NTSC Field and Line Numbering ........ 59
Table 16. PAL B,G,H,I Field and
Locked Loop......................................... 53
Figure 22. Gaussian Low Pass Filters.................. 54
Figure 23. Gaussian LPF Passband Detail........... 54
Figure 24. Output Processor Block Diagram....... 55
Figure 25. Adaptive Notch Filters ......................... 56
Figure 26. Luminance Notch Filter ....................... 56
Figure 27. Horizontal Timing................................. 61
Figure 28. External HSYNC and VSYNC Timing
for Field 1(3, 5, or 7) ............................. 62
Figure 29. NTSC Vertical Interval.......................... 62
Figure 30. PAL-B,G,H,I,N Vertical Interval............ 62
Figure 31. PAL-M Vertical Interval ........................ 63
Figure 32. Pixel Grab Locations............................ 64
Figure 33. Relationship Between Pixel Count
and Pixel Grab Value............................ 65
Line Numbering.................................... 59
Table 17. PAL M Field and Line Numbering....... 59
Table 18. Vertical Blanking Period...................... 60
Table 19. Vertical Burst Blanking Period............ 60
Table 20. Table of Line Idents, LID[4:0] .............. 60
Table 21. Timing Offsets ...................................... 61
Table 22. PAL VINDO operation .......................... 63
Table 23. Pixel Grab Control................................ 66
Table 24. Parallel Port Control............................. 67
Table 25. Serial Port Addresses.......................... 69
Figure 1. Logic Symbol.......................................... 4
Figure 2. Pixel Data Format................................... 4
Figure 3. Fundamental Decoder
Figure 34. Microprocessor Parallel Port –
Write Timing.......................................... 66
Block Diagram ...................................... 40
Figure 4. Comparison of the Frequency
Spectrum of NTSC and PAL
Figure 35. Microprocessor Parallel Port –
Read Timing.......................................... 68
Figure 36. Serial Port Read/Write Timing............. 69
Figure 37. Serial Interface –
Composite Video Signals .................... 40
Figure 5. Examples of Notch and Bandpass
Filters..................................................... 41
Figure 6. ............................................................... 41
Figure 7. Chrominance Vector Rotation in
PAL and NTSC...................................... 42
Figure 8. Chrominance Vector Rotation Over
4 Fields in NTSC................................... 42
Figure 9. Chrominance Vector Rotation Over
4 Fields in PAL...................................... 42
Figure 10. TMC22x5yA Line Based Comb
Filter Architecture ................................ 43
Typical Byte Transfer........................... 70
Figure 38. Equivalent Digital Input Circuit........... 71
Figure 39. Equivalent Digital Output .................... 71
Figure 40. Threshold Levels for Three-state........ 71
Figure 41. Input Timing Parameters ..................... 72
Figure 42. Functional Block Diagram of the
TMC22x5yA G/Y, B/U, and R/V Output
Stage...................................................... 73
Figure 43. Output Timing Parameters .................. 74
REV. 1.0.0 2/4/03
3
TMC22x5yA
PRODUCT SPECIFICATION
comb filtering, and simple decoding. The TMC22153A
10-bit three-line comb filter can be programmed to emulate
any of the other parts. All prototyping can be performed with
this version to evaluate performance tradeoffs, and lower-
cost versions are easily substituted in production.
General Description
The TMC22x5yA digital decoder can be used as a universal
input to digital video processing systems by decoding digital
composite video and transcoding digital component inputs
into a common data format.
Input Processor
The digital comb filter decoder implements one of sixteen
comb filter architectures to produce luminance and color dif-
ference component signals which are virtually free of the
cross-color and cross-luminance artifacts associated with
simple bandsplit filter decoders.
The digitized video and clocks provided to the decoder can
be either locked to the line frequency or the subcarrier fre-
quency of the digitized waveform, providing broadcast qual-
ity decoding from the NTSC square pixel rate of 12.27 MHz
to the PAL four times subcarrier pixel rate of 17.73 MHz.
Table 1.TMC22x5yA Decoder Family
TMC2215yA TMC2205yA
MSB
VA
LSB
VA
VA
VA
VA
1
9
8
2
0
Function
10-bit Data
3
2
1
3
2
1
VB
G/Y
VB
G/Y
VB
G/Y
VB
G/Y
VB
G/Y
9
9
8
8
2
2
1
1
0
0
•••
•••
10 bit
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
B/C
R/C
B/C
B/C
R/C
B/C
R/C
B/C
R/C
B9
R9
B8
B2
R2
B1
R1
B0
R0
8-bit Data
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
R/C
R8
D1 Interface
Line-Locked Mode
VA
VA
VA
2
VB
G/Y
N/C
N/C
9
8
VB
G/Y
VB
G/Y
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
9
9
8
8
2
2
f -Locked Mode
SC
8 bit
Genlock Mode
NTSC Frame Comb
NTSC/PAL Field Comb
3-Line Comb
B/C
R/C
B/C
B/C
R/C
B9
R9
B8
B2
R2
R/C
R8
Figure 2. Pixel Data Format
Inputs containing embedded GRS (CADEKA Video Input
Processors), TRS words (D1 multiplexed component sig-
nals), and TRS-ID words (deserialized D2 signals) can be
used to lock the internal horizontal and vertical state
machines to the embedded information. If this information is
not provided, external horizontal and vertical syncs are
required for all line-locked input formats, and are optional
for NTSC inputs locked to four times the subcarrier (4*Fsc).
A simple sync separator is provided for digitized inputs
locked to the subcarrier frequency: the internal sync separa-
tor locks to the mid point of syncs during the vertical field
group, then flywheels during the active portion of the field.
For this reason, the DHSYNC and DVSYNC operations are
not guaranteed in subcarrier mode.
2-Line Comb
✔
✔
✔
✔
✔
✔
Line Grab
Pixel Grab
✔
✔
Because the cost/performance tradeoff varies among applica-
tions, the TMC22x5yA decoder has been developed as a
family of six parts. They are all assembled in the same
package, and fit the same footprint. The register maps are
identical.
VIDEOA
VIDEOB
G/Y
B/C
R/C
9-0
9-0
9-0
B9-0
R9-0
CLOCK
LDV
Adaptive Comb Filter
FID
2-0
AVOUT
DHSYNC
DVSYNC
HSYNC
VSYNC
MASTER
BUFFER
TMC22x5yA
The line based adaptive comb filter in the TMC22x5yA adds
or subtracts the high frequency data from three adjacent field
lines to produce the average of the high frequency luminance
by canceling the chrominance signals, which in flat fields of
color are 180 degrees apart. Unfortunately flat fields of color
are rare and, when vertical transitions in the picture occur,
the output of the comb filter contains a mixture of both high
frequency luminance and chrominance, at which time the
comb fails. To avoid the comb filter artifacts that occur when
this happens, three sets of error signals are sent to a user-pro-
grammable lookup table, allowing the output of the comb fil-
ter to be mixed with the output of an internal bandsplit
decoder.
Multistandard
Digital
Video
Decoder
SER
SET
RESET
D
A
7-0
1-0
SA
2-0
SDA
SCL
CS
R/W
65-22x5yA-02
Figure 1. Logic Symbol
The devices come in 8- and 10-bit resolution versions (see
Figure 2 for data alignment between 8- and 10-bit versions).
Within each resolution version there are three models, offer-
ing three-line adaptive comb filtering, two-line adaptive
To produce these comb fail error signals, the video on each
of the inputs to the comb filter is passed through a simple
bandsplit decoder. The low-frequency portion of the signal is
4
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
assumed to be luminance and the high frequency portion is
processed as chrominance to find the magnitude and phase of
the chrominance vector. These three components are then
compared across the (0H & 1H) and (1H & 2H) taps of the
comb filter to produce the difference in luminance, chromi-
nance magnitude, and chrominance phase. These differences
are then translated in the user-programmable lookup table to
produce the “K” signal which controls the complementary
mix between the output of the comb filter and the simple
bandsplit decoder. That is, the “K” signals controls how
much of the combed high frequency luminance signal is sub-
tracted from the simple bandsplit chrominance for chroma
combs, or added to the low frequency output of the bandsplit
for luma comb filters.
Parallel and Serial Microprocessor Interfaces
The parallel microprocessor interface employs 12 pins, the
serial port uses 5. A single pin, SER, selects between the two
interface modes.
In parallel interface mode, one address line is decoded for
access to the internal control register and its pointer.
Controls are reached by loading a desired address through
the 8-bit D port, followed by the desired data (read or
7-0
write) for that address. The control register address pointer
auto-increments to address 3Fh and then remains there.
A 2-line serial interface may also be used for initialization
and control. The same set of registers accessed by the paral-
lel port is available to the serial port. The device address in
Output Processor
the serial interface is selected via pins SA
.
2-0
The demodulated chrominance signal and the luminance
signal are passed through a programmable output matrix,
The RESET pin sets all internal state machines to their ini-
tialized conditions and places the decoder in a power-down
mode. All register data are maintained while in power-down
mode.
producing RGB, YUV, or YC C . When the clock is at
B R
27MHz, a D1 signal can be produced on the R/V output with
the embedded TRS words fixed to the external HSYNC and
VSYNC timing.
Pin Assignments
100
81
Pin Name
Pin Name
Pin Name
Pin Name
1
2
3
4
5
6
7
8
9
G/Y
26 R/Cr
27 R/Cr
51
52
53
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
GND
1
1
0
RESET
SET
G/Y
VIDEOA
1
80
0
0
LDV
GND
28 GND
29
30 DREF
31 FID
VIDEOA
1
SER
V
54 SA
VIDEOA
2
DD
0
V
DD
55 SA
VIDEOA
3
1
B/Cb
B/Cb
B/Cb
B/Cb
56 SA
VIDEOA
4
9
8
7
6
5
4
3
2
1
0
0
2
32 FID
57 GND
58 SDA
59 SCL
VIDEOA
5
1
33 FID
VIDEOA
6
2
34
35
36
37
38
VIDEOA
7
DHSYNC
DVSYNC
D
0
10 B/Cb
11 B/Cb
12 B/Cb
13 B/Cb
14 B/Cb
15 B/Cb
60
61
62
63
VIDEOA
8
CS
VIDEOA
9
R/W
A
0
D
1
MASTER
0
D
2
A
1
MASTER
1
39 GND
64 GND
65
66 VIDEOB
CLOCK
GND
40
41
42
43
44
45
V
V
DD
DD
16 GND
17
D
3
V
0
DD
GND
G/Y
V
DD
D
4
67 VIDEOB
1
18 R/Cr
19 R/Cr
20 R/Cr
21 R/Cr
22 R/Cr
23 R/Cr
24 R/Cr
25 R/Cr
D
5
68 VIDEOB
2
9
8
7
6
5
4
3
2
9
D
6
69 VIDEOB
G/Y
8
3
51
30
D
7
70 VIDEOB
G/Y
7
4
46 GND
71 VIDEOB
G/Y
6
5
47
48
49
V
72 VIDEOB
G/Y
5
DD
6
31
50
73 VIDEOB
G/Y
4
HSYNC
VSYNC
7
65-22x5y-03
74 VIDEOB
G/Y
3
8
50 BUFFER 75 VIDEOB
100 G/Y
2
9
REV. 1.0.0 2/4/03
5
TMC22x5yA
PRODUCT SPECIFICATION
Pin Descriptions
Pin Name
Inputs
Pin Number
Value
Pin Function Description
VIDEOA
VIDEOB
VSYNC
86, 85, 84, 83,
82, 81, 80, 79,
78, 77
TTL
Video input A. An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOA ).
9-0
9-2
75, 74, 73, 72,
71, 70, 69, 68,
67, 66
TTL
TTL
Video input B. An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOB ).
9-0
9-2
49
Vertical sync input. A vertical sync signal (active low) occurring at the
start of the first vertical sync pulse in a vertical field group. A falling edge
of VSYNC which is coincident with a falling edge of HSYNC indicates
field 1. This signal is active only when SPGIP
= 00.
1-0
HSYNC
48
TTL
TTL
Horizontal sync input. A horizontal sync signal (active low) occurring
at the falling edge of the video sync. This signal is active only when
SPGIP
= 00.
1-0
MASTER
88, 87
Master decoder control.
1-0
00
01
10
11
Adaptive comb decoder
Simple bandsplit decoder
Reserved
Flat notched luma and simple bandsplit chroma
BUFFER
CLOCK
50
89
52
TTL
TTL
TTL
Control register select. This signal switches between two sets of
registers which control the gain or hue values in the output matrix.
When BUFFER = 0, registers 17-1F are active. When BUFFER = 1,
registers 27-2F take control.
Master processing clock. The clock signal can either be at twice the
pixel data rate in the line locked modes, or at four times the subcarrier
frequency in the subcarrier mode. The interpretation of the CLOCK
signal is set by the CKSEL register bit.
SET
Programmable function pin. The function specified by the SET
register is active when SET is low. The decoder returns to its previous
operation when SET goes high.
Outputs
G/Y
B/C
R/C
93, 94, 95, 96,
97, 98, 99, 100,
1, 2
TTL
TTL
TTL
Green or Luminance digital output. For 8-bit versions (TMC2205yA)
9-0
the data are left-justified (G/Y ).
9-2
6, 7, 8, 9, 10,
11, 12, 13, 14,
15
Blue or CB digital output. For 8-bit versions (TMC2205y) the data are
B9-0
R9-0
left-justified (B/C ).
B 9-2
18, 19, 20, 21,
22, 23, 24, 25,
26, 27
Red or CR digital output. For 8-bit versions (TMC2205yA) the data are
left-justified (R/C ).
R 9-2
DVSYNC
DHSYNC
LDV
35
34
3
TTL
TTL
TTL
Vertical sync output. The DVSYNC signal occurs once per field and
lasts for 1 video line.
Horizontal sync output. The DHSYNC signal occurs once per line and
lasts for 64 clock periods.
Data synchronization output. LDV can be an internally or externally
generated clock signal. The internal LDV signal is produced when the
CLOCK input is at twice the pixel data rate (PXCK); and is a pixel data
rate clock phase locked to the falling edge of the HSYNC. The external
LDV can be selected under software control, and must be at the
CLOCK, or a sub multiple of the CLOCK, frequency.
6
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Pin Descriptions (cont.)
Pin Name
Pin Number
Value
Pin Function Description
DREF
30
TTL
Decoder reference signal. This is a dual function pin, controlled by
register 24, that can function as an active video output indicator or
output as a clamp pulse. When set to the active video output function,
the DREF pin is HIGH during the video portion of each line and LOW
during the horizontal and vertical blanking levels. When set to output a
clamp pulse, the clamp pulse is controlled by register 24 and 25
allowing a user to program when a 0.5 µSec pulse is output relative to
HSYNC.
FID
2-0
33, 32, 31
TTL
Field identification output. A 3 bit field ident from the DRS signal.
µP Interface
D
45, 44, 43, 42,
41, 38, 37, 36
TTL
TTL
Parallel control port data I/O. All control parameters are loaded into
and read back over this 8 bit data port.
7-0
A
63, 62
Parallel control port address inputs. These pins govern whether the
microprocessor interface selects a table/register address or reads/
writes table/register contents.
1-0
CS
60
TTL
TTL
Parallel control port chip select. When CS is high the microprocessor
interface port, D , is set to HIGH impedance and ignored. When CS
7-0
is LOW, the microprocessor can read or write parameters over D
.
7-0
R/W
61
Parallel control port read/write control. When R/W and CS are LOW,
the microprocessor can write to the control registers or XLUT over
D . When R/W is HIGH and CS is LOW, it can read the contents of
7-0
any selected XLUT address or control register over D
.
7-0
RESET
SER
51
53
TTL
Chip master reset. Bringing RESET LOW sets the software reset
control bit, SRESET, LOW and disables the digital outputs. If HRESET
is LOW the decoder outputs remain disabled after RESET goes HIGH
until the SRESET bit is set high by the host. If HRESET is HIGH when
RESET goes HIGH the decoder the internal state machines are
enabled.
TTL
Serial/parallel interface select. This pin will select between a parallel
(HIGH) or serial (LOW) interface port.
SDA
SCL
58
59
R-Bus
R-Bus
TTL
Serial data interface. Bi-directional serial interface to the control port.
Serial interface clock.
SA
56, 55, 54
Serial Address. Three bits providing the lsbs of the serial chip ID used
2-0
to identify the decoder.
Power Supply
V
5, 17, 29, 40,
47, 65, 91
+5 V
Power Supply. Positive power supply for digital circuits, +5V.
Ground. Ground for digital circuits, 0V.
DD
GND
4, 16, 28, 39,
46, 57, 64, 76,
90, 92
0.0 V
REV. 1.0.0 2/4/03
7
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Map
Reg Bit Name
Function
The TMC22x5yA is initialized and controlled by a set of
registers which determine the operating modes.
Luma Processor Control
06 7-6
reserved, set to zero
Adaptive notch enable
Adaptive notch rounding
Adaptive notch threshold
Adaptive notch select
Notch enable
An external controller is employed to write and read the
Control Registers through either the 8-bit parallel or 2-line
06
06
5
4
ANEN
ANR
serial interface port. The parallel port, D , is governed by
7-0
06 3-2 ANT
pins CS, R/W, and A . The serial port is controlled by SDA
1-0
and SCL.
06
06
1
0
ANSEL
NOTCH
Reg Bit Name
Global Control
Software reset
Function
Comb Processor Control
07
07
07
07
07
07
07
7
6
5
4
3
2
1
LS1BY
LS1IN
Line store 1 bypass
00
00
7
6
SRST
HRST
Line store 1 input
Hardware reset
LS2DLY
SPLIT
Line store 2 delay
00 5-3 SET
00 DHVEN
00 1-0 STD
SET pin function
Line store 2 data width
Bandsplit filter bypass
Bandsplit filter select
2
Output H&V sync enable
Selects video standard
BSFBY
BSFSEL
BSFMSB
Input Processor Control
Inverts msb of bandsplit
filter
01
01
01
01
01
01
01
01
7
6
5
4
3
2
1
0
reserved, set to zero
Input mux control
IPMUX
IP8B
07
0
GRSDLY
Delays input to GRS
decode by 1H
8 bit input format
TDEN
TRS detect enable
TRS blank enable
Chroma input msb invert
AB mux control
Mid-Sync Level
Mid-sync level
Extended DRS
TBLK
08 7-0 MIDS
IPCMSB
ABMUX
CKSEL
09 7-4 PCKF
09 3-0 VSTD
Clock rate
Input clock rate select
Video standard
Burst Loop Control
Output Control
02
02
7
6
BLLRST
VIPEN
BLL auto. reset enable
0A
7
OP8B
Output rounded to 8 bits
Output limit select
Video Input Processor
enable
0A 6-5 OPLMT
0A 4-3 MSEN
Mixed sync enable
02 5-4 LOCK
Global lock mode
BLL lock mode
Color kill disable
Demod bypass
0A
0A
0A
0B
0B
0B
2
1
0
7
6
5
OPCMSB
YBAL
Chroma output msb invert
Luma color correction
Output burst enable
02
02
02
02
3
2
1
0
BLM
KILD
BUREN
FMT422
CDEC
DMODBY
CINT
Enables C C output mux
B R
C C interpolation enable
B R
C C decimation enable
B R
Chroma Processor Control
YUVT
Enables D1 output
reserved, set to zero
DRS output enable
DRS data rate
03 7-5 BLFS
03 CCEN
03 3-2 CCOR
Burst loop filter select
Chroma coring enable
Chroma coring threshold
Gaussian filter bypass
Gaussian filter select
0B 4-2
4
0B
0B
1
0
DRSEN
DRSCK
03
03
1
0
GAUBY
Comb Filter Control
GAUSEL
0C 7-6 ADAPT
Adaption mode
Burst Threshold
Burst threshold
Pedestal
Pedestal level
0C
5
YCES
YC input error signal
control
04 7-0 BTH
05 7-0 PED
0C
4
YCSEL
luma/chroma comb filter
select
0C 3-0 COMB
Comb filter architecture
REV. 1.0.0 2/4/03
8
PRODUCT SPECIFICATION
TMC22x5yA
Reg Bit Name
Function
Reg Bit Name
Function
V gain, 8 lsbs
0D 7-6 CEST
Chroma error signal
transform
1A 7-0 VG0
1B 7-6 YG0
1B 5-3 UG0
7-0
Y gain, 2 msbs
U gain, 3 msbs
9-8
0D
0D
0D
5
4
3
CESG
Chroma error signal gain
Luma error signal gain
10-8
YESG
1B
2
reserved, set to zero
V gain, 2 msbs
Y offset, 8 lsbs
reserved, set to zero
Y offset, msb
CESTBY
Chroma error signal
bypass
1B 1-0 VG0
9-8
1C 7-0 YOFF0
1D 7-3
7-0
0D
0D
0D
2
1
0
XFEN
FAST
YWBY
XLUT filter enable
Adaption speed select
Luma weighting bypass
XLUT input select
XLUT special function
Y output select
1D
2
YOFF0
7-0
1E 7-1 SYSPH0
8
1D 1-0 SG0
Msync gain, 2 msbs
7 lsbs of phase
V axis flip
0E 7-6 XIP
6-0
0E 5-4 XSF
0E 3-2 YMUX
0E 1-0 CMUX
1E
0
VAXISO
1F 7-0 SYSPH0
8 msbs of phase
14-7
C output select
Normalized Subcarrier Frequency
0F
0F 6-5 CAT
0F DCES
0F 3-2 IPCF
7
reserved, set to zero
Adaption Threshold
20 7-4 FSC
20 3-0
Bottom 4 bits of f
SC
3-0
reserved, set to zero
4
D1 C C error signal
B R
21 7-0 FSC
22 7-0 FSC
23 7-0 FSC
Lower 8 bits of f
11-4
SC
Comb filter input select
Middle 8 bits of f
19-12
27-20
SC
SC
0F
1
YCCOMP
YC or Composite input
select
Top 8 bits of f
Clamp Control
0F
0
SYNC
Sync processor select
24
24
7
6
DRFSEL
PFLTBY
Clamp pulse enable
Phase filter enable
Int. clamp selection
Clamp bypass
Sync Pulse Generator
10 7-0 STS
11 7-0 STB
12 7-0 BTV
Sync to sync 8 lsbs
Sync to burst
7-0
24 5-4 CLPSEL
1-0
VCLPEN
24 2-0 BAND
24
3
Burst to video
Clamp offset
2-0
25 7-0 CPDLY
13 7-0 AV
14 7-6
Active video line 8 lsbs
reserved, set to zero
Active video line 2 msbs
reserved, set to zero
Sync to sync 3 msbs
reserved, set to zero
7-0
Clamp pulse delay
7-0
Output Format Control
reserved, set to zero
14 5-4 AV
9-8
26 7-6
14
3
26
26
26
5
4
3
LDVIO
LDV clock select
Output clock select
DPC enable
14 2-0 STS
10-8
OPCKS
DPCEN
15
7
15 6-2 VINDO
Number of lines in vertical
window
26 2-0 DPC
Decoder product code
15
15
1
0
VDIV
Action inside VINDO
Action outside VINDO
reserved, set to zero
new field detect delay
SPG input select
Buffered register set 1
Active when BUFFER pin set HIGH
VDOV
27 7-0 SG1
28 7-0 YG1
29 7-0 UG1
2A 7-0 VG1
2B 7-6 YG1
2B 5-3 UG1
Msync gain, 8 lsbs
Y gain, 8 lsbs
7-0
7-0
7-0
7-0
9-8
10-8
16 7-6
16 5-4 NFDLY
16 3-2 SPGIP
16 1-0 MSIP
U gain, 8 lsbs
V gain, 8 lsbs
Mixed sync separator input
select
Y gain, 2 msbs
U gain, 3 msbs
reserved, set to zero
V gain, 2 msbs
Y offset, 8 lsbs
reserved, set to zero
Buffered register set 0
Active when BUFFER pin set LOW
2B
2
17 7-0 SG0
18 7-0 YG0
19 7-0 UG0
Msync gain, 8 lsbs
Y gain, 8 lsbs
7-0
7-0
7-0
2B 1-0 VG1
9-8
2C 7-0 YOFF1
2D 7-3
7-0
U gain, 8 lsbs
REV. 1.0.0 2/4/03
9
TMC22x5yA
PRODUCT SPECIFICATION
Reg Bit Name
Function
Y offset, msb
Reg Bit Name
Function
2D
2
YOFF1
Status - Read Only
8
2D 1-0 SG1
Msync gain, 2 msbs
7 lsbs of phase
V axis flip
40 7-0 DDSPH
DDS phase, 8 msbs
Pixel count reset
Start of burst gate
Half line flag
7-0
2E 7-1 SYSPH1
41
41
41
41
41
41
41
41
42
42
7
6
5
4
3
2
1
0
7
6
LINEST
BGST
6-0
2E
0
VAXIS1
2F 7-0 SYSPH1
8 msbs of phase
VACT2
PALODD
VFLY
14-7
Video Measurement
PAL Ident
30
30
30
30
30
30
30
30
7
6
5
4
3
2
1
0
set to zero
Vertical count reset
Field grab
LGF
Line grab flag
FGRAB
LGRAB
PGRAB
FLD
LGEN
Line grab enable
Ext line grab enable
reserved, set to zero
Pixel grab gate
Line grab
LGEXT
Pixel grab
Field flag (F in D1 output)
PGG
VBLK
Vertical blanking (V in D1
output)
PGEN
PGEXT
Pixel grab enable
Ext pixel grab enable
Pixel grab, 8 lsbs
Line grab, 8 lsbs
reserved, set to zero
Field grab number
Msb of line grab
Pixel grab, 3 msbs
G/Y grab, 8 msbs
B/U grab, 8 msbs
R/V grab, 8 msbs
reserved
42
5
HBLK
Horizontal blanking (H in
D1 output)
31 7-0 PG
7-0
7-0
42 4-0 LID
Line identification
Y/G overflow
32 7-0 LG
33
33 6-4 FG
43
43
43
43
43
43
7
6
5
4
3
2
YGO
YGU
UBO
UBU
VRO
VRU
7
Y/G underflow
C /B overflow
B
33
3
LG
8
C /B underflow
B
33 2-0 PG
34 7-0 GY
35 7-0 BU
36 7-0 RV
37 7-6
10-8
9-2
C /R overflow
R
C /R underflow
R
9-2
43 1-0
44
reserved
9-2
7
MONO
Color kill active
Frequency/Phase error
DRS signal
44 6-0 FPERR
45 7-0 DRS
37 5-4 GY
37 3-2 BU
37 1-0 RV
G/Y grab, 2 lsbs
B/U grab, 2 lsbs
R/V grab, 2 lsbs
Luma grab, 8 msbs
Msync grab, 8 msbs
U grab, 8 msbs
1-0
1-0
1-0
46 7-0 PARTID
47 7-0 REVID
Reads back xx
h
Revision number
reserved
38 7-0
39 7-0
3A 7-0
3B 7-0
3C 7-6
3C 5-4
3C 3-2
3C 1-0
Y
9-2
48- 7-0
4A
M
9-2
U
9-2
9-2
1-0
4B
7
PKILL
Phase kill from comb fail
Comb filter status
XLUT output
V
Y
V grab, 8 msbs
4B 6-5 CFSTAT
4B 4-0 XOP
Luma grab, 2 lsbs
Msync grab, 2 lsbs
U grab, 2 lsbs
M
1-0
1-0
1-0
4C- 7-0
FF
reserved
U
Notes:
V
V grab, 2 lsbs
1. Functions are listed in the order of reading and writing.
Test Control
2. For each register listed above up to register 3F, all bits not
specified are reserved and must be set to zero to ensure
proper operation.
3D 7-0 TEST
3E 7-0 TEST
Must be set to zero
Must be set to zero
Vertical Blanking Control
3F
3F
7
6
VBIT20
V bit control
PEDDIS
Pedestal control
Closed caption control
3F 5-0 CCDEN
5-0
Auto-increment stops at 3F
10
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions
Global Control Register (00)
7
6
5
4
3
2
1
0
SRST
HRST
SET
DHVEN
STD
Reg
Bit
Name
Description
00
7
SRST
Software reset. When LOW, resets and holds internal state machines and
disables outputs. When HIGH (normal), starts and runs state machines and
enables outputs. This bit is ignored while HRST is high.
00
6
HRST
SET
Hardware reset. When HRST is HIGH, SRST is forced low when RESET pin
is taken LOW. State machines are reset and held. When HRST is low the
RESET pin can be taken HIGH at any time. The state machines remain
disabled until SRST is programmed HIGH. When HRST is high the state
machines are enabled as soon as the RESET pin goes HIGH.
00
5-3
SET pin function. These bits control the set function when the SET pin goes
low.
A = all outputs high-impedance
B = internal state machines
C = burst locked loop
SET
000
001
Function
Reset and hold A, B, & C.
Set output to BLUE and flywheel B & C. (RGB outputs)
Set output to "color" and flywheel B & C (YC C outputs)
B R
010
011
100
101
110
111
Hold A, lock B & C to external input
Reset C only
Reset B & C
Set output to BLUE and lock B & C to input video (RGB output)
Line and pixel grab depending on VMCR
6-0
(reg 30)
Toggle reset function of SET = 010. For each SET = 0 pulse the
chip operation will change from normal to that of SET = 010 or
visa versa.
The first SET pulse after a software or hardware reset, with SET = 111,
causes a toggle to SET = 010.
00
00
2
DHVEN
STD
Output H&V sync enable. Disables DHSYNC and DVSYNC signals when
HIGH.
1-0
Selects video standard. Selects video standard.
SET
00
Function
NTSC
01
reserved
10
PAL/M
11
All PAL standards except PAL/M
REV. 1.0.0 2/4/03
11
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Input Processor Control (01)
7
6
5
4
3
2
1
0
Reserved
IPMUX
IP8B
TDEN
TBLK
IPCMSB
ABMUX
CKSEL
Reg
Bit
Name
Description
Reserved, set to zero.
01
01
7
6
Reserved
IPMUX
Input mux control. Used to select the Video Input Processor, D1, or D2 data
as the VA input to the input processor.
VIDEOA is selected for VA and VIDEOB is selected for VB when IPMUX is
set LOW. VIDEOB is selected for VA and VIDEOA for VB when IPMUX is set
HIGH. For YC inputs, the luma data must be passed through the VA input and
chroma through the VB input.
IPMUX should be set LOW for line locked composite inputs.
01
01
5
4
IP8B
8 bit input format. Bottom two bits of inputs VIDEOA
set to zero when HIGH.
and VIDEOB are
9-0
9-0
TDEN
TRS detect enable. When HIGH, the TRS words embedded in incoming
video are used to reset the horizontal and vertical state machines. When LOW
the externally provided or internally generated HSYNC and VSYNC are used
to reset the horizontal and vertical state machines.
01
3
TBLK
TRS blank enable. Blanks the TRS and AUX data words when HIGH. For line
locked and D1 data, the TRS and AUX data words are set to the luma and
chroma blanking levels as appropriate. For D2 (4*f ) data, the TRS and
SC
AUX data words are set to the sync tip level.
01
01
2
1
IPCMSB
ABMUX
Chroma input msb invert. The msb of the chroma or C C data are inverted
when HIGH.
B R
AB mux control. Selects the primary and secondary inputs to the decoder
from the DA and DB outputs of the input processor. When ABMUX is LOW,
DA is selected as the primary and DB as the secondary decoder input.
01
0
CKSEL
Input clock rate select. Set HIGH for line locked clocks and LOW for
subcarrier locked clocks. Line locked clocks should be at twice the pixel data
rate, and the subcarrier clock should be at four times the subcarrier
frequency.
12
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Burst Loop Control (02)
7
6
5
4
3
2
1
0
BLLRST
VIPEN
LOCK
BLM
KILD
DMODBY
CINT
Reg
Bit
Name
Description
02
02
7
BLLRST
BLL reset enable. When LOW, the automatic BLL reset is disabled. When
HIGH, the BLL will be reset if the BLL loses lock and fails to reacquire lock
within 8 fields.
6
VIPEN
LOCK
Video Input Processor enable. Selects interface protocol for CADEKA video
input devices. Active only when LOCK
= 10.
1-0
VIPEN Function
0
1
Video Input Processor Interface
TMC22071 Interface
02
5-4
Global Lock mode. Sets the decoder locking mode.
LOCK Function
00
01
10
11
Line Locked Mode
Subcarrier Locked Mode
Video Input Processor Mode
D1 Mode
02
3
BLM
BLL lock mode. Sets the decoder burst locking mode.
BLM Function
0
1
Frequency Lock
Phase Lock
02
02
02
2
1
0
KILD
Color kill disable. Color killer is disabled when HIGH.
DMODBY
CINT
Demod bypass. Chroma data bypasses the demodulator when HIGH.
C C interpolation enable. Interpolation of C C input data from 0:2:2 to
B R
B
R
0:4:4 is enabled when HIGH.
REV. 1.0.0 2/4/03
13
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Chroma Processor Control (03)
7
6
5
4
3
2
1
0
BLFS
CCEN
CCOR
GAUBY
GAUSEL
Reg
Bit
Name
Description
Burst loop filter select.
BLFS f (Mpps)
03
7-5
BLFS
Recommended Criteria
S
000
000
001
001
010
010
011
011
100
101
110
111
13.5
15
PAL, Line-Locked YC
PAL, Line-Locked YC
12.27
13.5
13.5
15
NTSC, Line-Locked YC
PAL, Line-Locked Composite
NTSC, Line-Locked YC
PAL, Line-Locked Composite
NTSC, Subcarrier-Locked YC
PAL, Subcarrier-Locked Composite
PAL, Subcarrier-Locked YC
NTSC, Line-Locked Composite
NTSC, Line-Locked Composite
NTSC, Subcarrier-Locked Composite
14.32
17.73
17.73
13.5
12.27
14.32
03
03
4
CCEN
CCOR
Chroma coring enable. Enables Chroma Coring when HIGH.
Chroma coring threshold. Sets the Chroma Coring threshold.
3-2
CCOR
00
Function
1 lsb
2 lsb
3 lsb
4 lsb
01
10
11
03
03
1
0
GAUBY
Gaussian filter bypass. The chroma data bypasses the Gaussian LPF when
HIGH.
GAUSEL
Gaussian LPF select. Selects the Gaussian filter response to be used on the
demodulated chrominance.
GAUSEL
Function
0
1
Select Gaussian LPF resp. 2
Select Gaussian LPF resp. 1
See Figure 22 for filter responses.
14
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Burst Threshold (04)
7
6
5
4
3
2
1
0
BTH
Reg
Bit
Name
Description
04
7-0
BTH
Burst threshold. The 8 bit value to be compared against the demodulated
U and V component data. If over 127 lines occur in a field in which the burst
is below this threshold, then the color is set to chroma black for the next field.
Pedestal (05)
7
6
5
4
3
2
1
0
PED
Reg
Bit
Name
Description
05
7-0
PED
Pedestal level. An 8 bit magnitude subtracted from the luma data to remove
the setup before processing by the output matrix.
Luma Processor Control (06)
7
6
5
4
3
2
1
0
Reserved
ANEN
ANR
ANT
YSEL
NOTCH
Reg
06
Bit
7-6
5
Name
Reserved
ANEN
ANR
Description
Reserved, set to zero.
06
Adaptive notch enable. Enables adaptive notch when HIGH.
Adaptive notch rounding. Sets adaptive notch rounding point.
06
4
ANR
Function
Round to 10 bits
Round to 8 bits
0
1
06
3-2
ANT
Adaptive notch threshold level. Sets the adaptive notch threshold.
ANT
00
Function
Magnitude difference less than 32
Magnitude difference less than 24
Magnitude difference less than 16
Magnitude difference less than 8
01
10
11
06
06
1
0
YSEL
Adaptive notch select. Selects adaptive notch filter response.
YSEL
Function
0
1
Adaptive notch response ANF1
Adaptive notch response ANF2
NOTCH
Notch enable. Adaptive notch filter ANF3 selected when HIGH and ANEN is
HIGH, non-adaptive notch filter selected when HIGH and ANEN is LOW.
Function may be overridden by XSF (Reg 0E, bits 5-4).
REV. 1.0.0 2/4/03
15
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Comb Processor Control (07)
7
6
5
4
3
2
1
0
LS1BY
LS1IN
LS2DLY
SPLIT
BSFBY
BSFSEL
BSFMSB
GRSDLY
Reg
Bit
7
Name
LS1BY
LS1IN
Description
07
07
Line store 1 bypass. Bypasses linestore 1 when HIGH.
Line store 1 input. Selects the input of linestore 1:
6
LS1IN
Function
0
1
Primary Input
Secondary Input
07
07
5
4
LS2DLY
SPLIT
Line store 2 delay. LSTORE2 uses STS to store 1H when LOW and uses
VL to store SAV to EAV (or max count) when HIGH.
Line store 2 delay. Splits data through LSTORE2, 9 bits chroma and 7 bits
luma when HIGH (chroma combs) and 8 bits chroma and 8 bits luma when
LOW (luma comb).
07
07
3
2
BSFBY
Bandsplit filter bypass. Bandsplit filter is bypassed when HIGH.
Bandsplit filter select. Selects the bandsplit filter to be used:
BSFSEL
BSFSEL
Function
0
1
Select bandsplit filter response 1
Select bandsplit filter response 2
07
07
1
0
BSFMSB
GRSDLY
Inverts msb of bandsplit filter. When HIGH, inverts the msb of the input to
the bandsplit filter.
Delays input to GRS decode. When HIGH, delays the input to the GRS
extraction circuit by 1H. Genlock only.
Mid-Sync Level (08)
7
6
5
4
3
2
1
0
MIDS
Reg
Bit
Name
Description
08
7-0
MIDS
Mid sync level. Sets the mid point of syncs for the mixed sync separator, in
the subcarrier locked mode.
16
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Extended DRS (09)
7
6
5
4
3
2
1
0
PCKF
VSTD
Reg
Bit
Name
PCKF
Description
Clock rate.
09
7-4
PCKF
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Function
13.50 MHz
reserved
reserved
reserved
14.32 MHz
17.73 MHz
reserved
reserved
12.27 MHz
14.75 MHz
15.00 MHz
reserved
reserved
reserved
reserved
reserved
09
3-0
VSTD
Video Standard. Selects the video standard.
Function
VSTD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
NTSC-M
NTSC-EIAJ
reserved
reserved
reserved
reserved
reserved
reserved
PAL-B, G, H, I
PAL-M
PAL-N (Argentina, Paraguay, Uruguay)
PAL-N (Jamaica)
reserved
reserved
reserved
reserved
REV. 1.0.0 2/4/03
17
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Output Control (0A)
7
6
5
4
3
2
1
0
OP8B
OPLMT
OPLMT
MSEN
OPCMSB
YBAL
BUREN
Reg
Bit
Name
Description
0A
7
OP8B
Output rounded to 8 bits. Rounds the outputs to 8 bits when HIGH. The two
lsbs are set to zero.
0A
6-5
OPLMT
Output limit select. Sets the output format and limiters:
OPLMT
Function
00
RGB output format
limited to 4 to 1016
01
YC C output format
B R
Y limited to 4 to 1016
C C limited to ±504
B R
10
11
RGB output format
limited to 4 to 1016
YC C output format
B R
Y limited to 64 to 940
C C limited to ±448
B R
0A
4-3
MSEN
Mixed sync enable. Sets composite sync output format:
MSEN
00
Function
No sync, & “super blacks” disabled
01
10
11
No sync, & “super blacks” disabled
Sync on G/Y output only, & “super blacks” enabled
Sync on RGB outputs, & “super blacks” enabled
0A
0A
2
1
0
OPCMSB
YBAL
Chroma output msb invert. Inverts the msb of the C C or Chroma output
when HIGH.
B R
Luma color correction. Setting this bit HIGH forces the chroma to zero
whenever the luma equals or exceeds the luma limit.
0A
BUREN
Output burst enable. When HIGH, passes the burst through on the chroma
channel. Sets the burst region to zero when LOW.
Notes:
1. To enable “super blacks” and disable syncs of the output simply set MSEN[1] HIGH and the sync gain to zero.
18
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Output Control (0B)
7
6
5
4
3
2
1
0
FMT422
CDEC
YUVT
Reserved
DRSEN
DRSCK
Reg
Bit
Name
Description
Enables C C output mux. When HIGH, multiplexes the C and C data
0B
7
FMT422
B
R
B
R
onto the same data bus. The chroma or multiplexed C C output appears on
B R
the B/C output. The R/C output is forced low.
B
R
0B
0B
6
5
CDEC
YUVT
C C decimation enable. When HIGH, the C C data are decimated to
B R
0:2:2 in the output processor.
B
R
Enables D1 output. When HIGH, enables 4:2:2 multiplexed YC C onto the
B R
R/C data output with TRS words inserted into the output data stream. The Y
R
data are still available on the G/Y output and multiplexed C C is available on
B R
the B/U output.
0B
0B
0B
4-2
1
Reserved
DRSEN
DRSCK
Reserved, set to zero.
DRS output enable. When HIGH, enables the DRS onto the G/Y output.
DRS data rate. Sets the DRS output data rate.
0
DRSCK
Function
0
Embeds data bytes (8 bits) at PCK
clock rate
1
Embeds data nibbles (4 bits) at
PXCK clock rate
REV. 1.0.0 2/4/03
19
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Comb Filter Control (0C)
7
6
5
4
3
2
1
0
ADAPT
YCES
YCSEL
COMB
Reg
Bit
Name
Description
Adaption mode. Sets the 3-line comb filter adaption mode in NTSC.
0C
7-6
ADAPT
ADAPT[1:0]
Function
00
Adapts to best of 3 types of line based comb filters in NTSC
only.
01
10
Adapts to the best of two field or frame based comb filters
in NTSC only.
3 line (tap) comb only. Never adapts to a 2 line (tap) filter.
The higher set of comb filter error signals are sent to the
XLUT. NTSC or PAL comb filter.
11
Adapts to best of two 3 line chroma comb filters in PAL only.
0C
5
YCES
YC input error signal control. Error signal control for YC input, luma comb.
YCES
Function
0
LPF and HPF error signal, between (0H & 1H) or (1H & 2H) in
NTSC or between (0H & 2H) in PAL,are sent to XLUT
1
LPF error signal, between (0H & 1H) and (1H & 2H) in NTSC or
between (0H & 2H) in PAL, are sent to XLUT
0C
0C
4
YCSEL
COMB
Luma/chroma comb filter select. Selects luma or chroma comb filter.
YCSEL
Function
0
1
Chroma comb filter
Luma comb filter
3-0
Comb filter architecture.
COMB
Function
YC or composite comb filter architectures
PAL or NTSC 3 line comb
NTSC 3 line comb (0H & 1H)
NTSC 3 line comb (1H & 2H)
NTSC 2 line comb (0H & 1H)
NTSC (2 line) field comb
NTSC or PAL field comb
NTSC (2 line) frame comb
NTSC frame comb
0000
0001
0010
0011
0100
0101
0110
0111
D1 comb filter architectures
3 line comb
3 line comb (0H & 1H)
3 line comb (1H & 2H)
3 line comb (0H & 2H)
(2 line) field comb
field or 2 line (0H & 1H) comb
(2 line) frame comb
frame comb
1000
1001
1010
1011
1100
1101
1110
1111
20
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Comb Filter Control (0D)
7
6
5
4
3
2
1
0
CEST
CESG
YESG
CESTBY
XFEN
FAST
YWBY
Reg
Bit
Name
Description
Chroma error signal transform.
0D
7-6
CEST
CEST
00
Video Standard
PAL/NTSC
NTSC
Clock Rate (MHz)
4*Fsc & 13.5MHz
12.27MHz
01
10
PAL
14.75MHz
11
PAL
15MHz
0D
0D
5
4
CESG
YESG
Chroma error signal gain.
CESG
Function
0
1
Normal chroma fail signal levels
Double the chroma error signal levels
Luma error signal gain.
YESG
Function
0
1
Normal luma fail signal levels
Double the luma error signal levels
0D
0D
0D
3
2
1
CESTBY
XFEN
Chroma error signal bypass. When HIGH, bypasses chroma error signal.
XLUT filter enable. When HIGH, enables the LPF on the XLUT output.
FAST
Adaption speed select. When HIGH, the 3 line comb filter selects between
comb filter architectures on a pixel by pixel basis. When LOW, the selection
is filtered.
0D
0
YWBY
Luma weighting bypass. When HIGH bypasses the luma fail weighting.
REV. 1.0.0 2/4/03
21
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Comb Filter Control (0E)
7
6
5
4
3
2
1
0
XIP
Bit
XSF
YMUX
CMUX
Reg
Name
Description
XLUT input select. Selects the comb fail signals presented to the XLUT:
0E
7-6
XIP
XIP[1:0]
Input to XLUT
00
2 bits of phase error (X[7:6]), 3 bits of chroma
(X[5:3]) and luma magnitude error (X[3:0]).
01
10
4 bits of chroma (X[7:4]) and luma magnitude
error (X[3:0]).
3 bits of phase error (X[7:5]), 3 bits of chroma
magnitude error (X[4:2]), and 2 bits of luma
magnitude error (X[1:0]).
11
4 bits of phase error (X[7:4]) and chroma
magnitude error (X[3:0]).
0E
5-4
XSF
XLUT special function.
XSF
00
Luma
Comb
Chroma
Simple
Comb
01
Simple
10
Flat with notch
Flat with notch
Simple
Comb
11
0E
3-2
YMUX
Y output select. Output selection of luma 4:1 mux
YMUX
00
Output
Comb
01
Flat - Comb
Flat
10
11
Simple
0E
1-0
CMUX
C output select. Output selection of chroma 4:1 mux
CMUX Output
00
Comb
01
10
11
Flat - Comb
Flat
Simple
22
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Comb Filter Control (0F)
7
6
5
4
3
2
1
0
Reserved
CAT
DCES
IPCF
YCCOMP
SYNC
Reg
Bit
Name
Description
0F
0F
7
Reserved
CAT
Reserved, set to zero.
Adaption threshold. Fixes threshold at which different comb filters are selected.
6-5
0
0
1
1
0
1
0
1
5% of max error
15% of max error
25% of max error
50% of max error
0F
4
DCES
D1 C C error signal. When set LOW for D1 chroma comb filters:
B R
a) In 3 line comb filter architectures, the magnitude error between the component
data for that pixel selects the 3 line comb or adapts to a
2 line comb. On a “C pixel” the error signal selected on pixel (x+4) is sent to
B
the XLUT with the magnitude difference between “C pixels” on the same pair
R
of lines, but from pixel (x+3). Likewise on a “C pixel” the error signal selected
R
on pixel (x+5) is sent to the XLUT with the magnitude difference between “C
pixels” on the same lines but from pixel (x+4).
B
b) In 2 line comb filters the magnitude differences between the same pair of lines
is always sent to the XLUT, On a “C pixel” the error from the preceding “C
B
R
pixel” is used and on a “C pixel” the preceding “C pixel” would be used.
R
B
When set HIGH for D1 chroma filters:
This is used for 3 line comb filter architecture that are inhibited from adapting to 2
line comb filter architectures. The input to the XLUT is the magnitude error in C
R
between (0H & 1H) and (1H & 2H) on “C pixels” and the magnitude error
R
between (0H & 1H) and (1H & 2H) on “C pixels”.
B
0F
3-2
IPCF
Comb filter input select. Selects primary inputs to the comb filter.
IPCF
Function
0 0
0 1
1 0
1 1
Flat video
LPF output
HPF output
Reserved
0F
0F
1
0
YCCOMP
SYNC
YC or Composite input select. Selects YC inputs when HIGH and composite
inputs when LOW.
Sync processor select. The syncs are obtained by a LPF when HIGH and by the
comb filter when LOW.
Sync Pulse Generator (10)
7
6
5
4
3
2
1
0
STS
STS
STS
STS
STS
STS
STS
STS
0
7
6
5
4
3
2
1
Reg
10
Bit
Name
STS
Description
7-0
Sync to sync 8 lsbs. Bottom 8 bits of the number of pixels between sync
7-0
pulses.
REV. 1.0.0 2/4/03
23
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Sync Pulse Generator (11)
7
6
5
4
3
2
1
0
STB
Reg
Bit
Name
STB
Description
11
7-0
Sync to burst. Controls the number of pixels from sync to burst. This signal
starts the burst sample and hold. In SC mode, subtract 25 from the desired
delay to generate this value.
Sync Pulse Generator (12)
7
6
5
4
3
2
1
0
BTV
Reg
Bit
Name
BTV
Description
12
7-0
Burst to video. Controls the number of pixels from STB to the start of active
video.
Sync Pulse Generator (13)
7
6
5
AV
4
3
2
1
0
AV
AV
AV
AV
AV
AV
AV
0
7
6
5
4
3
2
1
Reg
13
Bit
Name
AV
Description
7-0
Active video line 8 lsbs. Bottom 8 bits of the number of pixels during the
7-0
active video line.
Sync Pulse Generator (14)
7
6
5
4
3
2
1
0
Reserved
AV
AV
Reserved
STS
STS
STS
8
9
8
10
9
Reg
14
Bit
7-6
5-4
3
Name
Reserved
AV
Description
Reserved, set to zero.
14
Active video line 2 msbs. Two most significant bits of AV.
Reserved, set to zero.
9-8
Reserved
STS
14
14
2-0
Sync to sync 3 msbs. Three most significant bits of STS.
10-8
24
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Sync Pulse Generator (15)
7
6
5
4
3
2
1
0
Reserved
VINDO
VDIV
VDOV
Reg
Bit
7
Name
Description
Reserved, set to zero.
15
15
Reserved
VINDO
6-2
Number of lines in vertical window. The number of lines (0 to 31) after the
last EQ pulse that the decoder passes through the Vertical INterval winDOw.
15
15
1
0
VDIV
Action inside VINDO. The vertical data inside the `VINDO' is passed
through a simple decoder when LOW, or is passed unprocessed on the luma
channel with the chroma channel set to zero when HIGH.
VDOV
Action outside VINDO. The vertical data after the `VINDO' and before the
end of vertical blanking is blanked (YUV = 0) when LOW, or passed through
the simple decoder when HIGH.
Sync Pulse Generator (16)
7
6
5
4
3
2
1
0
Reserved
NFDLY
SPGIP
MSIP
Reg
16
Bit
7-6
5-4
Name
Description
Reserved
NFDLY
Reserved, set to zero.
16
new field detect delay. NTSC frame detect delay:
NFDLY
00
Function
pixel count = 0
pixel count = 1
pixel count = 2
pixel count = 3
01
10
11
16
3-2
SPGIP
SPG input select. Selects the input to the Sync Pulse Generator:
SPGIP
00
Input
External HSYNC and VSYNC
01
Digitized sync (subcarrier mode)
TRS words embedded in the D1 data stream
TRS words embedded in the D2 data stream
10
11
16
16
1
0
MSIP
SMO
Mixed sync separator input. Set HIGH for external VIDEOB reference or
LOW for output of Low Pass Filter.
State Machine Offset. Set HIGH for a 1H offset and LOW for a 0H offset.
REV. 1.0.0 2/4/03
25
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Buffered register set 0 (17) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SG0
SG0
SG0
SG0
SG0
SG0
SG0
SG0
0
7
6
5
4
3
2
1
Reg
17
Bit
Name
SG0
Description
7-0
Msync gain, 8 lsbs. Bottom 8 bits of mixed sync scalar
7-0
lsb = 1/256
Buffered register set 0 (18) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YG0
YG0
YG0
YG0
YG0
YG0
YG0
YG0
0
7
6
5
4
3
2
1
Reg
18
Bit
Name
YG0
Description
7-0
Y gain, 8 lsbs. Bottom 8 bits of the luma gain
7-0
lsb = 1/256
Buffered register set 0 (19) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
UG0
UG0
UG0
UG0
UG0
UG0
UG0
UG0
7
6
5
4
3
2
1
1
9
0
0
8
Reg
19
Bit
Name
UG0
Description
7-0
U gain, 8 lsbs. Bottom 8 bits of the U gain
lsb = 1/256
7-0
Buffered register set 0 (1A) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
VG0
VG0
VG0
VG0
VG0
VG0
2
VG0
VG0
7
6
5
4
3
Reg
1A
Bit
Name
VG0
Description
7-0
V gain, 8 lsbs. Bottom 8 bits of the V gain
lsb = 1/256
7-0
Buffered register set 0 (1B) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YG0
YG0
UG0
UG0
UG0
8
Reserved
VG0
VG0
9
8
10
9
Reg
Bit
7-6
5-3
2
Name
Description
1B
1B
1B
1B
YG0
UG0
Y gain, 2 msb. Top 2 bits of the Y gain. msb = 2
U gain, 3 msbs. Top 3 bits of the U gain. msb = 4
Reserved, set to zero.
9-8
10-8
Reserved
VG0
1-0
V gain, 2 msbs. Top 2 bits of the V gain. msb = 2
9-8
26
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Buffered register set 0 (1C) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YOFF0
YOFF0
YOFF0
YOFF0
YOFF0
YOFF0
YOFF0
YOFF0
0
7
6
5
4
3
2
1
Reg
1C
Bit
7-0
Name
Description
Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset
YOFF0
7-0
Buffered register set 0 (1D) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
Reserved
YOFF0
SG0
SG0
8
8
9
Reg
1D
Bit
7-3
2
Name
Description
Reserved
Reserved, set to zero.
1D
YOFF0
Y offset, msb. msb of YOFF
8
1D
1-0
SG0
Msync gain, 2 msbs. Top 2 bits of mixed sync scalar.
9-8
msb = 2
Buffered register set 0 (1E) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
0
VAXIS0
6
5
4
3
2
1
Reg
1E
Bit
7-1
0
Name
Description
SYSPH0
VAXIS0
7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset
V axis flip. Flips the sign of the V axis when HIGH.
6-0
1E
Buffered register set 0 (1F) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
7
14
13
12
11
10
9
8
Reg
Bit
Name
Description
8 msbs of phase offset. Top 8 bits of 15 bit system phase offset.
1F
7-0
SYSPH0
14-7
Normalized Subcarrier Frequency (20)
7
6
5
4
3
2
1
0
FSC
FSC
FSC
FSC
0
Reserved
3
2
1
Reg
Bit
7-4
3-0
Name
FSC
Description
20
20
Bottom 4 bits of fsc. Bottom 4 bits of the 28 bit subcarrier SEED
3-0
Reserved
Reserved, set to zero.
REV. 1.0.0 2/4/03
27
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Normalized Subcarrier Frequency (21)
7
6
5
4
3
2
1
0
FSC
11
FSC
10
FSC
FSC
FSC
FSC
FSC
FSC
4
9
8
7
6
5
Reg
21
Bit
Name
FSC
Description
Lower 8 bits of fsc. Lower 8 bits of the 28 bit subcarrier SEED
7-0
11-4
Normalized Subcarrier Frequency (22)
7
6
5
4
3
2
1
0
FSC
19
FSC
18
FSC
17
FSC
16
FSC
15
FSC
14
FSC
13
FSC
12
Reg
22
Bit
Name
FSC
Description
Middle 8 bits of fsc. Middle 8 bits of the 28 bit subcarrier SEED
7-0
19-12
Normalized Subcarrier Frequency (23)
7
6
5
4
3
2
1
0
FSC
27
FSC
26
FSC
25
FSC
24
FSC
23
FSC
22
FSC
21
FSC
20
Reg
23
Bit
Name
FSC
Description
Top 8 bits of fsc. Top 8 bits of the 28 bit subcarrier SEED
7-0
27-20
28
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Normalized Subcarrier Frequency (24)
7
6
5
4
3
2
1
0
CLMPEN
PFLTEN
CLPSEL
1-0
CLPBY
CLPOF
2-0
Reg
Bit
Name
Description
24
7
DREFSEL
Decoder Reference Signal Select. When HIGH, enables a negative going
clamp pulse on the DREF pin. The position of the clamp pulse is controlled
by register 24. When LOW the DREF pin is HIGH during the active video
portion of each line and LOW during the horizontal and vertical blanking
intervals.
24
24
6
PFLTBY
Phase error filter bypass. When HIGH, no filtering is done on the phase
error signals for the comb filter adapter. When LOW, the filter is enabled.
5-4
CLPSEL
Internal black level clamp selection.
1-0
CLMP[1:0]
Function
00
01
10
Clamp disabled, black level set to 240
Clamp disabled, black level set to 256
Clamp enabled, use Delayed VIDEOB input as
reference
11
Clamp enabled, use LPF as reference
24
24
3
VCLPEN
BAND
Vertical clamp filter enable. When LOW, vertical clamp filter is disabled.
When HIGH, vertical clamp filter is enabled.
2-0
Clamp guard band. When an error value between two consecutive lines
black level is less than the guard band, it does not effect the filtered black
level.
2-0
BANDS[2:0]
000
Function
No guard band
error value < 2
error value < 4
error value < 6
error value < 8
error value < 10
error value < 12
error value < 15
001
010
011
100
101
110
111
Normalized Subcarrier Frequency (25)
7
6
5
4
3
2
1
0
CPDLY
7-0
Reg
Bit
Name
Description
25
7-0
CPDLY
Clamp pulse delay. Controls the number of clock cycles from hsync before
the 0.5 µSec clamp pulse is output to the AVOUT pin. This option is only
enabled when register 24 bit 7 is set HIGH.
7-0
REV. 1.0.0 2/4/03
29
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Output Format Control (26)
7
6
5
4
3
2
1
0
Reserved
LDVIO
OPCKS
DPCEN
DPC
Reg
26
Bit
7-6
5
Name
Description
Reserved, set to zero.
Reserved
LDVIO
26
LDV clock select. LDV is an output when LOW and an input when HIGH
26
4
OPCKS
Output clock select. The output data are clocked by the CLOCK pin when
LOW and by the LDV pin when HIGH.
26
26
3
DPCEN
DPC
DPC enable. When HIGH on the TMC22153A, the Decoder Product Code is
enabled: a value written into DPC determines the decoder product emulated
by the TMC22153A. In all other versions of the decoder, DPC is read-only,
and returns the code of the particular encoder version installed.
2-0
Decoder product code
DPC
000
Function
Reserved
001
010
011
100
101
110
111
TMC22051A
TMC22052A
TMC22053A
Reserved
TMC22151A
TMC22152A
TMC22153A
Read/Write in the TMC22153A only. Read-only in all other devices.
Buffered register set 1 (27) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SG1
SG1
SG1
SG1
SG1
SG1
SG1
SG1
0
7
6
5
4
3
2
1
Reg
27
Bit
Name
SG1
Description
7-0
Msync gain, 8 lsbs. Bottom 8 bits of the mixed sync scalar
7-0
lsb = 1/256
Buffered register set 1 (28) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YG1
YG1
YG1
YG1
YG1
YG1
YG1
YG1
0
7
6
5
4
3
2
1
Reg
28
Bit
Name
YG1
Description
7-0
Y gain, 8 lsbs. Bottom 8 bits of the luma gain
7-0
lsb = 1/256
30
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Buffered register set 1 (29) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
UG1
UG1
UG1
UG1
UG1
UG1
UG1
UG1
0
7
6
5
4
3
2
1
Reg
29
Bit
Name
UG1
Description
7-0
U gain, 8 lsbs. Bottom 8 bits of the U gain
7-0
lsb = 1/256
Buffered register set 1 (2A) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
VG1
VG1
VG1
VG1
VG1
VG1
VG1
VG1
0
7
6
5
4
3
2
1
Reg
2A
Bit
Name
VG1
Description
7-0
V gain, 8 lsbs. Bottom 8 bits of the V gain
7-0
lsb = 1/256
Buffered register set 1 (2B) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YG1
YG1
UG1
UG1
UG1
Reserved
VG1
VG1
9
8
10
9
8
9
8
Reg
Bit
Name
Description
2B
7-6
YG1
Y gain, 2 msbs. Top 2 bits of the Y gain
9-8
msb = 2
2B
5-3
UG1
U gain, 3 msbs. Top 3 bits of the U gain.
10-8
msb = 4
2B
2B
2
Reserved
VG1
reserved, set to zero
1-0
V gain, 2 msbs. Top 2 bits of the V gain
9-8
msb = 2
Buffered register set 1 (2C) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YOFF1
YOFF1
YOFF1
YOFF1
YOFF1
YOFF1
YOFF1
YOFF1
0
7
6
5
4
3
2
1
Reg
2C
Bit
7-0
Name
Description
Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset
YOFF1
7-0
REV. 1.0.0 2/4/03
31
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Buffered register set 1 (2D) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
Reserved
YOFF1
SG1
SG1
8
8
9
Reg
2D
Bit
7-3
2
Name
Description
Reserved
Reserved, set to zero.
2D
YOFF1
Y offset, msb. msb of YOFF
8
2D
1-0
SG1
Msync gain, 2 msbs. Top 2 bits of mixed sync scalar
9,8
msb = 2
Buffered register set 1 (2E) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
0
VAXISO
6
5
4
3
2
1
Reg
2E
Bit
7-1
0
Name
Description
SYSPH1
VAXIS1
7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset
V axis flip. Flips the sign of the V axis when HIGH.
6-0
2E
Buffered register set 1 (2F) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
7
14
13
12
11
10
9
8
Reg
Bit
Name
Description
8 msbs of phase offset. Top 8 bits of 15 bit system phase offset.
2F
7-0
SYSPH1
14-7
32
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Video Measurement (30)
7
6
5
4
3
2
1
0
Reserved
LGF
LGEN
LGEXT
RESERVED
PGG
PGEN
PGEXT
Reg
Bit
Name
Reserved
LGF
Description
Reserved, set to zero.
30
30
7
6
Line grab flag. Set HIGH when the decoder has grabbed a line, and must be
reset LOW before another line can be grabbed.
30
5
LGEN
Line grab enable. When HIGH, the line grabber is used to freeze the
contents of the line store, at the programmed line and field count. The phase
and frequency of the frozen line are also stored from the DRS, and are
continually used to reset the DDS, once per line, until LGF is set LOW. When
LGEN is LOW, the line freeze is disabled, the internal loops operate normally,
and the line grab signal is used only to gate the pixel grab.
30
4
LGEXT
Ext line grab enable. The SET pin is used to produce the line grabber pulse
when HIGH and the internal line decode is used when LGEXT is LOW.
30
30
3
2
Reserved
PGG
Reserved, set to zero.
Pixel grab gate. When HIGH the pixel grab is gated by the field and line grab
signals to enable one pixel per four fields in NTSC and 8 field in PAL to be
grabbed. This function is disabled if PGEN is set LOW.
30
30
1
0
PGEN
Pixel grab enable. When HIGH the 10 bit G/Y, B/U, and R/V data, and the
mixed sync and luma data after the comb filter, and the demodulated (B-Y)
and (R-Y) color difference signals are grabbed once every line at the
programmed pixel grab number. When LOW the contents of the pixel grab
registers are held and the pixel grab pulse is ignored.
PGEXT
Ext pixel grab enable. The SET pin is used to produce the pixel grab pulse
when HIGH and the internal pixel decode is used when PGEXT is LOW.
Video Measurement (31)
7
6
5
4
3
2
1
0
PG
PG
PG
PG
PG
PG
PG
PG
0
7
6
5
4
3
2
1
Reg
31
Bit
Name
PG
Description
Pixel grab, 8 lsbs. Bottom 8 bits of the pixel grab.
7-0
7-0
Video Measurement (32)
7
6
5
4
3
2
1
0
LG
LG
LG
LG
LG
LG
LG
LG
0
7
6
5
4
3
2
1
Reg
32
Bit
Name
LG
Description
Line grab, 8 lsbs. Bottom 8 bits of the line grab.
7-0
7-0
REV. 1.0.0 2/4/03
33
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Video Measurement (33)
7
6
5
4
3
2
1
0
Reserved
FG
LG
PG
10
PG
PG
8
8
9
Reg
Bit
Name
Reserved
FG
Description
Reserved.
33
33
33
33
7
6-4
3
Field grab number. Field grab number
Msb of line grab. msb of line grab
LG
8
2-0
PG
Pixel grab, 3 msbs. 3 msbs of pixel grab
10-8
Registers 34-3C are Read-Only
Register (34)
7
6
5
4
3
2
1
0
GY
GY
GY
GY
GY
GY
GY
GY
2
9
8
7
6
5
4
3
Reg
34
Bit
Name
GY
Description
G/Y grab, 8 msbs. Top 8 bits of the "grabbed" G/Y data
7-0
9-2
Register (35)
7
6
5
4
3
2
1
0
BU
BU
BU
BU
BU
BU
BU
BU
2
9
8
7
6
5
4
3
Reg
35
Bit
Name
BU
Description
B/U grab, 8 msbs. Top 8 bits of the "grabbed" B/U data
7-0
9-2
Register (36)
7
6
5
4
3
2
1
0
RV
RV
RV
RV
RV
RV
RV
RV
2
9
8
7
6
5
4
3
Reg
36
Bit
Name
RV
Description
R/V grab, 8 msbs. Top 8 bits of the "grabbed" R/V data
7-0
9-2
Register (37)
7
6
5
4
3
2
1
0
Reserved
Bit
GY
GY
BU
BU
RV
RV
0
1
0
1
0
1
Reg
37
Name
Description
Reserved.
7-6
5-4
3-2
1-0
Reserved
37
GY
BU
RV
G/Y grab, 2 lsbs. Bottom two bits of G/Y data
B/U grab, 2 lsbs. Bottom two bits of B/U data
R/V grab, 2 lsbs. Bottom two bits of R/V data
1-0
1-0
1-0
37
37
34
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Register (38)
7
6
5
4
3
2
1
0
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Reg
Bit
Name
Description
Luma grab, 8 msbs. Top 8 bits of the "grabbed" luma data after YPROC
38
7-0
Y
9-2
Register (39)
7
6
5
4
3
2
1
0
M
9
M
8
M
7
M
6
M
5
M
4
M
3
M
2
Reg
Bit
Name
Description
39
7-0
M
Msync grab, 8 msbs. Top 8 bits of the "grabbed" mixed sync data after
9-2
YPROC
Register (3A)
7
6
5
4
3
2
1
0
U
9
U
8
U
7
U
6
U
5
U
4
U
3
U
2
Reg
Bit
Name
Description
U grab, 8 msbs. Top 8 bits of the "grabbed" U data
3A
7-0
U
9-2
Register (3B)
7
6
5
4
3
2
1
0
V
9
V
8
V
7
V
6
V
5
V
4
V
3
V
2
Reg
Bit
Name
Description
V grab, 8 msbs. Top 8 bits of the "grabbed" V data
3B
7-0
V
9-2
Register (3C)
7
6
5
4
3
2
1
0
Y
1
Y
0
M
1
M
0
U
1
U
0
V
1
V
0
Reg
3C
3C
3C
3C
Bit
7-6
5-4
3-2
1-0
Name
Description
Luma grab, 2 lsbs. Bottom 2 bits of luma data
Y
1-0
M
Msync grab, 2 lsbs. Bottom 2 bits of mixed sync data
U grab, 2 lsbs. Bottom 2 bits of U data
1-0
1-0
1-0
U
V
V grab, 2 lsbs. Bottom 2 bits of V data
REV. 1.0.0 2/4/03
35
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Test Control (3D-3E)
7
6
5
4
3
2
1
0
TEST
Reg
Bit
Name
Description
3D-3E 7-0
TEST
Must be set to zero. Auto increment stops at 3F
Test Control (3F)
7
6
5
4
3
2
1
0
VBIT20
PEDDIS
CCDEN
CCDEN
CCDEN
CCDEN
CCDEN
CCDEN
0
5
4
3
2
1
Reg
Bit
Name
Description
VBIT20 enable. When HIGH the V bit within embedded TRS words is
3F
7
VBIT20
extended through line 20 for NTSC. When LOW, this V bit is HIGH up to line
16 for NTSC. The PAL operation is unaffected by this register bit.
3F
3F
6
5
PEDDIS
Pedestal disable. When HIGH, pedestal is not removed from lines with
LID = 00 to 06, lines 0 through 16
CCDEN
CCDEN
CCDEN
CCDEN
CCDEN
CCDEN
Closed caption data enable 5. When HIGH, enables NTSC line 21 field 0
or PAL line 22 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
5
4
3
2
1
0
3F
3F
3F
3F
3F
4
3
2
1
0
Closed caption data enable 4. When HIGH, enables NTSC line 22 field 0
or PAL line 23 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 3. When HIGH, enables NTSC line 23 field 0
or PAL line 24 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 2. When HIGH, enables NTSC line 283 field 1
or PAL line 334 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 1. When HIGH, enables NTSC line 284 field 1
or PAL line 335 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 0. When HIGH, enables NTSC line 285 field 1
or PAL line 336 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Status - Read Only (40)
7
6
5
4
3
2
1
0
DDSPH
Reg
Bit
Name
Description
40
7-0
DDSPH
DDS phase, 8 msbs. The top 8 bits of the sine data generated in the internal
DDS.
36
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Status - Read Only (41)
7
6
5
4
3
2
1
0
LINEST
BGST
VACT2
PALODD
VFLY
FGRAB
LGRAB
PGRAB
Reg
Bit
7
Name
Description
Pixel count reset. Pixel count reset
41
41
41
41
41
41
41
41
LINEST
BGST
6
Start of burst gate. Start of burst gate
Half line flag. Half line flag
5
VACT2
PALODD
VFLY
4
PAL Ident. PAL Ident (low on NTSC lines)
Vertical count reset. Vertical count reset
Field grab. Field grab
3
2
FGRAB
LGRAB
PGRAB
1
Line grab. Line grab
0
Pixel grab. Pixel grab
Status - Read Only (42)
7
6
5
4
3
2
1
0
FLD
VBLK
HBLK
LID
Reg
Bit
7
Name
FLD
Description
Field flag (F in D1 output). Field flag (F in D1 output)
42
42
42
42
6
VBLK
HBLK
LID
Vertical blanking (V in D1 output). Vertical blanking (V in D1 output)
Horizontal blanking (H in D1 output). Horizontal blanking (H in D1 output)
Line identification. Line identification
5
4-0
Status - Read Only (43)
7
6
5
4
3
2
1
0
YGO
YGU
UBO
UBU
VRO
VRU
Reserved
Reg
Bit
7
Name
YGO
Description
43
43
43
43
43
43
43
Y/G overflow. Y/G overflow
6
YGU
Y/G underflow. Y/G underflow
5
UBO
C /B overflow. C /B overflow
B B
4
UBU
C /B underflow. C /B underflow
B B
3
VRO
C /R overflow. C /R overflow
R R
2
VRU
C /R underflow. C /R underflow
R
R
1-0
Reserved
Reserved.
REV. 1.0.0 2/4/03
37
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Status - Read Only (44)
7
6
5
4
3
2
1
0
MONO
FPERR
Reg
Bit
Name
Description
44
7
MONO
Color kill flag. High when burst detected and LOW when monochrome
signal is detected.
44
6-0
FPERR
Frequency/Phase error. Top 7 bits of the modulo two pi frequency or phase
error. Reported once per line.
Status - Read Only (45)
7
6
5
4
3
2
1
0
DRS
Reg
Bit
Name
Description
45
7-0
DRS
DRS signal. The 8-bit Decoder Reference Signal.
Status - Read Only (46)
7
6
5
4
3
2
1
0
PARTID
Reg
Bit
Name
Description
46
7-0
PARTID
Part family ID. Reads back the 8-bit part ID number. Read-only. Returns
CDh.
Status - Read Only (47)
7
6
5
4
3
2
1
0
REVID
Reg
Bit
Name
Description
47
7-0
REVID
Recoder revision number.
REVID TMC22x5y Revision TMC22x5yA Revision
05
06
10
11
F
G
A
B
38
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Status - Read Only (48-4A)
7
6
5
4
3
3
2
1
1
0
Reserved
Status - Read Only (4B)
7
6
5
4
2
0
PKILL
CFSTAT
XOP
Reg
Bit
7
Name
Description
4B
4B
PKILL
Phase kill from comb fail. Phase kill from comb fail.
Comb filter status. Comb filter status.
6-5
CFSTAT
CFSTAT
00
STATUS
3 tap comb
01
3 tap [lower] comb
3-tap [upper] comb
2 tap comb
10
11
4B
4-0
XOP
XLUT output. XLUT output.
Status - Read Only (4C-FF)
7
6
5
4
3
2
1
0
Reserved
Reg
Bit
Name
Description
Reserved.
4C-FF 7-0
Reserved
REV. 1.0.0 2/4/03
39
TMC22x5yA
PRODUCT SPECIFICATION
The complete separation of composite video signals into
pure luminance (luma) and chrominance (chroma) signals is
practically impossible, especially when the input source
contains intraframe motion. Therefore, the luminance (luma)
signal will generally contain some high frequency chromi-
nance, termed cross luma, and the chroma signal will
contains some of the high frequency luma signal, centered
around the subcarrier frequency, termed cross color.
The degree of cross luma and cross color is directly propor-
tional to the filter used for theYC separation, the picture con-
tent, and the complexity of any post processing of the
decoded signals.
Decoder Introduction
All composite video decoders perform fundamentally the
same operation. The first stage is to separate the luminance
and chrominance. The second stage is to lock the internally
generated sine and cosine waveforms to the burst on the
decoded chrominance signal, demodulate, and then filter the
chrominance signal to produce the color difference signals.
The last stage either scales the luminance and color differ-
ence signals, or converts them into red, green, and blue
component video signals. These three stages are shown in
Figure 3.
–
G
Luminance
Y
Y
Green
Red
–
–
–
Matrix
YC Filter
R
B
–
Composite
–
–
U
V
C
Chrominance
Blue
Demodulation
–
sin(wt)
Burst Locked
Loop
cos(wt+φ)
65-22x5y-44
Figure 3. Fundamental Decoder Block Diagram
The Luma Notch and Chroma Bandpass Technique for
YC Separation
YC Separation
The relationship between the chrominance and luminance
bandwidths is shown for both PAL and NTSC in Figure 4,
wherein the shaded area denotes the part of the composite
video frequency spectrum shared by both the chrominance
and high frequency luminance signals.
The simplest method of separating these chrominance and
luminance signals, is to assume the chroma bandwidth is
limited to a few hundred kilohertz around the subcarrier
frequency. In this case a notch filter designed to remove just
these frequencies from the composite video frequency
spectrum provides the luma signal, while a bandpass filter
PAL
NTSC
Amplitude
Amplitude
(dB)
(dB)
Chrominance
Chrominance
Subcarrier
Subcarrier
Sound Carrier
Center Frequency
Sound Carrier
0
0
Center Frequency
-3
-3
Luminance
Luminance
Chrominance
(& High Frequency
Luminance)
Chrominance
(& High Frequency
Luminance)
-20
-20
Frequency (MHz)
Frequency (MHz)
1
2
3
4
5
6
1
2
3
4
4.5
Figure 4. Comparison of the Frequency Spectrum of NTSC and PAL Composite Video Signals
40
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Notch Filter
Bandpass Filter
Amplitude
(dB)
Amplitude
(dB)
Chrominance
Subcarrier
Chrominance
Subcarrier
0
0
-3
-3
Luminance
Chrominance
(& High Frequency
Luminance)
Chrominance
(& High Frequency
Luminance)
-20
-20
FSC
Frequency
FSC
Frequency
Figure 5. Examples of Notch and Bandpass Filters
centered at the subcarrier frequency produces the chroma
signal. This simple technique works well in pictures contain-
ing large flat areas of color, however this is rarely the case.
If, as is generally true, the picture contains high frequency
luma and chroma transitions, for example herring bone suit
jackets, branches of trees, text, etc., cross color and cross
luma artifacts are evident.
the V component of the chrominance signal. This document
refers to line based comb decoders when discussing decoders
that use inputs from sequential scan lines, i.e. lines from the
same field, field based comb decoders when describing
decoders that use inputs from sequential fields, and finally
frame based comb decoders when examining decoders that
use inputs from sequential frames.
The presence of cross color or cross luma is generally
acceptable when viewing the decoded picture on a monitor
from several feet, as would be the case in most homes on
commercial television sets. However, these artifacts become
increasingly difficult to process, or ignore, when the image is
to be compressed or manipulated. In these cases more
sophisticated methods of separating the luma and chroma
signals, such as frame, field, or line based comb filter decod-
ers, are required.
Delay = 1/T
1/2
+
Amplitude
1.0
Another important disadvantage of the “luma notch filter and
bandpass chroma” technique is that once a notch filter has
been used on the luminance channel this portion of the lumi-
nance frequency spectrum is lost. This effect becomes
increasingly objectionable if the decoder component outputs
are subsequently re-encoded into a composite video signal.
1/2T 1T 3/2T 2T 5/2T 3T 7/2T 4T 9/2T 5T 11/2T 6T
Frequency
Figure 6.
Composite Line-Based Comb Decoders
The phase relationship of the quadrature modulated chromi-
nance signal can also be represented as in Figure 7. The three
line comb based decoder is clearly biased towards 1H which
illustrates the inherent one line delay through a 3 line comb,
while a two line comb based decoder is biased towards 0H.
In the following discussions a flat color represents video of
constant luma and chroma magnitude and phase.
Comb Filter Architectures forYC Separation
A comb filter uses the relationship between the number of
subcarrier cycles per line period, to cancel the chrominance
signal over multiple line periods. This is shown for an NTSC
two line comb filter in Figure 6. In NTSC there a 227.5 sub-
carrier cycles per line period, therefore the subcarrier can be
canceled by simply adding two consecutive field scan lines.
In PAL(B/I/ etc.) there are 283.7516 subcarrier cycles per
line period, ignoring the 0.0016 cycle advance caused by the
25Hz offset, the PAL subcarrier can be canceled by adding
the first and third line of three consecutive field scan lines.
Due to the 270 degree advance, it is not possible to use infor-
mation from consecutive field lines without adding a PAL
modifier. A PAL modifier produces a 90 degree phase shift in
the chrominance signal by multiplying the chrominance
signal by a signal at two times the subcarrier frequency that
is phased locked to the subcarrier burst reference in the com-
posite video waveform. In addition the PAL modifier inverts
In NTSC, adding two adjacent lines of flat color will cancel
the chroma and leave the luma whereas subtracting two lines
of flat color will cancel the luma and leave the chroma. In a 3
line comb filter the flat color on 0H and 2H is added to pro-
vide the flat color average before adding or subtracting from
1H.
In PAL, adding the flat color from 0H and 2H will cancel the
chroma and leave the luma while subtracting the flat color
from 0H and 2H will cancel the luma and leave the chroma.
However, chroma generated in this manner has no simple
REV. 1.0.0 2/4/03
41
TMC22x5yA
PRODUCT SPECIFICATION
phase relationship to the chroma on 1H. Therefore normally
0H and 2H are added together to produce the average luma
across 3 lines and this is then subtracted from 1H to produce
the combed chroma.
0H and FR0H and the two consecutive field lines FR0H and
FR1H are 180 degrees apart. The flat color on FR0H and
FR1H can be added or subtracted to provide the luminance
or chrominance to subtract from 0H.
LINE no FIELD 1
FIELD 2 FIELD 3 FIELD 4
I
FIELD LINE no
PAL
U
NTSC
I
283
(1H)
I
Q
Q
N
0
1
0
Q
I
(FR1H)
V
U
21
22
23
24
Q
Q
I
M
(F1H)
I
V
284
285
286
Q
Q
Q
Q
I
N+1
2H
1H
0H
(FR0H)
Q
(0H)
Q
I
Q
(F0H)
Q
I
1
0
M+1
N+2
I
V
Q
I
I
U
V
Q
1
0
M+2
N+3
I
I
U
Q
Q
I
I
I
I
Q
Q
1
0
M+3
N+4
U
I
V
Q
65-22x5y-49
65-22x5y-48
Figure 8. Chrominance Vector Rotation Over 4
Fields in NTSC
Figure 7. Chrominance Vector Rotation in PAL and NTSC
Composite Field-Based Comb Filters
YC Line-Based Comb Filters
In NTSC field based comb decoders, there is an external
delay of 263 lines, therefore the 2 adjacent picture lines 0H
and F0H and the two consecutive field lines F0H and F1H
are 180 degrees apart. The flat color on F0H and F1H can be
added or subtracted to provide the luminance or chromi-
nance to subtract from 0H.
The luminance and chrominance signals, are by definition,
already separated for YC inputs. However, if the original
source was composite, there is a distinct possibility that there
is some residual luminance (cross color) in the chrominance
signal and some residual chrominance (cross luma) in the
luminance signal. It is therefore legitimate to treat these
signals as if they were simply the output from bandsplit
filters and process the luma and chroma signals accordingly.
PAL Field Decoders
D1 Line-Based Comb Filters
Composite, PAL Field Comb Filters
In PAL field based comb decoders, there is an external delay
of 312 lines, therefore the 2 adjacent picture lines 0H and F0H
are 180 degrees apart. In fields 5, 6, 7, and 8 the U and V
vectors are 180 degrees advanced from fields 1, 2, 3, and 4.
A D1 data stream consists of multiplexed Y, C and C
component data. If the original source was composite there
B
R
maybe luminance (cross color) in C C and chrominance
B R
(cross luma) in Y. In the first case any luminance that was
passed through a demodulator along with the chroma to
LINE no FIELD 1 FIELD 2 FIELD 3 FIELD 4
produce the baseband C C color difference signals would
B R
V
U
have the same characteristics as chroma. That is to say, the
cross color would advance by 180° every line in NTSC and
every 2 lines in PAL. It is therefore possible to remove this
cross color in a comb filter. In the latter case any chromi-
nance that is still in theY data can obviously be removed in a
comb filter as well.
U
23
336
24
337
V
U
U
(F0H)
V
U
V
V
(FR0h)
V
(0H)
U
V
U
V
U
V
U
The original source for the D1 signal could also have been
computer graphics. In this case, the comb filter can be used
to remove the picture flicker and convert the output to RGB.
U
U
(FR0H)
V
V
U
25
338
26
U
V
V
U
V
NTSC Frame and Field Based
Decoders
65-22x5y-50
Figure 9. Chrominance Vector Rotation
Over 4 Fields in PAL
Composite Frame-Based Comb Filters
In NTSC the chrominance vectors advance by 180 degrees
every line, therefore after 525 lines the 2 adjacent frame lines
42
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
in Figure 10. The last step is to provide a complementary
The TMC22x5yA Comb Filter
Architecture
cross fade between the YCOMB signal and the output of the
complementary bandsplit filter, shown as SIMPLE in Figure
10. The FLAT signal is simply a delayed version of the input
to the comb filter, therefore the sum of Output1 and Output2
will always be equal to the FLAT video input.
The TMC22x5yA, when implementing a line based comb
filter, has a core architecture as shown in Figure 10. The con-
cept of the complementary bandsplit filter is also observed in
the complementary comb filter architecture. It is therefore
possible to adapt between the complementary comb filter
and bandsplit filter without throwing away any of the
original composite video frequency spectrum.
The TMC22x53A comb filter architecture has three taps.
These taps are three consecutive field lines in a line based
comb, three consecutive picture lines in a field based comb,
or lines that are one frame and one field line apart in the
frame based comb. In addition to these different inputs to the
comb filter, NTSC and PAL video signals comb over differ-
ent taps in different architectures, as described in the comb
filter introduction.
The first step in the complementary comb filter is to separate
the high frequency luminance from the chrominance signal.
This combed high frequency luma signal is shown as
YCOMB in Figure 10. The second step is to produce an array
of comb filter error signals that indicate the degree of confi-
dence that theYCOMB signal is just the high frequency luma
and not a combination of high frequency luma and chroma
smeared over the number of lines used in the comb filter. The
signal representing this degree of confidence is termed “K”
The total internal pipeline latency is 1H + 40 pixels for 3 line
comb filters, for all other comb filter and simple decoder
architectures the pipeline latency is 40 pixels.
XLUT
Output1
–
SIMPLE
Input
1H
Bandsplit
COMB
YCOMB
Output2
+
X
Filters
Filter
Simple +/- {k * Ycomb}
1H
K
XLUT
Figure 10. TMC22x5yA Line Based Comb Filter Architecture
REV. 1.0.0 2/4/03
43
TMC22x5yA
PRODUCT SPECIFICATION
TMC22x5yA Functional Description
Input Processor
LPF Output
Input
LPF
The input processor selects between the two external video
sources on VIDEO A and VIDEO B. If the TRS stripper or
GRS stacker is active, then the user must select the input
with either the GRS (in genlock mode) or with the embedded
TRS words as output VA. If the input data are separate luma
HPF Output
–
and chroma orY and C C data the input processor must be
B R
65-22x5y-53
programmed to put the chrominance or C C onto output
B R
VB and the luminance or Y onto VA.
Figure 12. Complementary Bandsplit Filter
To ensure that the chrominance data or the C C data are in
B R
The complementary bandsplit filter separates the base band
composite video into two bands by passing it through a low
pass filter and subtracting the low pass (luma) data from the
composite video to produce the high pass (chroma) data. As
the base bandwidths and subcarrier frequencies of the differ-
ent NTSC and PAL video formats are so different, and the
decoder has to be capable of working over a large frequency
range, it is necessary to provide two low pass filters. These
filters are selectable by the BSFSEL register bit and are inde-
pendent of the video standard. A comparison of the different
data rates to normalized subcarrier frequencies is provided in
Table 2.
two’s complement arithmetic format, the register bit MSBI
inverts the msb of the DB input. For composite inputs, the
IPCMSB register bit should be set LOW, as the ABMUX
register bit is used to select the input(s) to the comb filter.
Bandsplit Filter (BSF)
In its simple mode of operation, the TMC22x5yA uses a
complementary bandsplit filter, instead of a notch filter for
the luma and a bandpass for the chroma. The notch and
bandpass filter technique, removes frequency bands from the
composite video spectrum which can never be retrieved.
The complementary bandsplit filter technique, shown in
Figure 12, allows the decoded component video signals to be
re-encoded into a composite video signal with the minimum
of losses to the composite video spectrum.
The complementary bandsplit low pass frequency response
is shown in Figure 13 and Figure 14.
msb
x
Input Processor Control Register
IPMUX IP8B TDEN TBLK
lsb
ICPMSB ABMUX CKSEL
TRS Stripper (D1/D2/D3)
and
GRS Stacker (TMC22071)
VA
DA
Primary Data
to Comb Filter
VideoA
2:2 MUX
2:2 MUX
VB
DB
Secondary Data
to Comb Filter
MSB
Invert
VideoB
65-22x5y-52
Figure 11. Input Processor
44
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
1
0
0
-10
-20
-30
-40
-1
-2
-3
-4
-5
-6
Bandsplit Filter 2
Bandsplit Filter 2
Bandsplit Filter 1
Bandsplit Filter 1
-50
-60
-70
Normalized Frequency
Normalized Frequency
Figure 14. Bandsplit Filter, Passband Response
Figure 13. Bandsplit Filter, Full Frequency Response
Table 2. Normalized Subcarrier Frequency as a Function of Pixel Data Rates
FSC
Pixel Rate (MHz)
(MHz)
Normalized FSC
Comments
12.27
3.57954545
3.57954545
4.43361875
3.57954545
4.43361875
4.43361875
4.43361875
3.57561149
3.58205625
3.57561149
0.2917
NTSC square pixel rate
13.50
0.2652
NTSC D1 pixel rate
13.50
0.3284
PAL-I D1 pixel rate
14.32
0.2500
NTSC four times subcarrier (D2/D3)
PAL-I square pixel rate
14.75
0.3006
15.00
0.2956
PAL-I square pixel rate
17.73
0.2500
PAL-I four times subcarrier (D2/D3)
PAL-M D1 pixel rate
13.5
0.2649
13.5
0.2653
PAL-N D1 pixel rate
14.30
0.2500
PAL-M four times subcarrier (D2/D3)
luma and chroma SIMPLE signals, and in the generation of
the comb fail signals. These signals are denoted xHL, xHH,
and xHF where L denotes the low frequency portion of the
signal, H the high frequency portion of the signal and F the
full frequency spectrum of the input signal from line x; and
are shown in Figure 15.
Comb Filter Input
The inputs to the comb filter are selected from either the high
frequency outputs of the bandsplit filters, if using a chroma
comb filter, or the full composite waveforms when imple-
menting a luma comb. The two sets of high and low fre-
quency signals from the bandsplit filters are used for both the
REV. 1.0.0 2/4/03
45
TMC22x5yA
PRODUCT SPECIFICATION
0HF
0HL
Primary
Input
LPF
BSFSEL
0HH
–
1HF
1HL
2:1
MUX
LSTORE1
[9:0]
2:1
MUX
Secondary
Input
LPF
LS1IN
BSFSEL
LS1BY
1HH
2HH
2HF
–
LSTORE2
2HH
1HH
+
2:1
MUX
1HH (lsbs)
1HL (lsbs)
2:1
MUX
LSTORE2
2HX
LSTORE2
2HL
2HL
1HL
Split
VIDEOB
DELAY
65-22x5y-56
Figure 15. Block Diagram of Comb Filter Input
The primary and secondary inputs are selected within the
input processor. The primary input is normally the undelayed
composite video signal in line, field, and frame based comb
filters or either the luma or chroma channel when processing
YC or D1 signals. The secondary provides the field or frame
delayed composite input for field and frame based comb
filters and the chroma or luma channel when processing YC
or D1 signals.
luma error signals. In the case of luma combs an equal
number of bits of the 1HH and 1HL signals are delayed and
summed together to produce the 2HF signal for the outer tap
of the luma comb filter. The configuration of LSTORE2 is
determined by the SPLIT register bit.
It is important to note that when implementing a field or
frame based comb filter the secondary input must be selected
by setting the LSIN register bit HIGH, and the first line store,
LSTORE1, must be bypassed by setting the LS1BY register
bit HIGH.
When implementing a line based comb filter the outputs of
1H bandsplit filter, ie 1HH, 1HL, are delayed through the
second line store, LSTORE2. The number of bits delayed is
dependent upon the type of comb filter being implemented.
For chroma comb filters all the bits of the 1HH signal are
delayed, as this information supplies the outer tap of the
chroma comb filter, while only the upper bits of 1HL are
delayed as this data is used only in the generation of the
For YC and D1 processing the secondary input bypasses the
comb filter completely and provides the VIDEOB signal
input the 3:1 multiplexer used to select the FLAT signal,
see Figure 16.
46
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
VIDEOB data is always selected when theYCCOMP register
bit is HIGH, ie for YC inputs. The selection of 1HF or 0HF
depends upon the SIMP selection bit only when the
YCCOMP register bit is LOW. Therefore, whenYCCOMP is
LOW and 0Hx is selected by SIMP then 0HF is selected for
the FLAT signal, and when 1Hx is selected by SIMP then
1HF is selected for the FLAT signal. This ensures that the
FLAT and SIMPLE data selected for any comb filter is
delayed by the same amount as the data processed through
the comb filter to produce the COMB output.
Adaptive Comb Filter
The IPCF[1:0] register bits select the inputs to the adaptive
comb filter, this would normally be xHH for chroma combs,
xHF for luma combs, and xHL if the luminance signal was to
be sampled dropped on the output of the TMC22x5yA. The
Gaussian filters in the sample drop mode already limit the
chrominance bandwidth to 1.3MHz allowing a [2:1:1] data
format on the output, with the luminance signal having been
vertically filtered by a fixed 3 line comb filter.
The SIMP selection bit is an internally generated signal
based upon the comb filter selected. If a 3 line chroma, luma,
or D1 comb filter is selected, due to the internal 1H delay
inherent with this type of comb filter, the 1HL and 1HH
signals are selected for the respective luma and chroma
SIMPLE data signals. When any other type of comb filter is
selected 0HL and 0HH are selected.
The final selection is the output required for the combed
luminance and chrominance data. The output selection can
be SIMPLE, COMB, FLAT-COMB, or FLAT. Generally
COMB is selected based upon whether a luma or chroma
comb was selected and the complementary output selects
FLAT-COMB. In theYC andY & CbCr data modes the FLAT
signal selects the secondary data and SIMPLE or COMB can
be used to select the primary signal. In these modes the
bandsplit filter can be bypassed or used to remove low fre-
quency noise from the chrominance signal if chroma was
selected as the primary signal.
The DLYF selection bit is also internally generated from the
type of comb filter selected and whether or not the input is in
either the YC or Y & CbCr (ie D1 input) data formats. The
A
SIMP
2:1
MUX
B
4:1
MUX
Y Data
IPCF[1:0]
C
OHF
3:1
MUX
OHH
D
OHL
YMUX[1:0]
IPCF[1:0]
1HF
3:1
MUX
1HH
1HL
Adaptive
Comb
Filter
A: Comb
B: Simple
C: Flat - Comb
D: Flat
IPCF[1:0]
2HF
2HH
3:1
MUX
CMUX[1:0]
A
2HL
SIMP
2:1
MUX
B
4:1
MUX
C Data
C
DLYF
–
3:1
MUX
D
VideoB
65-22x5y-57
Figure 16. Signal Flow Around the Adaptive Comb Filter.
REV. 1.0.0 2/4/03
47
TMC22x5yA
PRODUCT SPECIFICATION
The comb filter architecture performs chrominance or lumi-
nance comb filtering on PAL or NTSC video signals, by
implementing one of sixteen independent chroma and luma
comb filter algorithms. The highest level of the adaptive
comb filter configuration is determined by the STA[3:0]
register bits as shown in Table 3.
several comb filter architectures. These comb filter architec-
tures weight the three lines by varying degrees depending
upon the degree of picture correlation between the inputs to
the comb filter. The simple example in Table 4 shows how
this process works, in which upper denotes error compari-
sons between the two lines stores and lower denotes error
comparisons between the input and the first line store. The
0H, 1H, and 2H terms used in the mathematical description
of the comb filter selection refer to the position with respect
to the internal line stores. The 0H term is the undelayed
input, 1H is the output of line store 1, and 2H is the output of
line store 2.
Table 3. Comb Filter Architecture
STA[3:0]
Comb Filter Description
0
YC or Composite, PAL or NTSC, 3 line
comb
1
2
3
4
5
6
YC or Composite, NTSC, 3 line comb (0H
& 1H)
In this example a 3 line comb is implemented when in the
flat areas of blue or yellow. However, when a difference
between the inputs is detected the 3 line comb filter adapts to
the 2 line comb filter whose inputs have the smallest differ-
ence. This illustrated on line n+4, at which time the comb
filter adapts to inputs from 1H (blue) and 2H (blue) and
ignores the 0H (yellow) inputs. In cases where there is a
difference between all inputs to the comb filter, a 3 line comb
filter is selected and the highest set of comb fail signals are
sent to the XLUT input logic.
YC or Composite, NTSC, 3 line comb (1H
& 2H)
YC or Composite, NTSC, 2 line comb (0H
& 1H)
YC or Composite, NTSC, (2 line) field
comb
YC or Composite, NTSC or PAL, field
comb
This technique would work well if pictures only contained
vertical transitions, which is obviously not the case. There-
fore the weighting of these comb filter taps, (0H, 1H, and
2H), are rarely just the simple ratios shown in Table 4. It is
worth noting that comb filters that use an even number of
lines in the comb filter architecture produce chrominance
and luminance signals that are vertically offset by one pic-
ture line, i.e. in the middle of the even number of lines used
in the comb filter input. While comb filters that use an odd
number of lines, in the comb filter architecture, the chromi-
nance and luminance produced is referenced to the center,
i.e. the middle line, of the comb filter. This approach can
consequentially cause aliasing in decoding composite video
signals containing high frequency diagonal transitions. The
FAST register bit, when set LOW, filters the comb filter
selection to decrease the sensitivity of the adaption algo-
rithm. The second method completely disables the adaption
between different comb filters, by setting the ADAPT[1:0]
register bits accordingly, see Table 5.
YC or Composite, NTSC, (2 line) frame
comb
7
8
YC or Composite, NTSC, frame comb
D1, Y or C C , 3 line comb
B
R
9
D1, Y or C C , 3 line comb (0H & 1H)
B R
10
11
12
13
D1, Y or C C , 3 line comb (1H & 2H)
B R
D1, Y or C C , 3 line comb (0H & 2H)
B
R
D1, Y or C C , (2 line) field comb
B
R
D1, Y or C C , field or 2 line comb
B
R
(0H & 1H)
14
15
D1, Y or C C , (2 line) frame comb
B
R
D1, Y or C C , Frame
B
R
The COMB signal can be produced in two ways. The first
method uses the comb fail detection circuits to select one of
Table 4. Simple Example of an Adaptive Comb Filter Architecture
Error signals
Line Input col- upper upper upper lower lower lower
no.
n+6
n+5
n+4
n+3
n+2
n+1
n
or
luma
sat.
hue
luma
sat.
hue
Comb filter selection
unknown without line n+7
[0H/4] + [1H/2] + [2H/4]
[0] + [1H/2] + [2H/2]
blue
x
0
x
x
x
0
x
x
blue
0
0
0
0
blue
0
0
0
>0
0
0
180
0
yellow
yellow
yellow
black
>0
0
0
180
0
0
[0H/2] + [1H/2] + [0]
0
0
0
0
[0H/4] + [1H/2] + [2H/4]
[0] + [1H/2] + [2H/2]
0
0
0
>0
x
>0
x
>0
x
x
x
x
unknown without line n-1
48
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
In either of these methods, the “K” signal can be used to cross
fade between the YCOMB and the SIMPLE bandsplit signals.
The resulting comb filter equation can be expressed as:
errors in the demodulated picture. In this example, the
chrominance signal would be demodulated with a 180
degree phase error. Unlike the “simple” decoder technique
any errors in the comb filter decoding produce components
that if re-encoded will never reproduce the original compos-
ite video waveform. It is therefore imperative that the num-
ber and magnitude of comb fails be kept to its absolute
minimum. This is not possible with non-adaptive comb filter
architectures, and all vertical and diagonal transitions in the
picture will cause irreversible picture degradation. For this
reason, all the TMC22x5yA comb filter decoders implement
an adaptive comb filter architecture.
Combed Luma = Simple + (K * Combed High
Frequency Luma)
Combed Chroma = Simple - (K * Combed High
Frequency Luma)
In the case of the chroma comb, the weighted combed high
frequency luma is subtracted from the SIMPLE high pass fil-
ter output to produce the combed chroma signal, and for
luma comb filters the weighted combed high frequency luma
is added to the SIMPLE low pass filter output to provide the
combed luminance signal.
To aid in this decision making process, comprehensive comb
fail signals are generated and fed to a user-programmable
lookup table (XLUT). The output of the lookup table pro-
vides the control for the cross fade between the comb and
simple bandsplit decoder.
Comb Fails
The inputs to the comb filter are monitored to detect discon-
tinuities that would cause the comb filter operation to fail.
Whenever a significant failure is predicted, the comb filter
architecture is modified and an error signal proportional to
the discontinuity is produced. For flat areas of color, it is a
relatively simple to produce an error signal that switches
between the outputs of the comb filter and the simple band
split filter without visibly softening the picture horizontally
or vertically. However, as horizontal frequencies increase
during vertical transitions, so the decision for switching
between the comb and simple bandsplit decoder becomes
more complex.
Comb Fail Detection
The traditional approach of using the low frequency data to
look for vertical luma transitions, and rectifying the high
frequency data to estimate vertical transitions in the chroma
provides adequate comb fail detection. However, chroma
signals that are equal in magnitude but 180 degrees apart in
phase, which can also have a small difference in luma level,
for example green and magenta, can produce undetected
comb fails in the comb filter output.
To overcome problems with simpler comb fail measurement
techniques, the TMC22x5yA generates an array of patented
comb fail and comb filter control signals. To produce these
signals each input to the comb filter is passed through a sim-
ple bandsplit decoder. This provides a luma signal from the
low frequency portion of the comb filter input, and the hue
(phase) and saturation (magnitude) from the high frequency
portion of the comb filter input. These signals are compared
and the differences in luma, hue, and saturation are used to
determine the type of comb filter used to generate the
YCOMB signal and to provide the cross fade control signal
“K”. The “K” signal can be weighted within the XLUT
lookup table, allowing the user to tailor the comb
A line based comb filter can separate the luma and chroma
signals from line repetitive composite video signals, with no
loss of luma or chroma bandwidth. However, if there is a ver-
tical transition, i.e. a change from one scan line to the next,
as shown for a NTSC two line comb in Figure 17, a comb
fail occurs. The comb fail shown in Figure 17, clearly illus-
trates the resulting vertical smearing of the luma and chroma
signals.
In addition to the smearing, the resulting phase of the
chrominance signal with respect to the burst can cause hue
filter response to their system requirements.
65-22x5y-58
Figure 17. Example of a Comb Fail Using a NSTC Two Line Comb Filter
REV. 1.0.0 2/4/03
49
TMC22x5yA
PRODUCT SPECIFICATION
provide the phase and magnitude of the in-phase and quadra-
ture components of the high frequency data. These compo-
nents are compared to determine the difference in phase and
magnitude between 0H & 1H in all configurations, LME and
LPE, and between 1H & 2H in NTSC or 0H & 2H in PAL,
UME and UPE. The magnitude error signals can be doubled
to facilitate inputs with low picture levels by setting the
CESG register bit HIGH. The doubled magnitude error
signals are limited to ensure no overflow occurs.
Generation of the Comb Fail Signals
Luma Error Signals
The signals from the 3 low pass filters, 0HL, 1HL, and 2HL
are subtracted from one another to produce an error signal
proportional to the luma comb fail. The resulting signals
(0HL - 1HL), produces LYE, and either (1HL - 2HL) in
NTSC or (0HL - 2HL) in PAL produces UYE. The LYE and
UYE luma error signals are rectified if negative. In cases
where the luminance component is constant, the error will be
zero. Where the luminance goes from black to white over 2
lines, the error signal will go to its maximum value.
The algorithm used to separate the quadrature components
depends upon the relationship between the normalized sub-
carrier frequency and the number of pixels per line. This
algorithm is preset for either a NTSC/M or PAL/I subcarrier
frequency and a pixel data rate of 13.5MHz. It is therefore
necessary to compensate for other pixel data rates by select-
ing the appropriate default using the CEST[1:0] register bits.
The luma error signals can be doubled to facilitate inputs
with low picture levels by setting the YESG register bit
HIGH. The resulting signal is clipped to ensure no overflow
occurs
Picture Correlation
Hue and Saturation Error Signals
The degree of picture correlation depends upon the differ-
ences between the UYE, UME, and UPE upper error signals
and the LYE, LME, and LPE lower error signals, and is mea-
sured as a percentage of full scale error. In flat fields of color
you would have 0% error in picture correlation, however in
sharp vertical transitions say between yellow and blue you
would have large % errors between UYE and LYE and
between UPE and LPE, while there would be 0% error
between UME and LME.
In the past, comb decoders have relied upon comparing the
difference in chroma magnitude between two lines to deter-
mine a comb fail. In fact, this chroma signal is normally the
output of the high-pass or band-pass filter, and therefore con-
tains all the high frequency luminance information as well.
As this signal was never demodulated, the sign bit was
immaterial and was used only to rectify the chroma signal.
This allowed chroma signals which where equal in magni-
tude but opposite in phase, and high frequency luminance
signals, to fool the comb fail circuit.
Adapting the Comb Filter
In NTSC it is possible to switch from a 3 line comb to a 2
line comb, and then to a simple decoder output. The 3 line
comb to 2 line comb switch can be disabled, forcing the 3
line comb to switch directly to simple. The switching
between these two comb architectures is independent of the
The TMC22x5yA uses a new, innovative approach to over-
come this problem. To detect comb failures in the high-
frequency portion of the video signal the outputs from the
three high-pass filters, 0HH, 1HH, and 2HH, are passed
through simple demodulators. The outputs from which
OHL
1HL
2HL
UYE
Luma
Comparison
LYE
YESG
YWBY
OHH
UPE
LPE
Hue
Comparison
Chroma
Demodulation
&
Rectangular
to Polar
1HH
Conversion
UME
LME
Saturation
Comparison
2HH
CESG
CSETBY
65-22x57-59
CEST[1:0]
Figure 18. Generation of Upper and Lower Comb Fail Signals
50
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
ADAPT[1:0]
YCSEL
FAST
UYE
LYE
2:1
MUX
CFSEL[3:0]
Filter
UPE
LPE
Comb
Fail
Logic
YERR
PERR
MERR
UME
LME
STA[3:0]
CAT[1:0]
65-22x5y-60
Figure 19. Comb Filter Selection
mix signal, K. For 3-line Y/C comb filters, an external 1H
delay is required in the uncombed channel to compensate for
the comb filter delay.
Table 5. Adaption Modes
ADAPT[1:0]
Function
00
Adapts to the best of 3 types of line
based comb filters in NTSC only.
This principle is equally true for NTSC frame and field based
comb decoders. The feature is not available for any of the
PAL comb filter architectures.
01
3 line (tap) comb always adapts to
lower 2 line (tap) comb, when the 3 line
(tap) comb fails. Normally used with
NTSC field and frame based comb
filters.
The Comb filter Adaption Threshold register bits CAT[1:0]
determine if 5%, 15%, 25%, or 50% errors in picture correla-
tion is required to adapt the NTSC comb filter. In NTSC, due
to the 180 degree advance in subcarrier phase per line, it is
possible to switch between the 3 line comb and the choice of
either the upper two line comb or the lower two line comb. If
this switching occurs on a pixel by pixel basis the picture
will contain vertical alias components. This artifact can be
reduced by either setting the FAST register bit LOW, which
filters the comb filter selection, and/ or setting the CAT[1:0]
register bits to a higher percentage threshold.
10
11
3 line (tap) comb only. Never adapts to
a 2 line(tap) filter. The higher set of
comb filter error signals are sent to the
XLUT. NTSC or PAL comb filter.
Adapts to best of two 3 line comb filters
in PAL only.
XLUT
The comb filter adaption is further controlled by the
ADAPT[1:0] register bit selection, when the COMB[3:0]
register bits select a 3 line comb. These bits control if the
comb filter adapts from a 3 line comb to the best of the upper
or lower 2 line combs, from a 3 line comb to just the lower 2
line comb, performs a fixed 3 line comb, or implements a
best of two 3 line combs in PAL. If the COMB[3:0] register
bits select one of the 2 line comb filters, the ADAPT[1:0]
register bits are ignored, and no adaption is implemented.
The CFSEL[1:0] signal, shown in Figure 19, controls which
comb filter is selected on a pixel by pixel basis, and can be
externally monitored by reading CFSTAT[1:0] in register
4Bh.
The comb fail signals control both the comb filter adaption
and the cross fade between the adaptive comb filter output
YCOMB and the SIMPLE bandsplit signal. Which of the fail
signals is fed to the XLUT is determined by which comb
filter is selected in NTSC. When a 3 line comb filter is
selected, the larger set of error signals are sent to the XLUT,
when a upper 2 line comb is selected UYE, UME, and UPE
error signals are selected, and when a lower two line comb
filter is selected the LYE, LME, and LPE error signals are
selected.
REV. 1.0.0 2/4/03
51
TMC22x5yA
PRODUCT SPECIFICATION
XFEN
YERR
2:1
MUX
K[4:0]
X[7:0]
XLUT
Input
Select
XLUT
PERR
MERR
Filter
65-22x5y-61
XIP[1:0]
Figure 20. XLUT Input Selection
For PAL comb filters the LYE, LME, and LPE errors signals
are always selected by default. In this way the error signals
into the XLUT always represent the comb filter being imple-
mented. The resolution of the error signals selected is con-
trolled by the XIP[1:0] register bits as shown in Table 6:
XLUT Input Selection. The position of these error signals on
the XLUT input address X[7:0] is also shown.
Table 7. XLUT Output Function. (cont.)
XLUT
OUTPUT
K
16
:
16 - 50% Bandsplit, 50% Comb
:
29
30
31
29
Table 6. XLUT Input Selection
30
XIP[1:0]
Function
32 - 100% Comb
00
2 bits of phase error (X[7:6]), 3 bits of
chroma (X[5:3]) and luma magnitude error
(X[3:0]).
The special function assigned to K = 0 is programmed into
the XSF[1:0] register bits, as shown in Table 8.
01
10
4 bits of chroma (X[7:4]) and luma
magnitude error (X[3:0]).
Table 8. XLUT Special Function Definitions
KIP
1-0
XLUT special function selection
3 bits of phase error (X[7:5]), 3 bits of
chroma magnitude error (X[4:2]), and 2
bits of luma magnitude error (X[1:0]).
Y
C
00
comb
simple
comb
simple
comb
11
4 bits of phase error (X[7:4]) and chroma
magnitude error (X[3:0]).
01
10
11
simple
flat with notch
flat with notch
The selected comb fail signals are translated by the user-
programmed configuration within the 256*5 XLUT into the
mix signal (K) which controls the 30 levels of cross-fade
between the weighted comb filter and the band split filters.
The 1 to 31 mix signal is modified on the input to the cross-
fade to produce a 0 to 32 control signal, as shown in Table 7.
The “Flat with notch” selection passes the FLAT input
through onto the luminance channel and selects the notch
filter, centered at 0.25 of the normalized clock frequency.
This mode is therefore only useful with inputs at 4*Fsc or in
cases when a notch at 0.25 of the normalized clock
frequency is adequate for application.
Table 7. XLUT Output Function.
XLUT
The XLUT output, is fed through a bypassable low-pass
filter KLPF to avoid switching between comb and simple
decoders on a pixel by pixel basis. When the special function
is selected (K = 0) the input to the KLPF is held and the filter
is automatically bypassed. The output of the XLUT can be
externally monitored by reading XOP[4:0] in register 4Bh.
OUTPUT
K
0
Special function (e.g. luma comb and HPF
on chroma)
1
2
3
:
0 - 100% Bandsplit
2
3
:
52
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
.
U Data
V Data
Gaussian
LPF
–
Chrominance
sin(wt)
Gaussian
LPF
65-22x5y-62
Burst
Locked Loop
cos(wt+φ)
Figure 21. Block Diagram of Digital Burst Locked Loop
Frame Bit
NTSC
Digital Burst Locked Loop
The digital burst locked loop provides sine and cosine signals
which are phase locked to the incoming burst signal. These
sine and cosine signals are used to demodulate the chromi-
nance data, producing the U and V color-difference signals.
The U data are phase-referenced to sin(wt) and the V data to
cos(wt). The demodulated signal is passed through a low pass
filter to remove signals at twice the subcarrier frequency.
The magnitude of the U and V data within the demodulated
burst signal provides the error signal which, after filtering, is
used to adjust the frequency and/or phase of the subcarrier
DDS. The output of the subcarrier DDS is translated into sine
and cosine signals in ROM-based lookup tables.
The PALODD signal is low on lines without the 180 degree
phase advance in the modulated V signal, termed NTSC
lines, and high for lines with the 180 degree phase advance,
termed PAL lines. This signal is used in the burst locked loop
to advance the phase of the cosine table on PAL lines. PAL-
ODD is always low for NTSC.
The middle bit (frame bit) of the field count is determined,
by the phase of the subcarrier on a given pixel and on a given
line. The signal used to determine this is NFDET (New Field
DETect), and occurs when the line count is zero and the pixel
count is one of four programmable pixel positions, zero, one,
two, or three.
PAL
The frame bit in PAL is detected through the Bruch blanking
sequence. The error signal control circuit generates a color
kill flag whenever a line is detected without a burst. It is
therefore possible to compare this signal with specific line
idents to determine the field sequence in both PAL-I and
PAL-M. A set of specific patterns determine the correct
phase of FID ; if any of these patterns is detected then FID
1
1
is forced to a known state and then flywheels until the next
fixed pattern is detected.
Table 9. PAL-B,G,H,I Bruch Blanking Sequence
Color Kill Counter
Internal
line #
Burst
present
Internal
frame #
The demodulated U and V components are compared to a
programmable burst level threshold. If both the U and V data
fall below this threshold, a color kill flag is set high. The
color kill counter is incremented once per line if the color
kill flag is high. If the count reaches 127 within one field, the
color kill circuit becomes active during the next field group.
When this occurs, the input video will be passed unaltered
on the luminance channel and the color difference signals
will be set to chroma black.
Internal field #
0 or 4
5
309
6
No
No
0 or 2
0 or 2
0 or 2
0 or 2
1 or 3
1 or 3
1 or 3
1 or 3
0 or 4
Yes
No
1 or 5
309
5
1 or 5
Yes
Yes
No
2 or 6
309
6
2 or 6
The color kill signal remains active until a field with less
than 127 lines without burst is encountered, at which time,
during the next vertical blanking period, the decoder is reset.
The operation of the color kill logic can be monitored exter-
nally by reading the MONO register bit in register 44h. The
MONO bit is HIGH for composite andYC video signals and
LOW for monochrome signals.
3 or 7
309
Yes
3 or 7
The frame bit is low for frames 0 and 2 and high for frames 1
and 3.
Field Flag, FLD
The FLD signal is the lsb of the field count FID and is
2-0
LOW for fields where the first vertical sync occurs in the first
half of the line and is HIGH for fields when it occurs in the
second half of the line. This signal is synchronized with the
frame and color frame flags in the FID generator.
REV. 1.0.0 2/4/03
53
TMC22x5yA
PRODUCT SPECIFICATION
Table 10. PAL-M Bruch Blanking Sequence
Internal
line #
Burst
present
Internal
frame #
0
-10
-20
-30
-40
-50
-60
-70
Internal field #
0 or 4
7
258
7
No
Yes
No
0 or 2
0 or 2
0 or 2
0 or 2
1 or 3
1 or 3
1 or 3
1 or 3
Demodulator Filter 1
0 or 4
1 or 5
Demodulator Filter 2
259
7
No
1 or 5
Yes
No
2 or 6
258
7
2 or 6
Yes
Yes
3 or 7
259
3 or 7
Normalized Frequency
Figure 22. Gaussian Low Pass Filters
The frame bit is low for frames 0 and 2 and high for frames 1
and 3.
PAL Color Frame Bit
0
-2
The PAL color frame bit is the msb of the field count, FID .
2
In NTSC this is always low, as NTSC has only a 4 field se-
quence. For both PAL-I and PAL-M inputs, the PAL color
frame bit is determined in the same way the frame bit is de-
termined in NTSC, by using the phase of the subcarrier on a
given pixel and on a given line.
Demodulator Filter 1
-4
-6
Demodulator Filter 2
-8
Hue Control
One of two programmable 16 bit system phase offsets can be
added to the subcarrier oscillator between SAV and EAV.
The selection is made by the BUFFER pin. This feature
allows the user to change the picture hue on known frames
without affecting the burst locked loop.
-10
Normalized Frequency
Figure 23. Gaussian LPF Passband Detail
Bypassing the Chrominance Demodulator
The demodulation of the chrominance signal needs to be
System Monitoring of the Burst Loop Error
The burst loop error signal is stored once per line in an 8 bit
register that can be accessed over the microprocessor port.
This allows the user to check for non-mathematical PAL in-
puts and to the change the decoder architecture from frame-
based to line-based or simple decoder depending on this in-
formation.
bypassed when the decoder is processing C C component
B R
data or when a YC output is required. The bypass operation
is controlled by the DMODBY register bit.
Bypassing the Demodulation Low Pass Filter
The demodulation low pass filter needs to be bypassed when
processing C C component data or when a YC output is
required. The C C data can also be passed through the
B R
B R
Demodulation Low Pass Filter
There are two different demodulation low pass filters that
can be selected under software. For PAL inputs with normal-
ized subcarrier frequencies greater than 0.3 of the sampling
frequency, it is recommended you use “demodulator filter 2”
to stop aliasing of the second harmonic of the demodulation
chrominance signal and the baseband color difference sig-
nals. Gaussian filters are used for both demodulation filters
as they have no negative coefficients and therefore have no
undershoots or overshoots which could cause in-band
ringing.
Gaussian filter if the bandwidth needs to be reduced. The
bypass operation is controlled by the GAUBY register bit.
Chrominance Coring
Chrominance coring, when active, sets the lsbs of the
chroma channel (below a programmable threshold) to zero.
VMCR Operation
5
When VMCR is HIGH, the decoder will grab one line of
5
video in LSTORE1. This effectively removes the comb filter
from the decoding process, and the comb filter output is
forced to simple mode.
54
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Output Processor
Mixed Sync
+
X
SGx[9:0]
Adaptive Luma
Notch Filter
Y Data
+
–
–
X
G/Y Data
YOFF[8:0]
YGx[9:0]
YSEL ANEN
ANT[1:0]
VIDEOB
PED[7:0]
Output
Formatter
Clamp
Circuit
LPF
256
240
X
B/Cb Data
R/Cr Data
CLMP[1:0]
VCLPEN
Fixed (B-Y)
Gain Stage
U Data
V Data
X
UGx[10:0]
X
Fixed (R-Y)
Gain Stage
X
65-22x5y-65
VGx[10:0]
Figure 24. Output Processor Block Diagram
clamp pulse can be used to control where an analog clamp
circuit grabs the analog reference to establish the correct
voltage level into the A/D. Usually the clamp pulse is gener-
ated on the back porch or duing the sync tip of a video line.
Clamp Circuit
A clamp pulse generated by the Burst Gate signal is used to
grab either a sample of the low-pass-filtered luma during the
video back porch, the signal on VIDEOB, or one of two
internally generated levels. The selection is made by the
CLMP[1:0] register bits.
Adaptive Notch Filter
The PAL line-locked comb decoder can never provide
perfect subcarrier cancellation due to the 25Hz offset in the
subcarrier frequency. This 25Hz offset causes residual and
phase modified subcarrier to be left on the luminance signal
which can produce a visible dot crawl on flat areas of color.
However, for all comb filter structures, the quality of the
comb depends on the quality of the sampling clock, as line to
line clock jitter will also cause small phase changes between
the inputs to the comb filter. It is therefore possible that
NTSC comb decoders may also require some coring of the
luma output. To meet the wide range of sample frequencies
that the decoder must deal with two separate coring filters
are selectable.
Table 11. Blanking Level Selection
CLMP[1:0]
Blanking Selection
Internal 240 level
00
01
10
11
Internal 256 level
External VIDEOB Input
Internal LPF Output
The blanking level is subtracted from the decoded luma.
If the sign is negative, the result is assumed to be mixed sync
and is passed through a delay and into the sync gain stage
within the output matrix. If the sign is positive, the result is
assumed to be pure luma (blanking to peak white) and is fed
to the pedestal removal circuit.
The luma signal from the pedestal stripper is compared
against the preceding pixel to detect the magnitude change
between pixels. This magnitude difference will be almost
zero for flat areas of picture, and large for high frequency
changes in the picture. The magnitude difference is com-
pared to one of four programmable thresholds. The program-
Pedestal Removal
The 8 bit programmable pedestal is subtracted from the pure
luma signal. The negative super black signals are clipped to
zero when register 0Ah bit 4 is set LOW, or the super black
signals are passed through the luma scalar when register 0Ah
bit 4 is HIGH.
mable threshold is selected by the ANT register bits as
1-0
shown in Table 12.
Table 12. Adaptive Notch Threshold Control
ANT
1-0
Magnitude difference
less than 16
Clamp Generator
00
01
10
11
The TMC22x5yA has the unique option to output a negative
going clamp pulse that is 0.5 µsec wide. This pulse can be
output on the AVOUT pin by placing a HIGH on register 24
bit 7. The pulse’s position relative to HSYNC can be varied
by register 25. This value is the number of PCK clock cycles
after an HSYNC that the pulse will be output to the pin. The
less than 12
less than 8
less than 4
REV. 1.0.0 2/4/03
55
TMC22x5yA
PRODUCT SPECIFICATION
If either of the error signals indicates that the magnitude
difference is above the programmed threshold, or if ANEN is
LOW, the adaptive notch filter is bypassed. The output of the
adaptive notch filter is rounded to 8 or 10 bits, or the luma
data that bypasses the coring filter is truncated to 8 or 10 bits
depending upon the CORO register bit.
Programmable U Scalar
The U scalar (UGx) provides the weighting required to
produce (B-Y) or C from the demodulated U signal.
B
hence
(B-Y) = UGx * U
0
-10
-20
where UGx = gain / 0.493, and
C
= UGx * U
B
Adaptive Notch
Filter 1
Adaptive Notch
Filter 32
-30
-40
-50
-60
-70
where UGx = (gain * 448) / Umax
UGx has a scaling range of 0 to (2047/256).
Programmable V Scalar
Adaptive Notch
Filter 2
The V scalar (VGx) provides the weighting required to
produce (R-Y) or C from the demodulated V signal.
R
Normalized Frequency
hence
(R-Y) = VGx * V
Figure 25. Adaptive Notch Filters
where VGx = gain / 0.877, and
Luma Notch Filter
C
= VGx * V
R
The simple luma notch filter is centered at 0.25 of normal-
ized frequency, it therefore intended for use only in the sub-
carrier mode (4 * fSC) and for limited use with 13.5MHz
NTSC as the subcarrier sits at 0.265 of normalized fre-
quency. The notch filter is enabled by setting the NOTCH
register bit HIGH.
where VGx = (gain * 448) / Vmax
VGx has a scaling range of 0 to (1023/256).
ProgrammableY Scalar
The Y scalar (YGx) provides the scaling for the luminance
0
-10
-20
-30
-40
-50
-60
-70
signal if the output is YC C , or controls the magnitude of
B R
the RGB output along with the U scalar and V scalar. It is not
possible to control the magnitude of the RGB signals inde-
pendently.
YGx has a scaling range of 0 to (1023/256).
Programmable MS Scalar
The sync scalar (SGx) provides the scaling for the sync
signal if the output requires sync on RGB. The programmed
sync scaling factor is used during the horizontal and vertical
burst blanking periods. During the active lines, the luma
scaling factor is used to allow scaling of “super blacks” etc.,
which will be passed down the mixed sync path because they
fall below the clamp level.
Normalized Frequency
Figure 26. Luminance Notch Filter
Matrix
SGx has a scaling range of 0 to (1023/256).
The magnitude of the decoded luminance and color differ-
ence signals will vary, not only with the standard, but also
with the input mode. For this reason the output matrix
contains programmable multipliers, and not just fixed
scaling factors. The following sub sections explain the differ-
ent scalar in the output matrix. The gain term in theY, mixed
sync, U and V scalar is the same - only the weighting makes
them different. The scalar are capable of independently
providing 6dB of gain if required.
Fixed (B-Y) and (R-Y) Scalars
These two scalars are zero when the output is YC C and
B R
provide the (B-Y) and (R-Y) weighting when the output is
RGB. These are fixed scaling factors and are derived from
the following equations.
(G-Y) = - [(0.299/0.587) * (R-Y)]
- [(0.114/0.587) * (B-Y)]
or
(G-Y) = - [(1043/2048) * (R-Y)]
- [(398/2048) * (B-Y)]
56
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Y Offset
Decoder Output
CCIR 601 Spec
The 8 bit Y offset adds any offset required in the Y or RGB
data outputs. For example 64 (16) for the 64 (16) to 940
Color
Red
Y
C
C
Y
C
C
R
B
R
B
325 -150 447 326 -151 448
(235) 10 bit (8 bit) 601 outputs. When the output is YC C
B R
this offset is applied to the luminance data only. TheY offset
also provides the blanking level for RGB
outputs with syncs.
Blue
163 448
64
-73
0
164
64
448 -72
Black
0
0
0
PAL digital composite input and RGB (0-1023) outputs:
Matrix Limiters
The different limiters are listed below, 10 bit data is
assumed.
Color
White
Yellow
Cyan
Y
U
0
V
0
572
507
401
336
236
171
65
-250
84
57
Table 13. Matrix Limiters
-352
-295
295
352
-57
0
LMT
1-0
Comments
Green
Magenta
Red
-165
165
-84
250
0
00
01
RGB output format, limited from 0 to 1023
YC C output format, Y limited from 0 to
B
R
1023 and C C limited to +/- 511.
B
R
10
11
RGB output format, limited from 64 to 940
YC C output format, Y limited from 64 to
Blue
B
R
Black
0
940 and C C limited to +/- 448
B
R
The nominal scaling factors are simply:
YGx = 1023/572 = 1 + (202/256)
Examples of Output Matrix Operation
From the SMPTE-170M specification:
UGx = (1023/572)*(1/0.492) = 3 + (163/256)
VGx = (1023/572)*(1/0.877) = 2 + (10/256)
YOFF= 0
PED = 0
Color
White
Yellow
Cyan
Y
U
0
V
0
584
523
423
361
267
205
105
44
-236
79
54
Color
White
Yellow
Cyan
G
1023
1023
1023
1023
0
R
1023
1023
0
B
1023
0
-332
-278
278
332
-54
0
Green
Magenta
Red
-156
156
-79
236
0
1023
1
Green
Magenta
Red
0
Blue
1023
1023
0
1022
1
Black
0
Blue
0
1023
0
YC C data ranges are:
B R
Black
0
0
Y data range is 64 to 940 (876)
C C data ranges are 64 to 960 (+/- 448)
B R
It is also possible with the architecture supplied to use the
limiters on the output of the matrix to clip the output video
deliberately by using a slightly larger gain than is required.
The Y_Offset can achieve the same by setting its value to be
one lsb less than the minimum clip level.
Matrix programming:
YGx = (876 / 540) = 1 + (159/256)
UGx = (448 / 236) = 1 + (230/256)
VGx = (448 / 332) = 1 + (89/256)
YOFF = 64
Buffer Registers
PED = 44
The BUFFER pin allows the user to externally switch
between two sets of internal registers that have the same
function. This register buffering allows the matrix gain,
picture hue, and luma offset to be changed at a known time
relative to the input data.
Decoder Output
CCIR 601 Spec
Color
White
Yellow
Cyan
Y
C
C
Y
C
B
C
R
B
R
939
0
0
940
0
0
Registers 17 to 1D are selected when the BUFFER pin is
LOW and registers 27 to 2D are selected when the BUFFER
841 -448
73
840 -448
72
pin is HIGH. If the msb of the decoder product code DPC is
678 150 -447 678 151 -448
578 -296 -376 578 -296 -375
2
LOW, an 8 bit decoder has been selected and the bottom 2
bits of registers 17 to 1A and 27 to 2A are forced to zero.
Green
Magenta 426 296 376 426 296 375
REV. 1.0.0 2/4/03
57
TMC22x5yA
PRODUCT SPECIFICATION
CBSEL, to produce the multiplexed C C data stream at the
B R
PCK clock rate. If the input was initially D1 then the
dropped samples will be the interpolated samples produced
Simple Luma Color Correction
If the YBAL register bit is set HIGH, and the luma data
reaches or exceeds the luma limits, there should be no C C
or UV data at that time; therefore the color data are set to
B R
by the chroma interpolation filter. If however the C C data
B R
are simply weighted UV data then the sample dropped
demodulated color difference signals (UV) will alias around
0.25 of the normalized sample frequency.
ZERO. If YBAL is set LOW then the C C /UV data are
B R
unaffected by the luma data.
C C MSB Inversion
B R
MultiplexedYC C Output (TRS Words
B R
Inserted)
The msb of the C C data can be inverted by setting the
B R
MSBO register bit HIGH. As this would affect the chroma
blanking level, this circuit appears at the output of the
MATRIX circuit.
When both the CDEC and YUVT register bits are HIGH the
Y, C , and C component data are multiplexed into a single
B
R
27MHz (PXCK) data stream with embedded TRS words.
The TRS words are generated based on the HSYNC or
VSYNC pulses provided to the decoder, and the internally
derived horizontal blanking (HBLK), vertical blanking
(VBLK), and the field flag (FLD). This mode of operation is
only available if a line locked PXCK clock, at 27MHz, is
provided. The TRS words will be generated with respect to
the HSYNC\ signal as per the ANSI/SMPTE 125M-1992
and CCIR 656 specifications.
Output Rounding
For compatibility with 8 bit systems, the output of the matrix
can be rounded to 8 bits by setting the RND8 register bit
HIGH.
Output Formats
RGB Outputs
The RGB data are simply passed through to the decoder out-
put. When the DRSEN register bit is HIGH the DRS data are
inserted into the green data path only.
YC Outputs
TheYC data are passed through to the decoder output. When
the DRSEN register bit is HIGH the DRS data are inserted
into the luminance data path only. The luminance appears on
G/Y, chrominance is on B/U and the R/V output is set to
zero, by setting the V_scalar to zero.
YUV Outputs
The YUV data are simply passed through to the decoder out-
put. When the DRSEN register bit is HIGH the DRS data are
inserted into the luminance data path only.
The LDV Clock
YC C Outputs
B
R
The decoder can accept clocks at either the pixel clock rate
(PCK) or at twice the pixel clock rate (PXCK). In the cases
where the clock provided is PXCK, for example the genlock
mode, the output data still needs to be at the PCK clock rate.
To aid in the design of external circuitry a LDV clock is pro-
vided if the LDVIO register bit is LOW, if LDVIO is HIGH
then the LDV pin becomes an input for an external clock.
The YC C data can be output in 3 ways, depending upon
B R
the CDEC, F422, and YUVT register bits. These output
modes are summarized in .
When CDEC is HIGH and F422 is HIGH, the G/Y output is
set to 64 and the B/U output is set to 512 between the EAV
TRS data word and the first preamble word of the SAV TRS,
i.e. during the digital horizontal blanking period. When
YUVT is HIGH, R/V is set to 512, 64, 512, 64, etc., starting
after the EAV TRS data word and finishing before the SAV
preamble.
If an external LDV clock is employed the user must ensure
that the rising edge of the external LDV meets the specified
setup and hold times relative to the input CLOCK pin. The
selection of which clock to use on the decoder output is set
by the OPSEL register bit. When OPSEL is set LOW the
output is clocked at the same rate as the clock on the
CLOCK pin, and when OPSEL is set HIGH the output is
clocked by the internal or external clock on the LDV pin.
Decimating C C Data
B R
Whenever the CDEC register bit is set HIGH the B/U and
R/V data are simply sample dropped, with respect to
Table 14. Output Format
CDEC
YUVT
F422
G/Y
B/U
R/V
Comments
0
1
1
1
x
0
0
1
x
0
1
x
G or Y
B or C
R or C
[4:4:4] data
[4:2:2] data
[4:2:2] data
B
R
Y
Y
Y
C
C
R
B
C C
0
B
R
C C
D1 data
[4:2:2] data & D1 output
B
R
58
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
*
Sync Pulse Generator
HBLK (Horizontal Blanking Period)
The horizontal blanking period is LOW between the start of
SAV and the end of EAV. This signal is used in several
places:
a) To clear the SYSPH offset when LOW, this is required
for correct operation of the subcarrier phase locked loop,
b) To aid in the comb filter management,
c) To remove the burst envelope on the demodulated UV
data,
The vertical and horizontal references to the decoder can be
from external VSYNC and HSYNC pulses, decoded from
TRS and TRS-ID words, or from the internal sync separator
which extracts the sync information from the digitized input
video.
The sync pulse generator (SPG) provides all the clock and
enable pulses required to synchronize the decoder operation
to the incoming video signal. These pulses are described
below, along with the microprocessor data required to
control them.
d) To remove the syncs on the BLUE and RED outputs.
BBLK (Vertical Burst Blanking Period)
The vertical burst blanking blanks the lines with no burst
from the burst phase locked loop. This signal is decoded from
Internal Field and Line Numbering Scheme
the line ident, LID , and is modified by the video standard
4-0
The internal line numbering of the digital decoder differs
from the standard video line numbering as shown in the
following tables. The internal line numbers for a 3 line comb
advance the numbering by 1 line with respect to the input,
but are identical with respect to the internally one line
delayed decoded video.
and the field count.
MBLK (Mixed Blanking)
This signal is used in the matrix to switch between the
sync scalar and the luma scalar. The MBLK signal is active
whenever HBLK is active or becomes active when VBLK
becomes active. MBLK is also active in PAL on line 310
when both VACT1 and FLD are HIGH and in NTSC and
PAL M on line 259 when VACT2 is HIGH and FLD is LOW.
Table 15. NTSC Field and Line Numbering
Standard Standard
Internal
Field #
Internal Line
#
*
Field #
1 & 3
1 & 3
2 & 4
2 & 4
Line #
FLD
The FLD is LOW for field 1 and HIGH for field 2.
1 - 3
1 & 3
0 & 2
0 & 2
1 & 3
260 - 262
0 - 259
*
4 - 263
LID
4-0
The line ID signals are used in the vertical comb filter
management to control the comb filter on the leading and
trailing lines of active video around the vertical blanking
period, to start and stop the VINDO operation, and in gener-
ating the vertical blanking and burst blanking periods.
264 - 265
266 - 525
260 - 261
0 - 259
Table 16. PAL B,G,H,I Field and Line Numbering
Standard Standard
Internal
Field #
Internal Line
#
*
VACT2
Field #
1 & 5
2 & 6
3 & 7
4 & 8
Line #
VACT2 is HIGH during the second half of all active lines.
1 - 312
0 & 4
1 & 5
2 & 6
3 & 7
0 - 311
0 - 312
0 - 311
0 - 312
*
GRABF
313 - 625
626 - 937
938 - 1250
The GRABF signal goes HIGH when the internal field count
is equal to the programmed field number for the GRAB
operation. f a pixel grab is being, this signal is held HIGH to
not inhibit the GRABS signal on each line.
*
Table 17. PAL M Field and Line Numbering
GRABL
The GRABL signal goes HIGH when the internal line count
is equal to the programmed line number for the GRAB
operation. If a pixel grab is being performed, this signal is
held HIGH to not inhibit the GRABS signal on each line.
Standard Standard
Internal
Field #
Internal Line
#
Field #
1 & 5
2 & 6
3 & 7
4 & 8
Line #
1 - 262
0 & 2
1 & 3
0 & 2
1 & 3
0 - 261
0 - 262
0 - 261
0 - 262
263 - 525
1 - 262
*
GRABP
The GRABP signal goes HIGH when the internal pixel count
is equal to the programmed pixel number for the GRAB
operation.
263 - 525
*
HSTBG (Burst gate)
DVSYNC and DHSYNC (Output Pins)
The burst gate starts the 16 clock period average of the
demodulated burst envelope. The position of the burst gate is
programmed into a register as the number of clock periods
from the falling edge of sync to the burst envelope.
The DVSYNC and DHSYNC signals are active when GCR2
is LOW. When GCR2 is HIGH these signals are three stated.
Three line comb based decoders have an inherent line delay,
therefore the input VSYNC and HSYNC signals can not be
just delayed by a few registers and output as DVSYNC and
DHSYNC: they need to be delayed by one complete line. In
all other comb filter configurations the DVSYNC and
* Signal is available over the microprocessor data bus.
REV. 1.0.0 2/4/03
59
TMC22x5yA
PRODUCT SPECIFICATION
DHSYNC are referenced to the input data (0HFLAT) and not
the output of the LSTORE1, i.e. 1HFLAT.
Table 19. Vertical Burst Blanking Period
Internal field no
Internal line no
0 - 5
The duration of the DVSYNC signal is fixed to one line and
the duration of the DHSYNC signal is 64 clock periods.
Both these signals are generated by the internal horizontal
and vertical state machines.
NTSC
0,2
259 - 261
0 - 6
1,3
The falling edge of these signals relative to the data matches
the requirements of the TMC22x91 family of digital encod-
ers.
260 - 262
0 - 5
PAL
0 & 4
1 & 5
2 & 6
3 & 7
0 & 4
1 & 5
2 & 6
3 & 7
309 - 311
0 - 5
AVOUT Active Video (Output Pin)
The decoder produces an active video signal starting 4 PCK
before the programmed start of active video and ending 4
PCK after the programmed end of active video. This signal is
used in both the video mixer (TMC22x8x) family and the
digital encoder (TMC22x9x) family. The end points of this
signal are flagged by the internally generated SAV and EAV
signals.
309 - 312
0 - 4
310 & 311
0 - 6
310 - 312
0 - 7
**
PAL-M
VBLK (Vertical Blanking Period)
The vertical blanking period conforms to the CCIR 656
specification for D1 component data streams. This signal is
259 - 261
0 - 7
decoded from the line ident, LID , and is active low.
4-0
259 - 262
0 - 6
Table 18. Vertical Blanking Period
Internal field no
Internal line no
0 - 5
258 & 261
0 - 6
NTSC
0,2
260 & 261
0 - 6
260 - 262
1,3
LID
4-0
List of Line Idents
260 - 262
0 - 21
The line numbers required to produce all the decoder control
signals are summarized in
PAL
0, 2, 4, & 6
1, 3, 5, & 7
0, 2, 4, & 6
1, 3, 5, & 7
310 & 311
0 - 22
Table 20. Table of Line Idents, LID[4:0]
Line no:
LID
4-0
311 & 312
0 - 5
0
1 - 4
5
00
PAL-M
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
260 & 261
0 - 6
6
260 & 262
7
8
BBLK (Vertical Burst Blanking Period)
9 - 16
17
The vertical burst blanking blanks the lines with no burst
from the burst phase locked loop. This signal is controlled by
the video standard and the field count. The burst blanking
signal is active low.
18
19 - 21
22
23
24
25 - 257
258
259
** Signal is available over the microprocessor data bus.
60
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
STS: The number of pixels between sync pulses
Table 20. Table of Line Idents, LID[4:0] (cont.)
Line no:
260 & 261
262
LID
4-0
STB: The number of pixels between the nominal mid point
of sync and the start of the 16 pixel burst gate. This value is
modified depending upon the mode of operation.
10
11
12
13
14
15
16
17
263 - 307
308
Table 21. Timing Offsets
Standard
Mode
Genlock
Offset required
309
x
-8
-8
310
x
x
Line locked
Subcarrier
D2 mode
D2 mode
D1 mode
311
-22
-12
-8
312
PAL
NTSC
x
Timing Parameters
+12
Subcarrier Programming
BTV: The number of pixels between the start of the 16 pixel
burst gate and the nominal start of active video.
The color subcarrier is produced by an internal 28 bit Direct
Digital Synthesizer (DDS) which is phase locked to the burst
signal of the digitized video input. The nominal frequency is
programmed into the DDS as follows:
AV: The number of active pixels in the active video line.
The difference between the sum of STB+BTV+AV sub-
tracted from STS provides the nominal front porch.
FREQ = (number of subcarrier cycles per line / number of
pixels per line) * 2^28
Horizontal and Vertical Timing Parameters
An example would be NTSC subcarrier mode
FREQ = (227.5 / 910) * 2^28 = 4000000 hex
When external horizontal and vertical syncs are provided the
timing shown in Figure 28 is required to synchronize the
internal state machines to beginning of a field (3, 5, or 7).
For field 2 (4, 6, or 8) the falling edge of VSYNC must occur
at least 2 clock periods but not more than (H-2) clock periods
after the falling edge of HSYNC, where H is the total num-
ber of pixels in an active video line.
Horizontal Timing
The horizontal video line is broken down into four horizontal
timing parameters.
STB
BTV
AV
STS
65-22x5y-68
Figure 27. Horizontal Timing
REV. 1.0.0 2/4/03
61
TMC22x5yA
PRODUCT SPECIFICATION
CLOCK
t
HP
t
SP
HSYNC
VSYNC
65-22x5y-12
Figure 28. External HSYNC and VSYNC Timing for Field 1 (3, 5, or 7)
Vertical Blanking
256
257
FIELDS 1 AND 3
17
18
6
•••
15
16
258
259
260
0
1
2
3
4
5
UVV
UVV
EE
EE
EE
SS
SS
SS
EE
EE
EB
UBB
UBB
UBB
UVV
UVV
HSYNC
VSYNC
FLD
259
FIELDS 2 AND 4
17
18
19
258
7
•••
16
260
261
0
1
2
3
4
5
6
UVV
UVE
EE
EE
ES
SS
SS
SE
EE
EE
EB
UBB
UBB
UVV
UVV
UVV
HSYNC
VSYNC
FLD
65-22x5y-69
Figure 29. NTSC Vertical Interval
62
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
309
310
FIELDS 1 AND 5
22
23
24
25
•••
•••
311
EE
312
EE
0
1
2
3
4
5
6
21
UVV
-VE
SS
SS
SE
EE
EE
-BB
UBB
UBB UVV
UVV
UVV
UVV
HSYNC
VSYNC
FLD
308
309
-VV
FIELDS 2 AND 6
23
24
•••
•••
310
EE
311
EE
0
1
2
3
4
5
6
7
21
22
UVV
ES
SS
SS
EE
EE
EB
UBB
UBB
UBB UBB
UVV
UVV
HSYNC
VSYNC
FLD
309
310
FIELDS 3 AND 7
22
23
24
25
•••
•••
311
EE
312
EE
0
1
2
3
4
5
6
21
UVV
-VE
SS
SS
SE
EE
EE
UBB
UBB
UBB UVV
UVV
UVV
UVV
HSYNC
VSYNC
FLD
308
309
FIELDS 4 AND 8
23
24
•••
•••
310
EE
311
EE
0
1
2
3
4
5
6
7
21
22
UVV
UVV
ES
SS
SS
EE
EE
EB
-BB
UBB
UBB UBB
UVV
UVV
HSYNC
VSYNC
FLD
65-22x5y-70
Figure 30. PAL-B,G,H,I,N Vertical Interval
REV. 1.0.0 2/4/03
63
TMC22x5yA
PRODUCT SPECIFICATION
258
259
FIELDS 1 AND 5
17
260
EE
261
EE
262
EE
0
1
2
3
4
5
6
7
8
•••
•••
16
UVV
UVV
SS
SS
SS
EE
EE
EE
-BB
-BB
UBB
UBB
UVV
HSYNC
VSYNC
FLD
259
FIELDS 2 AND 6
17
18
258
260
EE
261
EE
0
1
2
3
4
5
6
7
8
•••
•••
16
UVV
-VE
ES
SS
SS
SE
EE
EE
EB
-BB
UBB
UBB
UVV
UVV
HSYNC
VSYNC
FLD
258
259
-VV
FIELDS 3 AND 7
17
260
EE
261
EE
262
EE
0
1
2
3
4
5
6
7
8
•••
•••
16
UVV
SS
SS
SS
EE
EE
EE
-BB
UBB UBB
UBB
UVV
HSYNC
VSYNC
FLD
259
-VE
FIELDS 3 AND 7
17
18
257
258
260
EE
261
EE
0
1
2
3
4
5
6
7
8
•••
•••
16
UVV -VV
HSYNC
ES
SS
SS
SE
EE
EE
EB
UBB
UBB
UBB
UVV
UVV
VSYNC
FLD
65-22x5y-71
Figure 31. PAL-M Vertical Interval
64
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
VINDO Operation
Video Measurement
The VINDO circuit uses the line idents on LID , and the
4-0
The TMC22x5yA supports a comprehensive set of video
measurement techniques to aid the user in setting up the
gain, phase, etc. of the decoder and in tracking down system
errors.
blanking signals to control the comb filter output and the
blanking of the YUV data in the output matrix during the
vertical blanking period.
The vertical window VINDO starts on the first line after the
Pixel Grab
last equalizing pulse, at LID = 02. The VINDO stays
4-0
The pixel grab allows the user to grab one pixel every line,
or one pixel out of the four field sequence in NTSC or the 8
field sequence in PAL, under software control. The SET pin
HIGH from this line until the VINDO count = VINDO , or
4-0
the VBLK signal goes HIGH, at which time the VINDO goes
LOW. While the VINDO is HIGH the decoder operation is
controlled by VDIV, and during the time the VINDO and
VBLK are LOW the decoder operation is controlled by
VDOV.
can also be used to produce the pixel grab pulse if SET
110 and PGEXT is set HIGH.
=
2-0
The 10 bit G/Y, B/U, R/V outputs are stored in one set of
four 8 bit registers in the FORMAT block, while the 10 bit
Table 22. PAL VINDO operation
luma and mixed sync data and the 10 bit demodulated U and
V color difference signals are stored in a set of five 8 bit
registers in the GRAB circuit block. The pixel grab signal,
PIXEL, whether internally or externally generated, is inter-
nally delayed to ensure that the all the grabbed data are from
the same pixel relative to the line sync pulse. The PIXEL
signal is equal to PGRAB or the logical AND of PGRAB
with FGRAB and LGRAB, and is controlled by the LPGEN,
PGEN, and PGEXT register bits.
LID
4-0
VINDO VDIV VDOV
Y
C
00 - 01
02 - 0A
02 - 0A
02 - 0A
02 - 0A
0B - 17
x
1
1
0
0
x
x
0
1
x
x
x
x
x
x
0
1
x
normal normal
simple simple
flat
black
black
black
simple black
normal normal
The luma and mixed sync signals are multiplexed on the
YMS data bus and the U and V signals are multiplexed on
the UV data bus, at the PXCK clock rate. The pixel grab
signal accommodates for this when grabbing these
components.
NTSC VINDO operation
LID VINDO VDIV VDOV
Y
C
4-0
00 - 02
03 - 06
03 - 06
03 - 06
03 - 06
07 - 17
x
1
1
0
0
x
x
0
1
x
x
x
x
x
x
0
1
x
normal normal
simple simple
An example of the pixel grab feature, is grabbing a pixel in
the center of the burst period allowing the user to check the
burst height by reading the magnitude of the demodulated U
and V components. This allows the user to compensate for
any chrominance gain errors in the output matrix.
flat
black
black
black
black
simple
normal normal
Y
Y Data
C Data
YMS
Luma
Video A
Video B
dT
Proc
MS
Luma and
Chroma
Separation
G/Y
U
V
Output
LPF
Output
Matrix
Chroma
Demodulation
Formatter
and Buffer
UV
B/U
R/V
LPF
U Data
Grab
register 3A/3C
V Data
Grab
G/Y
Grab
register 3B/3C
register 34/37
Y Data
Grab
B/U
Grab
register 38/3C
register 35/37
MS Data
Grab
RV
Grab
register 39/3C
register 36/37
65-22x5y-72
Pixel
dT
Figure 32. Pixel Grab Locations
REV. 1.0.0 2/4/03
65
TMC22x5yA
PRODUCT SPECIFICATION
The SET pin can be used to provide an external grab signal
when PGEXT is set HIGH in register 30h and the SET
function in register 00h, SET[2:0] is programmed to 110
(binary). In this mode the falling edge on the SET pin
triggers the pixel grab.
Table 23. Pixel Grab Control
LGEXT PGEN PGEXT LGEN
GRABS signal
0
0
0
1
x
x
GRABS = 0
0
0
GRABS =
PGRAB
The GRABP, GRABL, and GRABF signals are available on
bits 0,1, and 2 respectively of the read only register 41. An
example of the pixel grab feature, would be grabbing a pixel
in the center of the burst period allowing the user to check
the burst height by reading the magnitude of the demodu-
lated U and V components. This would then allow the user to
compensate for any chrominance gain errors in the output
matrix.
0
1
0
1
GRABS=FGRAB
& LGRAB &
PGRAB
0
1
1
1
x
x
1
0
1
x
x
x
GRABS = NOT
(SET pin)
GRABS =
PGRAB
The pixel grab value is delayed by 29 pixels from the pixel
count. This is the delay for all the pixel grab registers. Figure
33 shows this delay relative to GHSYNC. This means that if
29 is placed in the PG value, the actual pixel grabbed is
pixel 0.
GRABS = NOT
(SET pin)
If a single pixel every 4 fields in NTSC and 8 fields in PAL is
required to be grabbed, PGG and PGEN in register 30h
should be set HIGH. The pixel grab signal is the logical
AND of the GRABP, GRABL, and GRABF signals. GRABP
goes HIGH whenever the pixel count equals the programmed
pixel grab number, GRABL goes HIGH for one line when-
ever the line count equals the programmed line number,
and the GRABF goes HIGH for a field whenever the field
number equals the programmed field count.
The top two bits of the PG value provide the quadrant and
the bottom 9 bits provide the offset within that quadrant.
The integer part of STS/4 gives the maximum count for each
quadrant while the fractional result (bottom two bits)
provides the 0,1,2, or 3 count offset for the last quadrant.
For pixels value <= 4*Int(STS/4)
PG[10:9] = quadrant number
PG[8:0] = max quadrant count - Int(STS/4) + pixel offset
If the same pixel on every line is required to be grabbed, then
PGG should be set LOW, which internally forces GRABL
and GRABF to be forced HIGH enabling the pixel grab
whenever GRABP goes HIGH.
For pixels value > 4*Int(STS/4)
The quadrant is always number 3, ie PG[10:9] = 11 while the
pixel in excess of 4*Int(STS/4) is added to 1536.
Pixel STS-1
STS-1
Pixel Count
0
Pixel 0
1
GHSYNC
0
STS-1
Pixel Grab
0
Pixel Grab
value 28
Pixel Grab
value 0
29 pixels
Figure 33. Relationship Between Pixel Count and Pixel Grab Value
66
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Examples:
cycle for the frozen line store is still clocked by PCK. The
subcarrier DDS and the internal read only registers will be
updated once per clock period as normal, but will reload the
DRS SEED and PHASE values at the beginning of each line.
The G/Y, B/U, and R/V outputs will remain active, and the
DHSYNC and DVSYNC signals will remained locked to the
input or flywheel if the input has been removed.
NTSC std with STS programmed to 858.
Base pixels per quadrant = Int(858/4) = 214
Pixel 0:
1. Pixel 0 <= 4*Int(858/4)
2. Required pixel 0 < 214 therefore quadrant = 0,
[PG[10:9] = 00]
The pixel grab function can be used in conjunction with the
frozen line to examine individual pixels inside the decoder.
3. PG[10:0] = 511 - 214 + (0+[0*214]) = 297
Parallel Microprocessor Interface
Pixel 56:
1. Pixel 56 <= 4*Int(858/4)
2. Required pixel 56 < 214 therefore quadrant = 0
[PG[10:9] = 00]
The parallel microprocessor interface, active when SER is
HIGH, employs a 12-line interface, with an 8-bit data bus
and one address bit: two addresses are required for device
programming and pointer-register management. Address bit
0 selects between reading/writing the register addresses and
reading/writing register data. When writing, the address is
presented along with a LOW on the R/W pin during the fall-
3. PG[10:0] = 511 - 214 + (56-[0*214]) = 353
Pixel 250:
1. Pixel 250 <= 4*Int(858/4)
ing edge of CS Eight bits of data are presented on D dur-
2. Required pixel 250 > 214 therefore quadrant =/= 0
3. Required pixel 250 < 428 therefore quadrant = 1,
[PG[10:9] = 01]
7-0
ing the subsequent rising edge of CS. One additional falling
edge of CS is needed to move input data to its assigned
working registers.
4. PG[10:0] = 1023 - 214 + (250-[1*214]) = 845
In read mode, the address is accompanied by a HIGH on the
R/W pin during a falling edge of CS. The data output pins go
Pixel 800:
1. Pixel 800 <= 4*Int(858/4)
to a low-impedance state t
after CS falls. Valid data are
after the falling edge of CS. Because
DOZ
2. Required pixel 800 > 214 therefore quadrant =/= 0
3. Required pixel 800 > 428 therefore quadrant =/= 1
4. Required pixel 800 > 642 therefore quadrant =/= 2
5. Required pixel 800 < 858 therefore quadrant = 3,
[PG[10:9] = 11]
present on D
t
7-0 DOM
this port operates asynchronously with the pixel timing,
there is an uncertainty in this data valid output delay of one
PXCK period. This uncertainty does not apply to t
.
DOZ
Writing data to specific control registers of the TMC22x5yA
requires that the 8-bit address of the control register of inter-
est be written. This control register address is the base
address for subsequent write operations. The base address
autoincrements by one for each byte of data written after the
data byte intended for the base address. If more bytes are
transferred than there are available addresses, the address
will not increment and remain at its maximum value of 3Fh.
6. PG[10:0]= 2047 - 214 + (800-[3*214]) = 1991
Pixel 856:
1. Pixel <= 4*Int(858/4)
2. Required pixel 856 > 214 therefore quadrant =/= 0
3. Required pixel 856 > 428 therefore quadrant =/= 1
4. Required pixel 856 > 642 therefore quadrant =/= 2
5. Required pixel 856 < 858 therefore quadrant = 3,
[PG[10:9] = 11]
Table 24. Parallel Port Control
6. PG[10:>0] = 2047 - 214 + (856-[3*214]) = 2047
A
R/W
Action
1-0
Pixel 857:
1. Pixel 857 > 4*Int(858/4)
2. Therefore quadrant = 3, [PG[10:9] = 11]
3. PG[10:0] = 1536 + (857-[4*214]) = 1537
00
00
01
01
10
10
0
Load D
7-0
(block 00)
into Control Register pointer
1
0
1
0
1
Read Control Register pointer on
D
7-0
Composite Line Grab
Load D
into addressed XLUT
Location pointer (block 01)
7-0
The composite line grab is only available in the 3 line comb
based decoders (TMC22053A and TMC22153A), and
allows the user to grab any line from the 4 field sequence in
NTSC or 8 field sequence in PAL when LGEN is set HIGH.
When the LGEN register bit is set HIGH the decoder auto-
matically switches to operate as a “simple” bandsplit
decoder. The SET pin can also be used to produce the line
Read addressed XLUT Location pointer
on D
.
7-0
Write D
to addressed Control
7-0
Register
Read addressed Control Register on
grab pulse if SET = 110 and LGEXT is set HIGH.
2-0
D
7-0
Once the line grab has been activated the subcarrier oscilla-
tor is frozen with the SEED and phase from the beginning of
the line, and the composite video in the 1H line store is
frozen by disabling the write signals in LSTORE1. The read
11
11
0
1
Write D
to addressed XLUT Location
7-0
Read addressed XLUT Location on D
7-0
REV. 1.0.0 2/4/03
67
TMC22x5yA
PRODUCT SPECIFICATION
t
t
PWHCS
PWLCS
CS
R/W
ADR
t
t
HA
SA
t
t
SD
HD
D
7-0
65-22x5y-16
Figure 33. Microprocessor Parallel Port – Write Timing
t
t
PWHCS
PWLCS
CS
R/W
ADR
t
t
HA
SA
t
t
HOM
DOM
D
7-0
65-22x5y-17
t
DOZ
Figure 34. Microprocessor Parallel Port – Read Timing
There are six components to serial bus operation:
Serial Control Port (R-Bus)
In addition to the 12-wire parallel port, a 2-wire serial
control interface is provided, and active when SER is LOW.
Either port alone can control the entire chip. Up to eight
TMC22x5yA devices may be connected to the 2-wire serial
interface with each device having a unique address.
• Start signal
• Slave address byte
• Block Pointer
• Base register address byte
• Data byte to read or write
• Stop signal
The 2-wire interface comprises a clock (SCL) and a bi-direc-
tional data (SDA) pin. The Decoder acts as a slave for receiv-
ing and transmitting data over the serial interface. When the
serial interface is not active, the logic levels on SCL and
SDA are pulled HIGH by external pull-up resistors.
When the serial interface is inactive (SCL and SDA are
HIGH) communications are initiated by sending a start sig-
nal. The start signal is a HIGH-to-LOW transition on SDA
while SCL is HIGH. This signal alerts all slaved devices that
a data transfer sequence is coming.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA must change only when SCL is LOW. If SDA changes
state while SCL is HIGH, the serial interface interprets that
action as a start or stop sequence.
The first eight bits of data transferred after a start signal com-
prise a seven bit slave address (the first seven bits) and a sin-
gle R/W bit (the eighth bit). The R/W bit indicates the
direction of data transfer, read from or write to the slave
device. If the transmitted slave address matches the address
of the device (set by the state of the SA input pins in Table
2-0
20), the TMC22x5yA acknowledges by bringing SDA LOW
on the 9th SCL pulse. If the addresses do not match, the
TMC22x5yA does not acknowledge.
68
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Reading (the R/W bit of the slave address byte HIGH)
Table 25. Serial Port Addresses
begins at the previously established base address. The
address of the read register autoincrements after each byte is
transferred.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
A
6
A
5
A
4
A
3
A
2
A
1
A
0
(MSB)
(SA ) (SA ) (SA )
2 1 0
To terminate a write sequence to the TMC22x5yA, a stop
signal must be sent. A stop signal comprises a LOW-to-
HIGH transition of SDA while SCL is HIGH. To terminate a
read sequence simply do not acknowledge (NOACK) the last
byte received and the TMC22x5yA will terminate the
sequence.
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A repeated start signal occurs when the master device driv-
ing the serial interface generates a start signal without first
generating a stop signal to terminate the current communica-
tion. This is used to change the mode of communication
(read, write) between the slave and master without releasing
the serial interface lines.
Data Transfer via Serial Interface
For each byte of data read or written, the MSB is the first bit;
that is, bit 7 of the 8-bit sequence.
Serial Interface Read/Write Examples
Write to one control register
• Start signal
If the TMC22x5yA does not acknowledge the master device
during a write sequence, the SDA remains HIGH so the mas-
ter can generate a stop signal. If the master device does not
acknowledge the TMC22x5yA during a read sequence, the
Decoder interprets this as “end of data.” The SDA remains
HIGH so the master can generate a stop signal.
• Slave Address byte (R/W bit = LOW)
• Block Pointer (00)
• Base Address byte
• Data byte to base address
• Stop signal
Writing data to specific control registers of the TMC22x5yA
requires that the 8-bit address of the control register of inter-
est be written after the slave address has been established.
This control register address is the base address for subse-
quent write operations. The base address autoincrements by
one for each byte of data written after the data byte intended
for the base address. If more bytes are transferred than there
are available addresses, the address will not increment and
remain at its maximum value of 3Fh. Any base address
higher than 3Fh will not produce an ACKnowledge signal.
Write to four consecutive XLUT locations
• Start signal
• Slave Address byte (R/W bit = LOW)
• Block Pointer (01)
• Base Address byte
• Data byte to base address
• Data byte to (base address + 1)
• Data byte to (base address + 2)
• Data byte to (base address + 3)
• Stop signal
Data are read from the control registers of the TMC22x5yA
in a similar manner. Reading requires two data transfer
operations:
Read from one XLUT location
The base address must be written with the R/W\ bit of the
slave address byte LOW to set up a sequential read
operation.
• Start signal
• Slave Address byte (R/W bit = LOW)
SDA
t
BUFF
t
t
t
t
STOSU
DHO
DSU
STASU
t
STAH
t
DAL
SCL
t
BAH
65-22x5y-18
Figure 35. Serial Port Read/Write Timing
REV. 1.0.0 2/4/03
69
TMC22x5yA
PRODUCT SPECIFICATION
• Block Pointer (01)
• Base Address byte
• Stop signal
• Base Address byte
• Stop signal
• Start signal
• Start signal
• Slave Address byte (R/W bit = HIGH)
• Data byte from base address
• Data byte from (base address + 1)
• Data byte from (base address + 2)
• Data byte from (base address + 3)
• Stop signal
• Slave Address byte (R/W bit = HIGH)
• Data byte from base address
• Stop signal
Read from four consecutive control registers
• Start signal
• Slave Address byte (R/W bit = LOW)
• Block Pointer (00)
(MSB)
(LSB)
SDA
SCL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ACK
65-22x5y-19
Figure 36. Serial Interface – Typical Byte Transfer
SDA
A6
A5
A4
A3
A2
SA2
SA1
SA0
ACK
SCL
65-22x5y-19A
Figure 37. Serial Interface – Chip Address
*Note:
To read from the XLUT, the initial read must be a dummy read. This means, for example, to read back XLUT location 0x02, read
back location 0x01, then read back 0x02 and ignore the information read back from the 0x01 location. This only needs to be done
once in a sequence. To read back the entire XLUT, set the pointer to 0xFF and ignore the data read from this register. The pointer
will then auto-increment to 0x00 allowing the next 256 locations read to be valid.
70
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Equivalent Circuits and Threshold Levels
V
V
DD
DD
p
p
Digital
Input
Digital
Output
n
n
27011B
27014B
GND
GND
Figure 38. Equivalent Digital Input Circuit
Figure 39. Equivalent Digital Output
tDIS
SET or RESET
tENA
0.5V
2.0V
0.8V
Three-State
Outputs
0.5V
65-22x5y-76
Figure 40. Threshold Levels for Three-state
REV. 1.0.0 2/4/03
71
TMC22x5yA
PRODUCT SPECIFICATION
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min.
Max.
Unit
Power Supply voltage
Digital Inputs
-0.5
+7.0
V
Applied Voltage
Forced current 3, 4
Digital Outputs
Applied voltage 2
Forced current 3, 4
-0.5
V
+0.5
V
DD
-20.0
+20.0
mA
-0.5
-3.0
V
DD
+0.5
V
+6.0
mA
Short circuit duration (single output in HIGH state to ground)
1 second
infinite
Analog Output Short circuit duration (all outputs to ground)
Temperature
Operating, ambient
junction
-20
110
140
300
220
150
°C
°C
°C
°C
°C
Lead, soldering (10 seconds)
Vapor Phase soldering (1 minute)
Storage
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed
only if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
t
PWHCK
t
PWLCK
PXCK
HSYNC
CVBS
t
HP2
t
SP2
PIXEL 0
PIXEL 1
PIXEL 2
t
SPI
t
HPI
Internal
PCK
t
CLH
LDV
65-22x5y-77
Figure 41. Input Timing Parameters
72
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Operating Conditions
Parameter
Min.
Nom.
Max.
Units
V
V
Power Supply Voltage
4.75
5.0
5.25
V
DD
IH
Input Voltage, Logic HIGH
TTL Compatible Inputs
2.0
V
DD
V
V
Serial Port (SDA and SCL)
Input Voltage, Logic LOW
TTL Compatible Inputs
0.7*V
DD
V
IL
GND
GND
0.8
0.3*V
V
V
Serial Port (SDA and SCL)
Output Current, Logic HIGH
Output Current, Logic LOW
Ambient Temperature, Still Air
DD
I
I
-2.0
4.0
70
mA
mA
°C
OH
OL
T
A
0
Pixel Interface (input)
f
Pixel Rate (CKSEL = 0)
Master Clock Rate = 2X pixel rate (CKSEL = 1)1
10
20
8
18
36
MHz
MHz
ns
CLK
t
t
t
t
t
t
CLOCK pulse width, HIGH
PWHCK
PWLCK
SP
CLOCK pulse width, LOW
13
8
ns
Pixel Data Input Setup Time
ns
Pixel Data Input Hold Time
2
ns
HP
HSYNC, VSYNC, and BUFFER setup time
HSYNC, VSYNC, and BUFFER hold time
5
ns
SP
6
ns
HP
Notes:
1. Tested at f
= 30MHz
CLK
To aid in the understanding of the timing relationship between the PXCK and LDV clock, when the LDV signal is used as the
TMC22x5yA output clock, the following block diagram of the TMC22x5yA output stage is provided.
Data In
PXCK
D
Q
D
Q
G/Y, B/U, and R/V
Output Data
Ck
Ck
2:1
mux
LDV
65-22x5y-78
Figure 42. Functional Block Diagram of the TMC22x5yA G/Y, B/U, and R/V Output Stage
REV. 1.0.0 2/4/03
73
TMC22x5yA
PRODUCT SPECIFICATION
Operating Conditions (continued)
Parameter
Min. Nom. Max. Units
Pixel Interface (output)
t
CLOCK to DHSYNC and DVYSNC, AVOUT, and FID
Time
Propagation
[2:0]
4
15
18
ns
POD
t
t
CLOCK to data, Propagation Time
4
15
15
18
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
POD
POD
HOD
HOD
HOD
ENA
DIS
Int. or Ext. LDV to data, Propagation Time
4
t
t
t
t
t
Clock to DHSYNC and DVSYNC, AVOUT, and FID
Hold Time
2.5
2.5
2.5
[2:0]
Clock to Data, Hold Time
Int. or Ext. LDV to Data, Hold Time
Enable to Low Z on Output Data
Disable to High Z on Output Data
CLOCK to LDV (i/p) signal HIGH
CLOCK to LDV (o/p) signal HIGH
23
23
30
30
0
t
t
9
CLH
CLH
10
14
PXCK
t
t
POD
POD
DHSYNC
G/Y, B/U
RV Data
PIXEL 0
PIXEL 1
PIXEL 2
TMC22x5y
Internal PCK
t
CLH
LDV
65-22x5y-79
Figure 43. Output Timing Parameters
74
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Operating Conditions (continued)
Parameter
Min.
Nom.
Max.
Units
Parallel Microprocessor Interface
t
t
t
t
t
t
CS Pulse Width, LOW
CS Pulse Width, HIGH
Address Setup Time
Address Hold Time
2
3
8
2
8
2
Pixels
Pixels
ns
PWLCS
PWHCS
SA
ns
HA
Data Setup Time (write)
Data Hold Time (write)
ns
SD
ns
HD
Serial Microprocessor Interface
t
t
t
t
t
t
t
SCL Pulse Width , LOW
1.0
0.48
0.48
0.48
0.48
1.0
µs
µs
µs
µs
µs
µs
ns
DAL
SCL Pulse Width, HIGH
DAH
Hold Time for START or Repeated START
Setup Time for START or Repeated START
Setup time for STOP
STAH
STASU
STOSU
BUFF
DSU
Bus Free Time Betweeen a STOP and a START condition
Data Setup Time
80
Electrical Characteristics
Parameter
Conditions
Min.
Typ.
Max.
275
50
Units
mA
mA
µA
I
I
I
I
I
Power Supply Current1
Power Supply Current, Disabled
Input Current, HIGH
V
DD
V
DD
V
DD
V
DD
V
DD
= Max, f
= 27MHz
PXCK
225
DD
DDQ
IH
= Max
= Max, V = V
IN DD
±10
±10
±10
Input Current, LOW
= Max, V = 0V
IN
µA
IL
Hi-Z Output Leakage Current,
Output HIGH
= Max, V = V
IN DD
µA
OZH
I
I
Hi-Z Output Leakage Current,
Output LOW
V
= Max, V = 0V
IN
±10
µA
OZL
DD
Short-Circuit Current
Output Voltage, HIGH
Output Voltage, LOW
-20
2.4
-80
mA
V
OS
V
V
G/Y , etc2., I
= MAX
9-0 OH
G/Y , etc2., I = MAX
OH
OL
0.4
0.4
0.6
10
V
9-0 OL
SDA, I = 3mA
OL
V
SDA, I = 6mA
OL
V
C
C
Digital Input Capacitance
Digital Output Capacitance
4
pF
pF
I
10
O
Notes:
1. Typical I
with V
= NOM and T = NOM, Maximum I
DD
with V = 5.25V and T = 70°C
DD A
DD
DD
A
2. G/Y , B/Y , R/V , DVSYNC, DHSYNC, LDV, AVOUT, FID
[9:0] [9:0] [9:0] [2:0]
REV. 1.0.0 2/4/03
75
TMC22x5yA
PRODUCT SPECIFICATION
Switching Characteristics
Parameter
Conditions
Min.
9
Typ.
Max.
Units
ns
t
t
t
Output Delay, CS to low-Z
DOZ
HOM
DOM
Output Hold Time, CS to high-Z
Output Delay, CS to Data Valid
10
ns
30
40
ns
Note:
Timing reference points are at the 50% level, digital output load <40pF.
System Performance Characteristics
Parameter
RES
Conditions
Min.
Typ.
8
Max.
Units
bits
Video Processing Resolution TMC2205xA
TMC2215xA
10
bits
76
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Programming Examples
Standard: NTSC-M
Mode: Line-Locked
Input Format: 13.5 Composite
Output Format: RGB (0-1023) Sync on Green
Decoder: Adaptive 3-Line Chroma Comb Filter
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
D8
5A
40
00
01
56
F8
00
00
2E
E0
00
A1
D2
43
00
20
23
00
00
28
00
00
00
00
00
07
00
10
2C
00
00
40
1B
00
00
00
90
00
00
12
13
00
00
00
49
00
00
00
F0
00
00
04
01
00
00
24
00
00
00
09
00
00
00
Standard: NTSC
Mode: Line-Locked
Input Format: NTSC Composite
Output Format: D1 Component
Decoder: 3 Line Adaptive Chroma Comb
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
C0
5A
40
00
01
56
F8
00
00
2E
E0
00
A1
D2
43
00
20
23
24
00
28
72
25
00
00
00
07
00
10
00
00
00
40
95
00
00
00
0E
00
00
34
51
00
00
74
49
00
00
80
40
00
00
04
00
00
00
64
00
00
00
08
00
00
00
REV. 1.0.0 2/4/03
77
TMC22x5yA
PRODUCT SPECIFICATION
Programming Examples (continued)
Standard: NTSC
Mode: Line-Locked
Input Format: 13.5 MHz Composite Video
Output Format: YUV
Decoder: Adaptive 3-Line Comb
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
D8
5A
40
00
01
56
F8
00
00
2E
E0
00
A1
D2
43
00
20
23
24
00
28
3C
25
00
00
00
07
00
10
2C
00
00
40
1B
00
00
00
90
00
00
34
13
00
00
00
49
00
00
80
F0
00
00
04
01
00
00
64
00
00
00
08
00
00
00
Standard: PAL
Mode: Line-Locked
Input Format: Composite
Output Format: YUV
Decoder: Adaptive 3-Line Comb
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
DB
60
90
00
01
53
15
00
00
32
13
00
24
CE
54
00
08
23
24
00
00
01
25
00
24
00
07
00
15
00
00
00
40
00
00
00
08
3E
00
00
36
03
00
00
00
49
00
00
C0
00
00
00
04
05
00
00
54
00
00
00
09
00
00
00
78
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Programming Examples (continued)
Standard: PAL
Mode: Line-Locked
Input Format: PAL-YC
Output Format: Y, Cb, Cr (D1 Out)
Decoder:
Register Map: No Comb
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
D3
60
90
00
07
53
15
00
00
44
13
00
00
D2
54
00
20
23
00
00
00
00
00
00
00
00
00
00
0C
00
00
00
40
88
00
00
08
BF
00
00
24
3C
00
00
60
49
00
00
03
40
00
00
00
00
00
00
0B
00
00
00
0A
00
00
00
Standard: NTSC-M
Mode: D1 Mode
Input Format: D1, C YC [Y] multiplexed data w/embedded TRS words
B
R
Output Format: D1 Output
Decoder: 2 Line Chroma comb of C C data
B R
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
C0
5A
00
00
1F
47
00
00
37
35
00
00
E3
D2
00
00
20
23
00
00
00
00
00
00
00
0A
00
00
0C
00
00
00
40
00
00
00
40
00
00
00
34
00
00
00
60
49
00
00
09
40
00
00
04
00
00
00
F8
00
00
00
02
00
00
00
REV. 1.0.0 2/4/03
79
TMC22x5yA
PRODUCT SPECIFICATION
Programming Examples (continued)
Standard: NTSC-M
Mode: D1 Mode
Input Format: D1, C YC [Y] Multiplexed Data w/TRS
B
R
Output Format: YC C , Output DHSync + DVSync
B R
Decoder: Simple Transcoder
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
C0
5A
00
00
1F
47
00
00
37
35
00
00
E3
D2
00
00
20
23
00
00
00
00
00
00
00
0A
00
00
0C
00
00
00
40
00
00
00
40
00
00
00
34
00
00
00
00
49
00
00
09
40
00
00
04
00
00
00
0A
00
00
00
02
00
00
00
Standard: NTSC-M
Mode: D1 Mode
Input Format: YC C
B R
Output Format: D1, C YC [Y] Multiplexed Data with TRS
B
R
Decoder: Simple Transcoder
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
C0
5A
00
00
0F
47
00
00
07
35
00
00
A3
D2
00
00
20
23
00
00
00
00
00
00
00
00
00
00
0C
00
00
00
40
00
00
00
00
00
00
00
34
00
00
00
60
49
00
00
09
40
00
00
04
00
00
00
0A
00
00
00
02
00
00
00
80
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Programming Worksheet
Standard:
Mode:
Input Format:
Output Format:
Decoder:
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
xx
xx
xx
xx
xx
xx
xx
xx
xx
The DRS appears on the
output at the
rate.
Bandsplit Filter
Demodulation Filter
0
-10
-20
-30
-40
0
-10
-20
-30
-40
-50
-60
-70
Bandsplit Filter 2
Demodulator Filter 1
Bandsplit Filter 1
Demodulator Filter 2
-50
-60
-70
Normalized Frequency
Normalized Frequency
Adaptive Notch Filter
Non-Adaptive Notch Filter
0
0
-10
-20
-30
-40
-50
-60
-70
-10
-20
-30
-40
-50
-60
-70
Adaptive Notch
Filter 1
Adaptive Notch
Filter 3
Adaptive Notch
Filter 2
Normalized Frequency
Normalized Frequency
REV. 1.0.0 2/4/03
81
TMC22x5yA
PRODUCT SPECIFICATION
Notes
82
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Mechanical Dimensions – 100 Lead MQFP Package
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Min.
Max.
2. Controlling dimension is millimeters.
A
—
.134
—
—
3.40
—
3. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall be .08mm (.003in.) maximum in excess of
the "B" dimension. Dambar cannot be located on the lower radius
or the foot.
A1
A2
B
.010
.100
.009
.005
.904
.783
.667
.547
.25
.120
.015
.009
.923
.791
.687
.555
2.55
.23
3.05
.38
3, 5
5
4. "L" is the length of terminal for soldering to a substrate.
5. "B" & "C" includes lead finish thickness.
C
.13
.23
D
22.95
19.90
16.95
13.90
23.45
20.10
17.45
14.10
D1
E
E1
e
.0256 BSC
.65 BSC
4
L
.025
.037
.65
.95
N
100
30
100
30
ND
NE
20
20
α
0°
7°
0°
7°
ccc
—
.004
—
.10
D
.20 (.008) Min.
D1
0° Min.
.13 (.30)
.005 (.012)
Datum Plane
R
C
B
e
E1
α
.13 (.005) R Min.
E
L
0.063" Ref (1.60mm)
Lead Detail
See Lead Detail
Base Plane
A
A2
-C-
Lead Coplanarity
ccc
B
Seating Plane
A1
C
REV. 1.0.0 2/4/03
83
TMC22x5yA
PRODUCT SPECIFICATION
Ordering Information
Temperature
Product Number
TMC22051AKHC
TMC22052AKHC
TMC22053AKHC
TMC22151AKHC
TMC22152AKHC
TMC22153AKHC
Range
Decoding
Simple
Resolution
8 bit
Package
Package Marking
22051AKHC
22052AKHC
22053AKHC
22151AKHC
22152AKHC
22153AKHC
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
100-Lead MQFP
100-Lead MQFP
100-Lead MQFP
100-Lead MQFP
100-Lead MQFP
100-Lead MQFP
2-Line Comb
3-Line Comb
Simple
8 bit
8 bit
10 bit
10 bit
10 bit
2-Line Comb
3-Line Comb
2/4/03 0.0m 001
Stock#DS7022x5yA
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