TMC2193KJC_技术文档

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TMC2193

10 Bit Encoder

• Programmable color space matrix

• 8:8:8 video reconstruction

• Four 10 bit D/A’s with independent trim

• Individual power down modes for each D/A

• Multiple output formats

Features

• Multiple input formats

– 24 bit RGB

– 20 bit CCIR601

– 10 bit CCIR656

– 10 bit Digital Composite

• Synchronization modes

– Master

– RGB

– Y P

P

R

B

– Betacam

– S-video

– Composite

– Slave

– Genlock

– CCIR656

– Digital composite output

• Pin-driven and data-driven, window keying

• Closed Caption waveform generation (13.5 MHz only)

• Sin(X)/X compensation ﬁlter

• 5 bit VBI line counter

• 3 bit ﬁeld counter

• Subcarrier modes

– Free-run

– Subcarrier reset

– Genlock

– DRS-lock

• Internal test pattern generation

– 100% Color Bars

• Ancillary Data Control (ANC)

• Pixel rates from 10 MHz to 15 MHz

• Programmable horizontal timing

• Programmable vertical blanking interval (VBI)

• Line-by-line pedestal enable

• Programmable pedestal height from -20 IRE to 20 IRE

• Programmable burst amplitude and phase

• Controlled edge rates for

– Sync

– 75% Color Bars

– Modulated Ramp

Applications

• Broadcast Television

• Nonlinear Video Processing

– Burst

– Active video

Block Diagram

sync/mid

REFDAC

CBYP1

DAC1

Gr/Y

gr/y

Gr/Y

PD[23:0]

Comp

PRE-

PROCESSOR

Bl/Pb

Rd/Pr

SYNC

INSERT

bl/cb

rd/cr

INTERP.

RREF1

CBYP2

DAC2

OVERLAY

MIXER

Bl/Pb

Y

OL[4:0]

KEY

COLOR

SPACE

MATRIX

RREF2

CBYP3

DAC3

U

V

CHROMA

PROCESSOR

Rd/Pr

Ch

INTERP.

COMP2

RREF3

CBYP4

Y

KEY

MIX

DAC4

SYNC

INSERT

CC

CVBS[9:0]

INTERP.

RREF4

DAC

REF.

FVHGEN

MPU

65-6294-01

REV. 1.0 3/26/03

TMC2193

PRODUCT SPECIFICATION

Table of Contents

Interpolation Filters . . . . . . . . . . . . . . . . . . . . . 27

x/Sin(x) Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Output Data Formats. . . . . . . . . . . . . . . . . . . . 27

Digital Composite Output . . . . . . . . . . . . . . . . 28

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Applications. . . . . . . . . . . . . . . . . . . . . . . . .1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . .1

10 Bit Encoder . . . . . . . . . . . . . . . . . . . . . . .1

LIst of Figures . . . . . . . . . . . . . . . . . . . . . . .3

LIst of Tables . . . . . . . . . . . . . . . . . . . . . . . .3

Pin Assignments . . . . . . . . . . . . . . . . . . . . .4

Pin Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . .4

Ancillary Data. . . . . . . . . . . . . . . . . . . . . . . . . . 28

Operating Modes. . . . . . . . . . . . . . . . . . . . . 29

Layering Engine. . . . . . . . . . . . . . . . . . . . . . . . 30

Overlay Mixer . . . . . . . . . . . . . . . . . . . . . . . 30

Hardware Keying . . . . . . . . . . . . . . . . . . . . . . . 31

Data Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Parallel Microprocessor Interface . . . . . . . . . 31

Serial Control Port (R-Bus). . . . . . . . . . . . . . . 33

Functional Description . . . . . . . . . . . . . . . .7

Input Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Gamma Correction . . . . . . . . . . . . . . . . . . . . . . 9

Color Space Matrix . . . . . . . . . . . . . . . . . . . . . . 9

Synchronization Modes . . . . . . . . . . . . . . . . . 12

Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 12

Blanking Control . . . . . . . . . . . . . . . . . . . . . . . 13

Pixel Data Control . . . . . . . . . . . . . . . . . . . . . . 13

Edge Shaping. . . . . . . . . . . . . . . . . . . . . . . . . . 13

Horizontal Programming. . . . . . . . . . . . . . . . . 14

Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chrominance Processor . . . . . . . . . . . . . . . . . 23

Data Transfer via Serial Interface . . . . . . . . 33

Serial Interface Read/Write Examples . . . . 34

Control Register Map . . . . . . . . . . . . . . . .35

Control Register Deﬁnitions . . . . . . . . . .37

Absolute Maximum Ratings. . . . . . . . . . .62

Operating Conditions . . . . . . . . . . . . . . . .62

Electrical Characteristics. . . . . . . . . . . . .64

Switching Characteristics . . . . . . . . . . . .64

System Performance Characteristics . . .65

Subcarrier Programming. . . . . . . . . . . . . . . 23

NTSC Subcarrier . . . . . . . . . . . . . . . . . 23

PAL Subcarrier . . . . . . . . . . . . . . . . . . . 23

PAL-M Subcarrier . . . . . . . . . . . . . . . . . 23

Subcarrier Synchronization. . . . . . . . . . . . . 24

SCH Phase Error Correction. . . . . . . . . . . . 24

Burst Envelope . . . . . . . . . . . . . . . . . . . . . . 25

Color-Difference Low-Pass Filters. . . . . . . . 25

Applications Discussion . . . . . . . . . . . . .65

Layout Considerations . . . . . . . . . . . . . . . . . . 66

Output Low-Pass Filters . . . . . . . . . . . . . . . . . 69

Mechanical Dimensions . . . . . . . . . . . . . .70

100-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . 70

Ordering Information . . . . . . . . . . . . . . . .72

Sync and Pedestal Insertion. . . . . . . . . . . . . . 25

Pedestal Enable . . . . . . . . . . . . . . . . . . . . . 25

Pedestal Height. . . . . . . . . . . . . . . . . . . . . . 26

Sync and Blank Insertion . . . . . . . . . . . . . . 26

Life Support Policy . . . . . . . . . . . . . . . . . .72

Closed Caption Insertion . . . . . . . . . . . . . . . . 26

Line Selection . . . . . . . . . . . . . . . . . . . . . . . 26

Parity Generation . . . . . . . . . . . . . . . . . . . . 26

Operating Sequence . . . . . . . . . . . . . . . . . . 26

2

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

List of Figures

List of Tables

Figure 1. Input Formats . . . . . . . . . . . . . . . . . . . . . .7

Figure 2. 24 bit Input Format . . . . . . . . . . . . . . . . . .7

Figure 3. CCIR656 Input Format . . . . . . . . . . . . . . .8

Figure 4. 10 bit Input Format . . . . . . . . . . . . . . . . . .8

Figure 5. 20 bit 4:2:2 Input Format . . . . . . . . . . . . .8

Figure 6. 20 bit 4:4:4 Input Format . . . . . . . . . . . . .8

Figure 7. Gamma Curves . . . . . . . . . . . . . . . . . . . .9

Figure 8. Propagation Delay through the

Table 1.

Table 2.

CSM Coefﬁcient Range . . . . . . . . . . . . 10

Expected Output Values for the

CSM with YCBCR Inputs . . . . . . . . . . . 11

Expected Output Values for the

CSM with RGB Inputs. . . . . . . . . . . . . . 11

Coefﬁcient sets YCBCR inputs. . . . . . . 11

PDC Edge Control . . . . . . . . . . . . . . . . 13

Horizontal Line Equations. . . . . . . . . . . 14

Horizontal Timing Speciﬁcations. . . . . . 15

Vertical Interval Timing

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Encoder . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 9. Horizontal Timing . . . . . . . . . . . . . . . . . .15

Figure 10. Horizontal Timing – Vertical Blanking . . .15

Figure 11. Horizontal Timing – 1st Half-line. . . . . . .16

Figure 12. Horizontal Timing – 2nd Half-line . . . . . .16

Figure 13. NTSC Vertical Interval . . . . . . . . . . . . . .17

Figure 14. PAL Vertical Interval . . . . . . . . . . . . . . . .19

Figure 15. PAL-M Vertical Interval . . . . . . . . . . . . . .21

Figure 16. Burst Envelope . . . . . . . . . . . . . . . . . . . .25

Figure 17. Gaussian Filter Response . . . . . . . . . . .25

Figure 18. Interpolation Filter. . . . . . . . . . . . . . . . . .27

Figure 19. Interpolation Filter – Passband

Speciﬁcations . . . . . . . . . . . . . . . . . . . . 16

Table 10. Default Horizontal Timing

Parameters . . . . . . . . . . . . . . . . . . . . . . 17

Table 11. NTSC Field/Line Sequence and

Identiﬁcation . . . . . . . . . . . . . . . . . . . . . 18

Table 12. PAL Field/Line Sequence and

Identiﬁcation . . . . . . . . . . . . . . . . . . . . . 20

Table 13. PAL-M Field/Line Sequence and

Identiﬁcation . . . . . . . . . . . . . . . . . . . . . 22

Detail . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 14. Standard Subcarrier Parameters . . . . . 24

Table 15. Line by Line Pedestal Enable . . . . . . . . 25

Table 16. Closed Caption Line Selection . . . . . . . 26

Table 17. D/A Outputs . . . . . . . . . . . . . . . . . . . . . 27

Table 18. Ancillary Data Format. . . . . . . . . . . . . . 28

Table 19. Ancillary Data Control – Phase . . . . . . 29

Table 20. Ancillary Data Control Frequency. . . . . 29

Table 21. Field Identiﬁcation and Subcarrier

Figure 20. X/SIN(X) Filter . . . . . . . . . . . . . . . . . . . .27

Figure 21. Layering Engine . . . . . . . . . . . . . . . . . . .30

Figure 22. Overlay Outputs . . . . . . . . . . . . . . . . . . .31

Figure 23. Data Keying . . . . . . . . . . . . . . . . . . . . . .31

Figure 24. Microprocessor Parallel Port –

Write Timing . . . . . . . . . . . . . . . . . . . . . .32

Figure 25. Microprocessor Parallel Port –

Read Timing . . . . . . . . . . . . . . . . . . . . . .32

Reset Modes . . . . . . . . . . . . . . . . . . . . 29

Figure 26. Serial Port Read/Write Timing . . . . . . . .33

Figure 27. Serial Interface – Typical Byte

Table 22. Layering and Keying Modes . . . . . . . . . 30

Table 23. Overlay Address Map. . . . . . . . . . . . . . 31

Table 24. Parallel Port Control . . . . . . . . . . . . . . . 32

Table 25. Serial Port Addresses. . . . . . . . . . . . . . 33

Table 26. Control Register Map . . . . . . . . . . . . . . 35

Transfer. . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 28. Serial Interface – Chip Address . . . . . . .34

Figure 29. Typical Analog Reconstruction Filter . . .65

Figure 30. Overall Response . . . . . . . . . . . . . . . . . .65

Figure 31. Typical Layout. . . . . . . . . . . . . . . . . . . . .67

Figure 32. ST-163E Layout . . . . . . . . . . . . . . . . . . .68

Figure 33. Pass Band . . . . . . . . . . . . . . . . . . . . . . .69

Figure 34. Stop Band. . . . . . . . . . . . . . . . . . . . . . . .69

Figure 35. 2T Pulse . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 36. Group Delay . . . . . . . . . . . . . . . . . . . . . .69

REV. 1.0 3/26/03

3

TMC2193

PRODUCT SPECIFICATION

Pin Assignments

100

81

1

Function

VDDA

DAC4

CBYP4

AGND

DAC3

CBYP3

VDDA

RREF3

AGND

DAC2

CBYP2

VDDA

RREF2

AGND

DAC1

CBYP1

VDDA

RREF1

REFDAC

KEY

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

Function

PD19

PD18

PD17

PD16

PD15

PD14

PD13

PD12

VDD

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

Function

PD1

81

82

83

84

85

86

87

88

89

Function

FLD2

1

80

2

PD0

FLD1

3

DGND

VDD

FLD0

4

CVBS9

CVBS8

CVBS7

CVBS6

CVBS5

CVBS4

CVBS3

CVBS2

CVBS1

CVBS0

RESET

PXCK

5

VSIN

6

HSIN

7

DCVEN

SER

8

9

CSVSCL

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

DGND

PD11

PD10

PD9

R/WVSDA 90

A1/SA1

A0/SA0

D7

91

92

93

94

95

96

97

98

99

30

51

PD8

D6

PD7

D5

31

50

PD6

D4

VDD

PD5

D3

DGND

VREF

PD4

D2

65-6294-14

PD3

D1

RREF4

PD2

D0

100 AGND

OL4

DGND

VDD

PDC

OL3

OL2

OL1

HSOUT

VSOUT

LINE4

LINE3

LINE2

LINE1

LINE0

OL0

DGND

PD23

PD22

PD21

PD20

Pin Deﬁnitions

Pin Name

Pin Number

Value

Description

CLOCK, SYNC, & CONTROL INPUTS (6 pins)

DCVEN

57

TTL

Digital CVBS Output Enable. When DCVEN is LOW, the

Comp2 output prior to the D/A is routed to D7-0, FLD2-1

providing a digital composite output. When DCVEN is HIGH,

D7-0 and FLD2-1 operate in their normal mode.

HSIN

KEY

56

20

TTL

Horizontal Sync Input. When operating in slave, Genlock, or

DRS-Lock the TMC2193 will start a new horizontal line with

each falling edge of HSIN.

Hard Key selection. When the control register bit HKEN is set

HIGH and the hardware KEY pin is high, the video data

considered to be the foreground. is routed to the COMP2

output. This control signal is data aligned so that the pixel that is

present on the PD port when KEY signal is latched is at the

midpoint of the key transition. When HKEN is LOW, Key is

ignored.

4

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Pin Deﬁnitions (continued)

Pin Name

Pin Number

Value

Description

PXCK

95

TTL

Pixel Clock Input. PXCK is a clock signal that period is twice

the sample rate of the pixel data. The operating range is 20 to

30 MHz. The clock is internally divided by 2 to generate the

internal pixel clock, PCK. PXCK drives the entire TMC2193

except the asynchronous microprocessor interface.

RESET

VSIN

94

55

TTL

Master Chip Reset. When LOW, All outputs are tri-stated and

the internal state machines and control registers are reset. At

rising edge of RESET, all outputs are active, the preset values

will be loaded into the control registers and the internal states

machines start to operate.

Vertical Sync Input. When operating in slave, Genlock, or

DRS-Lock the TMC2193 will start a new vertical field with each

falling edge of VSIN that is coincident with HSIN.

SYNC & CONTROL OUTPUTS (11 pins)

FLD[2:0]

HSOUT

LINE[4:0]

81–83

TTL

Field Identifier. Field Identifier outputs the current field number.

For all video standards the field identifier will cycle through the

eight counts.

74

Horizontal Sync Output. The alignment of HSOUT to the pixel

data port or DCVBS port is controlled by control register

TSOUT.

76–80

Vertical Blanking Interval Line Identifier. LINE identifies the

current line number for the first 31 lines. If the line count is

greater than 31 then LINE is 11111b. The first line with a vertical

serration is considered to be line 0.

PDC

73

TTL

Pixel Data Control.

When PDCDIR = LOW: At a rising edge, The next pixel starts a

controlled ramp of the PD data. At a falling edge, the pixel prior

is the last PD used in the ramp. The rising edge is determined

by the PDCCNT control register, the falling edge of PDC is

determined by the horizontal timing registers.

When PDCDIR = HIGH: PDCIN is used to override the internal

PDC. When HIGH, the internal PDC controls the blank and

unblank window. When LOW, the video remains blanked

regardless of the internal PDC. All edges have the same ramp

control as the internal PDC.

VSOUT

75

TTL

Vertical Sync Output. The alignment of VSOUT to the pixel

data port or DCVBS port is controlled by control register

TSOUT.

DATA INPUTS (39 pins)

CVBS[9:0]

OL[4:0]

84–93

TTL

Composite Data Input

Overlay Control

21–25

PD[23:0]

27–38, 41–52

Component Data Input

ANALOG INTERFACE – Video Out (5 pins)

Ref. DAC

DAC1

19

15

10

5

0.675Vp-p Selectable sync only or midpoint reference D/A

1.35Vp-p Composite or Green D/A

DAC2

1.35Vp-p Luma or Blue D/A

DAC3

1.35Vp-p Chroma or Red D/A

DAC4

2

1.35Vp-p Composite D/A with optional keying

REV. 1.0 3/26/03

5

TMC2193

PRODUCT SPECIFICATION

Pin Deﬁnitions (continued)

Pin Name

Pin Number

Value

Description

ANALOG INTERFACE – Support (9 pins)

C

BYP1

C

BYP2

C

BYP3

C

BYP4

R

REF1

16

11

6

0.1 µF

Reference Bypass Capacitor for DAC1 and Reference DAC.

Connection point for 0.1 µF Capacitor.

Reference Bypass Capacitor for DAC2. Connection point for

0.1 µF Capacitor.

Reference Bypass Capacitor for DAC3. Connection point for

0.1 µF Capacitor.

3

Reference Bypass Capacitor for DAC4. Connection point for

0.1 µF Capacitor.

18

1210 Ohm Current Setting Resistor. Connection point for external current

setting resistor for DAC1. The resistor is connected between

R

and GND. Output video levels are inversely proportional

REF1

to the value of R

.

REF1

R

13

8

1210 Ohm Current Setting Resistor. Connection point for external current

REF2

REF3

REF4

REF

setting resistor for DAC2. The resistor is connected between

R

and GND. Output video levels are inversely proportional

REF2

to the value of R

.

REF2

1210 Ohm Current Setting Resistor. Connection point for external current

setting resistor for DAC3. The resistor is connected between

R

and GND. Output video levels are inversely proportional

REF3

to the value of R

.

REF3

99

98

1210 Ohm Current Setting Resistor. Connection point for external current

setting resistor for DAC4. The resistor is connected between

R

and GND. Output video levels are inversely proportional

REF4

to the value of R

.

REF4

V

1.235 V

TTL

Voltage Reference Input. External voltage reference input,

internal voltage reference output, nominally 1.235V.

MPU INTERFACE (13 pins)

A[1:0]/S [1:0]

A

61, 62

When SER (HIGH), OLUT/control/pointer address.

When SER (LOW), SA[1:0] of serial chip address SA[6:0].

CS/SCL

59

TTL/R-BUS When SER (HIGH), microprocessor port clock.

When SER (LOW), serial bus clock.

D[7:0]

63–70

TTL

Bi-directional Data Bus.

RW/SDA

60

TTL/R-BUS When SER (HIGH), read/write control.

When SER (LOW), serial bus bi-directional data.

SER

58

TTL

Microprocessor Select. When LOW, the serial interface is

enabled. When HIGH, the parallel interface is enabled.

POWER & GROUND (17 pins)

A

4, 9, 14, 100

26, 40, 53, 71, 97

39, 54, 72, 96

1, 7, 12, 17

0.0V

Analog ground

GND

D

Digital ground

GND

DD

V

+5.0V

Digital positive power supply

Analog positive power supply

DDA

6

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Demuxing of multiplexed data streams depends on which

synchronization mode the encoder is operating in. For slave

and genlock modes the falling edge of HSIN must be LOW

Functional Description

Input Formats

Control Registers for this section

prior to the C data in order to demux the data correctly. For

B

master mode synchronization the falling edge of HSOUT

must be LOW prior to the Y data in order to demux the data

correctly. Finally, in 656 mode the demuxing of the data

stream is determined by the TRS codes, the ﬁrst sample after

the TRS is considered a C sample of the C Y C Y

B B R I

packet.

Address

0x05

Bit(s)

7

Name

D1OFF

INMODE

TSOUT

0x05

6-4

0

0x06

The control register D1OFF controls the formatting of the

incoming luminance data at the pixel data port. When

D1OFF is HIGH a blanking level of 64 is subtracted from

10

the luminance and when D1OFF is LOW the incoming the

pixel data is passed through. The inversion of the MSB’s on

The TMC2193 supports both RGB and YC C component

B R

sources on the pixel data port. For RGB sources the

TMC2193 will accept a 24 bit RGB source with a sample

rate of 4:4:4. YC C input sources are supported in 10 bit

B R

4:2:2, 20 bit 4:2:2, 20 bit 4:4:4, and 24 bit 4:4:4. In the 4:2:2

cases the color difference components are linearly interpo-

lated to 4:4:4 internally.

the C and C components is controlled by the INMODE

B

R

control register.

INMODE

x00

23

7

16 15 14

PD

9

8

0

7

0

C^B/BLUE

YC^BCR

0

7

CR/RED

Y/GREEN

101

9

0

110

9

C^BCR

CBCR

1

0

9

Y

2

111

9

65-6294-02

Figure 1. Input Formats

1. INMODE = 000 or 100, PD[7:0] = Y/G, PD[23:16] = C /B, PD[15:8] = C /R

B

R

n = (SY+BR+BU+CBP+AV)*2

0

128

x = (SY+BR+BU+CBP)*2

PXCK

t

H

t

S

(Y/G)

x+1

(Y/G)

x+2

(Y/G)

PD[7:0]

n-1

n

x

0

PD[23:16]

(C /B)

x+2

n

(C /B)

0

B

n-1

x

x+1

B

(C /R)

PD[15:8]

HSIN

(C /R)

R

(C /R)

n

R

(C /R)

x+2

0

n-1

R

x

x+1

R

t

SP

t

DO

t

DO

HSOUT

(TSOUT = 1)

65-6294-03

Figure 2. 24 Bit Input Format

2. INMODE = 101, PD[23:14] = YC C running at 27MHz.

B R

The PD port is clocked at twice the pixel rate, with the data

data value, after the SAV preamble, is treated as a C data

B

organized as C Y C Y, with the cosited Y's following the

point in the multiplexed C , Y, C Y , D1 data stream.

B R

B

R

C 's. In its CCIR-656 time base mode, the demuxed C , Y,

and C data is synchronized to the SAV preamble. The ﬁrst

R

B

Note: Figure 3, pixel numbering, reﬂects the SMPTE-125M

pixel numbering.

REV. 1.0 3/26/03

7

TMC2193

PRODUCT SPECIFICATION

128

(SY+BR+BU+CBP)*2

0

PXCK

t

S

t

H

C

Y

736

C

B718

Y

C

R718

Y

719

FF

00

FV

1

B736

FF

00

FV

C

B0

Y

C

R0

Y

C

B2

Y

2

718

PD[23:14]

0

1

0

t

DO

EAV

SAV

t

HS

HSOUT

(TSOUT = 1)

65-6294-04

Figure 3. CCIR656 Input Format

x = (SY+BR+BU+CBP)*2

n = (SY+BR+BU+CBP+AV)*2

0

128

PXCK

t

S

t

H

C

Bn

Y

C

Rn

Y

n+1

C

B0

Y

0

C

Bx

Y

x

C

Rx

Y

x+1

C

Bx+2

Y

x+2

n

PD[23:14]

HSIN

t

HP

SP

t

DO

HSOUT

(TSOUT = 1)

65-6294-05

Figure 4. 10 bit Input Format

3. INMODE = 111, PD[9:0] = Y, PD[23:14] = C /C

B

R

n = (SY+BR+BU+CBP+AV)*2

0

128

x = (SY+BR+BU+CBP)*2

PXCK

t

H

t

S

Y

n+1

Y

x

Y

x+1

Y

x+2

n

Y

0

Y

1

PD[9:0]

C

Bx

C

PD[23:14]

HSIN

C

Rn

C

Rx

R0

B0

Bx+2

Bn

t

SP

t

DO

HSOUT

(TSOUT = 1)

t

HS

65-6294-06

Figure 5. 20 bit 4:2:2 Input Format

4. INMODE = 110, PD[9:0] = Y at PCK, PD[23:14] = C -C at PXCK

B

R

n = (SY+BR+BU+CBP+AV)*2

0

128

x = (SY+BR+BU+CBP)*2

PXCK

t

H

t

S

Y

0

Y

x

Y

n

Y

n+1

PD[9:0]

t

H

t

S

C_B

0

C_B

C_R

x

PD[23:14]

HSIN

C_B

C_R

C_B

C_Rn+1

C_R

n

n+1

0

x

n

t

SP

t

DO

HSOUT

(TSOUT = 1)

65-6294-07

Figure 6. 20 bit 4:4:4 Input Format

8

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Gamma Correction

Color Space Matrix

Control Registers for this section

Address

0x04

Bit(s)

Name

Address

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

Bit(s)

7-0

7-4

3-0

7-4

2-0

7-4

2-0

7-4

3-0

7-4

3-0

2

Name

7

GAMENG

GAMENC

GAMSELG

GAMSELC

MCF1L

MCF2L

MCF3L

MCF4L

MCF5L

MCF6L

MCF7L

MCF8L

MCF9L

MCF10L

MCF1M

MCF2M

MCF3M

MCF4M

MCF5M

MCF6M

MCF7M

MCF8M

MCF9M

MCF10M

NMEH

0x04

6

5

4

0x04

Inherent in all CRT displays is a non-linearity between the

voltage applied to the electron guns and the CRT phosphor

brightness. Traditionally this non-linearity, gamma, is com-

pensated at the camera. However, many sources today are

mixed in the digital domain and do not contain any gamma

correction.

For this reason the TMC2193 contains optional gamma cor-

rection process. The TMC2193 contains two independent

gamma circuits, one for the Green data path and the other for

the Blue and Red data path. Each gamma processor has two

(2) gamma compensation curves, one for NTSC and one for

PAL, that can be applied to the incoming video data.

The formulas for the gamma curves are:

PAL:

NTSC: Y = 4.5 * X

Y = 1.099 * X^1/2.22– 0.099

Y = X^1/2.8

for 0 ≤ X ≤ 255

for 0 ≤ X ≤ 6

for 7 ≤ X ≤ 255

1024

896

768

640

512

384

256

128

0

PAL Gamma Curve

1-0

CSMFMT

The color space matrix (CSM) has four modes of operation,

which are controlled by CSMFMT. The CSMFMT bits con-

ﬁgures the color space matrix to produce the desired outputs

from the input source. The inputs for the CSM can be either

RGB or YC C . In all four modes YUV for the composite

B R

generation will always be one set of component outputs of

the CSM. The other set of components outputs can be either

NTSC Gamma Curve

RGB or YP P .

B R

0

32

64

96

128 160 192 224 256

RGB Inputs (0 to 255)

•

CSMFMT = 00 , YC C input source with YUV and

B R

YP P outputs.

B R

Figure 7. Gamma Curves

Matrix conﬁguration:

Y

U

V

Y

= MCF1 * Y

in

composite

= MCF4 * C

= MCF6 * C

B

R

= MCF8 * Y

in

component

P

= MCF9 * C

B

= MCF10 * C

R

REV. 1.0 3/26/03

9

TMC2193

PRODUCT SPECIFICATION

•

CSMFMT = 01 , YC C input source with YUV and

B R

RGB outputs.

Y

= MCF8 * Y

= MCF9 * U

composite

P

B

R

P

= MCF10 * V

Matrix conﬁguration:

Y

U

V

G

= MCF1 * Y

in

composite

•

CSMFMT = 11 , RGB input source withYUV and RGB

outputs.

= MCF4 * C

= MCF6 * C

B

R

Matrix conﬁguration:

= MCF8 * (MCF1 * Y + MCF2 * C

in

+ MCF3 * C )

B

Y

= MCF1 * G + MCF2 * B +

in in

composite

R

MCF3 * R

in

B

R

= MCF9 * (MCF1 * Y + MCF5 * C )

in

B

U

V

G

B

R

= MCF4 * B + MCF5 * Y

in

composite

= MCF10 * (MCF1 * Y

in

+

= MCF6 * R + MCF7 * Y

in

composite

MCF7 * C )

R

= MCF8 * G

in

•

CSMFMT = 10 , RGB input source with YUV and

YP P outputs.

B R

= MCF9 * B

= MCF10 * R

in

Matrix conﬁguration:

The color space matrix consists of 10 multipliers with inde-

pendently adjustable coefﬁcients, and a resolution of

0.00049 (1/2048). The amount of gain varies among coefﬁ-

cients, Table 1 summarizes the gain for each coefﬁcient.

Y

= MCF1 * G + MCF2 * B +

in in

composite

MCF3 * R

in

U

V

= MCF4 * B + MCF5 * Y

in

composite

= MCF6 * R + MCF7 * Y

in

composite

Table 1. CSM Coefﬁcient Range

Coefﬁcient

MCF1

Gain Range

0 to 2

Comment

MCF2

-1 to 1

Must be loaded in 2’s comp format.

11 bit coefficient.

MCF3

-1 to 1

MCF4

0 to 1

MCF5

-2 to 2

Negative values are enabled when CSMFMT is 1x, only the 12 LSB’s

are required to be loaded into the control registers. Must be loaded in 2’s

comp format.

MCF6

MCF7

0 to 1

11 bit coefficient.

-2 to 2

Negative values are enabled when CSMFMT is 1x, only the 12 LSB’s

are required to be loaded into the control registers. Must be loaded in 2’s

comp format.

MCF8

MCF9

MCF10

0 to 2

To aid in the programming of the color space matrix Table 2

and Table 3 provide a set of default input and output values

for 100% color bars. The component values given will be

after the preprocessing block and prior to the sync and ped-

estal insertion. The blank, pedestal, and sync values are

given as a reference. Table 4 and Table 5 give the default

coefﬁcients values for the CSM in all modes and standard

video formats.

10

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Table 2. Expected Output Values for the CSM withYC C Inputs

B

R

Inputs

5:2 Outputs

7:3 Outputs

Color

White

Yellow

Cyan

Y

C

Y

U

V

Y

U

V

Y

P

R

G

B

R

B

R

B

876

0

536

0

568

0

568

0

568 568 568

776 -448 73

614 151 448 376

514 -297 -375 315 -156 -278 340 -165 -294 340 -189 -238 568

475 -235 54

503 -249 57

514 -284 46

568

0

568

0

79 -332 407

84 -351 407

96 -284 568 568

Green

Magenta

Red

0

362 297 375 222 156 278 240 165 294 240 189 238

262 -151 448 160 -79 332 173 -84 351 173 -96 284

0

568 568

0

568

0

568

0

Blue

100 448 -73

61

0

235 -54

66

0

249 -57

66

0

284 -46

Black

Blank

Pedestal

Sync

0

64

240

44

8

256

0

256

0

256 256 256

12

Table 3. Expected Output Values for the CSM with RGB Inputs

Inputs

B

5:2 Outputs

7:3 Outputs

Color

White

Yellow

Cyan

G

R

Y

U

V

Y

U

V

Y

P

B

P

G

B

R

1020 1020 1020 536

1020

1020 1020

0

568

0

568

0

568 568 568

0

1020 475 -235 54

503 -249 57

79 -332 407 84 -351 407

315 -156 -278 340 -165 -294 340 -189 -238 568

514 -284 46

568

0

568

0

376

96 -284 568 568

Green

Magenta

Red

1020

0

1020 1020 222 156 278 240 165 294 240 189 238

0

568 568

0

1020

0

1020 160 -79 332 173 -84 351 173 -96 284

0

568

0

568

0

Blue

0

61

0

235 -54

66

0

249 -57

66

0

284 -46

Black

0

Table 4. Coefﬁcient setsYC C inputs

Table 5. Coefﬁcient setsYC C inputs

B R

B

R

YP P outputs

RGB Outputs

NTSC NTSC

-M PAL-I

54C 4E5 530

E34 E57 E3D

YP P outputs

RGB Outputs

NTSC NTSC

-M PAL-I -EIA -M PAL-I

B R

NTSC NTSC

-EIA

-M PAL-I -EIA

-EIA

2AC

085

15C

240

MCF1

MCF2

MCF3

MCF4

MCF5

MCF6

MCF7

MCF8

MCF9

54C 4E5

530

000

MCF1

MCF2

MCF3

MCF4

MCF5

MCF6

MCF7

MCF8

MCF9

278

07B

142

215

29E 2AC

278

07B

142

215

29E

082

155

234

000

48b

000

433

000

082

155

234

085

15C

240

000 C4E C96 C62

473

000

48B

433

473

92D 87B 8FC

668 5EC 646

C09 C09 C09 C09 C09 C09

668 5EC 646

000 000 000

54C 54C 54C

404

8F2

800

3B7 3EF

404

8F2

3B7 3EF

742

800

6B5 71C

8F2

8A8

8F2

800

920

679

8F2

474

8A8

800

48D 48D

514

8F2 9AB

6D8

MCF10 514

MCF10 654

REV. 1.0 3/26/03

11

TMC2193

PRODUCT SPECIFICATION

CCIR656

Synchronization Modes

The TMC2193 derives all synchronization from the embed-

ded TRS (timing reference signals) information. Blanking of

selected lines is determined by the v bit of the TRS. However

the control registers VBIENx can override and blank the

active video portion of VBI lines regardless of the state of the

v-bit.

Control Registers for this section

Address

0x06

Bit(s)

5-3

1

Name

MODE

TOUT

TSOUT

0x06

0

Genlock

The TMC2193 is driven by the input synchronization pins

HSIN and VSIN. When the falling edge of HSIN and VSIN

occurs at the same rising edge of PXCK the TMC2193 will

start a new ﬁeld.VSIN can be either a traditional pulse or the

MPEG style ﬁeld toggle. In both cases the TMC2193 will

ﬂywheel through ﬁelds 2, 4, 6, and 8 synchronizing only to

ﬁelds 1, 3, 5, and 7. The TMC2193 collects GRS data and

resets its subcarrier phase and frequency to the data embed-

ded in the GRS stream. The GRS detection occurs only on

the CBVS port.

The TMC2193 offers a variety of synchronization modes;

these are master, slave, genlock, 656 mode, and DRS-Lock.

In master mode, the TMC2193 generates its own timing and

the synchronization is supplied externally by HSOUT and

VSOUT signals. In slave and genlock modes the TMC2193

derives its timing from the input pins HSIN, VSIN. In 656

mode the timing is driven by the synchronization codes

embedded into the data stream.

Master

The TMC2193 drives the output pins HSOUT and VSOUT

to synchronize the incoming video. A new color frame starts

at the rising edge of RESET. The encoder always starts at the

1^stvertical serration in ﬁeld 8 and will freerun the ﬁeld and

line sequence. The control register bit SRESET can be used

to synchronize the start of the ﬁeld and line sequence in mas-

ter mode by resetting the FVHGEN state machine. Output

synchronization signal VSOUT can operate in a traditional

sync mode or in a MPEG style ﬁeld toggle mode.

DRS

The TMC2193 is driven by the input synchronization pins

HSIN and VSIN. When the falling edge of HSIN and VSIN

occurs at the same rising edge of PXCK the TMC2193 will

start a new ﬁeld.VSIN can be either a traditional pulse or the

MPEG style ﬁeld toggle. In both cases the TMC2193 will

ﬂywheel through ﬁelds 2, 4, 6, and 8 synchronizing only to

ﬁelds 1, 3, 5, and 7. Subcarrier phase adjustment is deter-

mined by the DRS data. The DRS detection can occur on

either the CBVS port or the pixel data port.

Slave

The TMC2193 is driven by the input synchronization pins

HSIN and VSIN. When the falling edge of HSIN and VSIN

occurs at the same rising edge of PXCK the TMC2193 will

start a new ﬁeld.VSIN can be either a traditional pulse or the

MPEG style ﬁeld toggle. In both cases the TMC2193 will

ﬂywheel through ﬁelds 2, 4, 6, and 8 synchronizing only to

ﬁelds 1, 3, 5, and 7.

Propagation Delay

The propagation delay from the pixel data (PD) input to the

D/A output is 64 PXCK’s. Figure 8 shows the propagation

delay for both master and slave synchronization modes. For

CCIR656 data streams, pixel 736 (pixel 0 in Figure 8) is the

midpoint of sync and is 32 PXCK’s (24 PXCK’s in PAL)

after the EAV TRS.

n = (SY+BR+BU+CBP+AV)*2

0

128

63

65

PXCK

C

Bn

Y

C

Rn

Y

n+1

C

B0

Y

0

n

PD[23:14]

HSIN

t

DO

HSOUT

(TSOUT = 1)

DACx

(ANALOG)

t

DCVBS

DO

(D[7:0],FLD[2:1])

COMP

1

0

65-6294-09

Midpoint of the

Falling Edge of Sync

Figure 8. Propagation Delay through the Encoder

12

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Blanking Control

Pixel Data Control

Control Registers for this section

The pixel data control has two modes of operation, as an

input or as an output. The mode of operation is determined

by the PDCDIR control register. When PDC is an input the

internally generated PDC is ANDed with the PDC pin. This

allows the user to blank any active video regions. When PDC

is an output, the internally generated PDC is the output for

the PDC pin.

Address

0x04

Bit(s)

1-0

2

Name

PDRM

0x06

PDCDIR

VBIENF1

VBIENF2

PDCCNT

0x18

4-0

7-0

0x19

The internal PDC control will toggle to a logic HIGH at the

pixel speciﬁed by PDCNT and toggle to a logic LOW four

pixels prior to the end of the active video region. The starting

point and ending point of the active video region (VA) are

determined by the control registers 10h to 1Fh. When PDC is

used as an input, the sloped edge of the active video region

will occur on the next four pixels following the toggle point.

0x1F

The content of VBIENFx[4:0] selects the ﬁrst line to contain

an active video region in each ﬁeld, all subsequent lines for

the remainder of the ﬁeld are active. To blank an entire ﬁeld,

the user zeroes the VBIENFx[4:0] control register. In

CCIR656 slave mode, the user can selectively blank any

enabled line by setting its TRS V bit HIGH. For 525-line

systems, NTSC line numbering is employed, with the ﬁrst

vertical serration starting on line 4. PAL line numbering is

used with 625-line systems, with each ﬁeld's line 1 being the

start of the ﬁrst vertical serration.

Edge Shaping

The TMC2193 has three modes of sloped edges on the active

video region and are controlled by PDRM control register.

Any line(s) enabled by the closed caption control are auto-

matically unblanked for the closed caption waveform, irre-

spective of the corresponding values of VBIENF.

Table 6. PDC Edge Control

PDRM[1:0]

Slope type at PDC (HIGH)

Slope type at PDC (LOW)

00

The following four pixels have the weighting of The following four pixels have the weighting of

1/8, 1/2, 7/8 and 1 for NTSC and 1/8, 3/8, 5/8, 1, 7/8, 1/2, and 1/8 for NTSC and 7/8, 5/8, 3/8,

and 7/8 for PAL.

and 1/8 for PAL.

01

1x

The fifth pixel is sampled and scaled 1/8, 1/2,

7/8 and 1 over the next four pixels for NTSC

and 1/8, 3/8, 5/8, and 7/8 over the next four

pixels for PAL.

The fifth pixel is sampled and scaled 1, 7/8,

1/2 and 1/8 over the next four pixels for NTSC

and 7/8, 5/8, 3/8, and 1/8 over the next four

pixels for PAL.

Slope is off, edge control is dictated by the PD Slope is off, edge control is dictated by the PD

stream from active video start stream to active video end

REV. 1.0 3/26/03

13

TMC2193

PRODUCT SPECIFICATION

Horizontal interval timing is fully programmable and is

established by loading the timing registers with the duration

of each horizontal element. The duration is expressed in

PCK clock cycles. In this way, any pixel clock rate between

10 MHz and 15 MHz can be accommodated, and any desired

standard or non-standard horizontal video timing may be

produced.

Horizontal Programming

Control registers for this section

Address

0x06

0x19

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

Bit(s)

7-6

7

Name

FORMAT

SHORT

T512

HALFEN

SY

6

Horizontal timing parameters can be calculated as follows:

5

t = N x ( PCK period )

7-0

7-6

5-4

3-2

1-0

= N x ( 2 x PXCK period )

BR

where N is the value loaded into the appropriate timing

register, and PCK is the pixel clock period.

BU

CBP

XBP

VA

When programming horizontal timing, subtract 5 PCK

periods from the calculated values of CBP and add 5 PCK

periods to the calculated value for VA. The control register

HALFEN enables the 1^sthalf line (UBV) on line 283 for

NTSC, PAL-M and line 23 for all other PAL standards when

it is LOW.

VC

VB

EL

EH

SL

SH

FP

XBP (MSB’s)

VA (MSB’s)

VB (MSB’s)

VC (MSB’s)

Table 7. Horizontal Line Equations

Line Type

EE

Line ID

00

Line Length Equals

EL + EH + EL + EH

SE

02

SL + SH + EL + EH

SS

03

SL + SH + SL + SH

ES

01

EL + EH + SL + SH

EB

10

EL + EH + EL + EH

UBB, -BB

UVV, -VV

UVE, -VE

UBV

0D, 05

0F, 07

0C, 04

0E

SY + BR + BU + CBP + VA + FP

SY + BR + BU + CBP + VC + FP + EL + EH

SY + BR + BU + XBP + VB + FP

14

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

SY

BR

BU

CBP

VA

FP

65-6294-10

Figure 9. Horizontal Timing

ming, any pixel rate between 10 and 15 Mpps can be accom-

modated, and any desired standard or non-standard vertical

video timing may be produced.

Table 8. Horizontal Timing Speciﬁcations

NTSC-M

PAL-I

PAL-M

Parameter

(µs)

Like horizontal timing parameters, vertical timing parame-

ters are calculated as follows:

FP

SY

BR

BU

CBP

VA

H

1.5

4.7

1.65

4.7

1.9

4.95

t = N x ( PCK period )

0.6

0.9

= N x ( 2 x PXCK period )

2.5

2.25

2.55

51.95

64.0

2.25

where N is the value loaded into the appropriate timing reg-

ister, and PCK is the pixel clock period.

1.6

1.8

52.6556

63.5556

51.692

63.492

The vertical interval comprises several different line types

based upon H, the Horizontal line time.

H = (2 x SL) + (2 x SH) [Vertical sync pulses]

= (2 x EL) + (2 x EH) [Equalization pulses]

Vertical interval timing is also fully programmable, and is

established by loading the timing registers with the dura-

tion’s of each vertical timing element, the duration expressed

in PCK clock cycles. In this way as with horizontal program-

H

H/2

EL

EH

SL

SH

65-6294-11

Figure 10. Horizontal Timing – Vertical Blanking

The VB and VC control registers are added to produce the

half-lines needed in the vertical interval at the beginning and

end of some ﬁelds. These must properly mate with compo-

nents of the normal lines.

REV. 1.0 3/26/03

15

TMC2193

PRODUCT SPECIFICATION

H/2

SY

BR

BU

XBP

VB

FP

65-6924-12

Figure 11. Horizontal Timing – 1st Half-line

H/2

EL

SY

BU

CBP

VC

FP

EH

BR

65-6294-13

Figure 12. Horizontal Timing – 2nd Half-line

Table 9. Vertical Interval Timing Speciﬁcations

NTSC-M

PAL-I

PAL-M

Parameter

(µs)

H

63.5556

29.4778

2.3

64

29.65

2.35

4.7

63.492

29.45

2.3

EH

EL

SH

SL

4.7

4.65

27.1

27.3

27.1

16

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Table 10. Default Horizontal Timing Parameters

Timing Register (hex)

Field Horizontal

Pixel

Rate

(Mpps) (MHz)

PXCK

Freq.

SY

20

3A

40

43

45

40

46

3E

44

47

BR BU CBP XBP VA

VC

26

05

1E

30

2B

0E

31

FE

12

22

VB

27

77

98

B5

B7

93

BF

8B

99

AC

EL EH²SL²SH

FP Note CBL

Rate

(Hz)

Freq.

(KHz)

Standard

21

07

08

09

0D

0C

0D

0B

0C

0D

22

1F

22

24

21

1E

22

1C

1E

20

23

0F

11

12

21

22

21

13

15

24

23

44

54

6D

4D

73

26

4C

25

8B

CB

F7

03

BE

11

86

Bf

28

1C

1F

21

23

20

23

1D

1F

21

29

6A

8E

A6

B5

90

BD

70

8E

A5

2A

4C

6D

84

93

70

9A

53

6E

84

2B

3A

40

43

45

40

47

3A

3F

42

2C

12

14

15

19

16

19

18

1A

1B

2D

65

75

65

75

61

65

2F

52

59

5F

61

59

62

52

57

5D

NTSC sqr. pixel

NTSC CCIR-601

59.94 15.734266

50.00 15.625000

60.00 15.750000

60.00 15,750000

12.27

13.50

14.32

14.75

13.50

15.00

12.50

13.50

14.30

24.54

27.00

28.64

29.50

27.00

30.00

25.01

27.00

28.60

NTSC 4x F

SC

PAL sqr. pixel

PAL CCIR-601

PAL 15 Mpps

PAL-M sqr.pixel

PAL-M CCIR-601

PAL-M 4x F

E8

SC

Notes:

1. XBP, VA, VC, and VB are 10 bit values. The 2 MSBs for these four variables are in Timing Register 2D.

2. EH and SL are 9 bit values. A most significant "1" is forced by the TMC2193 since EH and SL must range from 256 to 511.

EH and SL may be extended to 767. Only the eight LSBs are stored in Timing Registers 29 and 2A.

3. Every calculated timing parameter has a minimum value of 5 except EH and SL which have minimum values of 256.

Vertical Timing

The vertical timing is controlled by the FORMAT control

register, which dictates the ﬁeld and line sequence.

524

525

FIELDS 1 AND 3

21

22

10

•••

19

20

1

2

3

4

5

6

7

8

9

UVV

EE

SS

EE

UBB

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

263

FIELDS 2 AND 4

283

284

285

262

273

•••

282

264

EE

265

EE

266

267

268

269

SE

270

EE

271

EE

272

EB

UVV

UVE

ES

SS

UBB

UBV

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

65-6294-15

Figure 13. NTSC Vertical Interval

REV. 1.0 3/26/03

17

TMC2193

PRODUCT SPECIFICATION

Table 11. NTSC Field/Line Sequence and Identiﬁcation

Field 1

Field 2

Field 3

Field 4

FIELD ID = x00

FIELD ID = x01

FIELD ID = x10

FIELD ID = x11

Line

ID

LTYPE

Line

ID

ES

LTYPE

Line

ID

LTYPE

Line

266

267

268

269

270

271

272

273

…

ID

ES

LTYPE

01

4

5

SS

03

00

0D

0F

0C

00

266

267

268

269

270

271

272

273

…

01

03

02

00

10

0D

0E

0F

00

4

5

SS

03

00

0D

0F

0C

00

SS

03

6

SS

6

SS

03

7

EE

SE

7

EE

SE

02

8

EE

8

EE

00

9

EE

9

EE

00

10

…

19

20

21

22

…

262

263

264

265

UBB

UVV

UVE

EE

EB

10

…

19

20

21

22

…

262

263

264

265

UBB

UVV

UVE

EE

EB

10

UBB

UBV

UVV

EE

UBB

UBV

UVV

EE

0D

0E

0F

0F.

0F

00

282

283

284

…

282

283

284

…

524

525

1

524

525

1

EE

2

EE

2

EE

00

3

EE

3

EE

00

EE

SE

SS

ES

EB

Equalization pulse

Half-line vertical sync pulse, half-line equalization pulse

Vertical sync pulse

Half-line equalization pulse, half-line vertical sync pulse

Equalization broad pulse

UBB

UVV

UVE

UBV

Black burst

Active video

Half-line video, half-line equalization pulse

half-line black, half-line video

18

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

622

623

-VE

FIELDS 1 AND 5

23

24

25

26

•••

624

EE

625

EE

1

2

3

4

5

6

7

22

UVV

SS

SE

EE

-BB

UBB

UBB UBV

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

309

310

-VV

FIELDS 2 AND 6

336

337

•••

311

312

EE

313

314

SS

315

SS

316

EE

317

EE

318

EB

319

320

334

335

UVV

EE

ES

UBB

UBB UBB

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

622

-VV

623

-VE

FIELDS 3 AND 7

23

24

25

26

•••

624

EE

625

EE

1

2

3

4

5

6

7

22

SS

SE

EE

UBB

UBB UBV

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

309

310

FIELDS 4 AND 8

336

337

•••

311

EE

312

EE

313

ES

314

SS

315

SS

316

EE

317

EE

318

EB

319

-BB

320

334

335

UVV

UBB

UBB UBB

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

65-6294-16

Figure 14. PAL Vertical Interval

REV. 1.0 3/26/03

19

TMC2193

PRODUCT SPECIFICATION

Table 12. PAL Field/Line Sequence and Identiﬁcation

Field 1 & 5

Field 2 & 6

Field 3 & 7

Field 4 & 8

FIELD ID = 000, 100

FIELD ID = 001, 111

FIELD ID = 010, 110

FIELD ID = 011, 111

Line

ID

LTYPE

Line

ID

LTYPE

Line

ID

LTYPE

Line

313

314

315

316

317

318

319

320

…

ID

ES

LTYPE

01

1

2

SS

03

02

00

05

0D

0E

0F

07

00

313

314

315

316

317

318

319

320

…

ES

01

03

00

10

0D

0F

07

04

00

1

2

SS

03

02

00

0D

0E

0F

00

SS

03

3

SE

SS

3

SE

SS

03

4

EE

4

EE

00

5

EE

5

EE

00

6

-BB

UBB

UBV

UVV

-VV

EE

EB

6

UBB

UBV

UVV

EE

EB

10

7

UBB

UVV

-VV

-VE

EE

7

-BB

UBB

UVV

-VE

EE

05

…

22

23

24

25

26

…

309

310

311

312

…

22

23

24

25

26

…

309

310

311

312

0D

0F.

0F

04

334

335

336

337

…

334

335

336

337

…

622

623

624

625

622

623

624

625

00

EE

00

EE

SE

SS

ES

EB

Equalization pulse

Half-line vertical sync pulse, half-line equalization pulse

Vertical sync pulse

Half-line equalization pulse, half-line vertical sync pulse

Equalization broad pulse

UBB

-BB

UVV

-VV

UVE

-VE

UBV

Black burst

Black burst with color burst suppressed

Active video

Active video with color burst suppressed

Half-line video, half-line equalization pulse

Half-line video, half-line equalization pulse, color burst suppressed.

half-line black, half-line video

20

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

521

522

FIELDS 1 AND 5

18

523

EE

524

EE

525

EE

1

2

3

4

5

6

7

8

9

•••

17

UVV

SS

EE

-BB

UBB

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

280

281

260

FIELDS 2 AND 6

259

261

EE

262

EE

263

264

265

SS

266

SE

267

EE

268

EE

269

EB

270

-BB

271

•••

279

UVV

-VE

ES

SS

UBB

UBV

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

521

522

-VV

FIELDS 3 AND 7

18

523

EE

524

EE

525

EE

1

2

3

4

5

6

7

8

9

•••

17

UVV

SS

EE

-BB

UBB UBB

UBB

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

280

281

260

-VE

FIELDS 4 AND 8

258

259

261

EE

262

EE

263

264

265

SS

266

SE

267

EE

268

EE

269

EB

270

271

•••

279

UVV -VV

ES

SS

UBB

UBV

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

65-6294-17

Figure 15. PAL-M Vertical Interval

REV. 1.0 3/26/03

21

TMC2193

PRODUCT SPECIFICATION

Table 13. PAL-M Field/Line Sequence and Identiﬁcation

Field 1 & 5

Field 2 & 6

Field 3 & 7

Field 4 & 8

FIELD ID = 000, 100

FIELD ID = 001, 111

FIELD ID = 010, 110

FIELD ID = 011, 111

Line

ID

SS

LTYPE

Line

ID

ES

LTYPE

Line

ID

SS

LTYPE

Line

263

264

265

266

267

268

269

270

271

…

ID

ES

LTYPE

01

1

2

03

00

05

0D

…

263

264

265

266

267

268

269

270

271

…

01

03

02

00

10

05

1D

…

1

2

03

00

05

0D

…

SS

03

3

SS

3

SS

03

4

EE

SE

4

EE

SE

02

5

EE

5

EE

00

6

EE

6

EE

00

7

-BB

UBB

…

EB

7

-BB

UBB

…

EB

10

8

-BB

UBB

…

8

UBB

…

05

9

1D

…

17

18

…

259

260

261

262

…

17

18

…

258

259

260

261

262

UBB

UVV

…

0D

0F

…

279

280

281

…

UBB

UBV

UVV

…

0D

0E.

0F

…

UBB

UVV

-VV

-VE

EE

0D

0F

07

04

00

279

280

281

…

UBB

UBV

UVV

…

0D

0E.

0F

…

UVV

-VE

EE

0F

04

00

521

522

523

524

525

UVV

-VV

EE

0F

07

00.

00

521

522

523

524

525

UVV

EE

0F

00

EE

00

EE

00

EE

SE

SS

ES

EB

Equalization pulse

Half-line vertical sync pulse, half-line equalization pulse

Vertical sync pulse

Half-line equalization pulse, half-line vertical sync pulse

Equalization broad pulse

UBB

-BB

UVV

-VV

UVE

-VE

UBV

Black burst

Black burst with color burst suppressed

Active video

Active video with color burst suppressed

Half-line video, half-line equalization pulse

Half-line video, half-line equalization pulse, color burst suppressed.

half-line black, half-line video

22

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

NTSC Subcarrier

Chrominance Processor

For NTSC encoding, the subcarrier synthesizer frequency

has a simple relationship to the pixel clock period, repeating

over 2 lines: The decimal value for the subcarrier phase step

is:

Control registers for this section:

Address Bit(s)

Name

0x06

0x07

0x11

0x18

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

7-6

5-3

5

FORMAT

MODE

455 ⁄ 2

32

--------------------------

pixels ⁄ line

FREQx =

× 2

DDSRST

DRSSEL

GLKCTL1

GLKCTL0

GAUSS_BYP

FREQL

7

Where the number of pixels/line is:

6

PXCK Frequency

pixels ⁄ line = ------------------------------------------

H Period

5

3

This value must be converted to binary and split into four 8

bit registers, FREQM, FREQ2, FREQ3, and FREQL.

7-0

7-4

3-0

7-4

3-0

7-4

3-0

7-4

FREQ3

PAL Subcarrier

The PAL relationship is more complex, repeating only once

in 8 ﬁelds (the well-known 25 Hz offset):

FREQ2

FREQM

SYSPHL

SYSPHM

BURPHL

BURPHM

BRSTFULL

BRST1

(1135 ⁄ 4) + (1 ⁄ 625)

--------------------------------------------------

pixels ⁄ line

32

FREQx =

× 2

This value must be converted to binary and split as described

previously for NTSC. The number of pixels/line is found as

in NTSC.

PAL-M Subcarrier

BRST2

909 ⁄ 4

32

--------------------------

pixels ⁄ line

FREQ =

× 2

Subcarrier Programming

The color subcarrier is produced by an internal 32 bit digital

frequency synthesizer which is completely programmable in

frequency and phase. Separate registers, FREQx, SYSPHx,

BSTPHx, are provided for phase adjustment of the color

burst and of the active video, permitting external delay com-

pensation, color adjustment, etc. FREQx is the subcarrier

phase step per pixel and SYSPHx is phase offset at ﬁeld 1,

line 1 (line 4 for NTSC), pixel 1.

SYSPHx establishes the appropriate phase relationship

between the internal synthesizer and the chroma modulator.

The nominal value for SYSPHx is zero.

Other values for SYSPHx must be converted to binary and

split into two 8 bit registers, SYSPHM and SYSPHL.

Burst Phase (BURPHx) sets up the correct relative NTSC

modulation angle. The value for BURPH is:

BURPHx = SYSPHx

This value must be converted to binary and split into two 8

bit registers, BURPHM and BURPHL.

REV. 1.0 3/26/03

23

TMC2193

PRODUCT SPECIFICATION

Table 14. Standard Subcarrier Parameters

Subcarrier Register (hex)

BURPHM BURPHL SYSPHM SYSPHL FREQM FREQ2 FREQ3 FREQL

Field Horizontal

Pixel

Rate

(Mpps) (MHz)

PXCK Subcarrier

Rate

(Hz)

Freq.

(kHz)

Freq.

(MHz)

Standard

47

00

46

00

45

00

44

00

43

4A

43

40

4C

54

4B

49

43

40

42

AA

E0

00

F3

13

AA

45

DF

10

41

AA

F8

00

18

15

C6

00

3F

66

40

AB

3E

00

19

96

A1

51

D7

F5

NTSC sqr. pixel

NTSC CCIR-601

59.94 15.734266

50.00 15.625000

60.00 15.750000

60.00 15,750000

12.27

13.50

14.32

14.75

13.50

15.00

12.50

13.50

14.30

24.54 3.57954500

27.00 3.57954500

28.64 3.57954500

29.50 4.43361875

27.00 4.43361875

30.00 4.43361875

25.01 3.57561149

27.00 3.57561149

28.60 3.57561149

NTSC 4x F

SC

PAL sqr. pixel

PAL CCIR-601

PAL 15 Mpps

PAL-M sqr.pixel

PAL-M CCIR-601

PAL-M 4x F

SC

Subcarrier Synchronization

the TMC22x5y. The TMC22x5y produces a decoder refer-

ence signal (DRS) which contains ﬁeld identiﬁcation, PAL-

ODD status, relative phase and relative frequency of the

composite or S-video input. The DRS is sampled on either

the CVBS bus or the PD port, depending on DRSSEL, 60

PXCK’s after the falling edge of HSIN. The phase and fre-

quency values are used to update the DDS on a line to line

basis, thus synchronizing the subcarrier to an external com-

posite reference.

There are 5 modes of subcarrier synchronization in the

TMC2193, freerun, subcarrier reset, Genlock, DRS-lock and

Ancillary Data Control (ANC).

•

Freerun

At the rising edge of RESET the DDS starts to generate the

subcarrier reference and will continue to freerun the subcar-

rier. When setting the control register DDSRST is HIGH, the

TMC2193 will reset the DDS to the SYSPH value on the

next ﬁeld 1, line 1 (line 4 for NTSC), pixel 1 occurrence and

will reset this bit to be LOW. This allows the encoder to start

with the correct SCH relationship. The phase of the subcar-

rier reference will drift over time since a 32 bit accumulator

has a error of 0.5 Hz when generating the subcarrier refer-

ence for NTSC 13.5 MHz.

•

Ancillary Data Control (ANC)

Subcarrier synchronization in ANC mode is covered in the

Ancillary Data Control section of this data sheet.

SCH Phase Error Correction

SCH refers to the timing relationship between the 50% point

of the leading edge of horizontal sync and the positive or

negative zero-crossing of the color burst subcarrier refer-

ence. SCH error is usually expressed in degrees of subcarrier

phase. In PAL, SCH is deﬁned for line 1 of ﬁeld 1, but since

there is no color burst on line 1, SCH is usually measured at

line 7 of ﬁeld 1. The need to specify SCH relative to a partic-

ular line in PAL is due to the 25 Hz offset of PAL subcarrier

frequency. Since NTSC has no such 25 Hz offset, SCH

applies to all lines.

•

Subcarrier Reset

At the rising edge of RESET the DDS starts to generate the

subcarrier reference and will reset the DDS to the SYSPH

value every ﬁeld 1, line 1 (line 4 for NTSC), pixel 1 occur-

rence. This enables the encoder to maintain the proper SCH

relationship.

•

Genlock

The SCH relationship is important in the TMC2193 when

two video sources are being combined or if the composite

video output is externally combined with another video

source. In these cases, improper SCH phasing will result in a

noticeable horizontal jump of one image with respect to

another and/or a change in hue proportional to the SCH error

between the two sources.

The Genlock mode allows the TMC2193 to lock to a com-

posite reference when used in conjunction with the

TMC22071A Genlocking Video Digitizer. The TMC22071A

produces a genlock reference signal (GRS) which contains

ﬁeld identiﬁcation, PALODD status, relative phase and rela-

tive frequency of the composite reference. The GRS is sam-

pled on the CVBS bus 60 PXCK’s after the falling edge of

HSIN. The phase and frequency values are used to update

the DDS on a line to line basis, thus synchronizing the sub-

carrier to an external composite reference.

SCH phasing can be adjusted by modifying BURPH and

SYSPH values by equal amounts. SCH is advanced/delayed

by one degree by increasing/decreasing the value of BURPH

and SYSPH by approximately B6 . An SCH error of 15^ois

h

•

DRS-Lock

corrected with SYSPH and BURPH offsets of AAA .

h

The DRS-Lock mode allows the TMC2193 to lock its com-

posite output to the decoded composite or S-video input of

24

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Burst Envelope

0

-10

-20

-30

-40

-50

-60

-70

-80

The TMC2193 includes the ability to adjust the burst ampli-

tude and the shape of the burst. The Control Registers

BRSTFULL, BRST1 and BRST2 hold the magnitude of the

burst vector. BRSTFULL is the maximum amplitude of the

burst vector. BRST1 and BRST2 determine the intermediate

values of the burst vector for the burst envelope shaping. A 5

pixel burst envelope shaping occurs at the rising and falling

edges of burst. At the rising edge of burst the next 5 pixels

have the following weighting; BRSTFULL – BRST1,

BRSTFULL – BRST2, BRSTFULL/2, BRST2, and BRST1.

At the falling edge of burst the next 5 pixels have the follow-

ing weighting; BRST1, BRST2, BRSTFULL/2, BRSTFULL

– BRST2, and BRSTFULL – BRST1. With this ﬂexibility

the user determine the shape, amplitude and width of the

burst signal.

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (Pixel rate)

Figure 17. Gaussian Filter Response

BRSTFULL

BRST1

BRST2

Sync and Pedestal Insertion

Control Registers for this section

BRSTFULL/2

Address

0x06

0x10

0x11

0x14

0x15

0x16

0x17

0x1A

0x3F

0x4B

Bit(s)

7-6

1-0

5

Name

BRSTFULL - BRST2

BRSTFULL - BRST1

BLANK

MODE

OUTMODE

COMP2DB

VBIPEDEM

VBIPEDEL

VBIPEDOM

VBIPENOL

PEDHGT1

C2DB_OFF

NMBD

7-0

6-0

3

BU

65-6294-18

Figure 16. Burst Envelope

Color-Difference Low-Pass Filters

The chrominance portion of a composite video signal must

be sufﬁciently bandlimited to avoid cross-color and cross-

luminance distortion, and to preclude exceeding the allow-

able bandwidth of a video channel.

7-0

7-4

PEDHGT2

Pedestal Enable

The color-difference low-pass ﬁlters on the TMC2193

establish chrominance bandwidths which meet the speciﬁca-

tions outlined in CCIR Report 624-3, Table II, Item 2.6, for

system I over a range of pixel rates from 12.27 Mpps to

14.75 Mpps. Equal bandwidth is established for both color-

difference channels.

The TMC2193 has the ability to independently select lines

for pedestal insertion during the vertical blanking interval

(VBI). For 525-line systems and using the NTSC line num-

bering convention, in which the ﬁrst vertical serration is on

line 4 for ﬁeld 1 and line 266 for ﬁeld 2, the vertical interval

lines map to the control registers VBIPEDxy as shown in

Table 15.

Table 15. Line by Line Pedestal Enable

Bit

7

6

5

4

3

2

1

0

VBIPEDEL

VBIPEDEM

VBIPEDOL

VBIPEDOM

17

16

15

14

13

12

11

10

18

25*

279

287*

24

23

22

21

20

19

278

286

277

285

276

284

275

283

274

282

273

281

280

REV. 1.0 3/26/03

25

TMC2193

PRODUCT SPECIFICATION

Enabling the pedestal on line 25 enables it for the remainder

of ﬁeld 1, to line 262. Likewise, enabling the pedestal on line

288 enables it for the remainder of ﬁeld 2.

The TMC2193 includes a ﬂexible closed-caption processor.

It may be programmed to insert a closed caption signal on

any line within a range of 16 lines on ODD and/or EVEN

ﬁelds. Closed Caption insertion overrides all other conﬁgura-

tions of the encoder: if it is speciﬁed on an active video line,

it takes precedence over the video data and removes NTSC

setup if setup has been programmed for the active video

lines. Closed Caption is only available when the TMC2193

is in a 13.5 MHz pixel rate.

Pedestal Height

There are two control registers that set the pedestal height,

PEDHGT1, and PEDHGT2. PEDHGT1 determines the

height of the pedestal for the luminance channel on the com-

posite path and PDEHGT2 determines the height of the ped-

estal for the luminance channel on the component path. This

allows for independent pedestal control of the composite and

component paths. In both cases the range of the pedestal

height is from -22.1 to 21.74 IRE in .345 IRE increments.

Closed caption is turned on by setting CCON HIGH. When-

ever the encoder begins producing a line speciﬁed by

CCFLD and CCLINE, it will insert a closed caption line in

its place. If CCRTS is HIGH, the data contained in CCDx

will be sent. IF CCRTS is LOW, Null bytes (hex 00 with

ODD parity) will be sent.

Sync and Blank Insertion

The control register NBMD selects the sync and blank levels

for the component path, so that the correct ratio of sync to

blank and blank to 100% white for both a 5:2 and 7:3 stan-

dards are meet. If NBMD is LOW the component blank level

is a D/A code of 256 (314 mV), this is added to the lumi-

nance data for YPbPr or all three components for RGB out-

puts. The component sync level is a D/A code of 12 (14 mV)

which is added to the luminance data for YPbPr or to the

Green component for RGB outputs. If NBMD is HIGH the

component blank level is a D/A code of 240 (295 mV), this

is added to the luminance data for YPbPr or all three compo-

nents for RGB outputs. The component sync level is a D/A

code of 8 (9 mV) which is added to the luminance data for

YPbPr or to the Green component for RGB outputs. The

selection of which components have sync and blank codes

added to them is controlled by the OUTMODE control regis-

ter. Which can select from YPbPr, RGB with sync on green

or RGB with external sync.

Line Selection

The line to contain CC data is selected by a combination of

the CCFLD bit and the CCLINE bits. CCLINE is added to

the offset shown in Table 16 to specify the line.

Table 16. Closed Caption Line Selection

Standard

Offset

12

Field

ODD

Lines

525

12-27

274

16

EVEN

ODD

274-289

16-31

625

328

EVEN

328-343

Parity Generation

Standard Closed-Caption signals employ ODD parity, which

may be automatically generated by setting CCPAR HIGH.

Alternatively, parity may be generated externally as part of

the bytes to be transmitted, and, with CCPAR LOW, the

entire 16 bits loaded into the CCDx registers will be sent

unchanged.

For the composite path the blank and sync D/A codes are

determined by the FORMAT control register. For NTSC and

PAL-M formats the blank D/A code is 240 (295 mV) and the

sync D/A code is 8 (9 mV). For all other PAL formats the

blank D/A code is 256 (314 mV) and the sync D/A code is

12 (14 mV).

Operating Sequence

A typical operational sequence for closed-caption insertion

on line xx is:

In all cases the sync edges are sloped to insure the proper rise

and fall times in all video standards.

Read Register 1E and check that bit 7 is LOW, indicat-

ing that the CCDx registers are ready to accept data.

Closed Caption Insertion

Control Registers for this section

If ready, write two bytes of CC data into registers 1C

and 1D.

Address

0x1C

0x1D

0x1E

Bit(s)

7-6

1-0

7

Name

CCD1

Write into register 1E the proper combination of

CCFLD and CCLINE. CCPAR may be written as

desired. Set CCRTS HIGH.

CCD2

CCON

CCRTS

CCPAR

CCFLD

CCLINE

6

The CC data is transmitted during the speciﬁed line.

5

As soon as CCDx s transferred into the CC processor (and

CCRTS goes LOW), new data may be loaded into registers

1C and 1D. This allows the user to transmit CC data on sev-

eral consecutive lines by loading data for line n+1 while data

is being sent on line n.

4

3–0

26

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Interpolation Filters

x/Sin(x) Filter

Each video output on the TMC2193 is digitally ﬁltered with

sharp-cutoff low-pass interpolation ﬁlters. These ﬁlters

ensure that the frequency band above base-band video and

Control Registers for this section

Address

Bit(s)

Name

below the pixel frequency (f /4 to 3f /4, where f is the

PXCK frequency) are sufﬁciently suppressed.

S

0x11

4

SINEN

The TMC2193 contains a selectable X/sin(X) ﬁlter prior to

each DAC. The X/sin(X) ﬁlter boosts the high frequency

data to negate the sin(X)/X roll-off associated with D/A con-

verters.

Since these are ﬁxed-coefﬁcient digital ﬁlters, their ﬁlter

characteristics depend upon clock rate.

10

0

1.5

-10

-20

-30

-40

-50

-60

-70

-80

X/Sin(x) Filter

1

0.5

0

Compensated

D/A Output

-0.5

-1

Sin(x)/x D/A Roll-Off

-1.5

-2

0

0.2

0.4

Frequency (Pixel rate)

Figure 18. Interpolation Filter

0.6

0.8

1

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (PXCK)

Figure 20. X/SIN(X) Filter

0.5

0

-0.5

-1

Output Data Formats

Control Registers for this section

-1.5

-2

Address

0x10

0x11

0x3F

Bit(s)

Name

7

DAC4DIS

DAC3DIS

DAC2DIS

DAC1DIS

OUTMODE

OFMT

-2.5

-3

6

5

-3.5

-4

4

0

0.1

0.2

0.3

0.4

0.5

1-0

6

Frequency (Pixel rate)

Figure 19. Interpolation Filter – Passband Detail

3

REFSEL

SEL_CLK

SEL_PIX

7

4

The selection of the output format is determined by the

OUTMODE control register.

Table 17. D/A Outputs

Description

Ref. DAC

ref.

DAC1

Green

Y

DAC2

DAC3

DAC4

RGB

Blue

Red

Comp2/overlay

Y P P

ref.

P

B

P

R

B

R

S-VIDEO

ref.

Comp1

Y

Chroma

REV. 1.0 3/26/03

27

TMC2193

PRODUCT SPECIFICATION

Analog outputs of the TMC2193 are driven by four 10 bit

D/A converters and separate 9 bit reference D/A converter,

operating at twice the pixel rate. The outputs drive standard

video levels into 37.5 or 75 Ohm loads. An internal voltage

reference is used to provide reference current for the D/A

converters. For more accurate levels, an external ﬁxed or

variable voltage reference source is accommodated. The

video signal levels from the TMC2193 may be adjusted by

varying the common Vref or the four independent Rrefs.

Each video D/A converter has an independent reference

resistor that can adjust the output gain, with the exception of

the reference D/A whose reference resistor is shared with

DAC1. D/A Matching is achieved by trimming the each

external reference resistor of each D/A.

Ancillary Data

Control Registers for this section

Address

0x07

Bit(s)

Name

2

ANCFREN

ANCPHEN

ANCTREN

ANCID

0x07

1

0x07

0

0x08

7-0

The TMC2193 is designed to accept 15 words of ancillary

data after the active video pixels at the end of each horizontal

line. Ancillary data may occur once per line, once per ﬁeld,

once per eight ﬁelds, on random lines, or not al all. The

TMC2193 does not assume ancillary data is present on a reg-

ular basis.

Digital Composite Output

In addition, the TMC2193 supplies a 10 bit digital composite

signal on pins D[7:0] and FLD[2:1]. The digital composite

output can be either an interpolated signal on a non-interpo-

lated signal, this controlled by the control register

SEL_CLK.

Table 18. Ancillary Data Format

Word ID

ANC2

ANC1

ANC0

TT

Description

B

0

7

6

5

4

3

2

1

Ancillary Data Header (Timing

Reference Signal)

0

1

Data Type

TT6

0

TT5

D11

D5

x

TT4

D10

D4

x

TT3

D9

D3

SVF

x

TT2

D8

D2

F2

x

TT1

D7

D1

F1

x

TT0

D6

D0

F0

x

P

MM

Word

LL

Count

0

FIELD

Field ID/Synchronous Video Flag

reserved

x

PH1

PH0

FR4

FR3

FR2

FR1

FR0

Subcarrier Phase

PHV PH

12

PH

11

PH

10

PH

9

8

7

PH

x

PH

6

5

4

3

2

1

0

Subcarrier Frequency

FRV

x

FR

31

24

17

10

30

23

16

29

22

15

28

21

14

FR

27

20

13

26

19

12

25

18

11

FR

9

2

8

1

7

0

FR

3

FR

6

5

4

Note:

1. P = odd parity bit, x = reserved bit will be ignored

The ﬁrst three words of ancillary data comprise the TRS sig-

nal (ANC2-0) which indicates the end of active video. Also

ancillary data will be processed. If there is no match, the

TMC2193 ignores ancillary data.

known as the Ancillary data header, the TRS signal is a 00 ,

h

The word count data (D

11-0

packet indicate the number of words in ancillary data.

in MM, LL) in the ancillary data

FF , FF sequence. Except for the TRS words, ancillary data

h

bit 0 (B , LSB) is odd parity for B

.

0

7-1

Ancillary phase data is used to program the MSBs of the

PHASE register. ANCPHEN and PHV determine how ancil-

lary phase data is used. When ancillary data is not present,

the TMC2193 assumes PHV = LOW.

The data type word (TT) is used to specify the ancillary data

type. The TMC2193 compares this 7 bit value with the con-

tents of the ANCID control register. If there is a match, the

28

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Table 19. Ancillary Data Control – Phase

ancillary frequency data is used. When ancillary data is not

present, the TMC2193 assumes FRV = LOW.

ANCPHEN PHV Description

Table 20. Ancillary Data Control Frequency

0

1

x

0

1

Ignore ancillary phase data,

set PHASE = 0

ANCFREN

FRV Description

Ignore ancillary phase data,

no change to PHASE

0

x

0

1

Ignore ancillary frequency

data

Load ancillary phase data into

PHASE registers

1

Ignore ancillary frequency

data

Load ancillary frequency data

into FREQ3-0 registers

Ancillary frequency data is used to program the 32 bits of the

FREQ3-0 registers. ANCFREN and FRV determine how

Table 21. Field Identiﬁcation and Subcarrier Reset Modes

ANCTREN

SVF

F

2

F

1

F

0

F (EAV)

Field ID / Subcarrier Reset Mode

Basic Mode

0

x

0

1

Odd ﬁeld, reset subcarrier every 8 ﬁelds

x

Even field

Genlocking Mode

1

x

0

1

Odd ﬁeld, subcarrier free run

Even ﬁeld

Field Sequence Mode

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Field 1, reset subcarrier at field 1

Field 2

Field 3

Field 4

Field 5

Field 6

Field 7

Field 8

Note:

1. The F bit is part of the EAV timing reference code and tracks the F0 bit.

Operating Modes

The ﬁeld number bits (F ) from the ancillary data packet

2-0

In genlocking mode (ANCTREN and SVF = HIGH), the

subcarrier synthesizer is allowed to free run, with phase and

FIELD word, are used to program the encoder’s ﬁeld counter

depending upon the state of the synchronous video ﬂag

(SVF) and the ANCTREN bit in the control register.

frequency being set from the ancillary data packet PH

12-0

and FR

data. The ﬁeld counter increments just like it

does in basic mode.

31-0

In the basic operating mode (ANCTREN = LOW), all timing

is found in the F bit of EAV. F and SVF are ignored and

2-0

Field sequence mode (ANCTREN = HIGH and SVF =

LOW), is the same as basic mode except that the ﬁeld

the encoder subcarrier synthesizer is reset to the PHASE

value every eight ﬁelds (when the ﬁeld counter transitions

from 111 (ﬁeld 8) to 000 (ﬁeld 1).

counter is set by the F bits in the FIELD word of ancillary

2-0

data. If ancillary data is not present on a line, the ﬁeld

counter will continue to count as it does in basic mode.

When ancillary data is present, the contents of the ﬁeld

counter are loaded with ﬁeld data (F ). In this way, the

2-0

TMC2193 may be synchronized with an external source by

sending ﬁeld data only once.

In the basic mode, ANCFREN and ANCPHEN are typically

set LOW, ignoring ancillary frequency and phase data. If

ANCFREN and ANCPHEN are HIGH, the TMC2193 uses

the incoming ancillary frequency and phase data on a line-

by-line basis.

REV. 1.0 3/26/03

29

TMC2193

PRODUCT SPECIFICATION

Layering Engine

Control Registers for this section

Address

0x0A

Bit(s)

7-0

Name

DKEYMAX

DKEYMIN

EKEYMAX

EKEYMIN

FKEYMAX

FKEYMIN

0x0B

7-0

Address

0x04

0x05

0x07

0x09

Bit(s)

Name

0x0C

0x0D

0x0E

7-0

2

SKEN

7-0

3-2

6

OMIX

7-0

SKFLIP

HKEN

0x0F

7-0

7

6

BUKEN

SKEXT

DKDIS

EKDIS

FKDIS

LAYMODE

The TMC2193 features a robust layering engine with three

possible input layers controlled by two keying controls. The

layer assignments are shown in Table 22, along with the key-

ing control. The keying controls, KEY pin or OL4-0 are

aligned with the incoming pixel data stream and are then

delayed throughout the chip to be continuously aligned with

the input video streams. A generic overview of the keying

and layering features is shown in Figure 21.

5

4

3

2

1-0

Table 22. Layering and Keying Modes

LAYMODE

BACKGROUND

Image Source

PD

MIDGROUND

FOREGROUND

Image Source

OVERLAY

CVBS

Keying Control

OL4-0

Image Source

Keying Control

KEY or Data Key

OL4-0

0

1

2

3

CVBS

OVERLAY

PD

KEY or Data Key

OL4-0

CVBS

OVERLAY

PD

KEY or Data Key

OL4-0

CVBS

KEY or Data Key

OVERLAY

OL4-0

dT

PD

YC

PD

DATA KEY

LOGIC

dT

LOGIC

OVERLAY

MIXER

KEY

dT

OLUT

dT

COMP2

1/2AMP

KEYING

MIXER

CVBS

dT

65-6294-23

Figure 21. Layering Engine

Overlay Mixer

ors, see Table 22. Overlay Address Map. When OL4-0 equal

to 16, the overlay mixer produces a pixel data output with

half the luminance magnitude and chrominance magnitude.

Any OL4-0 value greater than 16 will result in a overlay mix

with a full amplitude overlay and the pixel data with half

amplitude pixel data (PD) or half amplitude CVBS data as its

values. This allows for transparent overlays or produce

shadow boxes around overlaid text.

The OL[4:0] bus provides the ability to overlay 30 different

24 bit values onto the pixel data path. The 24 bit overlay col-

ors must be the same format as the incoming Pixel data. For

Y,Cb,Cr input formats the range of Y values spans the entire

range of the format, 1 to 254, this enables super whites and

super blacks in the overlay palette.

When OL[4:0] is equal to 00h the pixel data port to be the

output of the overlay mixer. If OL[4:0] is in the range of 1 to

31 then the output source is one of 30 possible overlay col-

The midpoint of the rising and falling edges on the mixed

output is determined by the transition of the OL[4:0] pins in

30

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

relation to the PD port. Control register OMIX chooses

among the following set of coefﬁcients; either 0 1/8 1/2 7/8

1, 0 1/2 1 , or 0 1 to switch between the PD port and the over-

lay color. The timing diagram in Figure 22 identiﬁes the

three possible output formats that the mixer can produce.

A

B

C

D

E

F

G

H

I

PDx

OL[4:0]

A

>0

0

A

7/8B, 1/8OL 1/2C, 1/2OL 1/8D, 7/8OL

OL

1/8F, 7/8OL 1/2G, 1/2OL 7/8H, 1/8OL

I

MixOUT (OMIX = 3)

MixOUT (OMIX = 2)

MixOUT (OMIX = 1)

B

1/2C, 1/2OL

OL

1/2G, 1/2OL

H

OL

I

65-6294-24

Figure 22. Overlay Outputs

Table 23. Overlay Address Map

OL4-0

0

Result

Pixel data is passed through overlay mixer.

Overlay is mixed with PD or CVBS at the transitions.

Half amplitude PD or half amplitude CVBS is the output of COMP2.

Overlay is mixed with half amplitude PD or half amplitude CVBS at the transitions.

1-15

16

17-31

DKEYDIS, EKEYDIS, and FKEYDIS. On each channel the

eight (8) MSBs of the pixel data are compared against a

maximum key value and a minimum key value. If the pixel

data is greater than xKEYMIN and less than or equal to

xKEYMAX, then a key match is signaled for that channel.

Hardware Keying

The KEY input switches the input to the Comp2 data path

between the composite video generated from the PD port and

the CVBS data bus on a pixel-by-pixel basis. This is a “soft”

switch is executed over 3 PCK periods to minimize out-of-

band transients. Keying is accomplished in the digital com-

posite video domain. The coefﬁcients for the mix are 0, 1/8,

1/2, 7/8, and 1 . The COMP2 output is the ﬁnal output for all

overlay functions. The other three D/As will continue to

present PD port data when CVBS is active.

xKEYMAX

A

A<=B

B

KEY

MATCH

xKEYMIN

Hardware keying is enabled by the key Control Register

HKEN. Normally, keying is only effective during the active

video portion of the encoded video line (as determined by

Control Register VA). That is, the horizontal blanking inter-

val is generated by the encoder even if the KEY signal is

held HIGH through horizontal blanking. However, it is pos-

sible to allow digital horizontal blanking to be passed

through from the CVBS bus to the COMP2 output by setting

key Control Register BUKEN HIGH. In this mode, KEY is

always active, and may be exercised at will.

A

B

A<=B

xCHANNEL

65-6294-25

Figure 23. Data Keying

By allowing a window of possible key values on each chan-

nel the TMC2193 opens a key cube in the color space.

Parallel Microprocessor Interface

The parallel microprocessor interface is active when SER is

HIGH and employs a 12-line interface; an 8 bit data bus and

2 bit address location, 1 bit read/write select, and a chip

select controlling the timing. Two addresses are required for

device programming, one to the pointer and one to the data

location. When writing, the address is presented along with a

LOW on the R/W pin during the falling edge of CS. Eight

bits of data are presented on D7-0 during the subsequent ris-

ing edge of CS.

The KEY input is registered into the encoder just as Pixel

data is clocked into the PD port. It is internally pipelined, so

the midpoint of the KEY transition occurs at the output of

the pixel that was input at the same time at the KEY signal.

Data Keying

Data Keying occurs just prior to the gamma block. Data key-

ing for each channel Green/Y, Blue/C , and Red/C , is sepa-

b

r

rately enabled or disabled by the control registers

REV. 1.0 3/26/03

31

TMC2193

PRODUCT SPECIFICATION

In read mode, the address is accompanied by a HIGH on the

R/W pin during a falling edge of CS. The data output pins go

Red byte is transferred the base address will increment by

one (1).

to a low-impedance state t

present on D7-0 t

DOM

after CS falls. Valid data are

after the falling edge of CS. Because

DOZ

Table 24. Parallel Port Control

this port operates asynchronously with the pixel timing,

there is an uncertainty in this data valid output delay of one

A

R/W Action

1-0

00

01

10

11

0

1

0

1

0

1

0

1

Load D into Control Register

7-0

pointer (block 0)

PXCK period. This uncertainty does not apply to t

.

DOZ

Writing data to speciﬁc control registers of the TMC2193

requires that the 8 bit address of the control register of inter-

est be written prior to the data. This control register address

is the base address for subsequent write operations. The base

address auto increments by one for each byte of data written

after the data byte intended for the base address. If more

bytes are transferred than there are available addresses, the

address will not increment and remain at its maximum value

of 4Ch.

Read Control Register pointer on

D

7-0

Load D into addressed OLUT

Location pointer (block 0)

7-0

Read addressed OLUT Location

pointer on D

.

7-0

Write D to addressed Control

Register

7-0

Read addressed Control Register

Writing data to speciﬁc OLUT location of the TMC2193

requires that the 8 bit address of the OLUT location of inter-

est be written prior to the data sequence. This OLUT loca-

tion address is the base address for subsequent write

operations. The base address auto increments by one for

each sequence of three (3) bytes of data written after the data

byte intended for the base address. The sequence of data

on D

7-0

Write D to addressed OLUT

Location

7-0

Read addressed OLUT Location on

D

7-0

transfer is Y or Green, C or Blue, C or Red, after the C or

b

r

t

PWHCS

PWLCS

CS

R/W

ADR

t

HA

SA

t

SD

HD

D

7-0

65-6294-26

Figure 24. Microprocessor Parallel Port – Write Timing

t

PWHCS

PWLCS

CS

R/W

ADR

t

HA

SA

t

HOM

DOM

D

7-0

65-6294-27

t

DOZ

Figure 25. Microprocessor Parallel Port – Read Timing

32

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

bit indicates the direction of data transfer, read from or write

to the slave device. If the transmitted slave address matches

the address of the device (set by the state of the SA1-0 input

pins in Table 24), the TMC2193 acknowledges by bringing

SDA LOW on the 9th SCL pulse. If the addresses do not

match, the TMC2193 will not acknowledge.

Serial Control Port (R-Bus)

In addition to the 12-wire parallel port, a 2-wire serial con-

trol interface is provided, active when SER is LOW. Either

port alone can control the entire chip. Up to four TMC2193

devices may be connected to the 2-wire serial interface with

each device having a unique address.

Table 25. Serial Port Addresses

The 2-wire interface comprises a clock (SCL) and a bi-direc-

tional data (SDA) pin. The encoder acts as a slave for receiv-

ing and transmitting data over the serial interface. When the

serial interface is not active, the logic levels on SCL and

SDA need to be pulled HIGH by external pull-up resistors.

A1

A0

A6

1

A5

0

A4

1

A3

0

A2

1

(SA1) (SA0)

0

1

0

1

0

1

0

1

0

1

Data received or transmitted on the SDA line must be stable

for the duration of the positive-going SCL pulse. Data on

SDA must change only when SCL is LOW. If SDA changes

state while SCL is HIGH, the serial interface interprets that

action as a start or stop sequence.

1

0

1

0

1

0

1

0

1

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the ﬁrst bit

of the sequence.

There are six components to serial bus operation:

• Start signal

If the TMC2193 does not acknowledge the master device

during a write sequence, the SDA remains HIGH so the mas-

ter can generate a stop signal. If the master device does not

acknowledge the TMC2193 during a read sequence, the

encoder interprets this as “end of data”.

• Slave address byte

• Block Pointer

• Offset Pointer

• Data byte to read or write

• Stop signal

Writing data to speciﬁc control registers of the TMC2193

requires that the 8 bit address of the control register of inter-

est be written after the slave address has been established.

This control register address is the base address for subse-

quent write operations. The base address auto increments by

one for each byte of data written after the data byte intended

for the base address.

When the serial interface is inactive (SCL and SDA are

HIGH) communications are initiated by sending a start sig-

nal. The start signal is a HIGH-to-LOW transition on SDA

while SCL is HIGH. This signal alerts all slaved devices that

a data transfer sequence is coming.

The ﬁrst eight bits of data transferred after a start signal com-

prise a seven bit slave address and a single R/W bit. The R/W

SDA / R/W

t

BUFF

t

STOSU

DHO

DSU

STASU

t

STAH

t

DAL

SCL / CS

t

BAH

65-6294-28

Figure 26. Serial Port Read/Write Timing

Data are read from the control registers of the TMC2193 in a

similar manner. Reading requires two data transfer opera-

tions:

Reading (the R/W bit of the slave address byte HIGH)

begins at the previously established base address. The

address of the read register auto increments after each byte is

transferred.

The base address must be written with the R/W bit of the

slave address byte LOW to set up a sequential read opera-

tion.

To terminate a write sequence to the TMC2193, a stop signal

must be sent. A stop signal comprises a LOW-to-HIGH tran-

sition of SDA while SCL is HIGH. To terminate a read

REV. 1.0 3/26/03

33

TMC2193

PRODUCT SPECIFICATION

sequence simply do not acknowledge (NOACK) the last byte

received and the TMC2193 will terminate the sequence.

generating a stop signal to terminate the current communica-

tion. This is used to change the mode of communication

(read, write) between the slave and master without releasing

the serial interface lines.

A repeated start signal occurs when the master device driv-

ing the serial interface generates a start signal without ﬁrst

SDA

SCL

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ACK

65-6294-29

Figure 27. Serial Interface – Typical Byte Transfer

SDA

SCL

A

6

A

5

A

4

A

3

A

2

SA

0

R/W

ACK

1

65-6294-30

Figure 28. Serial Interface – Chip Address

Serial Interface Read/Write Examples

Write to four consecutive OLUT locations

• Start signal

• Slave Address byte (R/W bit = LOW)

• Block Pointer (01)

Write to one control register

• Start signal

• Slave Address byte (R/W bit = LOW)

• Block Pointer (00)

• Offset Pointer

• Offset Pointer (base address)

• Data byte to base address (Y or Green)

• Data byte to base address (Cb or Blue)

• Data byte to base address (Cr or Red)

• Data byte to base address +1 (Y or Green)

• Data byte to base address +1 (Cb or Blue)

• Data byte to base address +1 (Cr or Red)

• Data byte to base address +2 (Y or Green)

• Data byte to base address +2 (Cb or Blue)

• Data byte to base address +2 (Cr or Red)

• Data byte to base address +3 (Y or Green)

• Data byte to base address +3 (Cb or Blue)

• Data byte to base address +3 (Cr or Red)

• Stop signal

• Data byte to base address

• Stop signal

Write to four consecutive control registers

• Start signal

• Slave Address byte (R/W bit = LOW)

• Block Pointer (00)

• Offset Pointer

• Data byte to base address

• Data byte to (base address + 1)

• Data byte to (base address + 2)

• Data byte to (base address + 3)

• Stop signal

Read from one control register

• Start signal

• Slave Address byte (R/W bit = LOW)

• Block Pointer (00)

• Offset Pointer

• Stop signal

• Start signal

• Slave Address byte (R/W bit = HIGH)

• Data byte from base address

• NOACK

Write to one OLUT location

• Start signal

• Slave Address byte (R/W bit = LOW)

• Block Pointer (01)

• Offset Pointer (base address)

• Data byte to base address (Y or Green)

• Data byte to base address (Cb or Blue)

• Data byte to base address (Cr or Red)

• Stop signal

34

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Read from four consecutive control registers

• Start signal

• Slave Address byte (R/W bit = LOW)

• Block Pointer (00)

• Offset Pointer

• Stop signal

• Slave Address byte (R/W bit = HIGH)

• Data byte from base address

• Data byte from (base address + 1)

• Data byte from (base address + 2)

• Data byte from (base address + 3)

• NOACK

• Start signal

Control Register Map

Table 26. Control Register Map

Table 26. Control Register Map (continued)

Reg Bit Mnemonic

Function

Reg Bit Mnemonic

Ancillary Data ID Register

08 7-0 ANCID Ancillary Data Identification

Keying/Overlay Engine

Hardware KEY Enable

Burst KEY Enable

Function

TMC2193 Identiﬁcation Registers (Read only)

00 7-0 PARTID2

Reads back 97h

Reads back 21h

Reads back 93h

Silicon revision #

01 7-0 PARTID1

02 7-0 PARTID0

03 7-0 REVID

09

7

6

5

4

3

2

HKEN

BUKEN

SKEXT

DKDIS

EKDIS

FKDIS

Gamma Filters Register

Data KEY Operation Select

Green/Y Data KEY Disable

04

7

6

5

4

GAMENG

Gamma Filter Enable – Green

Gamma Filter Enable – Blue Red

Gamma Filter Selection – Green

GAMENC

GAMSELG

GAMSELC

Blue/C Data KEY Disable

B

Red/C Data KEY Disable

R

Gamma Filter Selection – Blue

Red

09 1-0 LAYMODE

Layer Assignment Select

Key Value Registers

04

3

2

SRESET

SKEN

Software RESET

0A 7-0 DKEYMAX

0B 7-0 DKEYMIN

0C 7-0 EKEYMAX

0D 7-0 EKEYMIN

0E 7-0 FKEYMAX

0F 7-0 FKEYMIN

Green/Y Maximum Data Key

Value

Data KEY Enable

04 1-0 PDRM

Pixel Data Ramping Mode

Green/Y Minimum Data Key

Value

Input Format Register

Blue/C Maximum Data Key

B

Value

05

7

D1OFF

YCBCR Input Formatting

Input Mode Select

05 6-4 INMODE

05 3-2 OMIX

Blue/C Minimum Data Key

B

Value

Overlay Mixer Select

Video Input Select

05 1-0 SOURCE

Red/C Maximum Data Key

R

Value

General Control Register

06 7-6 FORMAT

06 5-3 MODE

Video Format

Red/C Minimum Data Key

R

Value

Video Mode

DAC Control Registers

06

2

1

0

PDCDIR

TOUT

PDC Directional Control

External Sync Output Control

External Sync Delay Control

10

7

6

5

4

3

2

DAC4DIS

DAC3DIS

DAC2DIS

DAC1DIS

Reserved

OLUTDIS

D/A #4 Disable

D/A #3 Disable

D/A #2 Disable

D/A #1 Disable

Set to 0.

TSOUT

Horizontal Ancillary Data Control Register

07

7

6

5

LDFID

Field Lock Select

Soft Key Inversion

DDS Reset

SKFLIP

DDSRST

Overlay LUT Disable

Output Modes

10 1-0 OUTMODE

07 4-3 Reserved

07

2

1

0

ANCFREN

ANCPHEN

ANCTREN

Ancillary Frequency Enable

Ancillary Phase Enable

Ancillary Timing Enable

REV. 1.0 3/26/03

35

TMC2193

PRODUCT SPECIFICATION

Table 26. Control Register Map (continued)

Reg Bit Mnemonic

Function

Reg Bit Mnemonic

Function

24 7-0 XBP

Extended Color Back Porch

Duration

11

7

6

5

4

3

2

1

0

DRSSEL

OFMT

DRS Selection

Component Data Formatting

Composite 2 Overflow Control

X/Sin(x) Filter Enable

Reference DAC Output Selection

Luma Disable

25 7-0 VA

26 7-0 VC

Active Video Region Duration

COMP2DB

SINEN

Active Video Region 2nd Half

Line Duration

REFSEL

LUMDIS

CHRMDIS

BURSTDIS

27 7-0 VB

Active Video Region 1st Half

Line Duration

Chroma Disable

28 7-0 EL

29 7-0 EH

Equalization Pulse Low Duration

Burst Disable

Equalization Pulse High

Duration

VBI Ped Enable Registers

2A 7-0 SL

2B 7-0 SH

Vertical Sync Pulse Low

Duration

14 7-0 VBIPEDEM

15 7-0 VBIPEDEL

16 7-0 VBIPEDOM

17 7-1 VBIPEDOL

VBI Pedestal Enable, Even Fields

VBI Pedestal Enable, Odd Fields

Vertical Sync Pulse High

Duration

2C 7-0 FP

Front Proch Duration

17

0

HVA

Horizontal and Vertical Sync

Alignment

2D 7-6 XBP

Extended Color Back Porch

Duration

Vertical Blanking Interval Enable Registers

2D 5-4 VA

2D 3-2 VB

Active Video Duration

18

7

Reserved

GLKCTL1

GLKCTL0

Active Video Region 1st Half

Line Duration

6

5

Genlock Control Register 1

Genlock Control Register 0

VBI Active Video Enable, Field 1

Test Register

2D 1-0 VC

Active Video Region 2nd Half

Line Duration

18 4-0 VBIENF1

2E 7-5 FIELD

2E 4-0 LTYPE

Fiele Identification (read only)

19

7

6

5

SHORT

T512

Line Type Identification (read

only)

EH/SL Offset Control Bit

Half Line Enable

HALFEN

2F 7-0 CBL

Color Bar Duration

19 4-0 VBIENF2

VBI Active Video Enable, Field 2

Color Space Matrix Registers

Pedestal Height Register

Reserved

1A 6-0 PEDHGT1

30 7-0 MCF1L

31 7-0 MCF2L

32 7-0 MCF3L

33 7-0 MCF4L

34 7-0 MCF5L

35 7-0 MCF6L

36 7-0 MCF7L

37 7-0 MCF8L

38 7-0 MCF9L

39 7-0 MCF10L

3A 7-4 MCF1M

3A 3-0 MCF2M

3B 7-4 MCF3M

Matrix Coefficient #1

Matrix Coefficient #2

Matrix Coefficient #3

Matrix Coefficient #4

Matrix Coefficient #5

Matrix Coefficient #6

Matrix Coefficient #7

Matrix Coefficient #8

Matrix Coefficient #9

Matrix Coefficient #10

Matrix Coefficient #1

Matrix Coefficient #2

Matrix Coefficient #3

Set to 0.

1A

7

Composite Pedestal Height

Closed Caption Registers

1C 7-0 CCD1

1D 7-0 CCD2

First Byte of CC Data

Secons Byte of CC Data

Enable CC Data Packet

Request to Send Data

Auto Parity Generation

CC Field Select

1E

7

6

5

4

CCON

CCRTS

CCPAR

CCFLD

1E 3-0 CCLINE

CC Line Select

Timing Registers

1F 7-0 PDCNT

20 7-0 SY

21 7-0 BR

22 7-0 BU

23 7-0 CBP

Pixel Data Control Start

Horizontal Sync Tip Duration

Breezeway Duration

3B

3

Reserved

3B 2-0 MCF4M

Matrix Coefficient #4

Burst Duration

Color Back Porch Duration

36

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Table 26. Control Register Map (continued)

Reg Bit Mnemonic

42 7-0 FREQ2

Function

Reg Bit Mnemonic

Function

Subcarrier Frequency

System Phase

Burst Phase

3C 7-4 MCF5M

Matrix Coefficient #5

Set to 0.

43 7-0 FREQM

44 7-0 SYSPHL

45 7-0 SYSPHM

46 7-0 BURPHL

47 7-0 BURPHM

48 7-0 BRSTFULL

3C

3

Reserved

3C 2-0 MCF6M

3D 7-4 MCF7M

3D 3-0 MCF8M

3E 7-4 MCF9M

3E 3-0 MCF10M

Matrix Coefficient #6

Matrix Coefficient #7

Matrix Coefficient #8

Matrix Coefficient #9

Matrix Coefficient #10

DCVBS Clock Select

RGB Limit Control

Burst Phase

Burst Height – Maximum

Amplitude

3F

7

6

5

4

3

2

SEL_CLK

49 7-0 BRST1

4A 7-0 BRST2

Burst Height – 1st Intermediate

Value

RGB_CLIP

GAUSS_BVP Gaussian Bypass Select

Burst Height – 2nd Intermediate

Value

SEL_PIX

C2DB_OFF

NMEH

DCVBS Output Selection

COMP2DB Offset Selection

Pedestal Height Register

NTSC-M Component

Enhancement

4B

7

NBMD

Component Blank and Sync

Level Selection

3F 1-0 CSMFMT

Color Space Matrix

Configuration

4B 6-0 PEDHGT2

Note:

1. For each register listed above, all bits not specified are

reserved and should be set to logic LOW to ensure proper

operation.

Component Pedestal Height

Subcarrier Registers

40 7-0 FREQL

41 7-0 FREQ3

Subcarrier Frequency

Control Register Deﬁnitions

Part Identiﬁcation Register (0x00)

7

6

5

4

3

2

1

0

PARTID2

Reg

Bit

Name

Description

00

7-0

PARTID2

(Read Only) 0x97

Part Identiﬁcation Register (0x01)

7

6

5

4

3

2

1

0

PARTID1

Reg

Bit

Name

Description

01

7-0

PARTID1

(Read Only) 0x21

REV. 1.0 3/26/03

37

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Part Identiﬁcation Register (0x02)

7

6

5

4

3

2

1

0

PARTID0

Reg

Bit

Name

Description

02

7-0

PARTID0

(Read Only) 0x93

Revision Identiﬁcation Register (0x03)

7

6

5

4

3

2

1

0

REVID0

Reg

Bit

Name

Description

03

7-0

REVID0

Reads back the revision number of the part.

Gamma Filters Register (0x04)

7

6

5

4

3

2

1

0

GAMENG

GAMENC

GAMSELG

GAMSELC

SRESET

SKEN

PDRM

Reg

Bit

Name

Description

Gamma Filter Enable – Green.

04

7

GAMENG

When is GAMENG is LOW, gamma filter on the Green path is bypassed.

When is GAMENG is HIGH, gamma filter on the Green path is enabled.

04

6

GAMENC

Gamma Filter Enable – Blue Red.

When GAMENC is LOW, gamma filter on the Blue and Red path is

bypassed. When GAMENC is HIGH, gamma filter on the Blue and Red path

is enabled.

04

5

GAMSELG

GAMSELC

SRESET

SKEN

Gamma Filter Selection – Green.

When GAMSELG is LOW, Green = (Green)^1/2.8

When GAMSELG is HIGH, Green = (Green) ^1/2.2

4

Gamma Filter Selection – Blue Red.

When GAMSELC is LOW, Blue = (Blue)^1/2.8, Red = (Red)^1/2.8

When GAMSELC is HIGH, Blue = (Blue) ^1/2.2,Red = (Red)^1/2.2

3

Software RESET.

When LOW, resets internal state machines and disables outputs.

When HIGH, state machines are active and outputs are enabled.

2

Data KEY Enable.

When SKEN is LOW, Data keying is disabled.

When SKEN is HIGH, Data keying is enabled.

1-0

PDRM

Pixel Data Ramping Mode. Pixel Data weighting for the rising edge of

active video.

NTSC:

PAL:

0

1/8

3/8

1/2

5/8

7/8

1

00

01

1X

Pixels are weighted on the edge.

Sample and hold the 5th pixel for the slope weighting

Hard switch

0

1

38

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

Input Format Register (0x05)

7

6

5

4

3

2

1

0

D10FF

INMODE

OMIX

SOURCE

Reg

Bit

Name

Description

YCBCR Input Formatting.

05

7

D1OFF

When D1OFF is HIGH, 64 is subtracted from Y data path of the PD port.

When D1OFF is LOW, pixel data is passed through.

05

6-4

3-2

INMODE

OMIX

Input Mode Select.

000 24 bit GBR

PD[7:0] = G PD[23:16] = B PD[15:8] = R

PD[7:0] = Y PD[23:16] = C PD[15:8] = C

R

100 24 bit YC C (4:4:4)

B

R

B

101 10 bit D1 (YC C )

PD[23:14] = YC C at 27MHz

B

R

B R

110 20 bit YC C (4:4:4)

PD[9:0] = Y PD[23:14] = C C (at 27MHz)

B

R

B

R

111 20 bit YC C (4:2:2)

PD[9:0] = Y PD[23:14] = C C

B

R

05

Overlay Mixer Select.

00

01

10

No mix – PD data is always passed

Hard mix – mixer performs a hard switch between PD and Overlay

Set1 mix – the pixel data has the following weighting on the

transition; 0, 1/2, 1

11

Set2 mix – the pixel data has the following weighting on the

transition; 0, 1/8, 1/2, 7/8, 1

1-0

SOURCE

Video Input Select. Chooses from internal test patterns or pixel data port.

00

01

10

11

PD PORT

Modulated Ramp

INTERNAL COLOR BAR (75%)

INTERNAL COLOR BAR (100%)

REV. 1.0 3/26/03

39

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

General Control Register (0x06)

7

6

5

4

3

2

1

0

FORMAT

MODE

PDCDIR

TOUT

TSOUT

Reg

Bit

Name

Description

Video Format.

06

7-6

FORMAT

00

01

10

11

NTSC

PAL – B,G,H,I,N

PAL – M

Reserved

06

5-3

MODE

Video Mode.

000 MASTER with free-running subcarrier

001 SLAVE with free-running subcarrier

010 CCIR656 with free-running subcarrier

011 GENLOCK with subcarrier phase and frequency locked to the GRS

information.

100 MASTER with subcarrier phase reset every 8 fields

101 SLAVE with subcarrier phase reset every 8 fields

110 CCIR656 with subcarrier phase reset every 8 fields.

111 DRS-Lock with subcarrier phase and frequency locked to the DRS

information.

06

2

PDCDIR

PDC Directional Control.

When PDC is LOW, the PDC pin is an output.

When PDCDIR is HIGH, the PDC pin is an input that can override the

internally generated PDC and blank the active video of a line.

06

1

0

TOUT

External Sync Output Control.

When TOUT = LOW, a MPEG style field toggle is the output on pin VSOUT.

When TOUT = HIGH, a traditional vertical sync is the output on pin VSOUT.

TSOUT

External Sync Delay Control.

When the TSOUT is LOW, HSOUT, VSOUT are delayed to match

propagation delay through the chip. When TSOUT is HIGH, HSOUT,

VSOUT are aligned with the incoming data on the PD port.

40

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

Horizontal Ancillary Data Control Register (0x07)

7

6

5

4

3

2

1

0

LDFID

SKFLIP

DDSRST

Reserved

ANCFREN

ANCPHEN

ANCTREN

Reg

Bit

Name

Description

07

7

LDFID

Field Lock Select. When LDFID is HIGH, the FLD[2:0] pins are used as

inputs to lock the field the that the TMC2193 is encoding. 5 PXCK’s after

the falling edge of HSIN the FLD[2:0] pins are sampled. When LDFID is

LOW, the FLD[2:0] pins output the current field that is being encoded.

6

5

SKFLIP

Soft Key Inversion.

When SKFLP is LOW, the key generated by the data keying is a normal

state. When SKFLP is HIGH, the key generated by the data keying is a

inverted state.

DDSRST

DDS Reset. By inserting a logic HIGH into this register the DDS

accumulator is reset to SYSPH value at the start of the next field 1 and

DDSRST is reset LOW. This enables the DDS to be reset when the

encoder is operating with a free running subcarrier.

07

4-3

2

Reserved

ANCFREN

Ancillary Frequency Enable.

When HIGH, the encoder gets subcarrier frequency data (FREQ3-0) from

incoming ancillary data (in accordance with FRV bit). When LOW,

FREQ3-0 registers contain the subcarrier frequency data.

07

1

0

ANCPHEN

ANCTREN

Ancillary Phase Enable.

When HIGH, the encoder gets subcarrier phase offset data (SCHPHL and

SCHPHM) from incoming ancillary data (in accordance with PHV bit).

When LOW, a default value of 0000h is used for subcarrier phase.

Ancillary Timing Enable.

When HIGH, the encoder decodes incoming ancillary data to determine

video timing (FIELD and SVF). When LOW, the ancillary timing reference

data is ignored.

Ancillary Data ID Register (0x08)

7

6

5

4

3

2

1

0

ANCID

Reg

Bit

Name

Description

08

7-0

ANCID

Ancillary Data Identification.

Bits 7-0 determine the ancillary data identification. Bit 0 is an odd parity bit.

The value in this register must match that of the incoming ancillary data.

REV. 1.0 3/26/03

41

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Keying/Overlay Engine Register (0x09)

7

6

5

4

3

2

1

0

HKEN

BUKEN

SKEXT

DKDIS

EKDIS

FKDIS

LAYMODE

Reg

Bit

Name

Description

09

7

HKEN

Hardware KEY Enable.

When LOW, the KEY pin is ignored.

When HIGH, the KEY pin is enabled.

6

BUKEN

SKEXT

DKDIS

Burst KEY Enable.

When LOW, the output video burst is generated internally.

When HIGH, the output video burst is taken from the CVBS port.

5

Data KEY Operation Select.

When LOW, data keying is allowed only during active video window.

When HIGH, data keying is allowed during frame.

4

Green/Y Data KEY Disable.

When LOW, Green/Y input data is enabled for data keying.

When HIGH, Green/Y input data is ignored for data keying.

3

EKDIS

Blue/C Data KEY Disable.

B

When LOW, Blue/C input data is enabled for data keying.

B

When HIGH, Blue/C input data is ignored for data keying.

B

2

FKDIS

Red/C Data KEY Disable.

R

When LOW, Red/C input data is enabled for data keying.

R

When HIGH, Red/C input data is ignored for data keying.

R

1-0

LAYMODE

Layer Assignment Select.

BACKGND

Mode Source

MIDGND

Source

FOREGND

Source

Key

0

1

2

3

PD

OVERLAY

CVBS

0L4-0

KEY

CVBS

KEY

PD

OVERLAY

PD

OL4-0

KEY

CVBS

OVERLAY

PD

OL4-0

KEY

OVERLAY

OL4-0

42

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

Key Value Register (0x0A)

7

6

5

4

3

2

1

0

DKEYMAX

Reg

Bit

Name

Description

0A

7-0

DKEYMAX

Green/Y Maximum Data Key Value.

DKEYMAX is compared against the 8 MSB’s of Green/Y channel. If

DKEYMAX is greater or equal to Green/Y and DKEYMIN less than Green/Y

then a match is signaled.

Key Value Register (0x0B)

7

6

5

4

3

2

1

0

DKEYMIN

Reg

Bit

Name

Description

0B

7-0

DKEYMIN

Green/Y Minimum Data Key Value.

DKEYMIN is compared against the 8 MSB’s of Green/Y channel. If

DKEYMAX is greater or equal to Green/Y and DKEYMIN less than Green/Y

then a match is signaled.

Key Value Register (0x0C)

7

6

5

4

3

2

1

0

EKEYMAX

Reg

Bit

Name

Description

0C

7-0

EKEYMAX

Blue/C Maximum Data Key Value.

B

EKEYMAX is compared against the 8 MSB’s of Blue/C channel. If

B

EKEYMAX is greater or equal to Blue/C and EKEYMIN less than Blue/C

B

then a match is signaled.

Key Value Register (0x0D)

7

6

5

4

3

2

1

0

EKEYMIN

Reg

Bit

Name

Description

0D

7-0

DKEYMIN

Blue/C Minimum Data Key Value.

B

EKEYMIN is compared against the 8 MSB’s of Blue/C channel. If

B

EKEYMAX is greater or equal to Blue/C and EKEYMIN less than Blue/C

B

then a match is signaled

REV. 1.0 3/26/03

43

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Key Value Register (0x0E)

7

6

5

4

3

2

1

0

FKEYMAX

Reg

Bit

Name

Description

0E

7-0

FKEYMAX

Red/C Maximum Data Key Value.

R

FKEYMAX is compared against the 8 MSB’s of Red/C channel. If

R

FKEYMAX is greater or equal to Red/C and FKEYMIN less than Red/C

R

then a match is signaled.

Key Value Register (0x0F)

7

6

5

4

3

2

1

0

FKEYMIN

Reg

Bit

Name

Description

0F

7-0

FKEYMIN

Red/C Minimum Data Key Value.

R

FKEYMIN is compared against the 8 MSB’s of Red/C channel. If

R

FKEYMAX is greater or equal to Red/C and FKEYMIN less than Red/C

R

then a match is signaled.

44

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

DAC Control Register (0x10)

7

6

5

4

3

2

1

0

DAC4DIS

DAC3DIS

DAC2DIS

DAC1DIS

Reserved

OLUTDIS

OUTMODE

Reg

Bit

Name

Description

D/A #4 Disable.

When DAC4DIS is LOW, the COMPOSITE D/A is enabled.

10

7

6

5

4

DAC4DIS

When DAC4DIS is HIGH, the COMPOSITE D/A is disabled.

DAC3DIS

DAC2DIS

DAC1DIS

D/A #3 Disable.

When DAC3DIS is LOW, the CHROMA /P /R D/A is enabled.

When DAC3DIS is HIGH, the CHROMA /P /R D/A is disabled.

R

D/A #2 Disable.

When DAC2DIS is LOW, the LUMA/P /B D/A is enabled.

When DAC2DIS is HIGH, the LUMA/P /B D/A is disabled.

B

D/A #1 Disable.

When DAC1DIS is LOW, the COMP/Y/G and reference D/A is enabled.

When DAC1DIS is HIGH, the COMP/Y/G and reference D/A is disabled.

10

3

2

Reserved

OLUTDIS

Set to 0.

Overlay LUT Disable.

When OLUTDIS is LOW, the olut is enabled.

When OLUTDIS is HIGH, the olut is disabled.

10

1-0

OUTMODE

Output Modes.

Bit[1:0]

00

01

10 (ext. sync)

11 (sync on G)

DAC1

Y

Comp1

Green

DAC2

DAC3

DAC4

P

Comp2

B

R

Y

Blue

C

Red

REV. 1.0 3/26/03

45

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

DAC Control Register (0x11)

7

6

5

4

3

2

1

0

DRSSEL

OFMT

COMP2DB

SINEN

REFSEL

LUMDIS

CHRMDIS

BURSTDIS

Reg

Bit

Name

Description

DRS Selection.

11

7

6

5

DRSSEL

When DRSSEL is HIGH, PD[7:0] is routed to the DRS detection block.

When DRSSEL is LOW, CVBS[9:2] is routed to the DRS detection block.

OFMT

Component Data Formatting.

When OFMT is LOW, the MSB’s of blue and red component data paths are

inverted to center the data around a D\A code of 512.

COMP2DB.

Composite 2 Overflow Control.

When COMP2DB is HIGH, the digital range of the composite sumer is 0 to

2047 with half the digital resolution. When COMP2DB is LOW, the digital

output of the composite summer is 0 to 1023, all values exceeding 1023 or

below 0 are clipped.

11

4

3

2

1

0

SINEN

X/Sine(X) Filter Enable.

When SINEN is LOW, the X/Sin(X) filter is bypassed.

When SINEN is HIGH, the X/Sin(X) filter is used to compensate for the

DAC roll-off at high frequencies.

REFSEL

LUMDIS

CHRMDIS

BURSTDIS

Reference DAC Output Selection.

When REFSEL is LOW, a composite sync is the output of the REFDAC.

When REFSEL is HIGH, a reference level equal to the DAC1’s midpoint is

the output of the REFDAC.

Luma Disable.

When LUMDIS is LOW, the luminance data on the composite data path is

enabled. When LUMDIS is HIGH, the luminance data on the composite

data path is disabled.

Chroma Disable.

When CHRMDIS is LOW, the chrominance data on the composite data

path is enabled. When CHRMDIS is HIGH, the chrominance data on the

composite data path is disabled.

Burst Disable.

When BURSTDIS is LOW, the burst is enabled.

When BURSTDIS is HIGH, the burst is disabled.

46

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

VBI Ped Enable Register (0x14)

7

6

5

4

3

2

1

0

VBIPEDEM

Reg

Bit

Name

Description

14

7-0

VBIPEDEM

VBI Pedestal Enable, Even Fields.

VBIPEDEM is the bits 15-8 of VBIPEDE[15:0]. VBIPEDE controls the

addition of pedestal on a line by line basis from line 10 in NTSC

(VBIPEDE[0] = HIGH) to line 24 (VBIPEDE[14] = HIGH) in the EVEN field

of NTSC. VBIPEDE[15] controls the pedestal from line 25 to line 263

inclusive.

VBI Ped Enable Register (0x15)

7

6

5

4

3

2

1

0

VBIPEDEL

Reg

Bit

Name

Description

15

7-0

VBIPEDEL

VBI Pedestal Enable, Even Fields.

VBIPEDEL is the bits 7-0 of VBIPEDE[15:0]. VBIPEDE controls the

addition of pedestal on a line by line basis from line 10 in NTSC

(VBIPEDE[0] = HIGH) to line 24 (VBIPEDE[14] = HIGH) in the EVEN field

of NTSC. VBIPEDE[15] controls the pedestal from line 25 to line 263

inclusive.

VBI Ped Enable Register (0x16)

7

6

5

4

3

2

1

0

VBIPEDOM

Reg

Bit

Name

Description

16

7-0

VBIPEDOM

VBI Pedestal Enable, Odd Fields.

VBIPEDOM is the bits 14-7 of VBIPEDO[14:0]. VBIPEDO controls the

addition of pedestal on a line by line basis from line 273 (VBIPEDE[0] =

HIGH) to line 286 (VBIPEDE[13] = HIGH) in the ODD field of NTSC.

VBIPEDO[14] controls the pedestal from line 287 to line 525 inclusive.

REV. 1.0 3/26/03

47

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

VBI Ped Enable Register (0x17)

7

6

5

4

3

2

1

0

VBIPEDOL

HVA

Reg

Bit

Name

Description

VBI Pedestal Enable, Odd Fields.

17

7-1

VBIPEDOM

VBIPEDOL is the bits 6-0 of VBIPEDO[14:0]. VBIPEDO controls the

addition of pedestal on a line by line basis from line 273 (VBIPEDE[0] =

HIGH) to line 286 (VBIPEDE[13] = HIGH) in the ODD field of NTSC.

VBIPEDO[14] controls the pedestal from line 287 to line 525 inclusive.

17

0

HVA

Horizontal and Vertical Sync Alignment.

When HVA is LOW, the falling edge of HSIN and VSIN must occur just prior

to the rising edge of PXCK to start an field 1. When HVA is HIGH, VSIN is

allowed to vary from HSIN by 32 pixels.

Vertical Blanking Interval Enable Register (0x18)

7

6

5

4

3

2

1

0

Reserved

GLKCTL1

GLKCTL0

VBIENF1

Reg

Bit

Name

Description

18

7

6

Reserved

GLKCTL1

Genlock Control Register 1.

When GLKCTL1 is LOW, the PALODD bit of the GRS stream is ignored.

When GLKCTL1 is HIGH, the PALODD bit of the GRS stream controls the

PALODD flip of the subcarrier.

18

5

GLKCTL0

VBIENF

Genlock Control Register 0.

When GLKCTL0 is LOW, the Color Frame bit of the GRS stream is ignored.

When GLKCTL0 is HIGH, the Color Frame bit of the GRS stream controls

the field sequence in the FVHGEN.

4-0

VBI Active Video Enable, Field 1.

The value of VBIENF1 determines which line blanking stops and active line

for EVEN fields in NTSC starting from line 4 to line 35 or an ODD fields for

PAL starting from line 1 to line 32.

48

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

Vertical Blanking Interval Enable Register (0x19)

7

6

5

4

3

2

1

0

SHORT

T512

HALFEN

VBIENF2

Reg

Bit

7

Name

SHORT

T512

Description

19

Test Register. Program LOW.

6

EH/SL Offset Control Bit.

When LOW, the true value of EH and SL is offset by 256.

When HIGH, the true value of EH and SL is offset by 512.

19

5

HALFEN

VBIENF2

Half Line Enable.

When LOW, half-line blanking occurs on line 283 (NTSC) or line 23 (PAL).

When HIGH, line 283 (NTSC) or line 23 (PAL) is treated as a full line of

active video.

4-0

VBI Active Video Enable, Field 2.

The value of VBIENF2 determines which line blanking stops and active line

for ODD fields in NTSC starting from line 4 to line 35 or an EVEN fields for

PAL starting from line 1 to line 32.

Pedestal Height Register (0x1A)

7

6

5

4

3

2

1

0

Reserved

PEDHGT1

Reg

Bit

Name

Description

1A

7

Reserved

PEDHGT1

6-0

Composite Pedestal Height.

PEDHGT1 is a 2’s comp value producing a pedestal height from -22.1 IRE

to 21.7 IRE with .345 IRE steps on the composite data path. The default 7.5

IRE pedestal for NTSC-M results from a hex code of 0010110b.

Closed Caption Register (0x1C)

7

6

5

4

3

2

1

0

CCD1

Reg

Bit

Name

Description

1C

7-0

CCD1

First Byte of CC Data.

Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if

CCPAR is HIGH.

REV. 1.0 3/26/03

49

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Closed Caption Register (0x1D)

7

6

5

4

3

2

1

0

CCD2

Reg

Bit

Name

Description

1D

7-0

CCD2

Second Byte of CC Data.

Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if

CCPAR is HIGH

Closed Caption Register (0x1E)

7

6

5

4

3

2

1

0

CCON

CCRTS

CCPAR

CCFLD

CCLINE

Reg

Bit

Name

Description

Enable CC Data Packet.

1E

7

CCON

Command the CC data generator to send either CC data or a NULL byte

whenever the specified line is transmitted.

1E

6

5

CCRTS

CCPAR

Request To Send Data.

This bit is set HIGH by the user when bytes 0x1C and 0x1D have been

loaded with the next two bytes to be sent. When the encoder’s line count

reaches preceding the line specified in bits 4-0 of this register the data will

be transferred from registers 0x1C and 0x1D, and RTS will be RESET

LOW. A new pair of bytes may then be loaded into registers 0x1C and

0x1D. If CCON = 1 and CCRTS = 0 when the CC line is to be sent, NULL

bytes will be sent.

1E

Auto Parity Generation.

When set HIGH, the encoder replaces the MSB of bytes 0x1C and 0x1D

with a calculated ODD parity. When set LOW, the CC processor transmits

the 16 bits exactly as loaded into registers 0x1C and 0x1D.

1E

4

CCFLD

CC Field Select.

When LOW, CC data is transmitted on the selected line of ODD fields.

When HIGH, it is sent on EVEN fields.

3-0

CCLINE

CC Line Select.

Defines (with an offset) the line on which CC data are transmitted.

Timing Register (0x1F)

7

6

5

4

3

2

1

0

PDCNT

Reg

Bit

Name

Description

1F

7-0

PDCNT

Pixel Data Control Start.

PDCNT determines the number of pixels (PCK’s) from the midpoint of the

falling edge of horizontal sync to the rising edge of PDC on active video

lines.

50

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

Timing Register (0x20)

7

6

5

4

3

2

1

0

SY

Reg

Bit

Name

Description

20

7-0

SY

Horizontal Sync Tip Duration.

This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Timing Register (0x21)

7

6

5

4

3

2

1

0

BR

Reg

Bit

Name

Description

21

7-0

BR

Breezeway Duration.

This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Timing Register (0x22)

7

6

5

4

3

2

1

0

BU

Reg

Bit

Name

Description

22

7-0

BU

Burst Duration.

This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Timing Register (0x23)

7

6

4

3

2

1

0

CBP

Reg

Bit

Name

Description

23

7-0

CBP

Color Back Porch Duration.

This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Timing Register (0x24)

7

6

4

3

2

1

0

XBP

Reg

Bit

Name

Description

24

7-0

CBP

Extended Color Back Porch Duration.

This 8 bit register holds the LSB’s of a 10 bit value extending from 0 to 1023

PCK cycles.

REV. 1.0 3/26/03

51

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Timing Register (0x25)

7

6

5

4

3

2

1

0

VA

Reg

Bit

Name

Description

25

7-0

VA

Active Video Region Duration.

This 8 bit register holds the LSB’s of a 10 bit value extending from 0 to 1023

PCK cycles.

Timing Register (0x26)

7

6

5

4

3

2

1

0

VC

Reg

Bit

Name

Description

26

7-0

VC

Active Video Region 2^ndHalf Line Duration.

This 8 bit register holds the LSB’s of a 10 bit value extending from 0 to 1023

PCK cycles.

Timing Register (0x27)

7

6

5

4

3

2

1

0

VB

Reg

Bit

Name

Description

27

7-0

VB

Active Video Region 1^stHalf Line Duration.

This 8 bit register holds the LSB’s of a 10 bit value extending from 0 to 1023

PCK cycles.

Timing Register (0x28)

7

6

5

4

3

2

1

0

VB

Reg

Bit

Name

Description

28

7-0

EL

Equalization Pulse Low Duration.

This 8 bit register holds a value extending from 0 to 255 PCK cycles.

52

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

Timing Register (0x29)

7

6

5

4

3

2

1

0

EH

Reg

Bit

Name

Description

29

7-0

EH

Equalization Pulse High Duration.

This 8 bit register holds 8 LSB’s of EH, The addition of 256 or 512 is

controlled by T512. The range is either 256 to 511 PCK cycles or 512 to

767 PCK cycles.

Timing Register (0x2A)

7

6

5

4

3

2

1

0

SL

Reg

Bit

Name

Description

2A

7-0

SL

Vertical Sync Pulse Low Duration.

This 8 bit register holds 8 LSB’s of SL, The addition of 256 or 512 is

controlled by T512. The range is either 256 to 511 PCK cycles or 512 to

767 PCK cycles.

Timing Register (0x2B)

7

6

5

4

3

2

1

0

SH

Reg

Bit

Name

Description

2B

7-0

SH

Vertical Sync Pulse High Duration.

This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Timing Register (0x2C)

7

6

5

4

3

2

1

0

FP

Reg

Bit

Name

Description

2C

7-0

FP

Front Porch Duration.

This 8 bit register holds a value extending from 0 to 255 PCK cycles.

REV. 1.0 3/26/03

53

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Timing Register (0x2D)

7

6

5

4

3

2

1

0

XBP

Bit

VA

VB

VC

Reg

Name

Description

Extended Color Back Porch Duration.

2 MSB’s of the 10 bit XBP, extending from 0 to 1023 PCK cycles.

2D

7-6

5-4

3-2

1-0

XBP

2D

VA

VB

VC

Active Video Duration.

2 MSB’s of the 10 bit VA, extending from 0 to 1023 PCK cycles.

Active Video Region 1^stHalf Line Duration.

2 MSB’s of a 10 bit VB, extending from 0 to 1023 PCK cycles.

Active Video Region 2^ndHalf Line Duration.

2 MSB’s of a 10 bit VC, extending from 0 to 1023 PCK cycles.

Timing Register (0x2E)

7

6

5

4

3

2

1

0

FIELD

LTYPE

Reg

Bit

Name

Description

2E

7-5

FIELD

Field Identification. (READ ONLY)

These three bits are updated 12 PXCK periods after each vertical sync.

They allow the user to determine field type on a continuous basis

2E

4-0

LTYPE

LineType Identification (READ ONLY)

These three bits are updated 5 PXCK periods after each horizontal sync.

They allow the user to determine line type on a continuous basis.

Timing Register (0x2F)

7

6

5

4

3

2

1

0

CBL

Reg

Bit

Name

Description

2F

7-0

CBL

Color Bar Duration.

This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Color Space Matrix Register (0x30)

7

6

5

4

3

2

1

0

MCF1L

Reg

Bit

Name

Description

30

7-0

MCF1L

Matrix Coefficient #1.

Bits 7-0 of MCF1.

54

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

Color Space Matrix Register (0x31)

7

6

5

4

3

2

1

0

MCF2L

Reg

Bit

Name

Description

31

7-0

MCF2L

Matrix Coefficient #2.

Bits 7-0 of MCF2.

Color Space Matrix Register (0x32)

7

6

5

4

3

2

1

0

MCF3L

Reg

Bit

Name

Description

32

7-0

MCF3L

Matrix Coefficient #3.

Bits 7-0 of MCF3.

Color Space Matrix Register (0x33)

7

6

5

4

3

2

1

MCF4L

Reg

Bit

Name

Description

33

7-0

MCF4L

Matrix Coefficient #4.

Bits 7-0 of MCF4.

Color Space Matrix Register (0x34)

7

6

5

4

MCF5L

Reg

Bit

Name

Description

34

7-0

MCF4L

Matrix Coefficient #5.

Bits 7-0 of MCF5.

Color Space Matrix Register (0x35)

7

6

5

4

0

MCF6L

Reg

Bit

Name

Description

35

7-0

MCF6L

Matrix Coefficient #6.

Bits 7-0 of MCF6.

REV. 1.0 3/26/03

55

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Color Space Matrix Register (0x36)

7

6

5

4

3

2

1

0

MCF7L

Reg

Bit

Name

Description

36

7-0

MCF7L

Matrix Coefficient #7.

Bits 7-0 of MCF7.

Color Space Matrix Register (0x37)

7

6

5

4

MCF8L

Reg

Bit

Name

Description

37

7-0

MCF8L

Matrix Coefficient #8.

Bits 7-0 of MCF8.

Color Space Matrix Register (0x38)

7

6

5

4

MCF9L

Reg

Bit

Name

Description

38

7-0

MCF9L

Matrix Coefficient #9.

Bits 7-0 of MCF9.

Color Space Matrix Register (0x39)

7

6

5

4

MCF10L

Reg

Bit

Name

Description

39

7-0

MCF10L

Matrix Coefficient #10.

Bits 7-0 of MCF10.

Color Space Matrix Register (0x3A)

7

6

5

4

MCF1M

MCF2M

Reg

Bit

Name

Description

3A

7-4

MCF1M

Matrix Coefficient #1.

Bits 11-8 of MCF1.

3A

3-0

MCF2M

Matrix Coefficient #2.

Bits 11-8 of MCF2.

56

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

Color Space Matrix Register (0x3B)

7

6

5

4

3

2

1

0

MCF3M

Reserved

MCF4M

Reg

Bit

Name

Description

3B

7-4

MCF3M

Matrix Coefficient #3.

Bits 11-8 of MCF3.

3B

3

Reserved

MCF4M

Set to 0.

2-0

Matrix Coefficient #4.

Bits 10-8 of MCF4.

Color Space Matrix Register (0x3C)

7

6

5

4

3

2

1

0

MCF5M

Reserved

MCF6M

Reg

Bit

Name

Description

3C

7-4

MCF5M

Matrix Coefficient #5.

Bits 11-8 of MCF5.

3C

3

Reserved

MCF6M

Set to 0.

2-0

Matrix Coefficient #6.

Bits 10-8 of MCF6.

Color Space Matrix Register (0x3D)

7

6

5

4

3

2

1

0

MCF7M

MCF8M

Reg

Bit

Name

Description

3D

7-4

MCF7M

Matrix Coefficient #7.

Bits 11-8 of MCF7.

3D

3-0

MCF8M

Matrix Coefficient #8.

Bits 11-8 of MCF8.

Color Space Matrix Register (0x3E)

7

6

5

4

3

2

1

0

MCF9M

MCF10M

Reg

Bit

Name

Description

3E

7-4

MCF9M

Matrix Coefficient #9.

Bits 11-8 of MCF9.

3E

3-0

MCF10M

Matrix Coefficient #10.

Bits 11-8 of MCF10.

REV. 1.0 3/26/03

57

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Color Space Matrix Register (0x3F)

7

6

5

4

3

2

1

0

SEL_CLK

RGB_CLIP

GAUSS_BYP

SEL_PIX

C2DB_OFF

NMEH

CSMFMT

Reg

Bit

Name

Description

DCVBS Output Selection.

3F

7

SEL_PIX

When SEL_PIX is HIGH, the interpolated pixel data is selected as the

output for the DCVBS port. When SEL_PIX is LOW, the non-interpolated

pixel data is selected as the output for the DCVBS port.

3F

6

RGB_CLIP

RGB Limit Control.

When RGB_CLIP is LOW, the RGB outputs are not limited.

When RGB_CLIP is HIGH, the RGB outputs are limited to a range of 256 to

1023 at the DAC outputs.

3F

5

4

3

GAUSS_BYP

SEL_CLK

Gaussian Bypass Select.

When GAUSS_BYP is LOW, the gaussian filter is enabled.

When GAUSS_BYP is HIGH, the gaussian filter is bypassed.

DCVBS Clock Select.

When SEL_CLK is LOW, the DCVBS output is clocked at the PXCK.

When SEL_CLK is HIGH, the DCVBS output is clocked at the PCK.

C2DB_OFF

COMP2DB Offset Selection.

When C2DB_OFF is HIGH an offset of 256 is added to the COMP2 output

allowing the chrominance data that extends below the sync level to be

passed through the outputs.

3F

2

NMEH

NTSC-M Component Enhancement.

When NMEH is LOW, the CSM performs the normal rounding operation on

multipliers 8, 9 , and 10. When NMEH is HIGH, the CSM extends the

number of rounding bits on multipliers 8, 9, and 10. This is recommended if

the input source is YC C and the component output is RGB.

B

R

1-0

CSMFMT

Color Space Matrix Configuration.

CSMFMT

Input

YC C

Component Output

00

01

10

11

YP P

B

R

B R

RGB

YP P

YC C

B

RGB

B R

RGB

Subcarrier Register (0x40)

7

6

5

4

3

2

1

0

FREQL

Reg

Bit

Name

Description

Subcarrier Frequency.

Bits 7-0 of the subcarrier frequency FREQL[31:0].

40

7-0

FREQL

58

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

Subcarrier Register (0x41)

7

6

5

4

3

2

1

0

FREQ3

Reg

Bit

Name

Description

41

7-0

FREQ3

Subcarrier Frequency.

Bits 15-8 of the subcarrier frequency FREQL[31:0].

Subcarrier Register (0x42)

7

6

5

4

3

2

1

0

FREQ2

Reg

Bit

Name

Description

42

7-0

FREQ2

Subcarrier Frequency.

Bits 23-16 of the subcarrier frequency FREQL[31:0].

Subcarrier Register (0x43)

7

6

5

4

3

2

1

FREQM

Reg

Bit

Name

Description

43

7-0

FREQM

Subcarrier Frequency.

Bits 31-24 of the subcarrier frequency FREQL[31:0].

Subcarrier Register (0x44)

7

6

4

3

2

SYSPHL

Reg

Bit

Name

Description

44

7-0

SYSPHL

System Phase.

Bits 7-0 of the video phase offset SYSPH[15:0].

Subcarrier Register (0x45)

7

6

4

3

2

0

SYSPHM

Reg

Bit

Name

Description

45

7-0

SYSPHM

System Phase.

Bits 15-8 of the video phase offset SYSPH[15:0].

REV. 1.0 3/26/03

59

TMC2193

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Subcarrier Register (0x46)

7

6

5

4

3

2

1

0

BURPHL

Reg

Bit

Name

Description

46

7-0

BURPHL

Burst Phase.

Bits 7-0 of the burst phase offset BURPH[15:0].

Subcarrier Register (0x47)

7

6

5

4

3

2

1

0

BURPHM

Reg

Bit

Name

Description

47

7-0

BURPHM

Burst Phase.

Bits 15-8 of the burst phase offset BURPH[15:0].

Burst Height Register (0x48)

7

6

5

4

3

2

1

0

BRSTFULL

Reg

Bit

Name

Description

48

7-0

BRSTFULL

Burst Height – Maximum Amplitude.

The 8 bit value assigned to U burst component in NTSC and to the U and V

components in PAL for the maximum burst amplitude. The burst envelopes

midpoint is derived from BRSTFULL. The value programmed into

BRSTFULL needs to be .707 of the magnitude of the burst vector.

Burst Height Register (0x49)

7

6

5

4

3

2

1

0

BRST1

Reg

Bit

Name

Description

49

7-0

BRST1

Burst Height – 1st Intermediate Value.

The 8 bit value assigned to U burst component in NTSC and to the U and V

components in PAL for the first intermediate value of the burst envelope.

The value programmed into BRST1 needs to be .707 of the magnitude of

the burst vector.

60

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Control Register Deﬁnitions (continued)

Subcarrier Register (0x4A)

7

6

5

4

3

2

1

0

BRST2

Reg

Bit

Name

Description

4A

7-0

BRST2

Burst Height – 2nd Intermediate Value.

The 8 bit value assigned to U burst component in NTSC and to the U and V

components in PAL for the second intermediate value of the burst

envelope. The value programmed into BRST2 needs to be .707 of the

magnitude of the burst vector.

Pedestal Height Register (0x4B)

7

6

5

4

3

2

1

0

NBMD

PEDHGT2

Reg

Bit

Name

Description

4B

7

NBMD

Component Blank and Sync Level Selection.

When NBMD is LOW, the blank level for Y or RGB is 256 and the sync level

is 12. When NMBD is HIGH, the blank level for Y or RGB is a D/A code of

240 and the sync level is a D\A code of 8.

4B

6-0

PEDGHT2

Component Pedestal Height.

PEDHGT2 is a 2’s comp value producing a pedestal height from -22.1 IRE

to 21.7 IRE with .345 IRE steps of the luminance data of the YP P

B R

component output.

REV. 1.0 3/26/03

61

TMC2193

PRODUCT SPECIFICATION

Absolute Maximum Ratings (beyond which the device may be damaged)

Parameter

Min.

Max.

Unit

Power Supply Voltage

-0.5

7.0

V

Digital Inputs

Applied Voltage²

Forced Current^3,4

-0.5

V

+ 0.5

V

DD

-20.0

20.0

mA

Digital Outputs

Applied Voltage²

-0.5

+ 0.5

V

DD

Forced Current^3,4

-20.0

20.0

1

mA

Short Circuit Duration (Single Output in HIGH state to GND)

Analog Output Short Circuit Duration (Single output to GND)

Temperature

second

Inﬁnite

Operating, Ambient

-20

-65

+110

+150

+300

+220

+150

°C

Operating, Junction, Plastic package

Lead, Soldering (10 seconds)

Vapor Phase Soldering (1 minute)

Storage

Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating

conditions. Functional operation under any of these conditions is NOT implied.

2. Applied voltage must be current limited to specified range, and measured with respect to GND.

3. Forcing voltage must be limited to specified range.

4. Current is specified as conventional current, flowing into the device.

Operating Conditions

Parameter

Min.

4.75

2.0

Nom.

Max.

Units

V

Power Supply Voltage

5.0

5.25

DD

IH

Input Voltage, Logic HIGH

TTL Compatible Inputs

CMOS Compatible Inputs

TTL Compatible Inputs

CMOS Compatible Inputs

V

DD

V

DD

V

0.7V

DD

V

IL

Input Voltage, Logic LOW

GND

0.8

V

0.3V

V

DD

I

Output Current, Logic HIGH

Output Current, Logic LOW

External Reference Voltage

-2.0

mA

V

OH

4.0

OL

V

1.235

1.020

REF

I

D/A Converter Reference Current (I

REF

= V

REF

/ R

,

mA

REF

flowing out of the R

pin)

REF

R

Reference Resistor, V

REF

= Nom.

1210

37.5

Ω

REF

OUT

A

Total Output Load Resistance

Ambient Temperature, Still Air

T

0

70

°C

Pixel Interface

f

t

Pixel Rate

10

20

15

30

Mpps

MHz

ns

PXL

Master Clock Rate, 2x pixel rate

PXCK Pulse Width, HIGH

PXCK Pulse Width, LOW

PXCK

PWHPX

PWLPX

15

17.5

ns

62

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Operating Conditions (continued)

Parameter

Min.

16

0

Nom.

Max.

Units

ns

t

Setup Time

Hold Time

SP

HP

ns

Parallel Microprocessor Interface

t

CS Pulse Width, LOW

CS Pulse Width, HIGH

Address Setup Time

Address Hold Time

4

6

PXCK

ns

PWLCS

PWHCS

SA

17

0

ns

HA

Data Setup Time (write)

Data Hold Time (write)

RESET Setup Time

RESET Hold Time

16

0

ns

SD

ns

HD

12

2

ns

SR

ns

HR

Serial Interface

t

SCL Pulse Width, LOW

1.3

0.6

1.3

300

µs

ns

D/AL

SCL Pulse Width, HIGH

D/AH

STAH

STASU

STOSU

BUFF

DSU

SDA Start Hold Time

SCL to SDA Setup Time (Stop)

SCL to SDA Setup Time (Start)

SDA Stop Hold Time Setup

SDA to SCL Data Setup Time

SDA to SCL Data Hold Time

DHO

REV. 1.0 3/26/03

63

TMC2193

PRODUCT SPECIFICATION

Electrical Characteristics

Symbol

Parameter

Conditions

Min.

Typ.

335

15

Max.

375

25

Units

mA

I

Power Supply Current

V

DD

= Max., f

= 27MHz

DD

PXCK

I

Power Supply Current

(D/A disabled)

V

= Max., f

mA

DDQ

V

Voltage Reference Output

1.235

50

V

µA

V

RO

I

Input Bias Current, V

REF

V

= Nom.

BR

REF

Input Current, Logic HIGH

Input Current, Logic LOW

Output Voltage, Logic HIGH

Output Voltage, Logic LOW

Hi-Z Leakage current, HIGH

Hi-Z Leakage current, LOW

Digital Input Capacitance

Digital Output Capacitance

= Max., V = V

IN DD

10

IH

IL

DD

= Max., V = GND

IN

-10

V

I

= Max.

2.4

OH

OL

OH

OL

= Max.

0.4

10

V

I

V

DD

V

DD

= Max., V = V

IN DD

µA

pF

V

OZH

OZL

= Max., V = GND

IN

-10

10

C

T = 25°C, f = 1MHz

A

4

I

T = 25°C, f = 1MHz

A

10

O

V

Video Output Compliance

Voltage

-0.3

2.0

25

OC

R

C

Video Output Resistance

Video Output Capacitance

15

kΩ

OUT

I

= 0 mA, f = 1 MHz

pF

OUT

Notes:

1. Typical I

with V = +5.0 Volts and T = 25°C.

DD A

DD

2. Timing reference points are at the 50% level.

Switching Characteristics

Parameter

Conditions

Min.

Typ. Max.

Units

PIPES

Pipeline Delay

PD to Analog Out

PD to DCVBS

64

66

PXCK

Periods

t

Output Delay, CS to low-Z

Output Delay, CS to Data Valid

Output Hold Time, CS to hi-Z

Output Delay

4

15

ns

DOZ

DOM

HOM

DO

10

PXCK to HSOUT, VSOUT,

PDC, LINE, FLD

15

t

D/A Output Current Risetime

D/A Output Current Falltime

Analog Output Delay

10% to 90% of full-scale

90% to 10% of full-scale

2

ns

R

F

10

DOV

Notes:

1. Timing reference points are at the 50% level.

2. Analog C <10 pF, D load <40 pF.

LOAD 7-0

3. Pipeline delay, with respect to PXCK, is a function of the phase relationship between the internally generated PCK (PXCK/2)

and PXCK, as established by the hardware RESET.

64

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

System Performance Characteristics

Parameter

RES D/A Converter Resolution

Conditions

Min.

Typ.

Max.

10

Units

Bits

%

10

E

Integral Linearity Error

0.25

0.10

LI

Differential Linearity Error

(monotonic)

%

LD

E

Gain Error

7.5

%FS

degree

%

G

dp

Differential Phase

Differential Gain

PXCK = 27.00 MHz,40 IRE Ramp

0.5

0.9

0

dg

SKEW

CHROMA to LUMA Output

Skew

1

ns

PSRR

Power Supply Rejection

Ratio

f=1kHz

0.5

%/%V

DD

Notes:

1. TTL input levels are 0.0 and 3.0 Volts, 10%-90% rise and fall times <3 ns.

2. Analog CLOAD <10 pF, D7-0 load <40 pF.

The circuit in Figure 31 shows the connection of power sup-

ply voltages, output reconstruction ﬁlters and the external

Applications Discussion

The suggested output reconstruction ﬁlter is shown in Figure

29. The phase and frequency response for the encoder and

the reconstruction ﬁlter is shown in Figure 30.

voltage reference. All V

same power source.

pins should be connected to the

DD

The full-scale output voltage level for each D/A:

= I x R = K x I x R

C6

27pF

V

OUTx

OUTx Lx REFx

Lx

D1

DIODE

SCHOTTKY

= K x (V /R ) x R

REF REFx Lx

L5 1.8µH

A_IN

A_OUT

where:

C7

D2

R8

75Ω

330pF

DIODE

SCHOTTKY

• I

is the full-scale output current sourced by the D/A

converter.

OUTx

C8

100pF

L6

1.0µH

R9

75Ω

• R is the resistive load on the D/A output pin.

Lx

65-6294-31

• K is a constant for the TMC2193 D/A converters (approx-

imately equal to 34).

Figure 29. Typical Analog Reconstruction Filter

• I

REFx

is the reference current ﬂowing out of the R

REFx

pin to ground.

• V

is the voltage measured on the V pin.

REF

0

-10

-20

-30

-40

0

• R

R

is the total resistance connected between the

pin and ground.

REFx

90

The reference voltage in Figure 31 is from an LM185 1.2

Volt band-gap reference. The suggested trim is designed to

give 10% of trim around 5K Ohms. This R

"gain" for that D/A converter. Varying R

REFx

cause the full-scale output voltage on the D/A to vary by

10%.

180

270

360

sets the

REFx

10% will

0

5

10

15

20

25

Frequency (MHz)

An alternative output reconstruction ﬁlter is the SMA-163E,

which contains 4 independent reconstruction ﬁlter. The

phase and frequency response of this ﬁlter is shown in the

Output Low-Pass Filters Section of this data sheet.

65-6294-32

Figure 30. Overall Response

REV. 1.0 3/26/03

65

TMC2193

PRODUCT SPECIFICATION

•

Decoupling capacitors should be applied liberally to

pins. For best results, use 0.1µF capacitors. Lead lengths

should be minimized. Ceramic chip capacitors are the

best choice.

Layout Considerations

Designing with high-performance mixed-signal circuits

demands printed circuits with ground planes. Wire-wrap is

not an option. Overall system performance is strongly inﬂu-

enced by the board layout. Capacitive coupling from digital

to analog circuits may result in poor picture quality. Con-

sider the following suggestions when doing the layout:

If there is dedicated digital power plane, it should not

overlap the TMC2193 footprint, the voltage reference,

or the analog outputs. Capacitive coupling of digital

power supply noise from this layer to the TMC2193 and

its related analog circuitry can have an adverse effect on

performance.

•

Keep analog traces (C , DACx) as

, V

, R

BYPx REF REF

short and far from all digital signals as possible. The

TMC2193 should be located near the board edge, close

to the analog output connectors.

•

The PXCK should be handled carefully. Jitter and noise

on this clock or its ground reference will translate to

noise on the video outputs. Terminate the clock line

carefully to eliminate overshoot and ringing.

•

The power plane for the TMC2193 should be separate

from that which supplies other digital circuitry. A single

power plane should be used for all of the V

DD

pins. If

the power supply for the TMC2193 is the same for the

system's digital circuitry, power to the TMC2193 should

be ﬁltered with ferrite beads and 0.1µF capacitors to

reduce noise.

Connect all unused inputs to the TMC2193 to either

ground or V . Do not leave them unconnected.

DD

•

The ground plane should be solid, not cross-hatched.

Connections to the ground plane should be very short.

66

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

A G N D

1 0 0

A G N D

1 4

A G N D

9

A G N D

4

D G N D

9 7

D G N D

7 1

D G N D

5 3

V D D

9 6

D G N D

4 0

V D D

7 2

D G N D

2 6

V D D

5 4

V D D

3 9

Figure 31. Typical Layout

REV. 1.0 3/26/03

67

TMC2193

PRODUCT SPECIFICATION

Figure 32. ST-163E Layout

68

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

mode, pin 6 must be well isolated from ground planes. When

operating in the +6dB gain mode, pin 6 must have a low

resistance path to ground.

Output Low-Pass Filters

The response at 5.0MHz typically varies < 0.25dB with

supplies of 5V to 8V. When operating in the 0dB gain

Figure 34. Stop Band

Figure 33. Pass Band

Figure 35. 2T Pulse

Figure 36. Group Delay

REV. 1.0 3/26/03

69

TMC2193

PRODUCT SPECIFICATION

Notes:

70

REV. 1.0 3/26/03

PRODUCT SPECIFICATION

TMC2193

Mechanical Dimensions

100-Lead MQFP

Notes:

Inches

Millimeters

Min. Max.

Symbol

Notes

1. All dimensions and tolerances conform to ANSI Y14.5M-1982.

2. Controlling dimension is millimeters.

Min.

Max.

A

—

.134

—

3.40

—

3. Dimension "B" does not include dambar protrusion. Allowable

dambar protrusion shall be .08mm (.003in.) maximum in excess of

the "B" dimension. Dambar cannot be located on the lower radius

or the foot.

A1

A2

B

.010

.100

.008

.005

.904

.783

.667

.547

.25

.120

.015

.009

.923

.791

.687

.555

2.55

.22

3.05

.38

3, 5

5

4. "L" is the length of terminal for soldering to a substrate.

5. "B" & "C" includes lead finish thickness.

C

.13

.23

D

22.95

19.90

16.95

13.90

23.45

20.10

17.45

14.10

D1

E

E1

e

.0256 BSC

.65 BSC

4

L

.028

.040

.73

1.03

N

100

30

100

30

ND

NE

20

α

0°

7°

0°

7°

ccc

—

.004

—

.12

D

.20 (.008) Min.

D1

0° Min.

.13 (.30)

Datum Plane

R

.005 (.012)

C

B

e

E1

α

.13 (.005) R Min.

Pin 1 Indentifier

E

L

0.076" (1.95mm) Ref

Lead Detail

See Lead Detail

Base Plane

A

A2

-C-

Lead Coplanarity

ccc

B

Seating Plane

A1

C

REV. 1.0 3/26/03

71

TMC2193

PRODUCT SPECIFICATION

Ordering Information

Product Number

Temperature Range

T = 0°C to 70°C

Screening

Package

Package Marking

TMC2193KJC

Commercial

100-pin MQFP

TMC2193

A

Life Support Policy

3/26/03 0.0m 003

Stock#DS30002193


型号：	TMC2193KJC
厂家：	CADEKA MICROCIRCUITS LLC.
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TMC2193KJC [CADEKA]

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