CLC1001 [CADEKA]
Ultra-Low Noise Amplifier; 超低噪声放大器
| 型号： | CLC1001 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Ultra-Low Noise Amplifier |
| 文件： | 总17页 (文件大小：1785K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Amplify the Human Experience
Comlinear® CLC1001
Ultra-Low Noise Amplifier
F E A T U R E S
General Description
n
n
n
n
n
n
n
0.6 nV/√Hz input voltage noise
The COMLINEAR CLC1001(single) is a high-performance, voltage feed-
back amplifier with ultra-low input voltage noise, 0.6nV/√Hz. The CLC1001
provides 2.1GHz gain bandwidth product and 410V/μs slew rate making it
well suited for high-speed data acquisition systems requiring high levels of
sensitivity and signal integrity. This COMLINEAR high-performance amplifier
also offers low input offset voltage.
1mV maximum input offset voltage
2.1GHz gain bandwidth product
Minimum stable gain of 10
410V/μs slew rate
130mA output current
-40°C to +125°C operating temperature
range
The COMLINEAR CLC1001 is designed to operate from 4V to 12V supplies.
It consumes only 12.5mA of supply current per channel and offers a power
saving disable pin that disables the amplifier and decreases the supply cur-
rent to below 225μA. The CLC1001 amplifier operates over the extended
temperature range of -40°C to +125°C.
n
n
n
Fully specified at 5V and ±5V supplies
CLC1001: Lead-free SOT23-6, SOIC-8
Future option CLC2001
A P P L I C A T I O N S
n
Transimpedance amplifiers
If a lower minimum stable gain is required, the CLC1002 offers a minimum
stable gain of 5.
n
Pre-amplifier
n
Low noise signal processing
n
Medical instrumentation
Typical Application - Single Supply Photodiode Amplifier
n
Probe equipment
n
Test equipment
n
Ultrasound channel amplifier
Ordering Information
Part Number
Package
Pb-Free
Yes
RoHS Compliant
Operating Temperature Range Packaging Method
CLC1001IST6X
CLC1001ISO8X*
CLC1001ISO8*
CLC1001AST6X
CLC1001ASO8X*
SOT23-6
SOIC-8
SOIC-8
SOT23-6
SOIC-8
SOIC-8
Yes
Yes
Yes
Yes
Yes
Yes
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
Reel
Reel
Rail
Yes
Yes
Yes
Reel
Reel
Rail
Yes
CLC1001ASO8*
Yes
*Preliminary Product Information
Moisture sensitivity level for all parts is MSL-1.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
SOT23 Pin Assignments
SOT23 Pin Configuration
Pin No.
Pin Name
OUT
Description
1
2
3
4
Output
OUT
1
2
3
6
5
4
+V
S
-V
Negative supply
S
+IN
-IN
Positive input
-
+
-V
S
DIS
-IN
Negative input
+IN
Disable. Enabled if pin is left floating or pulled
above V , disabled if pin is grounded or pulled
5
6
DIS
ON
below V
.
OFF
+V
Positive supply
S
SOIC Pin Assignments
SOIC Pin Configuration
Pin No.
Pin Name
NC
Description
1
2
3
4
5
6
7
No connect
Negative input
Positive input
Negative supply
No connect
Output
-IN1
1
8
7
DIS
+V
NC
+IN1
2
3
4
-IN1
S
-V
S
NC
6
5
OUT
NC
+IN1
OUT
-V
S
+V
Positive supply
S
Disable. Enabled if pin is left floating or pulled
8
DIS
above V , disabled if pin is grounded or pulled
ON
below V
.
OFF
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de-
vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
0
Max
14
Unit
Supply Voltage
V
V
Input Voltage Range
-V -0.5V
s
+V +0.5V
s
Reliability Information
Parameter
Min
-65
Typ
Max
Unit
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
6-Lead SOT23
150
150
260
°C
°C
°C
177
100
°C/W
°C/W
8-Lead SOIC
Notes:
Package thermal resistance (q ), JDEC standard, multi-layer test boards, still air.
JA
ESD Protection
Product
SOT23-6
Human Body Model (HBM)
2kV
2kV
Charged Device Model (CDM)
Recommended Operating Conditions
Parameter
Min
Typ
Max
Unit
Operating Temperature Range (CLC1001I)
Operating Temperature Range (CLC1001A)
Supply Voltage Range
-40
-40
4
+85
+125
12
°C
°C
V
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics at +5V
T = 25°C, V = +5V, R = 200Ω, R = 500Ω to V /2, G = 10; unless otherwise noted.
A
s
f
L
S
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
GBWP
-3dB Gain Bandwidth Product
-3dB Bandwidth
G = +40, VOUT = 0.2Vpp
G = +10, VOUT = 0.2Vpp
G = +10, VOUT = 2Vpp
G = +10, VOUT = 0.2Vpp
G = +10, VOUT = 2Vpp
2000
265
105
37
MHz
MHz
MHz
MHz
MHz
BWSS
BWLS
Large Signal Bandwidth
BW0.1dBSS
BW0.1dBLS
0.1dB Gain Flatness Small Signal
0.1dB Gain Flatness Large Signal
36
Time Domain Response
tR, tF
tS
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
VOUT = 1V step
2.4
11
6
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
VOUT = 1V step
%
Slew Rate
4V step
360
V/µs
Distortion/Noise Response
HD2
2nd Harmonic Distortion
1Vpp, 10MHz
1Vpp, 10MHz
1Vpp, 10MHz
> 100kHz
-80
-83
-79
0.6
4.2
dBc
dBc
HD3
3rd Harmonic Distortion
Total Harmonic Distortion
Input Voltage Noise
THD
dB
en
nV/√Hz
pA/√Hz
in
Input Current Noise
> 100kHz
DC Performance
VIO
dVIO
Ib
Input Offset Voltage
Average Drift
0.1
2.7
28
mV
µV/°C
µA
Input Bias Current
Average Drift
dIb
Io
45
nA/°C
µA
Input Offset Current
Power Supply Rejection Ratio
Open-Loop Gain
0.5
83
PSRR
AOL
IS
DC
dB
VOUT = VS / 2
per channel
82
dB
Supply Current
12
mA
Disable Characteristics
tON
Turn On Time
1V step, 1% settling
2Vpp, 5MHz
100
900
80
ns
ns
dB
pF
tOFF
Turn Off Time
OFFISO
OFFCOUT
Off Isolation
Off Output Capacitance
5.7
VOFF
VON
ISD
Power Down Voltage
Enable Voltage
DisabledifDISpinisgroundedorpulledbelowVOFF
Enabled if DIS pin is floating or pulled above VON
No Load, DIS pin tied to ground
Disabled if DIS < 1.5
Enabled if DIS > 3
130
V
V
Disable Supply Current
µA
Input Characteristics
RIN
CIN
Input Resistance
Non-inverting
2.6
1.6
MΩ
Input Capacitance
pF
0.8 to
5.1
CMIR
Common Mode Input Range
Common Mode Rejection Ratio
V
CMRR
DC , Vcm=1.5V to 4V
85
dB
Output Characteristics
RL = 500Ω
RL = 2kΩ
0.93to 4
V
V
VOUT
Output Voltage Swing
0.9 to
4.1
IOUT
ISC
Output Current
±130
±150
mA
mA
Short-Circuit Output Current
VOUT = VS / 2
Notes:
1. 100% tested at 25°C
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Electrical Characteristics at ±5V
T = 25°C, V = ±5V, R = 200Ω, R = 500Ω , G = 10; unless otherwise noted.
A
s
f
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
GBWP
-3dB Gain Bandwidth Product
-3dB Bandwidth
G = +40, VOUT = 0.2Vpp
G = +10, VOUT = 0.2Vpp
G = +10, VOUT = 2Vpp
G = +10, VOUT = 0.2Vpp
G = +10, VOUT = 2Vpp
2100
284
117
42
MHz
MHz
MHz
MHz
MHz
BWSS
BWLS
Large Signal Bandwidth
BW0.1dBSS
BW0.1dBLS
0.1dB Gain Flatness Small Signal
0.1dB Gain Flatness Large Signal
47
Time Domain Response
tR, tF
tS
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
VOUT = 1V step
2.2
11
3
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
VOUT = 1V step
%
Slew Rate
4V step
410
V/µs
Distortion/Noise Response
HD2
2nd Harmonic Distortion
2Vpp, 10MHz
2Vpp, 10MHz
2Vpp, 5MHz
> 100kHz
-81
-75
-74
0.6
4.2
dBc
dBc
HD3
3rd Harmonic Distortion
Total Harmonic Distortion
Input Voltage Noise
THD
dB
en
nV/√Hz
pA/√Hz
in
Input Current Noise
> 100kHz
DC Performance
VIO
dVIO
Ib
Input Offset Voltage(1)
-1
0.35
4.4
30
1
60
6
mV
µV/°C
µA
Average Drift
Input Bias Current (1)
Average Drift
-60
dIb
Io
44
nA/°C
µA
Input Offset Current
Power Supply Rejection Ratio (1)
Open-Loop Gain (1)
Supply Current (1)
0.8
83
PSRR
AOL
IS
DC
78
74
dB
VOUT = VS / 2
per channel
83
dB
12.5
16
mA
Disable Characteristics
tON
Turn On Time
1V step, 1% settling
2Vpp, 5MHz
125
840
80
ns
ns
dB
pF
tOFF
Turn Off Time
OFFISO
OFFCOUT
Off Isolation
Off Output Capacitance
5.6
VOFF
VON
ISD
Power Down Voltage
Enable Voltage
Disable Supply Current (1)
DisabledifDISpinisgroundedorpulledbelowVOFF
Enabled if DIS pin is floating or pulled above VON
No Load, DIS pin tied to ground
Disabled if DIS < 1.3
Enabled if DIS > 3
V
V
180
225
µA
Input Characteristics
RIN
CIN
Input Resistance
Non-inverting
4
MΩ
Input Capacitance
1.5
pF
-4.3 to
5.1
CMIR
Common Mode Input Range
V
CMRR
Common Mode Rejection Ratio (1)
DC , Vcm=-3.5V to 4V
75
90
dB
Output Characteristics
RL = 500Ω (1)
RL = 2kΩ
-3.8
±4
±4
3.8
V
VOUT
Output Voltage Swing
V
IOUT
ISC
Output Current
±130
±160
mA
mA
Short-Circuit Output Current
VOUT = VS / 2
Notes:
1. 100% tested at 25°C
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Typical Performance Characteristics
T = 25°C, V = ±5V, R = 200Ω, R = 500Ω, G = 10; unless otherwise noted.
A
s
f
L
Non-Inverting Frequency Response
Inverting Frequency Response
3
3
0
0
G = -10
G = +10
G = +20
G = +40
-3
-6
-9
-3
-6
-9
G = -20
G = -40
VOUT = 0.2Vpp
VOUT = 0.2Vpp
0.1
1
10
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. C
Frequency Response vs. R
L
L
3
3
CL = 470pF
Rs = 4.3Ω
0
-3
-6
0
-3
-6
CL = 100pF
Rs = 13Ω
Rl = 1K
Rl = 2K
CL = 47pF
Rs = 20Ω
Rl = 5K
CL = 22pF
Rs = 33Ω
CL = 10pF
Rs = 43Ω
VOUT = 0.2Vpp
VOUT = 0.2Vpp
-9
-9
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Frequency Response vs. V
-3dB Bandwidth vs. Output Voltage
OUT
1
0
300
250
200
150
100
50
-1
-2
-3
-4
-5
-6
-7
VOUT = 4Vpp
VOUT = 3Vpp
VOUT = 2Vpp
0
0.1
1
10
100
1000
0.0
1.0
2.0
3.0
4.0
Frequency (MHz)
VOUT (VPP)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Typical Performance Characteristics
T = 25°C, V = ±5V, R = 200Ω, R = 500Ω, G = 10; unless otherwise noted.
A
s
f
L
Non-Inverting Frequency Response at V = 5V
Inverting Frequency Response at V = 5V
S
S
3
3
0
0
G = +10
G = -10
-3
-3
G = -20
G = +20
G = -40
G = +40
-6
-6
VOUT = 0.2Vpp
VOUT = 0.2Vpp
-9
-9
0.1
1
10
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. C at V = 5V
Frequency Response vs. R at V = 5V
L S
L
S
3
3
CL = 470pF
Rs = 5Ω
0
0
CL = 100pF
Rs = 15Ω
Rl = 1K
Rl = 2K
Rl = 5K
-3
-6
-9
-3
-6
-9
CL = 47pF
Rs = 22Ω
CL = 22pF
Rs = 36Ω
CL = 10pF
Rs = 50Ω
VOUT = 0.2Vpp
VOUT = 0.2Vpp
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Frequency Response vs. V
at V = 5V
-3dB Bandwidth vs. Output Voltage at V = 5V
OUT
S
S
1
0
300
250
200
150
100
50
-1
-2
-3
-4
-5
-6
-7
VOUT = 2Vpp
VOUT = 1.5Vpp
VOUT = 1Vpp
0
0.1
1
10
100
1000
0.0
0.5
1.0
1.5
2.0
Frequency (MHz)
VOUT (VPP)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 200Ω, R = 500Ω, G = 10; unless otherwise noted.
A
s
f
L
Input Voltage Noise
Input Voltage Noise at V = 5V
S
2.6
2.4
2.2
2
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
10
10
0.0001
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
Frequency (MHz)
Frequency (MHz)
Input Voltage Noise (>10kHz)
Input Voltage Noise at V = 5V (>10kHz)
S
0.85
0.8
0.85
0.8
0.75
0.7
0.75
0.7
0.65
0.6
0.65
0.6
0.55
0.5
0.55
0.5
10
10
0.01
0.1
1
0.01
0.1
1
Frequency (MHz)
Frequency (MHz)
R
vs. Frequency
OUT
10
1
0.1
0.01
0.001
0.01
0.1
1
10
100
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 200Ω, R = 500Ω, G = 10; unless otherwise noted.
A
s
f
L
2nd Harmonic Distortion vs. R
3rd Harmonic Distortion vs. R
L
L
-65
-65
-75
-75
RL = 500Ω
RL = 500Ω
-85
-95
-85
-95
RL = 1kΩ
RL = 1kΩ
-105
-105
VOUT = 1Vpp
-115
VOUT = 1Vpp
-115
5
10
15
20
5
10
15
20
Frequency (MHz)
Frequency (MHz)
2nd Harmonic Distortion vs. V
3rd Harmonic Distortion vs. V
OUT
OUT
-65
-70
-55
-60
20MHz
20MHz
-65
10MHz
10MHz
-75
-70
-75
-80
-85
-90
-95
-80
-85
5MHz
-90
5MHz
-95
-100
-100
RL = 500Ω
RL = 500Ω
-105
-105
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
2nd Harmonic Distortion vs. Gain
3rd Harmonic Distortion vs. Gain
-50
-55
-60
-50
-55
-60
-65
-70
AV+40
-65
-70
-75
-80
-85
-90
-95
-100
AV+40
AV+20
AV+20
-75
-80
-85
-90
AV+10
15
AV+10
VOUT = 1VPP
RL = 500Ω
VOUT = 1VPP
-95
RL = 500Ω
-100
5
10
15
20
5
10
20
Frequency (MHz)
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 200Ω, R = 500Ω, G = 10; unless otherwise noted.
A
s
f
L
2nd Harmonic Distortion vs. R at V = 5V
3rd Harmonic Distortion vs. R at V = 5V
L
S
L
S
-65
-65
RL = 500Ω
RL = 500Ω
-75
-75
-85
-85
-95
-95
RL = 1kΩ
RL = 1kΩ
-105
-115
-105
-115
VOUT = 1Vpp
VOUT = 1Vpp
5
10
15
20
5
10
15
20
Frequency (MHz)
Frequency (MHz)
2nd Harmonic Distortion vs. V
at V = 5V
3rd Harmonic Distortion vs. V
at V = 5V
OUT S
OUT
S
-55
-60
-65
-55
-60
20MHz
-65
-70
-75
-80
-85
-90
-95
-70
-75
-80
-85
-90
-95
20MHz
10MHz
5MHz
5MHz
10MHz
-100
RL = 500Ω
0.5 0.75
RL = 500Ω
-105
1
1.25
1.5
1.75
2
2.25
2.5
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
2nd Harmonic Distortion vs. Gain at V = 5V
3rd Harmonic Distortion vs. Gain at V = 5V
S
S
-50
-55
-60
-65
-50
-55
AV+40
-60
AV+20
-65
-70
-70
-75
-80
AV+20
-75
-80
-85
-85
AV+10
AV+10
-90
-95
AV+40
-90
VOUT = 1VPP
VOUT = 1VPP
-95
RL = 500Ω
RL = 500Ω
-100
-100
5
10
15
20
5
10
15
20
Frequency (MHz)
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 200Ω, R = 500Ω, G = 10; unless otherwise noted.
A
s
f
L
Small Signal Pulse Response
Small Signal Pulse Response at V = 5V
S
0.15
2.65
0.1
0.05
0
2.6
2.55
2.5
-0.05
-0.1
-0.15
2.45
2.4
2.35
0
50
100
150
200
0
50
100
150
200
Time (ns)
Time (ns)
Large Signal Pulse Response
Large Signal Pulse Response at V = 5V
S
3
4
3.5
3
2
1
0
2.5
2
-1
-2
-3
1.5
1
0
50
100
150
200
0
50
100
150
200
Time (ns)
Time (ns)
Enable Response
Disable Response
5.5
1.5
1
5.5
1.5
1
Disable
Enable
4.5
4.5
3.5
2.5
1.5
0.5
-0.5
3.5
2.5
1.5
0.5
Output
0.5
0
0.5
0
Output
-0.5
-50
-0.5
-0.5
0
50
100
150
200
-100
0
100 200 300 400 500 600 700 800 900
Time (ns)
Time (ns)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
11
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 200Ω, R = 500Ω, G = 10; unless otherwise noted.
A
s
f
L
Enable Response at V = 5V
Disable Response at V = 5V
S
S
5.5
1.5
1
5.5
1.5
1
Disable
Enable
4.5
4.5
3.5
2.5
3.5
Output
Output
0.5
0
2.5
1.5
0.5
0
1.5
0.5
0.5
-0.5
-0.5
-0.5
-0.5
-50
0
50
100
150
200
-100
0
100 200 300 400 500 600 700 800 900
Time (ns)
Time (ns)
Off Isolation
Off Isolation at V = 5V
S
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
VOUT = 2Vpp
VOUT = 2Vpp
-100
1
-100
1
10
100
10
100
Frequency (MHz)
Frequency (MHz)
CMRR vs. Frequency
PSRR vs. Frequency
100
100
80
60
40
20
0
80
60
40
20
0
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
12
Data Sheet
total input voltage noise (amp+resistors) versus R and
Application Information
f
R . As the value of R increases, the total input referred
g
f
Basic Operation
noise also increases.
Figures 1 and 2 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
2.75
2.5
G = +11
2.25
2
G = +21
+Vs
1.75
6.8μF
G = +41
1.5
1.25
1
0.1μF
Input
+
-
0.75
0.5
Output
RL
100
1000
0.1μF
6.8μF
Rf (Ohms)
Rf
Figure 3: Input Referred Voltage Noise vs. R and R
f
g
Rg
G = 1 + (Rf/Rg)
-Vs
The noise caused by a resistor is modeled with either a
voltage source in series with the resistance:
Figure 1. Typical Non-Inverting Gain Circuit
+Vs
4kTR
6.8μF
R1
Or a current source in parallel with it:
0.1μF
+
Output
Rg
4kT
Input
-
i
=
RL
R
R
0.1μF
Rf
6.8μF
G = - (Rf/Rg)
-Vs
Op amp noise is modeled with three noise sources, e , i
n
n
For optimum input offset
voltage set R1 = Rf ||Rg
and i. These three sources are analogous to the DC input
i
voltage and current errors V , I and I .
os bn
bi
Figure 2. Typical Inverting Gain Circuit
The noise models must be analyzed in-circuit to deter-
mine the effect on the op amp output noise.
Achieving Low Noise in an Application
Making full use of the low noise of the CLC1001 requires
careful consideration of resistor values. The feedback and
Since noise is statistical in nature rather than a continuous
signal, the set of noise sources in circuit add in an RMS
(root mean square) fashion rather than in a linear fashion.
For uncorrelated noise sources, this means you add the
squares of the noise voltages. A typical non-inverting ap-
plication (see figure 1) results in the following noise at the
output of the op amp:
gain set resistors (R and R ) and the non-inverting source
f
g
impedance (R
) all contribute noise to the circuit and
source
can easily dominate the overall noise if their values are
too high. The datasheet is specified with an R of 22.1Ω,
g
at which point the noise from R and R is about equal to
f
g
the noise from the CLC1001. Lower value resistors could
be used at the expense of more distortion. Figure 3 shows
©2007-2008 CADEKA Microcircuits LLC
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13
Data Sheet
The effective load resistor (Rload ) will need to include
the effect of the feedback network. For instance,
eff
2
2
R
R
R
R
2
2
2
2
2
2
f
f
f
e = e 1+
+ in R
1+
+ i R
i
o
n
s
Rload in figure 3 would be calculated as:
eff
g
g
op amp noise terms e , i and i
R || (R + R )
n
n
i
L
f
g
2
2
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Rf
Rf
+ eR2s 1 +
+ e2Rg
+ e2Rf
Rg
Rg
external resistor noise terms for R , R and R
f
S
g
Here, P can be found from
D
P = P
+ P
- P
D
Quiescent
Dynamic Load
High source impedances are sometimes unavoidable, but
they increase noise from the source impedance and also
make the circuit more sensitive to the op amp current
noise. Analyze all noise sources in the circuit, not just the
op amp itself, to achieve low noise in your application.
Quiescent power can be derived from the specified I val-
S
ues along with known supply voltage, V
. Load power
Supply
can be calculated as above with the desired signal ampli-
tudes using:
(V
)
= V
/ √2
LOAD RMS
PEAK
Power Dissipation
( I
)
= ( V
)
/ Rload
LOAD RMS
LOAD RMS eff
Power dissipation should not be a factor when operat-
ing under the stated 500Ω load condition. However, ap-
plications with low impedance, DC coupled loads should
be analyzed to ensure that maximum allowed junction
temperature is not exceeded. Guidelines listed below can
be used to verify that the particular application will not
cause the device to operate beyond it’s intended operat-
ing range.
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
= (V - V
)
× ( I )
LOAD RMS
DYNAMIC
S+
LOAD RMS
Assuming the load is referenced in the middle of the pow-
er rails or V /2.
supply
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
Figure 4 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the pack-
ages available.
perature, the package thermal resistance value Theta
JA
(Ө ) is used along with the total die power dissipation.
JA
T
= T + (Ө × P )
Ambient JA D
Junction
2.5
Where T
is the temperature of the working environment.
Ambient
2
In order to determine P , the power dissipated in the load
D
SOIC-8
needs to be subtracted from the total power delivered by
the supplies.
1.5
SOT23-6
P = P
- P
load
D
supply
1
0.5
0
Supply power is calculated by the standard power equa-
tion.
P
= V
× I
supply
supply RMS supply
V
= V - V
S+ S-
-40
-20
0
20
40
60
80
100
120
supply
Ambient Temperature (°C)
Power delivered to a purely resistive load is:
Figure 4. Maximum Power Derating
2
P
= ((V
)
)/Rload
eff
load
LOAD RMS
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
14
Data Sheet
Driving Capacitive Loads
3
2
6
G = 10
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
4
1
2
Output
R , between the amplifier and the load to help improve
S
0
0
stability and settling performance. Refer to Figure 5.
Input
-1
-2
-3
-2
-4
-6
Input
+
-
Rs
Output
CL
RL
Rf
0
50
100
150
200
250
300
350
400
450
Rg
Time (us)
Figure 6. Overdrive Recovery
Figure 5. Addition of R for Driving
S
Capacitive Loads
Layout Considerations
Table 1 provides the recommended R for various capaci-
S
tive loads. The recommended R values result in <=1dB
peaking in the frequency response. The Frequency Re-
S
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
sponse vs. C plots, on page 7, illustrates the response of
L
the CLC1001.
C (pF)
L
R (Ω)
S
-3dB BW (MHz)
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
10
22
43
33
20
13
4.3
266
228
192
155
84
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
47
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
100
470
• Minimize all trace lengths to reduce series inductances
Table 1: Recommended R vs. C
S
L
Refer to the evaluation board layouts below for more in-
formation.
For a given load capacitance, adjust R to optimize the
S
tradeoff between settling time and bandwidth. In general,
reducing R will increase bandwidth at the expense of ad-
Evaluation Board Information
S
ditional overshoot and ringing.
The following evaluation boards are available to aid in the
testing and layout of these devices:
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified volt-
age range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point.
The recovery time varies, based on whether the input or
output is overdriven and by how much the range is ex-
ceeded. The CLC1001 will typically recover in less than
25ns from an overdrive condition. Figure 6 shows the
CLC1001 in an overdriven condition.
Evaluation Board #
CEB002
CEB003
Products
CLC1001 in SOT23-5
CLC1001 in SOIC-8
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
15
Data Sheet
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 7-11. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -V pin of the amplifier is not
S
directly connected to the ground plane.
Figure 9. CEB002 Bottom View
Figure 10. CEB003 Top View
Figure 11. CEB003 Bottom View
Figure 7. CEB002/CEB003 Schematic
Figure 8. CEB002 Top View
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
16
Data Sheet
Mechanical Dimensions
SOT23-6 Package
SOIC-8 Package
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
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