PCM2906DBR [BB]
STEREO AUDIO CODEC WITH USB INTERFACE SINGLE ENEDE ANALOG INPUT/OUTPUT AND S/PDIF; 立体声音频， USB接口单ENEDE模拟输入/输出编解码器和S / PDIF
| 型号： | PCM2906DBR |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | STEREO AUDIO CODEC WITH USB INTERFACE SINGLE ENEDE ANALOG INPUT/OUTPUT AND S/PDIF |
| 文件： | 总32页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLES042A − JUNE 2002 − REVISED JUNE 2004
ꢈꢉ ꢊꢋ ꢊꢌ ꢍ ꢎ ꢏ ꢐꢌ ꢁ ꢌꢏ ꢊꢁ ꢑꢐ ꢉꢒ ꢎꢈ ꢓ ꢐ ꢔꢉꢊ ꢋ ꢕꢍ ꢁꢊ ꢖ
ꢈꢐꢔ ꢗ ꢘ ꢊꢙ ꢊꢔ ꢏ ꢊꢏ ꢍꢔ ꢍ ꢘꢌ ꢗ ꢐ ꢔꢀ ꢎꢉ ꢚꢌ ꢎꢉ ꢀꢎ ꢉ ꢍꢔ ꢏ ꢈ ꢚꢀ ꢏꢐ ꢕ
D
Stereo DAC:
− Analog Performance at V
FEATURES
= 5 V
BUS
−
−
−
THD+N = 0.005%
SNR = 96 dB
Dynamic Range = 93 dB
D
D
D
PCM2904: Without S/PDIF
PCM2906: With S/PDIF
On-Chip USB Interface:
− With Full-Speed Transceivers
− Fully Compliant With USB 1.1
Specification
− Oversampling Digital Filter
−
−
Pass-Band Ripple = 0.1 dB
Stop-Band Attenuation = –43 dB
− Single-Ended Voltage Output
− Analog LPF Included
− Certified by USB-IF
− Partially Programmable Descriptors
− USB Adaptive Mode for Playback
− USB Asynchronous Mode for Record
− Bus Powered
D
D
Multifunctions:
(1)
− Human Interface Device (HID) Volume
Control and Mute Control
− Suspend Flag
Package: 28-Pin SSOP, Lead-Free Product
D
D
16-Bit Delta-Sigma ADC and DAC
APPLICATIONS
Sampling Rate:
− DAC: 32, 44.1, 48 kHz
− ADC: 8, 11.025, 16, 22.05, 32, 44.1, 48 kHz
D
D
D
D
USB Audio Speaker
USB Headset
USB Monitor
D
On-Chip Clock Generator With Single 12-MHz
Clock Source
USB Audio Interface Box
D
D
Single Power Supply: 5 V Typical (V
)
BUS
DESCRIPTION
Stereo ADC:
− Analog Performance at V
The PCM2904/2906 is Texas Instruments single-chip
USB stereo audio codec with USB-compliant full-speed
protocol controller and S/PDIF (PCM2906 only). The
USB protocol controller works with no software code,
but the USB descriptors can be modified in some areas
(for example, vendor ID/product ID). The
PCM2904/2906 employs SpAct architecture, TI’s
unique system that recovers the audio clock from USB
packet data. On-chip analog PLLs with SpAct enable
playback and record with low clock jitter and with
independent playback and record sampling rates.
= 5 V
BUS
−
−
−
THD+N = 0.01%
SNR = 89 dB
Dynamic Range = 89 dB
− Decimation Digital Filter
−
−
Pass-Band Ripple = 0.05 dB
Stop-Band Attenuation = –65 dB
− Single-Ended Voltage Input
− Antialiasing Filter Included
− Digital LCF Included
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
(1)
The descriptor can be modified by changing a mask.
SpAct is a trademark of Texas Instruments, Incorporated.
Apple. Mac, and Mac OS are trademarks of Apple Computer, Inc.
Intel is a trademark of Intel Corporation.
Microsoft, Windows, Windows Me, and Windows XP are trademarks of Microsoft Corporation.
Other trademarks are the property of their respective owners.
ꢀꢋ ꢌ ꢏꢎ ꢁ ꢉꢐ ꢌꢔ ꢏ ꢍꢉꢍ ꢛꢜ ꢝꢞ ꢟ ꢠꢡ ꢢꢛꢞꢜ ꢛꢣ ꢤꢥ ꢟ ꢟ ꢦꢜꢢ ꢡꢣ ꢞꢝ ꢧꢥꢨ ꢩꢛꢤ ꢡꢢꢛ ꢞꢜ ꢪꢡ ꢢꢦꢫ ꢀꢟ ꢞꢪꢥ ꢤꢢꢣ
ꢤ ꢞꢜ ꢝꢞꢟ ꢠ ꢢꢞ ꢣ ꢧꢦ ꢤ ꢛ ꢝꢛ ꢤ ꢡ ꢢꢛ ꢞꢜꢣ ꢧ ꢦꢟ ꢢꢬꢦ ꢢꢦ ꢟ ꢠꢣ ꢞꢝ ꢉꢦꢭ ꢡꢣ ꢐꢜꢣ ꢢꢟ ꢥꢠ ꢦꢜꢢ ꢣ ꢣꢢ ꢡꢜꢪ ꢡꢟ ꢪ ꢮ ꢡꢟ ꢟ ꢡ ꢜꢢꢯꢫ
ꢀꢟ ꢞ ꢪꢥꢤ ꢢ ꢛꢞ ꢜ ꢧꢟ ꢞ ꢤ ꢦ ꢣ ꢣ ꢛꢜ ꢰ ꢪꢞ ꢦ ꢣ ꢜꢞꢢ ꢜꢦ ꢤꢦ ꢣꢣ ꢡꢟ ꢛꢩ ꢯ ꢛꢜꢤ ꢩꢥꢪ ꢦ ꢢꢦ ꢣꢢꢛ ꢜꢰ ꢞꢝ ꢡꢩ ꢩ ꢧꢡ ꢟ ꢡꢠ ꢦꢢꢦ ꢟ ꢣꢫ
Copyright 2004, Texas Instruments Incorporated
www.ti.com
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www.ti.com
SLES042A − JUNE 2002 − REVISED JUNE 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE−LEAD
PCM2904DB
PCM2904DBR
PCM2906DB
PCM2906DBR
Rails
PCM2904DB
PCM2906DB
28-lead SSOP
28-lead SSOP
28DB
28DB
−25°C to 85°C
−25°C to 85°C
PCM2904
PCM2906
Tape and reel
Rails
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
PCM2904/PCM2906
-0.3 to 6.5
UNIT
V
Supply voltage, V
BUS
Ground voltage differences, AGNDC, AGNDP, AGNDX, DGND, DGNDU
(2)
0.1
V
SEL0, SEL1, TEST0 (DIN)
−0.3 to 6.5
Digital input voltage
V
V
−0.3 to (V
+ 0.3) <
DDI
4
(2)
D+, D–, HID0, HID1, HID2, XTI, XTO, TEST1 (DOUT) , SSPND
−0.3to V
+ 0.3) <
CCCI
4
V
L, V R, V
, V
R, V L
OUT
IN IN COM OUT
Analog input voltage
V
, V , V , V
, V
−0.3 to 4
10
CCCI CCP1I CCP2I CCXI DDI
Input current (any pins except supplies)
Ambient temperature under bias
mA
°C
−40 to 125
−55 to 150
150
Storage temperature, T
stg
°C
Junction temperature T
°C
J
Lead temperature (soldering)
260
°C, 5 s
°C
Package temperature (IR reflow, peak)
250
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
( ): PCM2906
(2)
2
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SLES042A − JUNE 2002 − REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS
all specifications at T = 25°C, V
, = 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted
IN
A
BUS
S
PCM2904DB, PCM2906DB
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Digital Input/Output
Host interface
Apply USB Revision 1.1, full speed
USB isochronous data format
Audio data format
Input logic level
Input Logic
(1)
V
V
V
V
V
V
V
V
2
2.52
2
3.3
0.8
3.3
0.9
5.25
0.8
5.25
0.9
10
IH
(1)
IL
(2) (3)
IH
(2) (3)
IL
Vdc
(4)
IH
(4)
IL
(5)
2.52
IH
(5)
IL
(1)(2)(4)
I
I
I
I
I
I
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
= 3.3 V
= 0 V
IH
(1)(2)(4)
10
IL
IH
(3)
= 3.3 V
= 0 V
50
65
80
Input logic current
µA
(3)
10
IL
(5)
= 3.3 V
= 0 V
100
10
IH
(5)
IL
Output Logic
(1)
V
V
V
V
V
V
2.8
2.8
2.8
OH
(1)
(6)
0.3
0.5
OL
I
I
I
I
= –4 mA
= 4 mA
OH
OH
OL
OH
OL
Output logic level
Vdc
(6)
OL
(7)
= −2 mA
= 2 mA
OH
(7)
0.5
OL
Clock Frequency
Input clock frequency, XTI
11.994
12.000
12.006
MHz
ADC Characteristics
Resolution
8, 16
1, 2
bits
Audio data channel
Clock Frequency
Sampling frequency
DC Accuracy
channel
f
s
8, 11.025, 16, 22.05, 32, 44.1, 48
kHz
Gain mismatch, channel-to-channel
Gain error
1
2
0
5
% of FSR
10 % of FSR
% of FSR
Bipolar zero error
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Pins 1, 2: D+, D–
Pin 21: XTI
Pins 5, 6, 7: HID0, HID1, HID2
Pins 8, 9: SEL0, SEL1
Pin 24: DIN
Pin 25: DOUT
Pin 28: SSPND
3
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SLES042A − JUNE 2002 − REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS(continued)
all specifications at T = 25°C, V
, = 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted
BUS S IN
A
PCM2904DB, PCM2906DB
PARAMETER
(1)
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Dynamic Performance
(2)
= –0.5 dB , V
CCCI
V
IN
V
IN
V
IN
= 3.67 V
0.01%
0.1%
5%
0.02%
(3)
= –0.5 dB
THD+N Total harmonic distortion plus noise
= –60 dB
Dynamic range
S/N ratio
A-weighted
A-weighted
81
81
80
89
dB
dB
dB
89
Channel separation
Analog Input
85
Input voltage
0.6 V
Vp−p
V
CCCI
Center voltage
Input impedance
0.5 V
CCCI
30
kΩ
–3 dB
150
kHz
dB
Antialiasing filter frequency response
Digital Filter Performance
f
IN
= 20 kHz
–0.08
Pass band
0.454 f
Hz
Hz
dB
dB
s
s
Stop band
0.583 f
s
Pass-band ripple
Stop-band attenuation
Delay time
0.05
–65
t
d
17.4/f
s
LCF frequency response
–3 dB
0.078 f
MHz
s
DAC Characteristics
Resolution
8, 16
1, 2
bits
Audio data channel
Clock Frequency
Sampling frequency
DC Accuracy
Gain mismatch, channel-to-channel
channel
f
s
32, 44.1, 48
kHz
1
2
2
5
% of FSR
Gain error
10 % of FSR
% of FSR
Bipolar zero error
(4)
Dynamic Performance
V
V
= 0 dB
0.005%
3%
0.016%
OUT
THD+N Total harmonic distortion plus noise
Dynamic range
= –60 dB
OUT
EIAJ, A-weighted
EIAJ, A-weighted
87
90
86
93
dB
dB
dB
SNR
Signal-to-noise ratio
Channel separation
96
92
(1)
f
= 1 kHz, using the System Two audio measurement system by Audio Precision in RMS mode with 20 kHz LPF, 400 Hz HPF in calculation.
IN
(2)
(3)
(4)
Using external voltage regulator for V
Using internal voltage regulator for V
(as shown in Figure 36 and Figure 37, using REG103xA−A)
(as shown in Figure 38 and Figure 39)
CCCI
CCCI
f
= 1 kHz, using the System Two audio measurement system by Audio Precision in RMS mode with 20 kHz LPF, 400 Hz HPF.
OUT
System Two and Audio Precision are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
4
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SLES042A − JUNE 2002 − REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS(continued)
all specifications at T = 25°C, V
, = 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted
BUS S IN
A
PCM2904DB, PCM2906DB
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Analog Output
Output voltage
V
O
0.6 V
0.5 V
Vp−p
V
CCCI
CCCI
Center voltage
Load impedance
AC coupling
–3 dB
10
kΩ
250
kHz
dB
LPF frequency response
f = 20 kHz
–0.03
Digital filter performance
Pass band
0.445 f
Hz
Hz
dB
dB
s
s
Stop band
0.555 f
s
Pass-band ripple
Stop-band attenuation
Delay time
0.1
–43
t
d
14.3 f
s
Power Supply Requirements
V
Voltage range
4.35
5
56
5.25
67
VDC
mA
µA
BUS
ADC, DAC operation
Supply current
(1)
Suspend mode
210
280
1.05
3.35
ADC, DAC operation
352
3.5
85
P
D
Power dissipation
mW
(1)
Suspend mode
(2)
Internal power supply voltage
3.25
−25
VDC
Temperature Range
Operating temperature
_C
θ
JA
Thermal resistance
28-pin SSOP
100
_C/W
(1)
(2)
In USB suspend state
Pins 10, 17, 19, 23, 27: V
, V
, V
, V
, V
CCCI CCP1I CCP2I CCXI DDI
PIN ASSIGNMENTS
PCM2904
PCM2906
(TOP VIEW)
(TOP VIEW)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
1
D+
D−
SSPND
D+
D−
SSPND
2
2
V
V
DDI
DDI
3
3
V
DGND
TEST1
TEST0
V
DGND
DOUT
DIN
BUS
DGNDU
HID0
BUS
DGNDU
HID0
4
4
5
5
6
6
HID1
HID2
SEL0
SEL1
V
HID1
HID2
SEL0
SEL1
V
CCXI
CCXI
7
7
AGNDX
XTI
XTO
AGNDX
XTI
XTO
8
8
9
9
V
10
11
12
13
14
V
V
10
11
12
13
14
V
CCCI
AGNDC
CCP2I
CCCI
AGNDC
CCP2I
AGNDP
AGNDP
V
V
V
L
V
V
V
V
V
V
L
V
V
V
IN
CCP1I
IN
CCP1I
R
L
R
L
IN
OUT
OUT
IN
OUT
OUT
R
R
COM
COM
5
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SLES042A − JUNE 2002 − REVISED JUNE 2004
PCM2904 Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AGNDC
AGNDP
AGNDX
D–
NO.
11
18
22
2
−
−
−
Analog ground for codec
Analog ground for PLL
Analog ground for oscillator
(1)
I/O USB differential input/output minus
(1)
I/O USB differential input/output plus
D+
1
DGND
DGNDU
HID0
26
4
−
−
I
Digital ground
Digital ground for USB transceiver
(3)
HID key state input (mute), active high
5
(3)
HID1
6
I
HID key state input (volume up), active high
(3)
HID2
7
I
HID key state input (volume down), active high
(5)
(5)
SEL0
8
I
Must be set to high
SEL1
9
I
Must be set to high
SSPND
TEST0
TEST1
28
24
25
3
O
I
Suspend flag, active low (Low: suspend, High: operational)
Test pin, must be connected to GND
O
−
−
−
−
−
−
−
I
Test pin, must be left open
V
V
V
V
V
V
V
V
V
V
V
Connect to USB power (V )
BUS
BUS
(4)
10
17
19
23
14
27
12
13
16
15
21
20
Internal analog power supply for codec
CCCI
CCP1I
CCP2I
CCXI
COM
DDI
(4)
(4)
Internal analog power supply for PLL
Internal analog power supply for PLL
(4)
Internal analog power supply for oscillator
(4)
Common for ADC/DAC (V /2)
CCCI
(4)
Internal digital power supply
L
IN
ADC analog input for L-channel
ADC analog input for R-channel
R
IN
I
L
O
O
I
DAC analog output for L-channel
DAC analog output for R-channel
OUT
R
OUT
(2)
Crystal oscillator input
XTI
XTO
O
Crystal oscillator output
(1)
(2)
(3)
LV-TTL level
3.3-V CMOS-level input
3.3-V CMOS-level input with internal pulldown. This pin informs the PC of serviceable control signals such as mute, volume up, or volume down,
which have no direct connection with the internal DAC or ADC. See the Interface #3 and End-Points sections.
(4)
(5)
Connect a decoupling capacitor to GND.
TTL Schmitt trigger, 5-V tolerant
6
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SLES042A − JUNE 2002 − REVISED JUNE 2004
PCM2906 Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTIONS
NO.
11
18
22
2
AGNDC
−
−
−
Analog ground for codec
AGNDP
AGNDX
D–
Analog ground for PLL
Analog ground for oscillator
(1)
I/O USB differential input/output minus
(1)
I/O USB differential input/output plus
D+
1
DGND
DGNDU
DIN
26
4
−
−
I
Digital ground
Digital ground for USB transceiver
(5)
S/PDIF input
24
25
5
DOUT
HID0
O
I
S/PDIF output
HID key state input (mute), active high
(3)
(3)
HID1
6
I
HID key state input (volume up), active high
HID key state input (volume down), active high
(3)
HID2
7
I
(6)
SEL0
SEL1
SSPND
8
I
Must be set to high
Must be set to high
(6)
9
I
28
3
O
−
−
−
−
−
−
−
I
Suspend flag, active low (Low: suspend, High: operational)
V
V
V
V
V
V
V
V
V
V
V
Connected to USB power (V
BUS
Internal analog power supply for codec
)
BUS
(4)
10
17
19
23
14
27
12
13
16
15
21
20
CCCI
CCP1I
CCP2I
CCXI
COM
DDI
(4)
Internal analog power supply for PLL
Internal analog power supply for PLL
(4)
(4)
Internal analog power supply for oscillator
Common for ADC/DAC (V
/2)
CCCI (4)
(4)
Internal digital power supply
L
IN
ADC analog input for L-channel
ADC analog input for R-channel
DAC analog output for L-channel
DAC analog output for R-channel
R
IN
I
L
O
O
I
OUT
R
OUT
(2)
Crystal oscillator input
XTI
XTO
O
Crystal oscillator output
(1)
(2)
(3)
LV-TTL level
3.3-V CMOS-level input
3.3-V CMOS-level input with internal pulldown. This pin informs the PC of serviceable control signals such as mute, volume up, or volume down,
which have no direct connection with the internal DAC or ADC. See the Interface #3 and End-Points sections.
(4)
(5)
(6)
Connect a decoupling capacitor to GND.
3.3-V CMOS level input with internal pulldown, 5 V tolerant
TTL Schmitt trigger, 5-V tolerant
7
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SLES042A − JUNE 2002 − REVISED JUNE 2004
PCM2904 FUNCTIONAL BLOCK DIAGRAM
V
V
V
V
V
DDI
AGNDC AGNDP AGNDX DGND DGNDU
CCCI CCP1I
CCP2I CCXI
Power
Manager
5-V to 3.3-V Voltage Regulator
SSPND
TEST0
TEST1
V
BUS
V
L
IN
ISO-In
End-Point
FIFO
ADC
V
IN
R
D+
D−
Analog
PLL
Control
Selector
V
COM
End-Point
Analog
PLL
SEL0
SEL1
V
L
OUT
ISO-Out
End-Point
FIFO
DAC
V
OUT
R
HID0
HID1
HID2
HID
End-Point
USB
Protocol
Controller
96 MHz
Tracker
(SpAct)
PLL (y 8)
12 MHz
XTI
XTO
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SLES042A − JUNE 2002 − REVISED JUNE 2004
PCM2906 FUNCTIONAL BLOCK DIAGRAM
V
V
V
V
V
DDI
AGNDC AGNDP AGNDX DGND DGNDU
CCCI CCP1I
CCP2I CCXI
5-V to 3.3-V Voltage Regulator
Lock
Power
Manager
SSPND
S/PDIF Decoder
DIN
V
BUS
V
L
IN
ISO-In
End-Point
FIFO
ADC
V
IN
R
D+
D−
Analog
PLL
Control
Selector
V
COM
End-Point
Analog
PLL
SEL0
SEL1
V
L
OUT
ISO-Out
End-Point
FIFO
DAC
V
OUT
R
HID0
HID1
HID2
HID
End-Point
S/PDIF Encoder
DOUT
USB
Protocol
Controller
96 MHz
Tracker
(SpAct)
PLL (y 8)
12 MHz
XTO
XTI
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BLOCK DIAGRAM OF ANALOG FRONT-END (RIGHT CHANNEL)
4.7 µF
30 kΩ
V R
IN
−
+
13
14
−
+
(+)
(−)
Delta-Sigma
Modulator
V
COM
+
(V /2)
CCCI
Reference
10 µF
10
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TYPICAL CHARACTERISTICS
ADC
DYNAMIC RANGE and SNR
vs
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
95
93
91
89
87
85
0.010
0.009
0.008
0.007
Dynamic Range
SNR
0.006
0.005
0.004
0.003
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 1. THD + N at –0.5 dB vs Temperature
Figure 2
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE and SNR
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
95
93
91
89
87
85
0.010
0.009
0.008
0.007
Dynamic Range
SNR
0.006
0.005
0.004
0.003
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
V
BUS
– Supply Voltage – V
V
BUS
– Supply Voltage – V
Figure 3. THD + N at –0.5 dB vs Supply Voltage
Figure 4
All specifications at T = 25°C, V
BUS
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, using REG103xA−A, unless otherwise noted.
IN
A
s
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ADC
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE and SNR
vs
vs
SAMPLING FREQUENCY
SAMPLING FREQUENCY
0.010
95
93
91
89
87
85
0.009
0.008
0.007
Dynamic Range
SNR
0.006
0.005
0.004
0.003
30
35
40
45
50
30
35
40
45
50
f
– Sampling Frequency – kHz
S
f
S
– Sampling Frequency – kHz
Figure 5. THD + N at –0.5 dB vs Sampling
Frequency
Figure 6
DAC
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE and SNR
vs
FREE-AIR TEMPERATURE
vs
FREE-AIR TEMPERATURE
0.008
98
97
96
95
94
93
92
91
90
0.007
SNR
0.006
Dynamic Range
0.005
0.004
0.003
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 7. THD + N at 0 dB vs Temperature
Figure 8
All specifications at T = 25°C, V
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, using REG103xA-A, unless otherwise noted.
IN
A
BUS
s
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DAC
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE and SNR
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
0.008
98
97
96
95
94
93
92
91
90
0.007
SNR
0.006
Dynamic Range
0.005
0.004
0.003
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
V
BUS
– Supply Voltage – V
V
BUS
– Supply Voltage – V
Figure 9. THD + N at 0 dB vs Supply Voltage
Figure 10
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE and SNR
vs
vs
SAMPLING FREQUENCY
SAMPLING FREQUENCY
0.008
98
97
96
95
94
93
92
91
90
SNR
0.007
0.006
Dynamic Range
0.005
0.004
0.003
30
35
40
45
50
30
35
40
45
50
f
S
– Sampling Frequency – kHz
f
S
– Sampling Frequency – kHz
Figure 11. THD + N at 0 dB vs Sampling Frequency
Figure 12
All specifications at T = 25°C, V
BUS
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, using REG103xA-A, unless otherwise noted.
IN
A
s
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SUPPLY CURRENT
OPERATIONAL and SUSPEND
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
0.30
0.28
0.26
0.24
0.22
0.20
70
60
50
40
30
20
Operational
Suspend
4.00
4.25
4.50
4.75
5.00
5.25
5.50
V
BUS
– Supply Voltage – V
Figure 13
OPERATIONAL SUPPLY CURRENT
SUSPEND SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
vs
SAMPLING FREQUENCY
70
60
50
40
30
20
0.40
0.35
0.30
0.25
0.20
0.15
0.10
USB Spec Limit for Device (0.3 mA)
30
35
40
45
50
−40
−20
0
20
40
60
80
100
f
S
– Sampling Frequency – kHz
T
A
– Free-Air Temperature – °C
Figure 14. Supply Current vs Sampling Frequency,
ADC and DAC at Same f
Figure 15. Supply Current vs Temperature in
Suspend Mode
S
All specifications at T = 25°C, V
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, using REG103xA-A, unless otherwise noted.
IN
A
BUS
s
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ADC DIGITAL DECIMATION FILTER FREQUENCY RESPONSE
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0
−20
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−40
−60
−80
−100
−120
−140
−160
0
8
16
Frequency [y f ]
24
32
0.0
0.2
0.4
0.6
0.8
1.0
Frequency[y f ]
S
S
Figure 16. Overall Characteristic
Figure 17. Stop-Band Attenuation
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0.2
0
−4
0.0
−0.2
−0.4
−0.6
−0.8
−8
−12
−16
−20
0.0
0.1
0.2
0.3
0.4
0.5
0.46
0.48
0.50
Frequency[y f ]
0.52
0.54
Frequency[y f ]
S
S
Figure 18. Pass-Band Ripple
Figure 19. Transition-Band Response
All specifications at T = 25°C, V
BUS
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted.
IN
A
s
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ADC DIGITAL HIGH-PASS FILTER FREQUENCY RESPONSE
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0.0
0.1
0.2
Frequency[y f /1000]
0.3
0.4
0
1
2
3
4
Frequency[y f /1000]
S
S
Figure 20. Stop-Band Characteristic
Figure 21. Pass-Band Characteristic
ADC ANALOG ANTIALIASING FILTER FREQUENCY RESPONSE
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
−10
−20
−30
−40
−50
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
1
10
100
1k
10k
0.01
0.1
1
10
100
f – Frequency – kHz
f – Frequency – kHz
Figure 22. Stop-Band Characteristic
Figure 23. Pass-Band Characteristic
All specifications at T = 25°C, V
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted.
IN
A
BUS
s
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DAC DIGITAL INTERPOLATION AND DE-EMPHASIS FILTER FREQUENCY RESPONSE
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0.2
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.0
−0.2
−0.4
−0.6
−0.8
0
1
2
3
4
0.0
0.1
0.2
0.3
0.4
0.5
Frequency[y f ]
Frequency[y f ]
S
S
Figure 24. Stop-Band Attenuation
Figure 25. Pass-Band Ripple
AMPLITUDE
vs
FREQUENCY
0
−2
−4
−6
−8
−10
−12
−14
−16
−18
−20
0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54
Frequency[y f ]
S
Figure 26. Transition-Band Response
All specifications at T = 25°C, V
BUS
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted.
IN
A
s
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DAC ANALOG FIR FILTER FREQUENCY RESPONSE
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
−10
−20
−30
−40
−50
0.2
0.0
−0.2
−0.4
−0.6
−0.8
0
8
16
24
32
0.0
0.1
0.2
0.3
0.4
0.5
Frequency[y f ]
Frequency[y f ]
S
S
Figure 27. Stop-Band Characteristic
Figure 28. Pass-Band Characteristic
DAC ANALOG LOW-PASS FILTER FREQUENCY RESPONSE
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0
−10
−20
−30
−40
−50
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
1
10
100
1k
10k
0.01
0.1
1
10
100
f – Frequency – kHz
f – Frequency – kHz
Figure 29. Stop-Band Characteristic
Figure 30. Pass-Band Characteristic
All specifications at T = 25°C, V
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted.
IN
A
BUS
s
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SLES042A − JUNE 2002 − REVISED JUNE 2004
USB INTERFACE
Control data and audio data are transferred to the PCM2904/2906 via D+ (pin 1) and D– (pin 2). All data to/from
the PCM2904/2906 is transferred at full speed. The device descriprtor contains the information described in
Table 1. The device descriptor can be modified on request; contact a Texas Instruments representative about
the details.
Table 1. Device Descriptor
USB revision
1.1 compliant
Device class
0x00 (device defined interface level)
0x00 (not specified)
0x00 (not specified)
8 byte
Device sub class
Device protocol
Max packet size for end-point 0
Vendor ID
0x08BB (default value, can be modified)
0x2904/0x2906 (default value, can be modified)
1.0 (0x0100)
Product ID
Device release number
Number of configurations
Vendor string
1
String #1 (see Table 3)
String #2 (see Table 3)
Not supported
Product string
Serial number
The configuration descriptor contains the information described in Table 2. The configuration descriptor can be
modified on request; contact a Texas Instruments representative about the details.
Table 2. Configuration Descriptor
Interface
Four interfaces
Power attribute
Max power
0x80 (Bus powered, no remote wakeup)
0xFA (500 mA. Default value, can be modified)
The string descriptor contains the information described in Table 3. The string descriptor can be modified on
request; contact a Texas Instruments representative about the details.
Table 3. String Descriptor
#0
#1
#2
0x0409
Burr-Brown from TI (default value, can be modified)
USB audio codec (default value, can be modified)
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DEVICE CONFIGURATION
Figure 31 illustrates the USB audio function topology. The PCM2904/2906 has four interfaces. Each interface
is constructed by alternative settings.
End-Point #0
Default
End-Point
FU
End-Point #2
(IF #1)
Analog Out
IT
TID1
OT
TID2
Audio Streaming
Interface
UID3
End-Point #4
(IF #2)
Analog In
OT
TID5
IT
TID4
Audio Streaming
Interface
Standard Audio Control Interface (IF #0)
End-Point #5
(IF #3)
HID Interface
PCM2904/2906
Figure 31. USB Audio Function Topology
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Interface #0
Interface #0 is the control interface. Alternative setting #0 is the only possible setting for interface #0. Alternative
setting #0 describes the standard audio control interface. The audio control interface is constructed by a
terminal. The PCM2904/2906 has the following five terminals.
D Input terminal (IT #1) for isochronous-out stream
D Output terminal (OT #2) for audio analog output
D Feature unit (FU #3) for DAC digital attenuator
D Input terminal (IT #4) for audio analog input
D Output terminal (OT #5) for isochronous-in stream
Input terminal #1 is defined as a USB stream (terminal type 0x0101). Input terminal #1 can accept 2-channel
audio streams consisting of left and right channels. Output terminal #2 is defined as a speaker (terminal type
0x0301). Input terminal #4 is defined as a microphone (terminal type 0x0201). Output terminal #5 is defined
as a USB stream (terminal type 0x0101). Output terminal #5 can generate 2-channel audio streams consisting
of left and right channels. Feature unit #3 supports the following sound control features.
D Volume control
D Mute control
The built-in digital volume controller can be manipulated by an audio-class-specific request from 0.0 dB to
–64 dB in steps of 1 dB. Each channel can be set for different values. The master volume control is not
supported. A request to the master volume is stalled and ignored. The built-in digital mute controller can be
manipulated by audio-class-specific request. A master mute control request is acceptable. A request to an
individual channel is stalled and ignored.
Interface #1
Interface #1 is the audio streaming data-out interface. Interface #1 has the following seven alternative settings.
Alternative setting #0 is the zero-bandwidth setting. All other alternative settings are operational settings.
ALTERNATIVE
SETTING
TRANSFER
MODE
SAMPLING RATE
(kHz)
DATA FORMAT
00
01
02
03
04
05
06
Zero bandwidth
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
Offset binary (PCM8)
Offset binary (PCM8)
16 bit
16 bit
8 bit
8 bit
8 bit
8 bit
Stereo
Mono
Stereo
Mono
Stereo
Mono
Adaptive
Adaptive
Adaptive
Adaptive
Adaptive
Adaptive
32, 44.1, 48
32, 44.1, 48
32, 44.1, 48
32, 44.1, 48
32, 44.1, 48
32, 44.1, 48
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Interface #2
Interface #2 is the audio streaming data-in interface. Interface #2 has the following 19 alternative settings.
Alternative setting #0 is the zero-bandwidth setting. All other alternative settings are operational settings.
ALTERNATIVE
SETTING
TRANSFER
MODE
SAMPLING RATE
(kHz)
DATA FORMAT
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
Zero bandwidth
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
2s complement (PCM)
16 bit
16 bit
16 bit
16 bit
16 bit
16 bit
16 bit
16 bit
16 bit
16 bit
8 bit
Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
48
48
44.1
44.1
32
32
22.05
22.05
16
16
16
8 bit
16
8 bit
8
8 bit
8
16 bit
16 bit
8 bit
11.025
11.025
11.025
11.025
12
8 bit
Interface #3
Interface #3 is the interrupt data-in interface. Alternative setting #0 is the only possible setting for interface #3.
Interface #3 constructs the HID consumer control device. Interface #3 reports the following three key statuses.
D Mute (0xE209)
D Volume up (0xE909)
D Volume down (0xEA09)
End-Points
The PCM2904/2906 has the following four end-points.
D Control end-point (EP #0)
D Isochronous-out audio data stream end-point (EP #2)
D Isochronous-in audio data stream end-point (EP #4)
D HID end-point (EP #5)
The control end-point is a default end-point. The control end-point is used to control all functions of the
PCM2904/2906 by the standard USB request and USB audio class specific request from the host. The
isochronous-out audio data stream end-point is an audio sink end-point, which receives the PCM audio data.
The isochronous-out audio data stream end-point accepts the adaptive transfer mode. The isochronous-in
audio data stream end-point is an audio source end-point that transmits the PCM audio data. The
isochronous-in audio data stream end-point uses the asynchronous transfer mode. The HID end-point is an
interrupt-in end-point. The HID end-point reports HID0, HID1, and HID2 pin status in every 32 ms.
The human interface device (HID) pins are defined as consumer control devices. The HID function is designed
as an independent end-point from both isochronous-in and -out end-points. This means that the result obtained
from the HID operation depends on the host software. Typically, the HID function is used as a primary audio-out
device.
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Clock and Reset
The PCM2904/2906 requires a 12-MHz ( 500 ppm) clock for the USB and audio functions. The clock can be
generated by a built-in oscillator with a 12-MHz crystal resonator. The 12-MHz crystal resonator must be
connected to XTI (pin 21) and XTO (pin 20) with one high-value (1-MΩ) resistor and two small capacitors, the
capacitance of which depends on the load capacitance of the crystal resonator. An external clock can be
supplied to XTI (pin 21). If an external clock is used, XTO (pin 20) must be left open. Because there is no clock
disabling signal, use of the external clock supply is not recommended. SSPND (pin 28) is unable to use clock
disabling.
The PCM2904/2906 has an internal power-on reset circuit, which is triggered automatically when V
(pin 3)
BUS
exceeds 2.5 V typical (2.7 V to 2.2 V). About 700 µs is required until internal reset release.
Digital Audio Interface (PCM2906)
The PCM2906 employs S/PDIF for both input and output. Isochronous-out data from the host is encoded to
the S/PDIF output and the DAC analog output. Input data is selected from either the S/PDIF or ADC analog
input. When the device detects S/PDIF input and successfully locks the received data, the isochronous-in
transfer data source automatically selected is S/PDIF; otherwise, the data source selected is the ADC analog
input.
Supported Input Data (PCM2906)
The following data formats are accepted by S/PDIF for input and output. All other data formats are unusable
as S/PDIF.
D 48-kHz 16-bit stereo
D 44.1-kHz 16-bit stereo
D 32-kHz 16-bit stereo
Mismatch between the input data format and the host command may cause unexpected results, with the
following exceptions:
D Recording in monaural format from stereo data input at the same data rate
D Recording in 8-bit format from 16-bit data input at the same data rate
A combination of the two foregoing conditions is not accepted.
For playback, all possible data-rate sources are converted to the 16-bit stereo format at the same source data
rate.
Channel Status Information (PCM2906)
The channel status information is fixed as consumer application, PCM mode, copyright, and digital/digital
converter. All other bits are fixed as 0s except for the sample frequency, which is set automatically according
to the data received through the USB.
Copyright Management (PCM2906)
Isochronous-in data is affected by the serial copy management system (SCMS). When the control bit indicates
that the received digital audio data is original, the input digital audio data is transferred to the host. If the data
is indicated as first generation or higher, the transferred data is routed to the analog input.
Digital audio data output is always encoded as original with SCMS control.
The implementation of this feature is optional. It is the designer’s responsibility to determine whether to
implement this feature in a product or not.
23
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INTERFACE SEQUENCE
Power-On, Attach, and Playback Sequence
The PCM2904/2906 is ready for setup when the reset sequence has finished and the USB device is attached.
After a connection has been established by setup, the PCM2904/PCM2906 is ready to accept USB audio data.
While waiting for the audio data (idle state), the analog output is set to bipolar zero (BPZ).
When receiving the audio data, the PCM2904/2906 stores the first audio packet, which contained 1-ms audio
data, into the internal storage buffer. The PCM2904/2906 starts playing the audio data when detecting the
following start-of-frame (SOF) packet.
5.0 V
(Typ)
V
BUS
(Pin 3)
2.5 V (Typ)
0 V
st
1
nd
2 Audio Data
Bus Reset
Set Configuration
Audio Data
Bus Idle
D+/D−
SOF
SOF
SOF
SSPND
V
L
R
BPZ
OUT
V
OUT
Device Setup
1 ms
700 µs
Internal Reset
Ready for Setup
Ready for Playback
Figure 32. Initial Sequence
Play, Stop, and Detach Sequence
When the host finishes or aborts the playback, the PCM2904/2906 stops playing after the last audio data has
played.
Record Sequence
The PCM2904/2906 starts audio capture into the internal memory after receiving the SET_INTERFACE
command.
Suspend and Resume Sequence
The PCM2904/2906 enters the suspend state after a constant idle state on the USB bus, approximately 5 ms.
While the PCM2904/2906 enters the suspend state, the SSPND flag (pin 28) is asserted. The PCM2904/2906
wakes up immediately on detecting a non-idle state on the USB.
24
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SLES042A − JUNE 2002 − REVISED JUNE 2004
V
BUS
(Pin 3)
Audio Data
Audio Data
Last Audio Data
SOF
D+/D−
SOF
SOF
SOF
SOF
V
L
R
OUT
V
OUT
Detach
1 ms
Figure 33. Play, Stop, and Detach
Audio Data
Audio Data
IN Token
Audio Data
SET_INTERFACE
IN Token
IN Token
D+/D−
SOF
SOF
SOF
SOF
SOF
V
L
R
IN
V
IN
1 ms
Figure 34. Record Sequence
Idle
D+/D−
SSPND
Active
5 ms
Suspend
Active
Figure 35. Suspend and Resume
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SLES042A − JUNE 2002 − REVISED JUNE 2004
PCM2904 TYPICAL CIRCUIT CONNECTION 1
Figure 36 illustrates a typical circuit connection for a simple application. The circuit illustrated is for information
only. The whole board design should be considered to meet the USB specification as a USB compliant product.
1.5 kΩ y 3
1.5 kΩ
PCM2904
22 Ω
22 Ω
D+
D–
D+
D–
V
SSPND
1
2
28
27
26
25
C
3
V
DDI
V
DGND
TEST1
3
BUS
BUS
GND
DGNDU
HID0
4
5
TEST0 24
C
4
6
HID1
V
CCXI
23
7
HID2
AGNDX 22
C
C
IC1
IN OUT GND ADJ EN
5
1 MΩ
SEL0
SEL1
XTI
8
21
20
19
6
1
2
3
4
5
XTO
9
3.60 V –
3.85 V
12 MHz
10
V
CCCI
V
CCP2I
MUTE/
Power
Down
C
C
7
11 AGNDC
AGNDP 18
C
1
C
9
8
V
V
V
L
V
12
13
14
17
16
15
IN
CCP1I
22 kΩ 12 kΩ
C
10
C
C
LPF,
11
R
IN
V
L
OUT
Amp
C
2
12
V
R
OUT
COM
LPF,
Amp
NOTES:
C , C , C , C : 1 µF (These capacitors must be less than 2 µF.)
3
1
4
2:
7
8
C , C 10 µF
C , C : 10 pF to 33 pF (depending on crystal resonator)
5
6
C , C , C , C : The capacitance may vary depending on design.
9
10 11 12
IC1 : REG103xA-A (TI) or equivalent. Analog performance may vary depending on IC1.
Figure 36. Bus-Powered Configuration for High-Performance PCM2904 Application
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SLES042A − JUNE 2002 − REVISED JUNE 2004
PCM2906 TYPICAL CIRCUIT CONNECTION 1
Figure 37 illustrates a typical circuit connection for a simple application. The circuit illustrated is for information
only. The whole board design should be considered to meet the USB specification as a USB compliant product.
1.5 kΩ y 3
1.5 kΩ
PCM2906
22 Ω
22 Ω
D+
D–
D+
D–
V
SSPND
1
2
28
27
26
25
C
3
V
DDI
V
DGND
DOUT
3
BUS
BUS
GND
DGNDU
HID0
4
5
DIN 24
C
4
6
HID1
V
CCXI
23
7
HID2
AGNDX 22
C
C
IC1
IN OUT GND ADJ EN
5
1 MΩ
SEL0
SEL1
XTI
8
21
20
19
6
1
2
3
4
5
XTO
9
3.60 V –
3.85 V
12 MHz
10
V
CCCI
V
CCP2I
MUTE/
Power
Down
C
C
7
11 AGNDC
AGNDP 18
C
1
C
9
8
V
V
V
L
V
12
13
14
17
16
15
IN
CCP1I
22 kΩ 12 kΩ
C
10
C
C
LPF,
11
R
IN
V
L
OUT
Amp
C
2
12
V
R
OUT
COM
LPF,
Amp
NOTES:
C , C , C , C : 1 µF (These capacitors must be less than 2 µF.)
3
1
4
2:
7
8
C , C 10 µF
C , C : 10 pF to 33 pF (depending on crystal resonator)
5
6
C , C , C , C : The capacitance may vary depending on design.
9
10 11 12
IC1 : REG103xA-A (TI) or equivalent. Analog performance may vary depending on IC1.
Figure 37. Bus-Powered Configuration for High-Performance PCM2906 Application
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SLES042A − JUNE 2002 − REVISED JUNE 2004
PCM2904 TYPICAL CIRCUIT CONNECTION 2
Figure 38 illustrates a typical circuit connection for a simple application. The circuit illustrated is for information
only. The whole board design should be considered to meet the USB specification as a USB compliant product.
1.5 kΩ y 4
PCM2904
22 Ω
D+
D–
D+
D–
V
SSPND
1
2
28
27
26
25
22 Ω
C
C
3
V
DDI
V
DGND
TEST1
3
BUS
BUS
GND
DGNDU
HID0
4
5
TEST0 24
4
6
HID1
V
CCXI
23
7
HID2
AGNDX 22
C
5
C
6
C
7
1 MΩ
SEL0
SEL1
XTI
8
21
20
19
XTO
9
12 MHz
C
C
1
10
V
CCCI
V
CCP2I
MUTE/
Power
Down
11 AGNDC
AGNDP 18
C
8
C
9
V
V
V
L
V
12
13
14
17
16
15
IN
CCP1I
C
10
C
11
LPF,
R
IN
V
L
OUT
Amp
C
12
2
V
R
OUT
COM
LPF,
Amp
NOTES:
C , C , C , C : 1 µF (These capacitors must be less than 2 µF.)
3
1
4
2:
7
8
C , C 10 µF
C , C : 10 pF to 33 pF (depending on crystal resonator)
5
6
C , C , C , C : The capacitance may vary depending on design.
9
10 11 12
In this case, the analog performance of the A/D converter may be degraded.
Figure 38. PCM2904 Bus-Powered Configuration
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SLES042A − JUNE 2002 − REVISED JUNE 2004
PCM2906 TYPICAL CIRCUIT CONNECTION 2
Figure 39 illustrates a typical circuit connection for a simple application. The circuit illustrated is for information
only. The whole board design should be considered to meet the USB specification as a USB compliant product.
1.5 kΩ x 4
PCM2906
22 Ω
D+
D–
D+
D–
V
SSPND
1
2
28
27
26
25
22 Ω
C
C
3
V
DDI
V
DGND
DOUT
3
BUS
BUS
GND
DGNDU
HID0
4
5
DIN 24
4
6
HID1
V
CCXI
23
7
HID2
AGNDX 22
C
5
C
6
C
7
1 MΩ
SEL0
SEL1
XTI
8
21
20
19
XTO
9
12 MHz
C
C
1
10
V
CCCI
V
CCP2I
MUTE/
Power
Down
11 AGNDC
AGNDP 18
C
8
C
9
V
V
V
L
V
12
13
14
17
16
15
IN
CCP1I
C
10
C
11
LPF,
R
IN
V
L
OUT
Amp
C
12
2
V
R
OUT
COM
LPF,
Amp
NOTES:
C , C , C , C : 1 µF (These capacitors must be less than 2 µF.)
3
1
4
2:
7
8
C , C 10 µF
C , C : 10 pF to 33 pF (depending on crystal resonator)
5
6
C , C , C , C : The capacitance may vary depending on design.
9
10 11 12
In this case, the analog performance of the A/D converter may be degraded.
Figure 39. PCM2906 Bus-Powered Configuration
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APPLICATION INFORMATION
OPERATING ENVIRONMENT
To get the appropriate operation, one of the following operating systems must be working on the host PC that
has the USB port assured by the manufacturer. If the condition is fulfilled, the operation of the PCM2904/2906
does not depend on the operating speed of the CPU.
Texas Instruments has confirmed following operating environments.
D Operating System
−
−
−
Microsoft Windows 98/98SE/Me Japanese/English Edition
Microsoft Windows 2000 Professional Japanese/English Edition
Microsoft Windows XP Home/Professional Japanese/English Edition (For Windows XP, use the
latest version of the USB audio driver that is available on Windows update site)
−
−
−
Apple Computer Mac OS 9.1 or later Japanese/English Edition
Apple Computer Mac OS X 10.0 or later English Edition
Apple Computer Mac OS X 10.1 or later Japanese Edition (For Mac OS X 10.0 Japanese Edition, plug
and play does not work for USB audio device appropriately)
D PC: Following PC-AT compatible computers for above OS (OS requirement must be met)
−
−
−
−
−
−
−
−
−
−
−
−
Motherboard using Intel 440BX or ZX chipset (using USB controller in the chipset)
Motherboard using Intel i810 chipset (using USB controller in the chipset)
Motherboard using Intel i815 chipset (using USB controller in the chipset)
Motherboard using Intel i820 chipset (using USB controller in the chipset)
Motherboard using Intel i845 chipset (using USB controller in the chipset)
Motherboard using Intel i850 chipset (using USB controller in the chipset)
Motherboard using Apollo KT133 chipset (using USB controller in the chipset)
Motherboard using Apollo Pro plus chipset (using USB controller in the chipset)
Motherboard using MVP4 or MVP3 chipset (using USB controller in the chipset)
Motherboard using Aladdin V chipset (using USB controller in the chipset)
Motherboard using SiS530 or SiS559 chipset (using USB controller in the chipset)
Motherboard using SiS735 chipset (using USB controller in the chipset)
NOTE: The OSs and PCs for which the operation of the PCM2904/2906 was confirmed are listed above. The PCM2904/2906 may also work with
other OSs and PCs that have not been tested. Furthermore, there is no assurance that the PCM2904/2906 will work with every PC having
a compatible chipset, because other design factors of the motherboard may also cause incompatibility.
The PCM2904/2906 has been acknowledged in the USB compliance test. However, the acknowledgement is just for the
PCM2904/2906 from Texas Instruments. Be careful that the acknowledgement is not for the customer’s USB system using
the PCM2904/2906.
30
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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相关型号：
PCM2906DBRG4
Stereo USB1.1 CODEC with line-out and S/PDIF I/O, Bus-powered (HID Interface + 500mA USB Current) 28-SSOP
TI
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