MPC801 [BB]
High Speed CMOS ANALOG MULTIPLEXER; 高速CMOS模拟多路复用器
| 型号： | MPC801 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | High Speed CMOS ANALOG MULTIPLEXER |
| 文件： | 总8页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
MPC801
High Speed
CMOS ANALOG MULTIPLEXER
FEATURES
● HIGH SPEED
● SELECTABLE TTL OR CMOS
COMPATIBILITY
80ns Access Time
800ns Settling to 0.01%
250ns Settling to 0.1%
● WILL NOT SHORT SIGNAL SOURCES —
Break-Before-Make Switching
● USER-PROGRAMMABLE
8-Channel Single-Ended or
4-Channel Differential
● SELF-CONTAINED WITH INTERNAL
CHANNEL ADDRESS DECODER
● 18-PIN HERMETIC DUAL-IN-LINE
PACKAGE
A2 Decode
DESCRIPTION
VREF
A2
H
L
Q
H
L
Q
L
The MPC801 is a high speed multiplexer that is user-
programmable for 8-channel single-ended operation
or 4-channel differential operation and for TTL or
CMOS compatibility.
H
L
In 1A
Out A
V
L
N
N
N
N
P
P
P
P
EN
A0
The MPC801 features a self-contained binary address
decoder. It also has an enable line which allows the
user to inhibit the entire multiplexer thereby facilitat-
ing channel expansion by adding additional multi-
plexers.
Decoder
A1
In 4A
A2
Q
High quality processing is employed to produce CMOS
FET analog channel switches which have low leakage
current, low ON resistance, high OFF resistance, low
feedthrough capacitance, and fast settling time.
A2
Decoder
In 1B
Out B
Q
Two models are available, the MPC801KG for opera-
tion from 0°C to +75°C.
Decoder
In 4B
Input Buffer and Decoders
Multiplexer
Switches
International Airport Industrial Park
Tel: (520) 746-1111
•
Mailing Address: PO Box 11400
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
• Tucson, AZ 85706
•
Twx: 910-952-1111
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1985 Burr-Brown Corporation
PDS-464A
Printed in U.S.A. October, 1993
SPECIFICATIONS
ELECTRICAL
At TA = +25°C and ±VCC = 15V, unless otherwise noted.
MPC801KG
TYP
PARAMETER
MIN
MAX
UNITS
ANALOG INPUTS
Voltage Range
–15
–VCC –2
+15
+VCC +2
V
V
Maximum Overvoltage
Number of Input Channels
Differential
4
8
6
Single-Ended
Reference Voltage Range(1)
ON Characteristics(2)
ON Resistance (RON) at +25°C
Over Temperature Range
RON Drift vs Temperature
RON Mismatch
10
V
500
700
750
1000
Ω
Ω
See Typical Performance Curves
< 10
Ω
ON Channel Leakage
Over Temperature Range
ON Channel Leakage Drift
OFF Characteristics
0.1
0.3
nA
nA
50
See Typical Performance Curves
OFF Isolation
90
0.05
0.6
dB
nA
nA
OFF Channel Input Leakage
Over Temperature Range
OFF Channel Input Leakage Drift
OFF Channel Output Leakage
Over Temperature Range
OFF Channel Output Leakage Drift
Output Leakage
50
50
See Typical Performance Curves
0.1
0.30
nA
nA
See Typical Performance Curves
(All channels disabled)(3)
Output Leakage with Overvoltage
+16V Input
0.02
nA
< 0.35
< 0.65
mA
mA
–16V Input
DIGITAL INPUTS
Over Temperature Range
TTL(4)
Logic “0” (VAL
Logic “1” (VAH
)
)
0.8
V
V
µA
µA
V
2.4
–6
IAH
IAL
TTL Input Overvoltage
CMOS
Logic “0” (VAL
Logic “1” (VAH
CMOS Input Overvoltage
Address A2 Overvoltage
Digital Input Capacitance
Channel Select(5)
Single-Ended
0.05
4
1
20
6
)
)
0.3VREF
V
V
V
V
pF
0.7VREF
–2
–VCC –2
+VCC +2
+VCC +2
5
3-bit Binary Code One of 8
2-bit Binary Code One of 4
Logic “0” Inhibits All Channels
Differential
Enable
POWER REQUIREMENTS
Over Temperature Range
Rated Supply Voltage
±15
V
Maximum Voltage Between
Supply Pins
33
V
Total Power Dissipation
Allowable Total Power Dissipation(6)
Supply Drain (+25°C)
360
mW
mW
725
At 1MHz Switching Speed
At 100kHz Switching Speed
+14, –12.5
+12.5, –12.5
mA
mA
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
2
MPC801
SPECIFICATIONS (CONT)
ELECTRICAL
At TA = +25°C and ±VCC = 15V, unless otherwise noted.
MPC801KG
TYP
PARAMETER
MIN
MAX
UNITS
DYNAMIC CHARACTERISTICS
Gain Error
Crosstalk(7)
< 0.0003
See Typical Performance Curves
%
TOPEN (Break-before-make delay)
Access Time at +25°C
Over Temperature Range
Settling Time(8)
20
80
110
ns
ns
ns
125
150
to 0.1% (20mV)
to 0.01% (2mV)
250
800
ns
ns
Common-Mode Rejection (Differential)
DC
60Hz
OFF Channel Input Capacitance, CS
OFF Channel Output Capacitance, CO
OFF Input to Output Capacitance, CDS
> 125
> 75
1.9
10
0.02
dB
dB
pF
pF
pF
TEMPERATURE
MPC800KG
Specification
Storage
0
–65
+75
+150
°C
°C
NOTES: (1) Reference voltage controls noise immunity, normally left open for TTL compatibility and connected to VDD for CMOS compatibility. (2) VIN = ±10V, IOUT
= 100µA. (3) Single-ended mode. (4) Logic levels specified for VREF (pin 8) open. (5) For single-ended operation, connect output A (pin 18) to output B (pin 2) and
use A2 (pin 9) as an address line. For differential operation connect A2 to –VCC. (6) Derate 8mW/°C above TA = +75°C. (7) 10Vp-p sine wave on all unused channels.
See Typical Performance Curves. (8) For 20V step input to ON channel, into 1kΩ load.
PIN CONFIGURATION
ORDERING INFORMATION
MODEL
PACKAGE
TEMPERATURE RANGE
Top View
MPC801KG
Cerdip
0°C to +75°C
+VCC
Out B
IN8/4B
IN7/3B
IN6/2B
IN5/1B
GND
1
2
3
4
5
6
7
8
9
18 Out A
17 –VCC
16 IN4/4A
15 IN3/3A
14 IN2/2A
13 IN1/1A
12 ENABLE
11 A0
PACKAGE INFORMATION
PACKAGE DRAWING
NUMBER(1)
MODEL
PACKAGE
MPC801KG
18-Pin Single-Wide Cerdip
266
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
VREF
A2
10 A1
®
3
MPC801
TYPICAL PERFORMANCE CURVES
At TA = +25°C and ±VCC = 15V, unless otherwise noted.
CROSS TALK vs SIGNAL FREQUENCY
1
LEAKAGE CURRENTS vs TEMPERATURE
1000
100
10
0.1
0.01
“ON” Channel
“OFF” Output
0.001
1
“OFF” Input
0.0001
0.1
0.00001
0.01
100
1k
10k
100k
1M
10M
1M
75
25
35
45
55
65
75
Signal Frequency (Hz)
Temperature (°C)
SETTLING TIME vs SOURCE RESISTANCE
COMBINED CMR vs FREQUENCY
FOR MODEL 3630 AND MPC800
(20V Step Change, RL = 1kΩ)
1000
800
600
400
140
120
100
80
G = 1000
To 0.01%
Balanced Source
Unbalanced = 1kΩ
To 0.1%
200
0
60
40
Unbalanced = 10kΩ
0
0.01
0.1
1
10
100
10
100
1k
10k
100k
Source Resistance (kΩ)
Frequency (Hz)
RON DRIFT vs TEMPERATURE
500
400
300
200
100
0
25
35
45
55
65
Temperature (°C)
®
4
MPC801
Input Offset Voltage
DISCUSSION OF
PERFORMANCE
STATIC TRANSFER ACCURACY
Bias and leakage currents generate an input offset voltage as
a result of the voltage drop across the multiplexer ON
resistance and source resistance. A load bias current of
10nA, a leakage current of 1nA, and an ON resistance of
700Ω will generate an offset voltage of 19µV if a 1000Ω
source is used, and 118µV if a 10kΩ source is used. In
general, for the MPC801 the offset voltage at the output is
determined by:
The static or DC transfer accuracy of transmitting the mul-
tiplexer input voltage to the output depends on the channel
ON resistance (RON), the load impedance, the source imped-
ance, the load bias current, and the multiplexer leakage
current.
VOFFSET = (IB + IL) (RON + RSOURCE
)
where:
Single-Ended
Multiplexer Static Accuracy
The major contributors to static transfer accuracy for single-
ended multiplexers are:
IB = Bias current of device multiplexer is driving
IL = Multiplexer leakage current
RON = Multiplexer ON resistance
RSOURCE = Source resistance
Source resistance loading error
Multiplexer ON resistance error
DC offset error caused by both load bias current and
multiplexer leakage current.
Differential Multiplexer Static Accuracy
Static accuracy errors in a differential multiplexer are diffi-
cult to control, especially when it is used for multiplexing
low level signals with full scale ranges of 10mV to 100mV.
Resistive Loading Errors
The source and load impedances will determine the ON
resistance loading errors. To minimize these errors:
The matching properties of the multiplexer, source and
output load play a very important part in determining the
transfer accuracy of the multiplexer. The source impedance
unbalance, common-mode impedance, load bias current
mismatch, load differential impedance mismatch, and com-
mon-mode impedance of the load all contribute errors to the
multiplexer. The multiplexer ON resistance mismatch, leak-
age current mismatch and ON resistance also contribute to
differential errors.
• Keep loading impedance as high as possible. This mini-
mizes the resistive loading effects of the source resistance
and multiplexer ON resistance. As a guideline, load
impedance of 108Ω or greater will keep resistive loading
errors to 0.002% or less for 1000Ω source impedances. A
106Ω load impedance will increase source loading error
to 0.2% or more.
• Use sources with impedances as low as possible. A
1000Ω source resistance will present less than 0.002%
loading error and 10kΩ source resistance will increase
source loading error 0.02% with a 108Ω load impedance.
Referring to Figure 2, the effects of these errors can be
minimized by following the general guidelines described in
this section, especially for low level multiplexing applica-
tions.
Input resistive loading errors are determined by the follow-
ing relationship (see Figure 1):
RS1A
RON1A
I BiasA
Source and Multiplexer Resistive Loading Error
Z Load
C
RD/2
CD/2
CD/2
RS + RON
ILA
VCC1
(RS + RON) =
x 100%
CM
RS + RON + RL
I BiasB
RS1B
RON1B
R
RCM
1
VCC4
CM
where, RS = RSOURCE
RD/2
ILB
RS4A
ROFF4A
RL = Load resistance
ROS = Multiplexer ON resistance
VCC16
RS4B
ROFF4B
RCM4
RS1
RON
I Bias
Vm
IL
VCC1
FIGURE 2. MPC801 Static Accuracy Equivalent Circuit
(Differential Operation).
Measured
Voltage
RS8
ROFF
Z Load
Load (Output Device) Characteristics
VCC8
• Use devices with very low bias current. Generally, FET
input amplifiers should be used for low level signals less
than 50mV FSR. Low bias current bipolar input amplifi-
ers are acceptable for signal ranges higher than 50mV
FSR. Bias current matching will determine input offset.
FIGURE 1. MPC801 Static Accuracy Equivalent Circuit
(Single-ended Operation).
®
5
MPC801
• The system DC common-mode rejection (CMR) can never
be better than the combined CMR of multiplexer and
driven load. System CMR will be less than the device
which has the lower CMR figure.
SETTLING TIME
Settling time is the time required for the multiplexer to reach
and maintain an output within a specified error band of its
final value in response to a step input. The settling time of
the MPC801 is primarily due to the channel capacitance and
a combination of resistances which include the source and
load resistances.
• Load impedances, differential and common-mode should
be 1010Ω or higher.
If the parallel combination of the source and load resistance
times the total channel capacitance is kept small, then the
settling time is primarily affected by internal RCs. For the
MPC801, the internal capacitance is approximately 10pF
differential or 20pF single-ended. With external capacitance
neglected, the time constant of source resistance in parallel
with load resistance and the internal capacitance should be
kept less than 40ns. This means the source resistance should
be kept to less than 4kΩ (assume high load resistance) to
maintain fast settling times.
Source Characteristics
• The source impedance unbalance will produce offset,
common-mode and channel-to-channel gain scatter
errors. Use sources which do not have large impedance
unbalances if at all possible.
• Keep source impedances as low as possible to minimize
resistive loading errors.
• Minimize ground loops. If signal lines are shielded, ground
all shields to a common point at the system analog
common.
If the MPC801 is used for multiplexing high level signals of
1V to 10V full scale ranges, the foregoing precautions
should be taken, but the parameters are not as critical as for
low level signal applications.
ACCESS TIME
This is the time required for the CMOS FET to turn ON after
a new digital code has been applied to the Channel Address
inputs. It is measured from the 50 percent point of the
address input signal to the 90 percent point of the analog
signal seen at the output for a 10V signal change between
channels.
Source
Load
Node A
RLOAD
CLOAD
CS
CROSSTALK
Crosstalk is the amount of signal feedthrough from the
3 differential or 7 signal-ended OFF channels appearing at
the multiplexer output. Crosstalk is caused by the voltage
divider effect of the OFF channel. OFF resistance, and
junction capacitances in series with the RON and RSOURCE
impedances of the ON channel. Crosstalk is measured with
RSOURCE
FIGURE 3. Settling Time Effects (Single-ended).
RSA
Node A
RDA
CSA
CDA
RCMS
Load
Source
CSB
CDB
CCMS
RDB
Node B
RSB
FIGURE 4. Settling and Common-Mode Effects (Differential).
®
6
MPC801
a 20Vp-p, 1000Hz sine wave applied to all OFF channels.
The crosstalk for these multiplexers is shown in the Typical
Performance Curves.
common-mode capacitance balance and reduce stray signal
pickup. If shields are used, all shields should be connected
as close as possible to system analog common or to the
common-mode guard driver.
COMMON-MODE REJECTION
(Differential Mode Only)
LOGIC LEVELS
The matching properties of the load, multiplexer and source
affect the common-mode rejection (CMR) capability of a
differentially multiplexed system. CMR is the ability of the
multiplexer and input amplifier to reject signals that are
common to both inputs, and to pass on only the signal
difference to the output. Protection is provided for common-
mode signals of ±2V above the power supply voltages with
no damage to the analog switches.
The logic level is user-programmable as either TTL-compat-
ible by leaving the VREF (pin 8) open, or CMOS-compatible
by connecting the VREF to VDD (CMOS supply voltage).
16-CHANNEL SINGLE-ENDED OPERATION
To use the MPC801 as a 8-channel single-ended multi-
plexer, output A (pin 18) is connected to output B (pin 2) to
form a single output, then all three address lines (A0, A1 and
A2) are used to address the correct channel.
The CMR of the MPC801 and Burr-Brown’s model 3630
instrumentation amplifier is 120dB at DC to 10Hz with a
6dB/octave rolloff to 80dB at 1000Hz. This measurement of
CMR is shown in the Typical Performance Curves and is
made with a Burr-Brown model 3630 instrumentation am-
plifier connected for a gain of 1000 and with source unbal-
ance of 10kΩ, 1kΩ and no unbalance.
The MPC801 can also be used as a dual channel single-
ended multiplexer by not connecting output A and B, but
then only one channel in one of the multiplexers can be
addressed at a time.
8-CHANNEL DIFFERENTIAL OPERATION
Factors which will degrade multiplexer and system DC
CMR are:
To use the MPC801 as an 4-channel differential multiplexer,
connect address line A2 to –VCC then use the remaining
two address lines (A0, and A1) to address the correct channel.
The differential inputs are the pairs of A1 and B1, A2 and B2,
etc.
• Amplifier bias current and differential impedance mis-
match.
• Load impedance mismatch.
• Multiplexer impedance and leakage current mismatch.
• Load and source common-mode impedance.
TRUTH TABLES
AC CMR rolloff is determined by the amount of common-
mode capacitances (absolute and mismatch) from each sig-
nal line to ground. Larger capacitances will limit CMR at
higher frequencies; thus, if good CMR is desired at higher
frequencies, the common-mode capacitances and unbalance
of signal lines and multiplexer to amplifier wiring must be
minimized. Use twisted-shielded pair signal lines wherever
possible.
MPC801 used as an 8-channel single-ended multiplexer or
4-channel dual multiplexer.
USE A2 AS DIGITAL ADDRESS INPUT
“ON” CHANNEL TO
ENABLE
A2
A1
A0
OUT A
OUT B
L
X
L
X
L
X
L
None
1A
None
None
None
None
None
1B
H
H
H
H
H
H
H
H
L
L
H
L
2A
L
H
H
L
3A
L
H
L
4A
INSTALLATION AND
OPERATING INSTRUCTIONS
The ENABLE input, pin 12, is included for expansion of the
number of channels on a single-node as illustrated in Figure
5. With the ENABLE line at a logic 1, the channel is selected
by the Channel Select Address (shown in the Truth Tables).
If ENABLE is at logic 0, all channels are turned OFF, even
if the Channel Address Lines are active. If the ENABLE line
is not to be used, simply tie it to logic 1.
H
H
H
H
None
None
None
None
L
H
L
2B
H
H
3B
H
4B
For 8-channel single-ended function, tie “out A” to “out B”, for dual
4-channel function use the A2 address pin to select between MUX A and
MUX B, where MUX A is selected with A2 low.
MPC801 used as a 4-channel differential multiplexer.
A2 CONNECT TO –VCC
“ON” CHANNEL TO
For the best settling time, the input wiring and interconnec-
tions between multiplexer output and driven devices should
be kept as short as possible. When driving the digital inputs
from TTL, open collector output with pullup resistors are
recommended.
ENABLE
A1
A0
OUT A
OUT B
L
X
L
X
L
None
1A
None
1B
H
H
H
H
L
H
L
2A
2B
H
H
3A
3B
To preserve common-mode rejection of the MPC801, use
twisted-shielded pair wire for signal lines and inter-tier
connections and/or multiplexer output lines. This will help
H
4A
4B
®
7
MPC801
CHANNEL EXPANSION
6), or up to five MPC801s can be connected in a two-tier
structure to form a 16-channel differential multiplexer. Pro-
gramming is accomplished with a 6-bit address.
Single-Tier Expansion
Up to eight MPC801s can be connected to a single node to
form a 64-channel single-ended multiplexer, or up to eight
MPC801s can be connected to two nodes to form a
32-channel differential multiplexer. Programming is
accomplished with a 6-bit address and a 1-of-8 decoder (see
Figure 5). The decoder drives the enable inputs of the
MPC801 turning on only one multiplexer at a time.
SINGLE VS MULTITIERED CHANNEL EXPANSION
In addition to reducing programming complexity, two-tier
configuration offers the added advantages over single-node
expansion of reduced OFF channel current leakage (reduced
Offset), better CMR, and a more reliable configuration if a
channel should fail in the ON condition (short). Should a
channel fail ON in the single-node configuration, data can-
not be taken from any channel, whereas only one-channel
group is failed (4 or 8) in the multitiered configuration.
Two-Tier Expansion
Up to nine MPC801s can be connected in a two-tier structure
to form a 64-channel single-ended multiplexer (see Figure
6-Bit Channel
6-Bit Channel
Address Generator
Address Generator
1 of 8
A0 A1 A2
In1
A0 A1 A2
Decoder
In1
In2
In3
In2
In3
MPC801
MPC801
Multiplexer
Enable
Output
Enable
Out A
Out B
A1 A2 A3
In1
In2
In3
Out A
Out B
In8
In8
MPC801
Enable
Out A
Out B
In8
A0 A1 A2
A0 A1 A2
In1
In2
In3
In1
In2
In3
Multiplexer
Output
MPC801
MPC801
Enable
Out A
Out B
Enable
Out A
Out B
In8
In8
To multiplexers 3 - 8
To multiplexers 3 - 8
FIGURE5. 64-channel, Single-tier, Single-endedExpansion.
FIGURE 6. 64-channel, Two-tier, Single-ended Expansion.
®
8
MPC801
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