DRV103H/2K5 [BB]
PWM LOW-SIDE DRIVER (1.5A and 3A) for Solenoids, Coils, Valves, Heaters, and Lamps; PWM低侧驱动器（ 1.5A和3A）的螺线管，线圈，阀，发热器和灯
| 型号： | DRV103H/2K5 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | PWM LOW-SIDE DRIVER (1.5A and 3A) for Solenoids, Coils, Valves, Heaters, and Lamps |
| 文件： | 总24页 (文件大小：1084K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV103
D
R
V
1
0
3
D
R
V
1
0
3
SBVS029A – JUNE 2001
PWM LOW-SIDE DRIVER (1.5A and 3A)
for Solenoids, Coils, Valves, Heaters, and Lamps
DESCRIPTION
FEATURES
The DRV103 is a low-side DMOS power switch employing
a pulse-width modulated (PWM) output. Its rugged design is
optimized for driving electromechanical devices such as
valves, solenoids, relays, actuators, motors, and positioners.
The DRV103 is also ideal for driving thermal devices such
as heaters, coolers, and lamps. PWM operation conserves
power and reduces heat rise, resulting in higher reliability. In
addition, adjustable PWM allows fine control of the power
delivered to the load. DC-to-PWM output delay time and
oscillator frequency are also externally adjustable.
● HIGH OUTPUT DRIVE: 1.5A and 3A Versions
● WIDE SUPPLY RANGE: +8V to +32V
● COMPLETE FUNCTION
Digitally Controlled Input
PWM Output
Adjustable Internal Oscillator: 500Hz to 100kHz
Adjustable Delay and Duty Cycle
● FULLY PROTECTED
Thermal and Current Limit Shutdown with
Status OK Indicator Flag
The DRV103 can be set to provide a strong initial closure,
automatically switching to a “soft” hold mode for power
savings. A resistor, analog voltage, or Digital-to-Analog
(D/A) converter can control the duty cycle. An output OK flag
indicates when thermal shutdown or over current occurs.
● PACKAGES: SO-8 and PowerPAD™ SO-8
APPLICATIONS
● ELECTROMECHANICAL DRIVER:
Two packages provide a choice of output current:
1.5A (SO-8) or 3A (PowerPAD™ SO-8 with exposed metal
heat sink).
Solenoids, Valves, Positioners, Actuators,
Relays, Power Contactor Coils, Heaters, Lamps
● HYDRAULIC AND PNEUMATICS SYSTEMS
● PART HANDLERS AND SORTERS
● CHEMICAL PROCESSING
The DRV103 is specified for –40°C to +85°C.
● ENVIRONMENTAL MONITORING AND HVAC
● THERMOELECTRIC COOLERS
Status OK
Flag
+VS
● DC MOTOR SPEED CONTROLS
● MEDICAL AND SCIENTIFIC ANALYZERS
● FUEL INJECTOR DRIVERS
Flyback
Diode
Load
DRV103
ESD
Thermal Shutdown
Over Current
DMOS
OUT
GND
PowerPAD is a trademark of Texas Instruments.
VREF
Oscillator
PWM
DMOS
Input
On
Off
Delay
Delay
Osc Freq
Duty Cycle
Adj
Adj
Adj
RFREQ
RPWM
CD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DRV103U
"
SO-8
"
182
"
–40°C to +85°C
DRV103U
"
DRV103U
DRV103U/2K5
Rails
Tape and Reel
"
DRV103H
"
PowerPAD™ SO-8
"
DDA
"
–40°C to +85°C
DRV103H
"
DRV103H
DRV103H/2K5
Rails
Tape and Reel
"
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500
pieces of “DRV103U/2K5” will get a single 2500-piece Tape and Reel.
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Supply Voltage, VS(2) ......................................................................... +40V
Input Voltage .................................................................. –0.2V to +5.5V(3)
PWM Adjust Input .......................................................... –0.2V to +5.5V(3)
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Delay Adjust Input .......................................................... –0.2V to +5.5V(3)
Frequency Adjust Input .................................................. –0.2V to +5.5V(3)
Status OK Flag and OUT .................................................... –0.2V to VS
Operating Temperature Range ......................................–55°C to +125°C
Storage Temperature Range .........................................–65°C to +150°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
(4)
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may de-
grade device reliability. (2) See Bypassing section for discussion about
operating near maximum supply voltage. (3) Higher voltage may be applied
if current is limited to 2mA. (4) The Status OK Flag will internally current limit
at about 10mA.
DRV103
2
SBVS029A
ELECTRICAL CHARACTERISTICS
At TC = +25°C, VS = +24V, Load = 100Ω, and 4.99kΩ “OK Flag” pullup to +5V, Delay Adj Capacitor = 100pF to Ground, Freq Adj Resistor = 205kΩ to Ground,
Duty Cycle Adj Resistor = 137kΩ to Ground, unless otherwise noted.
DRV103U, H
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT
Output Current(1)
SO-8 Package (U)
PowerPAD™ SO-8 Package (H)
IO = 1A
1.5
3
A
A
Output Saturation Voltage, Source
+0.4
+0.05
3.5
+0.6
+0.07
4.2
V
IO = 0.1A
V
Current Limit(2), (10)
Leakage Current
3
A
DMOS Output Off, VO = +32V
±1
±10
µA
DIGITAL CONTROL INPUT(3)
VCTR Low (output disabled)
VCTR High (output enabled)
ICTR Low (output disabled)
ICTR High (output enabled)
Propagation Delay
0
+1.2
+5.5
1
V
V
+2.2
VCTR = 0V
VCTR = +5.5V
0.01
120
1
µA
µA
µs
150
On-to-Off and Off-to-On
DELAY TO PWM(4)
DC to PWM Mode
Delay Equation(5)
See Note (6)
s
Delay Time
Minimum Delay Time(7)
CD = 0.1µF
CD = 0
90
110
18
140
ms
µs
DUTY CYCLE ADJUST
Duty Cycle Range
Duty Cycle Accuracy
vs Supply Voltage
Nonlinearity(8)
10 to 90
%
%
50% Duty Cycle, 25kHz
50% Duty Cycle, VS = VO = +8V to +32V
10% to 90% Duty Cycle
±2
±2
1
%
% FSR
DYNAMIC RESPONSE
Output Voltage Rise Time
Output Voltage Fall Time
Oscillator Frequency Range
Oscillator Frequency
VO = 10% to 90% of VS
VO = 90% to 10% of VS
External Adjust
0.2
0.2
2
2
µs
µs
0.5 to 100
25
kHz
kHz
ROSC = 205kΩ
20
30
OK FLAG
Normal Operation
Fault(90)
20kΩ Pull-Up to +5V
Sinking 1mA
+4.5
5.0
+0.22
2
V
V
+0.4
Sink Current
VOKFLAG = 0.4V
mA
µs
Over-Current Flag: Set
5
THERMAL SHUTDOWN
Junction Temperature
Shutdown
+160
+140
°C
°C
Reset from Shutdown
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
+24
0.4
V
V
+8
+32
0.8
IO = 0
mA
TEMPERATURE RANGE
Specified Range
–40
–55
–65
+85
+125
+150
°C
°C
°C
Operating Range
Storage Range
Thermal Resistance, θJA
SO-8 (U)
PowerPAD™ SO-8 (H)(10)
1in2 0.5oz. Copper on PCB
1in2 0.5oz. Copper on PCB
150
68
°C/W
°C/W
NOTES: (1) Output current is limited by internal current limit and by DRV103 power dissipation. (2) Output current resets to zero when current limit is reached.
(3) Logic High enables output (normal operation). (4) Constant DC output to PWM (Pulse-Width Modulated) time. (5) Maximum delay is determined by an external
capacitor. Pulling the Delay Adjust Pin LOW corresponds to an infinite (continuous) delay. (6) Delay to PWM
≈ CD •
106 (CD in
F • 1.1). (7) Connecting the Delay Adjust Pin to +5V reduces delay time to less than 1µs. (8) VIN at pin 3 to percent of duty cycle at pin 6. (9) OK Flag LOW indicates
fault from over-temperature or over-current conditions. (10) PowerPAD™ SO-8 (H) package has highest continuous current (2A) because the chip operates at a
lower junction temperature when underside metal tab is connected to a heat sink or heat spreader. θJA = 68°C/W measured on DRV103 demo board;
θJA = 58°C/W measured on JEDEC standard test board. H package θJC = 16.7°C/W.
DRV103
SBVS029A
3
PIN CONFIGURATION
SO
Top View
Duty Cycle Adj
Delay Adj
1
2
3
4
8
7
6
5
Input
Status OK Flag
+VS
Osc Freq Adj
GND
OUT
PIN DESCRIPTIONS
PIN #
NAME
DESCRIPTION
Pin 1 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a (2.75 x IREF) current source from VS. The voltage at this node linearly
sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage, or the voltage output of a D/A converter. The
active voltage range is from 1.3V to 3.9V to facilitate the use of single-supply control electronics. At 3.56V, output duty cycle is near
90%. At 1.5V, output duty cycle is near 10%.
Pin 2
Delay Adjust
This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results
in a delay of approximately 18µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than
1µs by tying the pin to 5V. This pin connects internally to a 3µA current source from VS and to a 2.6V threshold comparator. When
the pin voltage is below 2.6V, the output device is 100% ON. The PWM oscillator is not synchronized to the Input (pin 1), so the
duration of the first pulse may be any portion of the programmed duty cycle.
Pin 3
Oscillator
PWM frequency is adjustable. A resistor to ground sets the current IREF and the internal PWM oscillator frequency. A range of 500Hz
Frequency Adjust to 100kHz can be achieved with practical resistor values. Although oscillator frequency operation below 500Hz is possible, resistors
higher than 10M will be required. The pin then becomes a very high impedance node and is, therefore, sensitive to noise pickup
and PCB leakage currents.
Pin 4
Pin 5
GND
This pin must be connected to system ground for the DRV103 to function. It carries the 0.4mA quiescent current plus the full load
current when the power DMOS transistor is switched on.
OUT
The output is the drain of a power DMOS transistor with its source connected to ground. Its low on-resistance (0.5Ω typ) assures
low power dissipation in the DRV103. Gate drive to the power device is controlled to provide a slew-rate limited rise and fall time.
This reduces radiated RFI/EMI noise. A flyback diode is needed with inductive loads to conduct the load current during the off
cycle. The external diode should be selected for low forward voltage and low storage time. The internal clamp diode (an ESD
protection diode) provides some degree of back-EMF protection but it should not be used as a flyback diode.
Pin 6
Pin 7
+VS
This is the power supply pin. Operating range is +8V to +32V. +VS must be ≥ the supply voltage to the load.
Status OK Flag
Normally HIGH (active LOW), a Flag LOW signals either an over-temperature or over-current fault. The over-current flag (Status
OK) is LOW only when the output is ON (constant DC output or the “ON” portion of PWM mode). A thermal fault (thermal shutdown)
occurs when the die surface reaches approximately 160°C and latches until the die cools to 140°C. This output requires a pull-
up resistor and it can typically sink 2mA, sufficient to drive a low-current LED. Sink current is internally limited at 10mA typical.
Pin 8
Input
The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above the
typical switching threshold, 1.7V. Below this level, the output is disabled. Input current is typically 10nA when driven HIGH and 10nA
with the input LOW. The input should not be directly connected to the power supply (VS) or damage will occur.
LOGIC BLOCK DIAGRAM
Status OK
Flag
+VS
Flyback
Diode
Load
DRV103
ESD
Thermal Shutdown
Over Current
DMOS
OUT
GND
1.3V VREF
Oscillator
DMOS
PWM
Input
On
Off
Delay
2.75 • IREF
IREF
Delay
Adj
Osc Freq
Adj
Duty Cycle
Adj
RFREQ
RPWM
CD
DRV103
4
SBVS029A
TYPICAL CHARACTERISTICS
At TC = +25°C and VS = +24V, unless otherwise noted.
VOUT & IOUT WAVEFORMS
SOLENOID LOAD
VOUT & IOUT WAVEFORMS
RESISTIVE LOAD
PWM Mode
PWM Mode
+VS
+VS
Off
Off
On
Delay
Delay
0
0
+VS
RL
On
+VS
3
2
1
0
3
2
1
0
RL
IAVG
IAVG
0
0
Pull-In
On
0
50
100
0
50
100
140
140
Time (ms)
Time (ms)
QUIESCENT CURRENT
vs JUNCTION TEMPERATURE
CURRENT LIMIT SHUTDOWN WAVEFORMS
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
FPWM = 25kHz
DC = 50%
Delay = 150µs
On
5
Reset Period = 1/FPWM
VIN
Off
OK
Off
40V (Absolute Maximum)
0
OK
OK
OK
Status
OK
Flag
24
OK
0
32V
IO = 0A
Reset Period
24
VOUT
8V to 24V
0
IO = 3.5A
0
50
100
–60
–10
40
90
Temperature (°C)
Time (µs)
CURRENT LIMIT
vs JUNCTION TEMPERATURE
DELAY vs JUNCTION TEMPERATURE
150
145
140
135
130
125
120
115
110
105
100
3.8
3.7
3.6
3.5
3.4
3.3
CD = 0.1µF
+VS = 8V
+VS = 24V
+VS = 30V
+VS = 40V (Absolute Maximum)
–60
–10
40
90
–60
–10
40
90
140
Temperature (°C)
Temperature (°C)
DRV103
SBVS029A
5
TYPICAL CHARACTERISTICS (Cont.)
At TC = +25°C and VS = +24V, unless otherwise noted.
OSCILLATOR FREQUENCY
vs JUNCTION TEMPERATURE
MINIMUM DELAY vs JUNCTION TEMPERATURE
50
25.5
25.3
25.1
24.9
24.7
CD = 0pF
40
30
20
10
0
–60
–10
40
90
140
–60
–10
40
90
140
Temperature (°C)
Temperature (°C)
DUTY CYCLE vs JUNCTION TEMPERATURE
V
SAT vs JUNCTION TEMPERATURE
IO = 3A
50.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
50.6
50.4
50.2
50.0
49.8
49.6
49.4
49.2
RPWM = 137kΩ
IO = 1.5A
IO = 0.5A
IO = 0.1A
–60
–10
40
90
140
–60
–10
40
Temperature (°C)
90
140
Temperature (°C)
VFREQ vs JUNCTION TEMPERATURE
INPUT CURRENT vs INPUT VOLTAGE
1.287
1.286
1.285
1.284
1.283
1.282
1.281
1.280
1.279
1.278
1.277
1.276
300
250
200
150
100
50
0
–50
–60
–10
40
90
140
4
4.5
5
5.5
6
Temperature (°C)
Input Voltage (V)
DRV103
6
SBVS029A
set a longer delay time. A resistor, analog voltage, or a
voltage from a D/A converter can be used to control the duty
cycle of the PWM output. The D/A converter must be able
to sink a current 2.75 • IREF (IREF = 1.3V/RFREQ).
BASIC OPERATION
The DRV103 is a low-side, DMOS power switch employing
a Pulse-Width Modulated (PWM) output for driving electro-
mechanical and thermal devices. Its design is optimized for
two types of applications: a two-state driver (open/close) for
loads such as solenoids and actuators; and a linear driver for
valves, positioners, heaters, and lamps. Its low 0.5Ω “ON”
resistance, small size, adjustable delay to PWM mode, and
adjustable duty cycle make it suitable for a wide range of
applications.
Figure 2 illustrates a typical timing diagram with the Delay
Adjust pin connected to a 3.9nF capacitor, the duty cycle set
to 75%, and oscillator frequency set to 1kHz. See the “Delay
Adjust” and “Duty Cycle Adjust” text for equations and
further explanation. Ground (pin 4) must be connected to
system ground for the DRV103 to function. This serves as
the load current path to ground, as well as the DRV103
signal ground. The load (relay, solenoid, valve, etc.) should
be connected between the supply (pin 5) and output (pin 6).
For an inductive load, an external “flyback” diode is re-
quired, as shown in Figure 1. The diode serves to maintain
continuous current flow in the inductive load during OFF
periods of PWM operation. For remotely located loads, the
external diode is ideally located next to the DRV103. The
internal ESD clamp diode between the output and supply is
not intended to be used as a “flyback diode.” The Status OK
Flag (pin 7) provides fault status for over-current and
thermal shutdown conditions. This pin is active LOW with
output voltage of typically +0.3V during a fault condition.
Figure 1 shows the basic circuit connections to operate the
DRV103. A 1µF (22µF when driving high current loads) or
larger tantalum bypass capacitor is recommended on the
power-supply pin.
Input (pin 8) is level-triggered and compatible with standard
TTL levels. An input voltage between +2.2V and +5.5V
turns the device’s output ON, while a voltage of 0V to
+1.2V shuts the DRV103’s output OFF. Input bias current is
typically 1pA. Delay Adjust (pin 2) and Duty Cycle Adjust
(pin 1) allow external adjustment of the PWM output signal.
The Delay Adjust pin can be left floating for minimum delay
to PWM mode (typically 18µs) or a capacitor can be used to
+VS
RLED
+8V to +32V
2mA
LED
OK = LED “on”
3A
Flyback
Diode(1)
1µF
+
Relay
7
6
Status
OK
+VS
5
OUT
8
DRV103
TTL IN
NOTE: (1) Motorola MSRS1100T3 (1A, 100V)
Motorola MBRS360T3 (3A, 60V)
or
Delay
Adj
Osc Freq
Adj
Duty Cycle
Adj
GND
4
Microsemi SK34MS (3A, 40V)
2
3
1
RFREQ
RPWM
CD
FIGURE 1. DRV103 Basic Circuit Connections.
ON
TTL HIGH
Input (V)
OFF
OFF
1
TTL LOW
Period =
= TON + TOFF
FREQ
+VS
VO (V)
0
Delay Time
+VS/RL
TOFF
TON
IO (A)
0
Duty Cycle =
TON
TON + TOFF
0
1
2
3
4
Time (ms)
5
6
7
8
9
FIGURE 2. Typical DRV103 Timing Diagram, with CD = 3.9nF, OscFreq = 1kHz, and 75% Duty Cycle.
DRV103
SBVS029A
7
The internal Delay Adjust circuitry is composed of a 3µA
current source and a 2.6V comparator, as shown in Figure 3.
Thus, when the pin voltage is less than 2.6V, the output
device is 100% ON (DC output mode).
APPLICATIONS INFORMATION
POWER SUPPLY
The DRV103 operates from a single +8V to +32V supply
with excellent performance. Most behavior remains un-
changed throughout the full operating voltage range. Param-
eters that vary significantly with operating voltage are shown
in the Typical Performance Curves. The DRV103 supply
voltage should be ≥ the supply voltage on the load.
OSCILLATOR FREQUENCY ADJUST
The DRV103 PWM output frequency can be easily pro-
grammed over a wide range by connecting a resistor (RFREQ
)
between the Osc Freq Adj pin (pin 3) and ground. A range of
500Hz to 100kHz can be achieved with practical resistor
values, as shown in Table II. Refer to “PWM Frequency vs
RFREQ” typical performance curve shown in Figure 4 for
additional information. Although oscillator frequency opera-
tion below 500Hz is possible, resistors higher than 10M will
be required. The pin becomes a very high impedance node and
is, therefore, sensitive to noise pickup and PCB leakage
currents if very high resistor values are used. Refer to Figure
3 for a simplified circuit of the frequency adjust input.
ADJUSTABLE DELAY TIME (INITIAL 100% DUTY CYCLE)
A unique feature of the DRV103 is its ability to provide an
initial constant DC output (100% duty cycle) and then
switch to PWM mode output to save power. This function is
particularly useful when driving solenoids that have a much
higher pull-in current requirement than continuous hold
requirement.
The duration of this constant DC output (before PWM
output begins) can be externally controlled by a capacitor
connected from Delay Adjust (pin 2) to ground according to
the following equation:
OSCILLATOR FREQUENCY
(Hz)
RFREQ (nearest 1% values)
(Ω)
100k
50k
25k
10k
5k
47.5k
100k
205k
523k
1.07M
11.3M
Delay Time ≈ CD • 106
(time in seconds, CD in Farads • 1.1)
500
Leaving the Delay Adjust pin open results in a constant
output time of approximately 18µs. The duration of this
initial output can be reduced to less than 1µs by connecting
the pin to 5V. Table I provides examples of delay times
(constant output before PWM mode) achieved with selected
capacitor values.
TABLE II. Oscillator Frequency Resistance.
PWM FREQUENCY vs RFREQ
1000M
100M
10M
1M
INITIAL CONSTANT
OUTPUT DURATION
CD
1µs
18µs
110µs
1.1ms
11ms
110ms
1.1s
Pin 2 Tied to +5V
Pin 2 Open
100pF
100k
10k
1nF
10nF
100nF
1µF
1k
10
100
1k
10k
100k
1M
Frequency (Hz)
11s
10µF
FIGURE 4. Using a Resistor to Program Oscillator Frequency.
TABLE I. Delay Adjust Times.
R
FREQ (kΩ) = 6808417/F(1.0288)
+VS
3µA
CD
Reset
+2.6V
Input
VREF
VFREQ
IREF
+1.3V
RFREQ
FIGURE 3. Simplified Delay Adjust and Frequency Adjust Inputs.
8
DRV103
SBVS029A
A 100pF capacitor in parallel with RPWM is recommended
when switching a high load current to maintain a clean
output switching waveform, as shown in Figure 6.
The DRV103’s adjustable PWM output frequency allows it
to be optimized for driving virtually any type of load.
ADJUSTABLE DUTY CYCLE (PWM Mode)
The DRV103’s externally adjustable duty cycle provides an
accurate means of controlling power delivered to a load.
Duty cycle can be set over a range of at least 10% to 90%
with an external resistor, analog voltage, or the voltage
output of a D/A converter. A low duty cycle results in
reduced power dissipation in the load. This keeps the DRV103
and the load cooler, resulting in increased reliability for both
devices.
RPWM
only on
Pin 1
With
100pF in
Parallel with
RPWM
Resistor Controlled Duty Cycle
Duty cycle is easily programmed by connecting a resistor
(RPWM) between the Duty Cycle Adjust pin (pin 1) and
ground. High resistor values correspond to high duty cycles.
Table III provides resistor values for typical duty cycles.
Resistor values for additional duty cycles can be obtained
from Figure 5. For reference purposes, the equation for
calculating RPWM is included in Figure 5.
Time (10µs)
FIGURE 6. Output Waveform at High Load Current.
Voltage Controlled Duty Cycle
Duty cycle can also be programmed by an analog voltage,
V
PWM. With VPWM ≈ 3.56V, duty cycle is about 90%.
DUTY CYCLE
(%)
RPWM (Nearest 1% Values)
25kHz
Decreasing this voltage results in decreased duty cycles.
Table IV provides VPWM values for typical duty cycles. The
“Duty Cycle vs Voltage” typical performance curve for
additional duty cycles is shown in Figure 7.
5kHz
100kHz
5
374k
402k
475k
549k
619k
681k
750k
825k
887k
953k
1M
75k
80.6k
95.3k
110k
124k
137k
150k
165k
182k
196k
200k
16.9k
19.1k
22.6k
26.1k
29.4k
33.2k
37.4k
40.2k
44.2k
47.5k
49.9k
10
20
30
40
50
60
70
80
90
95
DUTY CYCLE AND DUTY CYCLE ERROR
vs VOLTAGE
100
90
80
70
60
50
40
30
20
10
0
2
1.5
1
TABLE III. Duty Cycle Adjust Resistance.
0.5
0
DUTY CYCLE vs RPWM
1M
–0.5
–1
–1.5
–2
5kHz
1
2
3
4
25kHz
100k
VPWM (V)
FIGURE 7. Using a Voltage to Program Duty Cycle.
At VS = 24V and F = 25kHz: VPWM = 1.25 +
0.026 • %DC.
100kHz
10k
DUTY CYLE
(%)
VPWM
(V)
0
20
40
60
80
100
Duty Cycle (%)
5
1.344
1.518
1.763
2.283
2.788
3.311
3.561
3.705
10
20
40
60
80
90
95
FIGURE 5. Using a Resistor to Program Duty Cycle.
At 25kHz: RPWM (kΩ) = 67.46 + 1.41 • %DC.
TABLE IV. Duty Cycle Adjust Voltage.
DRV103
SBVS029A
9
The Duty Cycle Adjust pin is internally driven by an
oscillator frequency dependent current source and connects
to the input of a comparator as shown in Figure 8. The
DRV103’s PWM adjustment is inherently monotonic. That
is, a decreased voltage (or resistor value) always produces
an increased duty cycle.
+5V
5kΩ
Pull-Up
TTL or HCT
OK
7
Thermal Shutdown
Over Current
5
OUT
3.9V
PWM
OSC
4
1.3V
DRV103
+VS
2.75 • IREF
FIGURE 9. Non-Latching Fault Monitoring Circuit.
+5V
RPWM
74XX76A
VS
Q
20kΩ
OK
OK
J
Q
FIGURE 8. Simplified Duty Cycle Adjust Input.
OK Reset
CLR
CLK
K
(1)
GND
STATUS FLAG
The OK Flag (pin 7) provides a fault indication for over-
current and thermal shutdown conditions. During a fault
condition, the Status OK Flag output is driven LOW (pin
voltage typically drops to 0.3V). A pull-up resistor, as
shown in Figure 9, is required to interface with standard
logic. Figure 9 also gives an example of a non-latching fault
monitoring circuit, while Figure 10 provides a latching
version. The OK Flag pin can sink up to 10mA, sufficient
to drive external logic circuitry, a reed relay, or an LED, as
shown in Figure 11, to indicate when a fault has occurred.
In addition, the OK Flag pin can be used to turn off other
DRV103s in a system for chain fault protection.
7
OK
Thermal Shutdown
Over Current
5
4
OUT
PWM
DRV103
NOTE: (1) Small capacitor (10pF) may be required in noisy environments.
FIGURE 10. Latching Fault Monitoring Circuit.
Over Current Fault
An over-current fault occurs when the PWM peak output
current is greater than approximately 3.75A. The OK flag is
not latched. Since current during PWM mode is switched on
and off, the OK flag output will be modulated with PWM
timing (see OK flag waveforms in the Typical Performance
Curves).
+5V
5kΩ
(LED)
HLMP-Q156
OK
7
Avoid adding capacitance to pin 6 (Out) as it may cause
momentary current limiting.
Over-Temperature Fault
Thermal Shutdown
Over Current
5
4
OUT
A thermal fault occurs when the die reaches approximately
160°C, producing a similar effect as pulling the input low.
Internal shutdown circuitry disables the output. The OK
Flag is latched in the LOW state (fault condition) until the
die has cooled to approximately 140°C.
PWM
DRV103
FIGURE 11. LED to Indicate Fault Condition.
DRV103
10
SBVS029A
PACKAGE MOUNTING
THERMAL RESISTANCE vs
CIRCUIT BOARD COPPER AREA
Figure 12 provides recommended PCB layouts for both the
SO-8 (U) and the PowerPAD™ SO-8 (H) packages. Al-
though the metal pad of the PowerPAD™ SO-8 (H) package
is electrically connected to ground (pin 4), no current should
flow in this pad. Do NOT use the exposed metal pad as a
power ground connection or erratic operation will result. For
lowest overall thermal resistance, it is best to solder the
PowerPAD™ directly to a circuit board, as illustrated in
Figure 13. Increasing the “heat sink” copper area improves
heat dissipation. Figure 14 shows typical junction-to-ambi-
ent thermal resistance as a function of the PC board copper
area.
80
70
60
50
40
30
DRV103 (H)
Power PAD
Surface-Mount Package
1oz. copper
0
1
2
3
4
5
Copper Area (inches2)
150 (ref)
FIGURE 14. Heat Sink Thermal Resistance vs Circuit Board
Copper Area.
POWER DISSIPATION
DRV103 power dissipation depends on power supply, signal,
and load conditions. Power dissipation (PD) is equal to the
product of output current times the voltage across the conduct-
ing DMOS transistor times the duty cycle. Using the lowest
possible duty cycle necessary to assure the required hold force
can minimize power dissipation in both the load and in the
DRV103. For low current, the output DMOS transistor on-
resistance is 0.5Ω, increasing to 0.6Ω at high output current.
95 x 95
DRV103(H)
Package
C - C
215 (ref)
153
158
273
277
At very high oscillator frequencies, the energy in the DRV103’s
linear rise and fall times can become significant and cause an
increase in PD.
Application Bulletin SBFA002 at www.ti.com, explains how to
calculate or measure power dissipation with unusual signals
and loads.
60 (ref)
THERMAL PROTECTION
50 nom
18
22
Power dissipated in the DRV103 will cause its internal junction
temperature to rise. The DRV103 has an on-chip thermal
shutdown circuitry that protects the IC from damage. The
thermal protection circuitry disables the output when the junc-
tion temperature reaches approximately +160°C, allowing the
device to cool. When the junction temperature cools to approxi-
mately +140°C, the output circuitry is again enabled. Depend-
ing on load and signal conditions, the thermal protection circuit
may cycle on and off. This limits the dissipation of the driver
but may have an undesirable effect on the load.
FIGURE 12. Recommended PCB Layout.
DRV103 Die
Pad-to-Board
Solder
Signal Trace
Any tendency to activate the thermal protection circuit indi-
cates excessive power dissipation or an inadequate heat sink.
For reliable operation, junction temperature should be limited
to +125°C, maximum. To estimate the margin of safety in a
complete design (including heat sink), increase the ambient
temperature until the thermal protection is triggered. Use
worst-case load and signal conditions. For good reliability,
thermal protection should trigger more than 40°C above the
maximum expected ambient condition of your application.
This produces a junction temperature of 125°C at the maxi-
mum expected ambient condition.
Copper Pad
Copper Traces
Thermal Vias
FIGURE 13. PowerPAD Heat Transfer.
DRV103
SBVS029A
11
The internal protection circuitry of the DRV103 was designed
to protect against overload conditions. It was not intended to
replace proper heat sinking. Continuously running the
DRV103 into thermal shutdown will degrade reliability.
To maintain junction temperature below 125°C, the heat
sink selected must have a θHA less than 26.3°C/W. In other
words, the heat sink temperature rise above ambient must be
less than 52.6°C (26.3°C/W • 2W).
Another variable to consider is natural convection versus
forced convection air flow. Forced-air cooling by a small fan
can lower θCA (θCH + θHA) dramatically.
HEAT SINKING
Most applications will not require a heat sink to assure that
the maximum operating junction temperature (125°C) is not
exceeded. However, junction temperature should be kept as
low as possible for increased reliability. Junction tempera-
ture can be determined according to the equation:
As mentioned earlier, once a heat sink has been selected, the
complete design should be tested under worst-case load and
signal conditions to ensure proper thermal protection.
TJ = TA + PDθJA
(1)
(2)
RFI/EMI
Any switching system can generate noise and interference
by radiation or conduction. The DRV103 is designed with
controlled slew rate current switching to reduce these ef-
fects. By slowing the rise and fall times of the output to
0.3µs, much lower switching noise is generated.
where, θJA = θJC + θCH + θHA
TJ = Junction Temperature (°C)
TA = Ambient Temperature (°C)
PD = Power Dissipated (W)
θJC = Junction-to-Case Thermal Resistance (°C/W)
θCH = Case-to-Heat Sink Thermal Resistance (°C/W)
Radiation from the DRV103-to-load wiring (the “antenna”
effect) can be minimized by using “twisted pair” cable or by
shielding. Good PCB ground planes are recommended for
low noise and good heat dissipation. Refer to Bypassing
section for notes on placement of the flyback diode.
θHA
= Heat Sink-to-Ambient Thermal Resistance (°C/W)
θJA = Junction-to-Air Thermal Resistance (°C/W)
Using a heat sink significantly increases the maximum
allowable power dissipation at a given ambient temperature.
BYPASSING
The answer to the question of selecting a heat sink lies in
determining the power dissipated by the DRV103. For DC
output into a purely resistive load, power dissipation is simply
the load current times the voltage developed across the
conducting output transistor times the duty cycle. Other loads
are not as simple. For further insight on calculating power
dissipation, refer to Application Bulletin SBFA002 at
www.ti.com. Once power dissipation for an application is
known, the proper heat sink can be selected.
A 1µF tantalum bypass capacitor is adequate for uniform
duty cycle control when switching loads of less than 0.5
amps. Larger bypass capacitors are required when switching
high current loads. A 22µF tantalum capacitor is recom-
mended for heavy-duty (3A) applications. It may also be
desirable to run the DRV103 and the load on separate power
supplies at high load currents. Near the absolute maximum
supply voltage of 40V, bypassing is especially critical. In the
event of a current overload, the DRV103 current limit
responds in microseconds, dropping the load current to zero.
With inadequate bypass, energy stored in the supply line
inductance can lift the supply sufficiently to exceed voltage
breakdown with catastrophic results.
Heat Sink Selection Example
A PowerPAD™ SO-8 (H) package is dissipating 2W. The
maximum expected ambient temperature is 35°C. Find the
proper heat sink to keep the junction temperature below
125°C.
Place the flyback diode at the DRV103 end when driving
long (inductive) cables to a remotely located load. This
minimizes RFI/EMI and helps protect the output DMOS
transistor from breakdown caused by dI/dt transients. Fast
rectifier diodes such as epitaxial silicon or Schottky types
are recommended as flyback diodes.
Combining Equations 1 and 2 gives:
TJ = TA + PD(θJC + θCH + θHA
)
(3)
TJ, TA, and PD are given. θJC is provided in the specification
table, 16.7°C/W. θCH depends on heat sink size, area, and
material used. A semiconductor’s package type and mount-
ing can also affect θCH. A typical θCH for a soldered-in-place
PowerPAD™ SO-8 (H) package is 2°C/W. Now we can
solve for θHA
:
TJ – TA
PD
θ HA
=
– θ +θCH
(
JC
)
125°C – 35°C
θ HA
=
– 16.7°C / W + 2°C / W
( )
(4)
2W
θ
HA= 26.3°C / W
DRV103
12
SBVS029A
APPLICATIONS CIRCUITS
+12V
5.6kΩ
22µF
"Fault"
HLMP-0156
1MΩ
Microsemi
SK34MS
3A 40V Schottky
Relay
+
7
6
OK
+VS
DRV103
5
OUT
1.7V
8
Input
+
47µF
Tantalum
CT
316kΩ
CT (µF)
TON (s)
47
22
10
10
5
2
4
GND
Delay
Adj
Duty Cycle
Adj
Freq
Adj
4.7
2.2
1
0.5
2
1
3
137kΩ
205kΩ
0.22µF
FIGURE 15. Time Delay Relay Driver.
+28V
22µF
+
Relay
24kΩ
6
+VS
DRV103
5
OUT
8
Input
4
GND
Delay
Adj
Duty Cycle
Adj
Freq
Adj
3.9kΩ
2
1
3
137kΩ
205kΩ
0.1µF
Housing
FIGURE 16. Remotely Operated Solenoid Valve or Relay.
DRV103
SBVS029A
13
+12V
22µF
+
3kΩ
6
+VS
IRF4905
DRV103
5
OUT
8
TTLIN
High = Load ON
Low = Load OFF
Input
4
GND
Delay
Adj
Duty Cycle
Adj
Freq
Adj
(1)
12V
70A
LOAD
2
1
3
RPWM
10MΩ
CD
F ~ 500Hz
NOTE: (1) Flyback diode required for inductive loads: IXYS DSE160-06A.
FIGURE 17. High Power High Side Driver.
+8V to +32V
2mA
Microsemi
SK34MS
3A 40V
Linear
Valve
Schottky
22µF
+
Actuator
HLMP-Q156
“Fault”
7
6
Status
OK
+VS
5
4
OUT
GND
8
DRV103
TTL IN
High = ON
Low = OFF
Delay
Adj
Duty Cycle
Adj
Freq
Adj
NC
2
1
3
205kΩ
1.3V 5% Duty Cycle
3.7V 95% Duty Cycle
DATA
DAC
FIGURE 18. Linear Valve Driver.
DRV103
14
SBVS029A
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
DRV103H
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE SO PowerPAD
DDA
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DRV
103H
DRV103H/2K5
DRV103H/2K5G3
DRV103HG3
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
DDA
D
2500
2500
75
Green (RoHS
& no Sb/Br)
-40 to 85
DRV
103H
Green (RoHS
& no Sb/Br)
CU SN
-40 to 85
DRV
103H
Green (RoHS
& no Sb/Br)
CU SN
-40 to 85
DRV
103H
DRV103U
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
DRV
103U
DRV103U/2K5
DRV103U/2K5G4
DRV103UG4
D
2500
2500
75
Green (RoHS
& no Sb/Br)
DRV
103U
D
Green (RoHS
& no Sb/Br)
DRV
103U
D
Green (RoHS
& no Sb/Br)
DRV
103U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV103U/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DRV103U/2K5
D
8
2500
Pack Materials-Page 2
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