DF1750U [BB]
Dual Channel DIGITAL DECIMATION FILTER; 双通道数字抽取滤波器
| 型号： | DF1750U |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Dual Channel DIGITAL DECIMATION FILTER |
| 文件： | 总13页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DF1750
Dual Channel
DIGITAL DECIMATION FILTER
FEATURES
DESCRIPTION
● USER SELECTABLE FOR 1/4 OR 1/2
The DF1750 is a high performance 1/4 or 1/2 decimat-
ing digital filter that is designed for digital audio appli-
cations. This device decimates and filters 2x or 4x (2fs
or 4fs) oversampled data from the output of an ADC to
a data frequency of fs. The technique of oversampling
and decimating allows the input to an oversampling
ADC to be processed by a much lower order, linear
phase, analog low-pass filter. This simultaneously im-
provessystemperformancewhilereducingcircuitcom-
plexity and cost.
DECIMATING RATIOS
● USER SELECTABLE FOR 16- OR 18-BIT
INPUT DATA
● SERIAL DATA INPUT IS COMPATIBLE
WITH THE BURR-BROWN PCM1750 ADC
● FILTERS OUT-OF-BAND NOISE WITH
STOPBAND ATTENUATION > 95dB
● PASSBAND RIPPLE < 0.0005dB
● SINGLE +5V SUPPLY OPERATION WITH
LOW POWER DISSIPATION OF ONLY
250mW
The DF1750 provides output data word rates (fs) up to
50.5kHz and it is compatible with the Burr-Brown
PCM1750, dual 18-bit analog-to-digital converter.
SCSL1
IBCK
SCSL2
2DS
DINL
DINR
XTI
XTO
System Clock
Input Interface Circuit
FIR Filter Circuit
IMOD
CKEN
CKO
CC
BBC
IBO
Timing Control
TEST
OW20
FSEN
Output Interface Circuit
LRCK
WDCK
BCK
DOUT
MUTE
LRPOL OBPOL
International Airport Industrial Park
•
Mailing Address: PO Box 11400
Cable: BBRCORP
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
•
Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111
•
•
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
© 1990 Burr-Brown Corporation
PDS-1092
Printed in U.S.A. October, 1993
PIN CONFIGURATION
Top View
SOIC
Top View
DIP
VDD1
CKO
NC
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CKO
VDD1
CKEN
(NC)
SCSL1
SCSL2
TEST
2DS
CKEN
XTO
3
SCSL1
SCSL2
TEST
(NC)
3
XTO
4
XTI
4
5
XTI
MUTE
DOUT
BCK
5
6
MUTE
(NC)
IMOD
6
7
V
SS2
2DS
7
8
DINR
CC
VSS1
DOUT
BCK
IMOD
(NC)
8
9
WDCK
OBPOL
LRPOL
LRCK
FSEN
OW20
9
10
11
12
13
14
BBC
IBCK
IBO
(NC)
V
SS2
10
(NC)
DINR 11
(NC) 12
CC 13
VSS1
DINL
VDD2
WDCK
OBPOL
(NC)
BBC 14
(NC) 15
IBCK 16
IBO 17
DINL 18
VDD2 19
(NC) 20
LRPOL
LRCK
FSEN
(NC)
OW20
PIN DESCRIPTION
PIN NO.
PIN NO.
DIP SOIC
NAME
I/O*
DESCRIPTION
Clock output (the same as XTI
DIP SOIC
NAME
I/O*
DESCRIPTION
Output data bit select
1
1
CKO
o
15
21
OW20
ip
frequency), CKO = L when CKEN = H
(16bit: OW20 = H, 20 bit: OW20 = L)
–
2
2
3
(NC)
SCSL1
–
16
22
23
(NC)
FSEN
ip
XTI Frequency select
ip
I/O pin select
(FSEN = H: BCK, WDCK, LRCK pin=Input
(FSEN = L: BCK, WDCK, LRCK pin=Output)
fs clock
3
4
4
5
SCSL2
TEST
ip
ip
(Refer to XTI pin description)
Test, (Test = L; test mode)
17
18
24
25
LRCK
LRPOL
ip
ip
LRCK polarity select
(LRPOL = H: Lch/Rch=Low/High)
(LRPOL = L: Lch/Rch=High/Low)
–
5
6
7
(NC)
2DS
–
26
(NC)
ip
1/4 or 1/2 decimating select
2DS = H: 1/4 decimating,
ip
ip
2DS = L: 1/2 decimating
A/D converter interface mode select
19
20
21
–
–
22
23
27
28
29
30
31
32
33
OBPOL
WDCK
VSS1
(NC)
(NC)
ip
ip/o
–
BCK polarity select
2fs clock
GND 1
6
–
7
8
–
9
8
9
10
11
12
13
IMOD
(NC)
VSS2
DINR
(NC)
CC
–
ip
GND 2
Rch input data
BCK
DOUT
ip/o
o
Output data bit clock
Data output (Lch or Rch serial
data output).
o
o
A/D converter control signal
A/D converter control signal
10
–
14
15
BBC
(NC)
–
24
25
34
35
36
(NC)
MUTE
XTI
ip
i
Data output mute, (MUTE = L: DOUT = L)
Oscillator Input
(512fs: SCSL1 = H, SCSL2 = H)
(256fs: SCSL1 = H, SCSL2 = L)
(768fs: SCSL1 = L, SCSL2 = H)
(384fs: SCSL1 = L, SCSL2 = L)
Oscillator Output
11
16
IBCK
ip
Input data bit clock input
12
13
14
–
17
18
19
20
IBO
DINL
VDD2
(NC)
o
ip
–
Input data bit clock output
Lch input data
+5V
26
–
27
28
37
38
39
40
XTO
(NC)
CKEN
VDD1
o
ip
CKO output select, (CKEN = H, CKO = L)
+5V
–
*i = Input pin
ip = Input with pull-up resistor
o = Output pin
ip/o = Input with pull-up resistor when FSEN = H,
output with FSEN = L.
®
DF1750
2
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formancedegradationtocompletedevicefailure.Burr-Brown
Corporationrecommendsthatallintegratedcircuitsbehandled
and stored using appropriate ESD protection methods.
Supply Voltage (VDD) .......................................................... –0.3V to +7.0V
Input Voltage (VIN) ...................................................... –0.3V to VDD + 0.3V
Soldering Temperature .................................................................. +255°C
Soldering Time ...................................................................................... 10s
Storage Temperature ...................................................... –40°C to +125°C
PACKAGE INFORMATION
PACKAGE DRAWING
MODEL
PACKAGE
NUMBER(1)
DF1750P
DF1750U
28-Pin Plastic DIP
40-Pin Plastic SOIC
215
252
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
DC SPECIFICATIONS
ELECTRICAL
VDD = 4.5V to 5.5V, VSS = 0V, TA = –20°C to +80°C unless otherwise specified.
DF1750P/U
PARAMETER
PIN
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
INPUTS
Logic Family
Logic Voltages
CMOS
XTI
XTI
XTI
(1),(2)
VIL1
VIH1
VCLK
VIL2
VIH2
IIL1
IIH1
IIL2
ILH1
For Clock Input
For Clock Input
For AC Coupling
FSEN = H
FSEN = H
VIN = 0V
VIN = VDD
VIN = 0V, FSEN = H
VIN = VDD, FSEN = H
0.3VDD
0.5
V
V
VP-P
V
0.7VDD
1.8
(1),(2)
2.4
V
Logic Currents
XTI
XTI
(1),(2)
5
5
10
10
10
20
1.0
µA
µA
µA
µA
(1),(2)
Input Leakage Current
OUTPUTS
Logic Family
Logic Voltages
CMOS
+5
(2),(3)
(2),(3)
VOL
VOH
IOL = 1.6mA, FSEN = L
IOH = –0.4mA, FSEN = L
0.4
V
2.5
POWER SUPPLY REQUIREMENTS
Supply Voltage
Supply Current
V
DD1, V DD2
IDD
PD
V
mA
mW
VDD = 5V(4), FSEN = H
Nominal VDD
30
250
Power Dissipation
TEMPERATURE RANGE (AMBIENT, TA)
Specification
Operating
–20
–20
+80
+80
°C
°C
NOTES: (1) Refers to pins SCSL1, SCSL2, TEST, 2DS, IMOD, DINR, IBCK, DINL, OW20, MUTE, OBPOL, LRPOL, FSEN, CKEN. (2) Refers to pins BCK, WDCK,
LRCK. (3) Refers to pins CKO, CC, BBC, IBO, DOUT. (4) Test Condition; SCSL1 = H, SCSL2 = H, TEST = H, 2DS = H, IMOD = H, OW20 = H, MUTE = H,
OBPOL = H, LRPOL = H, FSEN = L, CKEN = L. TCY = 38ns (XTI Clock Period), CL= 0pF (Capacitive Load), DINL, DINR (Applicable Input Data).
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
DF1750
AC SPECIFICATIONS
ELECTRICAL
VDD = 4.5V to 5.5V, VSS = 0V, TA = –20°C to +80°C unless otherwise specified.
XTI Clock
CONDITION
SCSL1 SCSL2
SYS
DF1750P/U
TYP
PARAMETER
SYMBOL
FREQ
MIN
MAX
UNIT
Crystal
Oscillator
Frequency
FOSC
H
H
L
H
L
H
L
512fs(1)
256fs
768fs
384fs
8
4
12
6
26
13
26
20
MHz
MHz
MHz
MHz
VIH1
1/2VDD
VIL1
XTI
L
tCW
tCW
H
H
L
H
L
H
L
512fs
256fs
768fs
384fs
15
38
15
25
70
140
50
ns
ns
ns
ns
tCY
External Clock
Pulse Width
tCW
L
100
AC Coupling is required with an external clock.
H
H
L
H
L
H
L
512fs
256fs
768fs
384fs
38
77
38
50
125
250
84
ns
ns
ns
ns
External Clock
Pulse Period
tCY
L
167
NOTE: (1) fs = Sampling frequency.
ADC CONTROL SIGNAL TIMING (CC, BBC, AND IBO) WITH IMOD = H
DF1750P/U
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
2DS = H
CC Pulse Width (H)
S/H Acquisition Time
CC-BBC Time
BBC Pulse Period
BBC Pulse Width (H)
BBC Pulse Width (L)
BBC-IBO Time
IBO Pulse Period
IBO Pulse Width (H)
IBO Pulse Width (L)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
65
670
285
228
65
140
140
228
140
65
1/256fs
9/256fs
4/256fs
3/256fs
1/256fs
2/256fs
2/256fs
3/256fs
2/256fs
1/256fs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T1
1.5V
CC
T4
T2
T3
T5
T7
1.5V
1.5V
BBC
T6
T8
2DS = L
CC Pulse Width (H)
S/H Acquisition Time
CC-BBC Time
BBC Pulse Period
BBC Pulse Width (H)
BBC Pulse Width (L)
BBC-IBO Time
IBO Pulse Period
IBO Pulse Width (H)
IBO Pulse Width (L)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
130
1350
570
456
130
280
280
456
280
130
1/256fs
9/256fs
4/256fs
3/256fs
1/256fs
2/256fs
2/256fs
3/256fs
2/256fs
1/256fs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T9
IBO
T10
®
DF1750
4
SERIAL INPUT TIMING (IBCK, DINL, DINR) WITH IMOD=H
DF1750P/U
PARAMETER
2DS = H
SYMBOL
MIN
TYP
MAX
UNIT
IBCK Pulse Width
IBCK Pulse Period
Data Word Latch
Set-up Time
Data Word Latch
Hold Time
DINL, DINR
Set-up Time
DINL, DINR
Hold Time
tIBW
tIBY
tSL
50
1/256fs
ns
ns
ns
3/12.928MHz(1) 3/256fs
50
1.5V
1.5V
CC
tSL
tHL
tHL
tSD
tHD
50
25
25
ns
ns
ns
IBCK
tIBW
tIBW
tHD
tIBY
tSD
2DS = L
DINL
DINR
1.5V
IBCK Pulse Width
IBCK Pulse Period
Data Word Latch
Set-up Time
Data Word Latch
Hold Time
DINL, DINR
Set-up Time
DINL, DINR
tIBW
tIBY
tSL
50
1/128fs
ns
ns
ns
3/12.928MHz(1) 3/128fs
50
Normally, IBO output is connected to IBCK
(Refer to the applications diagram).
tHL
tSD
tHD
50
25
25
ns
ns
ns
Hold Time
NOTE: (1) 12.928MHz = 256 x 50.5kHz (max sampling frequency).
ADC CONTROL SIGNAL TIMING (CC, BBC, AND IBO) WITH IMOD = L
DF1750P/U
PARAMETER
2DS = H
SYMBOL
MIN
TYP
MAX
UNIT
tCCW
tCCW
CC Pulse Width (H)
BBC Pulse Width
BBC Pulse Period
IBO Pulse Width
IBO Pulse Period
CC-BBC Time
tCCW
tBBW
tBBY
tBOW
tBOY
tCCBB
tCCBO
tBBBO
1/8fs
1/128fs
1/64fs
1/128fs
1/64fs
0
ns
ns
ns
ns
ns
ns
ns
ns
130
130
CC
1.5V
tBBY
tCCBB
tBBW
tBBW
-5
130
130
20
CC-IBO Time
BBC-IBO Time
1/128fs
1/128fs
BBC
IBO
1.5V
1.5V
tBBBO
tBOY
2DS = L
tBOW
tCCBO
CC Pulse Width (H)
BBC Pulse Width
BBC Pulse Period
IBO Pulse Width
IBO Pulse Period
CC-BBC Time
tCCW
tBBW
tBBY
tBOW
tBOY
tCCBB
tCCBO
tBBBO
1/4fs
1/64fs
1/32fs
1/64fs
1/32fs
0
ns
ns
ns
ns
ns
ns
ns
ns
280
280
tBOW
–5
280
280
20
CC-IBO Time
BBC-IBOTime
1/64fs
1/64fs
®
5
DF1750
SERIAL INPUT TIMING (IBCK, DINL, DINR) WITH IMOD = L
DF1750P/U
PARAMETER
2DS = H
SYMBOL
MIN
TYP
MAX
UNIT
IBCK Pulse Width
IBCK Pulse Period
Data Word Latch
Set-up Time
Data Word Latch
Hold Time
DINL, DINR
Set-up Time
DINL, DINR
Hold Time
tIBW
tIBY
tSL
100
1/3.232MHz(1)
50
1/128fs
1/64fs
ns
ns
ns
1.5V
1.5V
CC
tHL
tSL
tHL
tSD
tHD
50
25
25
ns
ns
ns
IBCK
tIBW
tIBW
tIBY
tSD
tHD
2DS = L
DINL
DINR
1.5V
IBCK Pulse Width
IBCK Pulse Period
Data Word Latch
Set-up Time
tIBW
tIBY
tSL
100
1/3.232MHz(1)
50
1/64fs
1/32fs
ns
ns
ns
Normally, IBO output is connected to IBCK.
(Refer to the application diagram).
Data Word Latch
Hold Time
DINL, DINR
Set-up Time
DINL, DINR
tHL
tSD
tHD
50
25
25
ns
ns
ns
Hold Time
NOTE: (1) 3.232MHz = 64 x 50.5kHz (max sampling frequency).
SERIAL OUTPUT TIMING WITH FSEN = H
DF1750P/U
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
REMARKS
LRCK
1.5V
BCK Pulse Width
BCK Pulse Period
LRCK Pulse Width
LRCK Pulse Period
LRCK Set-up Time
LRCK Hold Time
Output Data
Hold Time
Output Data
Delay Time
tBCW
tBCY
tLCW
tLCY
tBL
100
1/128fs
ns
ns
µs
µs
ns
ns
ns
tBL
1/3.232MHz(1) 1/64fs
1/2fs
tLB
Duty = 50%
1/50.5kHz
1/fs
1.5V
1.5V
BCK
50
50
0
tBCW
tBCY
tLB
tH
tBCW
(OBPOL = H)
CL = 0pF
tH, tD
tD
100
ns
CL = 15pF
DOUT
NOTE: (1) 3.232MHz = 64 x 50.5kHz (max sampling frequency).
SERIAL OUTPUT TIMING WITH FSEN = L
DF1750P/U
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
1.5V
1.5V
BCK
tOBCW tOBCW
tOBCY
BCK Pulse Width
BCK Pulse Period
WDCK Pulse Width
WDCK Pulse Period
LRCK Pulse Width
LRCK Pulse Period
Output Data
tOBCW
tOBCY
tWDCW
tWDCY
tLRCW
tLRCY
tDHL
140
1/128fs
1/64fs
1/4fs
1/2fs
1/2fs
1/fs
ns
ns
µs
µs
µs
µs
ns
ns
(OBPOL
=H)
tDHL
tDLH
LRCK
WDCK
DOUT
–10
–10
30
30
Delay Time
tDLH
®
DF1750
6
THEORY
According to the Nyquist Theorem, digital audio recordings
sampled at a rate of 44.1kHz (CD) or 48kHz (DAT) should
accurately reproduce the full 20kHz audio bandwidth.
Unfortunately, if frequencies higher than1/2 the sample rate
are seen at the input of an analog-to-digital converter,
aliasing back into the baseband will occur. At these sample
frequencies, the way to assure that aliasing does not occur
is to use complicated high order filters at the input of the
ADC . These filters can be expensive and they can also have
undesirable phase characteristics. These problems can be
avoided by using an oversampling ADC (such as the
PCM1750) with a decimating filter, where a high order
filter can be replaced with a low order filter which has very
little phase distortion (Figure 1).
Signal
(a)
(b)
(c)
(d)
(e)
(f)
0
0
1.0
2.0
3.0
4.0 x fs
Band limited by the
analog filter.
1.0
1.0
1.0
1.0
1.0
2.0
2.0
2.0
3.0
3.0
3.0
3.0
3.0
4.0 x fs
Foldover
Noise
Signal
0
4.0 x fs
With the oversampling-decimating technique, the input
signal (Figure 2a) is band limited by a low order analog
low-pass filter as shown in Figure 2b. This signal is 4-times
oversampled, with its spectra and foldover noise shown in
Figure 2c. The DF1750 first rejects the high frequency
components of the 4fs ADC output (Figure 2d). A 1/2
decimating filter then processes this data into a 2fs data
stream. This output spectra is shown in Figure 2e. The high
frequency components of the 2fs data are then removed,
producing the output spectra shown in Figure 2f. A second
1/2 decimating filter processes the 2fs data to a final fs data
stream and the original signal is restored without distortion
(Figure 2g). Note, when operating in the 1/2 decimating
mode the DF1750 processes data through the first LPF and
a single 1/2 decimating filter only.
Foldover
Noise
Signal
0
4.0 x fs
Foldover
Noise
Foldover
Noise
Signal
0
2.0
4.0 x fs
Foldover
Noise
Foldover
Noise
Signal
0
2.0
4.0 x fs
1
2
3
Analog
Filter
Sampling
A/D
(g) Signal
0
F/N
1.0
F/N
2.0
F/N
3.0
F/N
4.0 x fs
2nd 1/2
Deci-
mating
1st 1/2
Deci-
mating
4
5
6
7
2nd
LPF
1st
LPF
FIGURE 2. The Associated Spectra of the Oversampling-
Decimating Technique.
FIGURE 1. A Block Diagram of an Oversampling ADC
Followed by Digital Decimation.
®
7
DF1750
THEORETICAL FILTER
CHARACTERISTICS
1/4 DECIMATING, INPUT DATA FREQUENCY = 4fs
1/2 DECIMATING, INPUT DATA FREQUENCY = 2fs
PARAMETER
CHARACTERISTICS
PARAMETER
CHARACTERISTICS
Passband
Stopband
DC to 0.4583fs
0.5417fs and Above
Passband
Stopband
DC to 0.4583fs
0.5417fs and above
Passband Ripple
Stopband Attenuation
±0.0005 dB
Passband Ripple
Stopband Attenuation
Group Delay Time
±0.0002dB
95dB min, 0.5417fs to 1.4583fs
Constant, Linear Phase
95dB min, 0.5417fs to 1.4583fs
88dB min, 1.4583fs to 2.5417fs
95dB min, 2.5417fs to 3.4583fs
Constant, Linear Phase
Group Delay Time
0
20
0
20
40
40
60
60
80
80
100
100
0.5
1
1.5
2
(x fs)
0.5
1
2
3
4
(x fs)
DF1750 1/4 Decimating Filter Tranfer Characteristics.
DF1750 1/2 Decimating Filter Transfer Characteristics.
—0.001
—0.0005
0
—0.001
—0.0005
0
0.0005
0.001
0.0005
0.001
0.1
0.2
0.3
0.4 0.45
0.1
0.2
0.3
0.4 0.45
(x fs)
(x fs)
DF1750 1/4 Decimating Passband Frequency Response.
DF1750 1/2 Decimating Passband Frequency Response.
0
20
0
20
40
40
60
60
80
80
100
100
0.5
0.55
0.6
0.5
0.55
0.6
(x fs)
(x fs)
DF1750 1/4 Decimating Transitionband Frequency Response.
DF1750 1/2 Decimating Transitionband Frequency Response.
®
DF1750
8
FUNCTIONAL DESCRIPTION
1/4 AND 1/2 DECIMATING FUNCTIONS
1 WORD
1/4 or 1/2 decimating filtering converts 4fs or 2fs oversampled
data back to a sampling rate of fs data by a digital filtering
algorithm. 2DS is used to select 1/4 or 1/2 decimating.
IBCK
DINL
DINR
MSB
2
3
14(16)15(17) LSB
2DS = H; 1/4 decimating (0.5417fs ~ 3.4583fs)
2DS = L; 1/2 decimating (0.5417fs ~ 1.4583fs)
SIPO Loading Timing
Latch Timing
The filter arithmetic block consists of two 1/2 decimating
finite impulse response (FIR) filters as shown in Figure 3.
The numbers in the parenthesis in the DINL and DINR waveforms are
applicable to the 18-bit input mode.
1st FIR
1/2 Decimating
Filter
2nd FIR
1/2 Decimating
Filter
2fs
4fs
FIGURE 4. SIPO Input Data Loading Timing.
2fs
fs
INPUT
OUTPUT
(21 Taps)
(141 Taps)
2DS
(1) IMOD = H
FIGURE 3. Filter Arithmetic Structure
CC
SYSTEM CLOCK
DINL
DINR
L1
L2
L3
L4
The system clock frequency can be 256fs, 364fs, 512fs, or
768fs selectable with SCSL1 and SCSL2 as indicated in
Table I. An external clock (applied to Pin XTI) or crystal
oscillator (Pins XTI and XTO) can be employed. AC cou-
pling is required for an external clock.
R1
R2
R3
R4
L1
L2
L3
L4
LATCH (L) LOADING
LATCH (R) LOADING
R1
R4
R2
R3
The XTI input clock is available as an output at pin CKO,
when CKEN = L. CKO stays low when CKEN = H.
(2) IMOD = L
CC
SCSL1
SCSL2
H
L
H
L
H
L
DINL
L1
L2
L3
L4
XTI Clock
FXI
512fs
256fs
768fs
384fs
Frequency
R1
R2
R3
R4
DINR
Clock
Input
External Clock or
Crystal Oscillator
L1
L2
L3
L4
LATCH (L) LOADING
LATCH (R) LOADING
Internal System
Clock
R1
R2
R3
R4
FSYS
256fs
Frequency
TABLE I. System Clock and Internal Clock Frequency
Selection.
FIGURE 5. Input Data Latch/Loading Timing.
SERIAL DATA INPUT
The DF1750 is programmed for accepting the correct num-
ber of input data bits per word by the IMOD pin. A 16-bit
input word is selected with IMOD = L and an 18-bit input
word is selected with IMOD = H. Set IMOD = H for use
with the PCM1750. The serial input data format is two's
complement and MSB first. Both the left and right channel
data are loaded into the DF1750 simultaneously.
Each bit of the data is loaded to each channel’s SIPO (Serial/
parallel conversion register) by the rising edge of the Input
Bit Clock, IBCK (Figure 4). After the serial input data is
loaded, the data is latched into a parallel register by the
rising edge of CC for IMOD = H and the falling edge of CC
for IMOD = L (Figure 5).
®
9
DF1750
ADC CONTROL SIGNALS (CC, BBC, AND IBO) WITH IMOD = H
(1) 1/4 Decimating (2DS = H)
(1/4fs)
31
0
1
2
3
4
2
5
3
25
16
30 31
0
1
(128fs)
BBC
1
2
15
15
16
17
17
18
LSB
19
CC
(SOUTL) DINL
MSB
3
(SOUTL) DINR
IBO
(2) 1/2 Decimating (2DS = L)
(1/2fs)
31
0
1
2
3
4
2
5
3
25
30 31
0
1
(64fs)
BBC
1
2
15
15
16
17
17
18
LSB
19
CC
(SOUTL) DINL
3
16
MSB
(SOUTL) DINR
IBO
(SOUTL) (SOUTR) are outputs of the PCM1750.
FIGURE 6. ADC Control Signals With IMOD = H. (Applicable for use with the Burr-Brown PCM1750 ADC).
b. Sampling rate clock (LRCK)
ADC CONTROL SIGNALS
When FSEN = H, apply a 50% duty cycle sampling
frequency (fs) to pin LRCK.
(CC, BBC AND IBO) WITH IMOD = L
When FSEN = L, a fs clock generated from the system
clock is available at pin LRCK.
(1) 1/4 Decimating (2DS = H)
(1/4fs)
15
0
1
2
12
13
14
15
(64fs)
BBC
IBO
c. Word Clock (WDCK)
When FSEN = L, WDCK provides a 2fs clock that is
derived from the system clock.
CC
d. Output bit clock
DINL
DINR
MSB
2
3
14
15 LSB
When FSEN = H, apply a 64fs clock to pin BCK.
When FSEN = L, a 64fs clock generated from the system
clock is available at pin BCK.
(2) 1/2 Decimating (2DS = L)
(1/2fs)
15
0
1
2
12
13
14
15
e. LRCK polarity selection (LRPDL)
LRPOL = H; Lch/Rch = Low/High
LRPOL = L; Lch/Rch = High/Low
(Regardless of LRCK’s I/O mode).
(32fs)
BBC
IBO
CC
f. BCK polarity selection (OBPOL)
OBPOL = H; DOUT changes state at rising edge of
BCK.
DINL
DINR
MSB
2
3
14
15 LSB
FIGURE 7. ADC Control Signals with IMOD = L.
OBPOL = L; DOUT changes state at falling edge of
BCK.
(Regardless of BCK’s I/O mode).
OUTPUT INTERFACE
(BCK, WDCK, LRCK, OBPOL, LRPOL, FSEN)
The output of the DF1750 can be interfaced to many different
devices by programming the output interface pins. These pins
provide the following functions:
g. Timing relation between XTI and BCK, WDCK, LRCK
clocks.
When FSEN = H, clocks to BCK and LRCK must be
synchronized to XTI. However, there is no limit on their
phase differences (between XTI and BCK, LRCK clocks).
a. Output control clocks, BCK, WDCK, LRCK I/O
selection (FSEN).
FSEN = H; BCK WDCK, LRCK = Input
FSEN = L; BCK WDCK, LRCK = Output
®
DF1750
10
SERIAL DATA OUTPUT
LRCK
The number of bits per output data word is selected with the
OW20 pin. With OW20 = H a 16-bit output is selected and
with OW20 = L a 20-bit output is selected.
(LRPOL = H)
Lch WORD
MSB LSB
Rch WORD
MSB LSB
The serial output data format is two's complement and MSB
first. The left and right channel outputs are alternated, with
the left channel preceding the right channel. Each data word
is allocated in each pulse of LRCK and the LSB is located
at the end of the LRCK pulse as shown in Figure 8.
DOUT
FIGURE 8. Output Timing.
The output of the DF1750 can be muted by the use of the
MUTE pin. When MUTE = L, the output stays low (muted).
Under normal operation MUTE = H.
TIMING DIAGRAMS
INPUT
1/4 decimating
(2DS = H)
IMOD = H
1/2fs
1/4fs
1281
16
24
40
48
56
64
INTERNAL
CLOCK
8
32
(128fs)
CC
BBC
IBCK
DINL
DINR
INVALID
INVALID 1
2
3
4
5
6
7
8
9 10 1112 13 1415 1617 18
1 2 3 4 5 6 7 8 9 10 1112 13 1415 16 17 18
NOTE: Bit 1 is the most significant bit.
1/4 decimating
(2DS = H)
IMOD = L
1/2fs
1/4fs
CC
BBC (64fs)
IBCK (64fs)
DINL
DINR
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
NOTE: Bit 1 is the most significant bit.
®
11
DF1750
1/2 decimating
(2DS = L) IMOD = H
1/2fs
64
1
8
16
24
32
INTERNAL
CLOCK
(64fs)
CC
BBC
IBCK
DINL
DINR
INVALID
1
2
3
4
5
6
7
8
9
10
11
12 13 14
15 16
17 18
INVALID
NOTE: Bit 1 is the most significant bit.
1/2 decimating
(2DS = L)
IMOD = L
1/2fs
CC
BBC (32fs)
IBCK (32fs)
DINL
DINR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NOTE: Bit 1 is the most significant bit.
OUTPUT
LRCK
(LRPOL = H)
(LRPOL = L)
WDCK
BCK (64fs)
641
8
16
24
32
40
48
56
64
(OBPOL = H)
(OBPOL = L)
DOUT
LSB
16
MSB
1
Lch
LSB
16
MSB
1
Rch
LSB
16
(OW20 = H)
LSB
20
MSB
1
Lch
LSB
20
MSB
1
Rch
LSB
20
(OW20 = L)
APPLICATIONS
PCM1750 by the DF1750. The 4fs oversampled data of the
PCM1750 is filtered by the DF1750 to provide a data stream
of fs. A PCM1750/DF1750 evaluation board, DEM1133, is
available from Burr-Brown. This board incorporates the fea-
tures mentioned above as well as an AES/EBU interface, test
points for monitoring both the serial and parallel data outputs,
and a breadboard area for user experimentation.
A typical circuit configuration for digital audio recording is
shown in Figure 9. Each of the stereo input channels passes
through a six pole Generalized Immittance Converter (GIC)
low pass analog filter. This filter features extremely low
distortionandnegligiblephaseshift.Thebandlimitedsignals
are 4x oversampled by the dual-channel PCM1750 A/D
converter. Clock and convert signals are provided to the
®
DF1750
12
®
13
DF1750
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