DF1760U [TI]

Multi-Bit Enhanced Noise Shaping 20-Bit; 多位增强型噪声成形20位


型号：	DF1760U
厂家：	TEXAS INSTRUMENTS
描述：	Multi-Bit Enhanced Noise Shaping 20-Bit 多位增强型噪声成形20位 DSP外围设备微控制器和处理器外围集成电路光电二极管 LTE
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PCM1760P/U

DF1760P/U

Multi-Bit Enhanced Noise Shaping 20-Bit

ANALOG-TO-DIGITAL CONVERSION SYSTEM

FEATURES

DESCRIPTION

● DUAL 20-BIT MONOLITHIC MODULATOR

The PCM1760 and DF1760 combine for a low-cost,

high-performance dual 20-bit, 48kHz sampling ana-

log-to-digital conversion system which is specifically

designed for dynamic applications.

(PCM1760) AND MONOLITHIC

DECIMATING DIGITAL FILTER (DF1760)

● HIGH PERFORMANCE:

THD+N: –92dB typ, –90dB max

Dynamic Range: 108dB typ

The PCM1760/DF1760 pair form a 4-bit, 4th order,

64X oversampling analog-to-digital converter.

SNR: 108dB min, 110dB typ

Channel Separation: 98dB typ, 94dB min

The PCM1760 is a delta-sigma modulator that uses a

4-bit quantizer within the modulation loop to achieve

very high dynamic range.

● 64X OVERSAMPLING

● CO-PHASE CONVERSION

The DF1760 is a high-performance decimating digital

filter. The DF1760 accepts 4-bit 64fs data from the

PCM1760 and decimates to 20-bit 1fs data.

● RUNS ON 256fs OR 384fs SYSTEM

CLOCK

● VERSATILE INTERFACE CAPABILITY:

16-, 20-Bit Output

The FIR filter of the DF1760 has pass-band ripple of

less than ±0.001dB and greater than 100dB of the

reject band attenuation.

MSB First or LSB First Format

● OPTIONAL FUNCTIONS:

Offset Error Calibration

Overflow Detection

Power Down Mode (DF1760)

● RUNS ON ±5V SUPPLIES (PCM1760) AND

5V SUPPLY (DF1760)

● COMPACT 28-PIN PACKAGES:

28-Pin DIP and SOIC

PCM1760

DF1760

4 Stage, 4-Bit

Delta-Sigma

Modulator

64fs

4fs

Analog

Input (L)

1/16

Filter

FIR

Filter

Data

Timing

Control

and

Timing

Control

and

64fs

Interface

4 Stage, 4-Bit

Delta-Sigma

Modulator

System

Clock

256/384fs

256fs

Analog

Input (R)

International Airport Industrial Park

•

Mailing Address: PO Box 11400

Cable: BBRCORP

•

Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd.

•

Tucson, AZ 85706

Tel: (520) 746-1111 Twx: 910-952-1111

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1174C

Printed in U.S.A. July, 1994

SBAS025

SPECIFICATIONS

ELECTRICAL

At T_A= +25°C, ±V_CC, ±V_dd= +5V, +V_DD= +5V, f_S= 48kHz and ext. components = ±2% unless otherwise noted.

PCM1760/DF1760

PARAMETER

RESOLUTION

ANALOG INPUT

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

Input Range

R_IN1 = 2.2kΩ

±2.5

Vp-p

Input Impedance

_IN1 = 2.2kΩ

R_IN

Ω

SAMPLING FREQUENCY

Cover Range of fs

ACCURACY

Integrator Constants: Application⁽¹⁾

kHz

Gain Error

±0.5

±1.0

±0.5

±0.4

% FSR⁽²⁾

ppmfs/°C

Gain Mismatch

Bipolar Zero Error

Gain Drift

_IN= 0 at 20s After Power-On

0°C to +70°C

±100

±20

Bipolar Zero Drift

0°C to +70°C

DYNAMIC CHARACTERISTICS⁽⁴⁾

THD+N/(0dBFS)

P, U

P-L, U-L

f_IN= 1kHz

–92

–90

–76

–44

108

110

±0.1

–90

–88

–70

–42

THD+N/(–20dBFS) P, U

P-L, U-L

THD+N/(–60dBFS) P, U

P-L, U-L

P, U

_IN= 1kHz

Dynamic Range

SNR

_IN= 1kHz, V_IN= –60dBFS, A Filter

_IN= 0, A Filter

_IN= 20kHz

104

108

106

P-L, U-L

P, U

P-L, U-L

Frequency Response

Channel Separation

_IN= 1kHz, A Filter

DIGITAL FILTER

Over Sample Rate

Ripple in Band

Stopband Attenuation –1

Stopband Attenuation –2

0 - 0.04535fs

0.5465fs - 63.4535fs

0.5465fs - 3.4535fs

±0.0001

–94

–100

LOGIC INPUTS AND OUTPUTS

Logic Family Input

TTL Level Compatible CMOS

Frequency (System Clock 1)

Frequency (System Clock 2)

Duty Cycle (System Clock 1)

Duty Cycle (System Clock 2)

Data Clock Input

256fs

384fs

256fs

384fs

12.288

18.432

MHz

Logic Family Output

Data Clock Output

CMOS

Data Coding

Two's Complement

Data Bit Length

Data Format

Output Data Delay

Selectable

1.5

Bits

fs = 48kHz

POWER SUPPLY REQUIREMENTS

Supply Voltage

±V_CC

±V_dd

+V_DD

PCM1760

DF1760

±4.75

4.75

±5.0

5.0

±5.25

5.25

Supply Current

+I_CC

–I_CC

+I_dd

–I_DD

PCM1760

–30

–8

–45

–12

6.6

500

275

PCM1760

+I_DD–1

+I_DD–2

Power Consumption

DF1760, Normal Mode

DF1760, Power-Down Mode

PCM1760

DF1760, Normal Mode

DF1760, Power-Down Mode

370

200

TEMPERATURE RANGE

Operating

Storage

PCM1760/DF1760

–50

+25

+70

+125

°C

NOTES: (1) Integrator Constants are determined by the external components shown in the block diagram. (2) FSR means Full Scale Range, digital output code is from

90000H to 70000H, FSR = 5.0V. (3) Use 20-bit DAC, 20kHz LPF, 400Hz HPF, average response. (4) Average response using a 20-bit reconstruction DAC with 20kHz

low-pass filter and 400Hz high-pass filter.

PCM1760P/U DF1760P/U

ABSOLUTE MAXIMUM RATINGS—PCM1760

ABSOLUTE MAXIMUM RATINGS—DF1760

Supply Voltage .................................................................................... 7.0V

Voltage Mismatch ............................................................................... 0.1V

Digital Input ............................................................................... +V_DD+0.5V

Supply Voltage ..................................................................................... ±6V

Voltage Mismatch ............................................................................... 0.1V

Analog Input ........................................................................................ ±V_CC

Digital Input ............................................................................... +V_DD+0.3V

GND –0.3V

V_SS–0.5V

Input Current

±20mA

Power Dissipation/P ....................................................................... 460mW

Power Dissipation/U....................................................................... 440mW

Lead Temperature/P (soldering, 10s) .............................................. 260°C

Lead Temperature/U (soldering, 10s, reflow)................................... 235°C

Operating Temperature.......................................................... 0°C to +70°c

Storage Temperature ...................................................... –50°C to +125°C

Power Dissipation/P ....................................................................... 580mW

Power Dissipation/U....................................................................... 550mW

Lead Temperature/P (soldering, 10s) .............................................. 260°C

Lead Temperature/U (soldering, 10s) .............................................. 235°C

Operating Temperature......................................................... 0°C to +70°C

Storage Temperature ...................................................... –50°C to +125°C

ORDERING INFORMATION

PACKAGE INFORMATION

MODEL

PACKAGE

THD +N (fs)

SNR

PACKAGE DRAWING

PCM1760P

PCM1760U

PCM1760P-L

PCM1760U-L

DF1760P

PDIP

SOIC

PDIP

SOIC

PDIP

SOIC

–90dB

–88dB

108dB

106dB

MODEL

PACKAGE

NUMBER⁽¹⁾

PCM1760P

PCM1760U

PCM1760P-L

PCM1760U-L

28-Pin PDIP

28-Pin SOIC

28-Pin PDIP

28-Pin SOIC

800

804

800

804

DF1760U

DF1760P

DF1760U

28-Pin PDIP

28-Pin SOIC

801

805

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix D of Burr-Brown IC Data Book.

PIN ASSIGNMENTS PCM1760

PIN I/O⁽¹⁾

NAME

DESCRIPTION

Top View

SOIC/DIP

–

Out-2R

In-2R

Out-1R

In-1R

SERVO DC

+V_CC

AGND

–V_CC

BGDC

In-1L

Out-1L

In-2L

Out-2L

BPODC-L

L/RCK

Strobe

256fs

–V_DD

DGND

+V_DD

D₀

Right Channel Second Integrator Output

Right Channel Second Integrator Input

Right Channel First Integrator Output

Right Channel First Integrator Input

Servo Amp Decoupling Capacitor

+5V Analog Supply Voltage

Analog Common

–5V Analog Supply Voltage

Band Gap Reference Decoupling Capacitor

No Connection

Left Channel First Integrator Input

Left Channel First Integrator Output

Left Channel Second Integrator Input

Left Channel Second Integrator Output

No Connection

Left Channel Bipolar Offset Decoupling Capacitor

LR Clock Output (64fs)

Data Strobe Output (128fs)

256fs Clock Input

–5V Digital Supply Voltage

Digital Common

+5V Digital Supply Voltage

D₀Data Output (LSB)

28 NC

Out-2R

In-2R

27 BPODC-R

26 D₃

Out-1R

In-1R

25 D₂

24 D₁

SERVO DC

+V_CC

23 D₀

–

AGND

22 +V_DD

21 DGND

20 –V_DD

19 256fs

18 Strobe

17 L/RCK

16 BPODC-L

15 NC

PCM1760

–V_CC

BGDC

NC 10

In-1L 11

Out-1L 12

In-2L 13

D₁

D₂

D₃

D₁Data Output

D₂Data Output

D₃Data Output (MSB)

Right Channel Bipolar Offset Decoupling Capacitor

No Connection

BPODC-R

Out-2L 14

NOTE: (1) O = Output terminal; I = Input terminal.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PCM1760P/U DF1760P/U

PIN ASSIGNMENTS DF1760

PIN I/O⁽¹⁾

NAME

DESCRIPTION

Top View

SOIC/DIP

OVL

OVR

D₃

Left Channel Overflow Output (Active High)

Right Channel Overflow Output (Active High)

D3 Data Input (MSB)

28 V_SS2

OVL

OVR

D₃

–

D₂

D₁

D₀

TP1

V_SS1

V_DD1

D2 Data Input

D1 Data Input

D0 Data Input (LSB)

Test Pin (No Connection)

Common Channel 1

27 V_DD2

26 TP2

D₂

25 CLKSEL

24 S/M

+5V Channel 1

256fs Clock Output

256fs

Strobe

LRCK

CALD

CAL

SYSCLK

SCLK

L/R

SDATA

FSYNC

LRSC

/PD

Mode2

Mode1

S/M

D₁

Data Strobe Clock Input (128fs)

LR Clock Input

Calibration Function Enable (Active Low)

Calibration Output (High During Calibration)

System Clock Input (256fs or 384fs)

Data Clock

LR Channel Phase Clock

Serial Data Output (1fs)

Frame Clock (2fs)

Phase Control of LR Channel Phase Clock

Power Down Mode Enable Input (Active Low)

Output Format Selection Input 2

Output Format Selection Input 1

Slave/Master Mode Selection Input (High Makes

Slave Mode

System Clock Selection Input (High Makes 256fs)

Test Pin (No Connection)

+5V Channel 2

D₀

23 Mode 1

22 Mode 2

21 /PD

I↑

TP1

V_SS1

V_DD1

DF1760

I↑ /O

I↑

20 LRSC

19 FSYNC

18 SDATA

17 L/R

256fs 10

Strobe 11

LRCK 12

CALD 13

CAL 14

16 SCLK

15 SYSCLK

I↑

–

CLKSEL

TP2

V_DD2

–

V_SS2

Common Channel 2

NOTE: (1) O = Output terminal; I = Input terminal.

BLOCK DIAGRAM OF DF1760

D₃

D₂

D₁

1/16

Decimation

Filter

Input

LAT

Boost

Filter

D₀

Strobe

LRCK

CALD

CAL

V_SS1

V_DD1

Input

RAM

Calib-

ration

Output

Control

Multiplier

ALU

P/S

Coefficient

Overflow DET

Main

Timing

Control

Temporary

RAM

Test

256fs

SYSCLK

CLKSEL

/PD

V_SS2

V_DD2

TP1 OVL

TP2 OVR MODE 1 (16-, 20-Bit)

S/M

SDATA

MODE 2

LRSC

FSYNC

L/R

SCLK

PCM1760P/U DF1760P/U

BLOCK DIAGRAM OF PCM1760

C₁R

C₂R

C₃R

C₄R

R_T1R

R_T2R

R_Z1R

R_IN1R

R_IN2R

RCH, V_IN

In-1R

Out-1R

In-2R

Out-2R

BPODC-R

S/H_INR

RCH

S/H

SERVO

D₃

D₂

RCH

BPO

D₁

I_OUT

RCH

DAC

RCH

ADC

D₀

I_OUTR

+V_DD

+V_CC

AGND

–V_CC

+5V

DGND

Servo

Amp

Band Gap

Bias

–V_DD

–5V

256fs

I_OUTL

Sub

LCH

DAC

LCH

ADC

I_OUTL

Strobe

L/R CK

BGDC

LCH

BPO

LCH

S/H

S/H_INL

In-1L

Out-1L

In-2L Out-2L

BPODC-L

R_IN1L

R_IN2L

R_Z1L

LCH, V_IN

External Components Condition

_IN1R/L C₁, C₂R/L R_TIR/L

C₁L

C₂L

C₃L

C₄L

R_IN2R/L

2.2kΩ

C₃, C₄R/L R_T2 R/L

1800pF 560Ω

2200pF

470Ω

R_Z1 R/L

1.2kΩ

1.3kΩ

R_T1L

R_T2L

PCM1760P/U DF1760P/U

TYPICAL PERFORMANCE CURVES

OVERALL PASS-BAND

CHARACTERISTICS OF THE DF1760

1.0

OVERALL CHARACTERISTICS OF THE DF1760

0.5

–50

–0.5

–1.0

–100

–150

fs ÷ 4

fs ÷ 2

(fs)

TOTAL PASS-BAND FREQUENCY RESPONSE,

COMBINATION OF PCM1760 AND DF1760

PASS-BAND CHARACTERISTICS

OF THE FIR PORTION OF THE DF1760

0.3

0.2

0.1

0.0010

0.0005

–0.1

–0.0005

–0.0010

–0.2

–0.3

0.1

100

fs ÷ 4

fs ÷ 2

Frequency (kHz)

TYPICAL FFT ANALYSIS OF THE 1kHz fs INPUT SIGNAL

–20

–40

–60

–80

–100

–120

–140

–160

–180

–200

Frequency (kHz)

fs = 48.000000kHz

F_C1= 1.171876kHz

PCM1760P/U DF1760P/U

BASIC CONNECTION DIAGRAM OF PCM1760 AND DF1760

PCM1760P/U DF1760P/U

OFFSET CALIBRATION MODE

FUNCTIONS OF

THE DIGITAL FILTER

SYSTEM CLOCK

The offset error is calibrated by storing the digital data when

the input is zero in registers and subtracting it from the

future data with actual signal input.

The DF1760 can accept a system clock of either 256fs or

384fs. If a 384fs system clock is used, the DF1760 divides

by 2/3 to create the 256fs system clock required for the

PCM1760. The system clock is applied to pin 15 (SYSCLK

input). The actual clock selection is done by setting pin 25

(CLKSEL input) “high” for 256fs clock and “LOW” for

384fs clock.

CALD

CALIBRATION

Disable

Enable

To enable the calibration mode, set the CALD input (Pin 13)

“LOW”. The calibration mode is disabled by setting the

CALD input (Pin 13) “HIGH”. The calibration cycle is

initiated by setting the /PD input (Pin 21) “LOW” for more

than 2 system clock periods and then setting it “HIGH”.

During the calibration cycle, the CAL output (Pin 14)

becomes “HIGH”, all the serial data is forced to “LOW”,

and the L/R (Pin 17), SCLK (Pin 16) and FSYNC (Pin 19)

pins become input terminals after the completion of the

calibration cycle. The CAL output is “LOW”.

The detailed timing requirements for the system clock are

shown in Figure 3c.

CLKSEL

SYSCLK

256fs

384fs

MASTER/SLAVE MODE

The DF1760 can be used in both the master mode and slave

mode. In the master mode, the DF1760 outputs L/R (left/

right channel phase clock), SCLK (data clock) and FSYNC

(frame clock 2fs) signals. In the slave mode, the DF1760

accepts L/R, SCLK and FSYNC signals. The mode selection

is done by taking pin 24 (S/M INPUT) “HIGH” for slave

mode and “LOW” for master mode.

POWER DOWN MODE/RESET

The /PD input (Pin 21) has two functions. First, it should be

set at “HIGH” after application or restoration of power (V_SS

and/or V_DD) to accomplish the power-on/mode reset func-

tion. The detail timing requirements for this function are

shown in Figure 3f. Second, the DF1760 is placed in the

power down mode by setting the /PD input (Pin 21) “LOW”.

Set the /PD input (Pin 21) “HIGH” for normal operation

mode.

S/M

MODE

Slave

Master

/PD

OPERATION

OUTPUT DATA FORMAT

Normal

Power Down

The serial output data has four possible formats. The selec-

tion of the formats can be done by the Mode 1 and Mode 2

inputs.

The power dissipation of the DF1760 in the power down

mode is about 1/10 of the normal operation mode. During

the power down mode, the L/R, SCLK, and FSYNC pins

become input pins and all the serial data is forced “LOW”.

The 256fs output is enabled even in the power down mode.

MODE 1

MODE 2

FORMATS

MSB First, 16 Bits, Falling Edge

MSB First, 20 Bits, Falling Edge

MSB First, 20 Bits, Rising Edge

LSB First, 20 Bits, Falling Edge

The detailed timing of the power down mode operation and

the offset calibration is shown in Figure 3b.

LR CHANNEL PHASE CLOCK

The status of the LR channel phase clock can be set by the

LRSC input.

+Detect Level

LRSC

L/R CLOCK AND CHANNEL

H = LCH,

L = LCH,

L = RCH

H = RCH

–Detect Level

T_OR

T_OF

T_OR

T_OF

OVERFLOW DETECTION

OVL (OVR)

When a near-to-clipping input condition is detected, OVL

output (Pin 1), or OVR output (Pin 2), becomes “HIGH” for

a duration of 4096/fs (about 85ms) depending upon on the

channel detected.

DESCRIPTION

NAME

MIN

TYP MAX UNITS

Delay from Overflow Detection

to OVL (OVR) Output

T_OR

T_OF

–

The OVL and OVR output return to “LOW” after

4096/fs duration automatically.

OVL (OVR) Output Pulse Width

4096

1/fs

FIGURE 3a. DF1760 Overflow Detection.

PCM1760P/U DF1760P/U

T_SLKHT_SLKL

T_PDW

/PD

CAL

T_PCF

SCKL

T_PCR

T_DSS

T_DSV

T_PSF

T_CSV

SDATA

T_SLR

T_SDR

L/R

DESCRIPTION

NAME MIN

TYP

MAX UNITS

T_SF

Pulse Width of /PD Input

T_PDW

–

1/Fclk

FSYNC

Delay from /PD Input to

CAL Output

T_PCR

T_PCF

T_PSF

–

4096

–

1/Fclk

1/fs

DESCRIPTION

NAME MIN

TYP

MAX UNITS

Calibration Cycle Duration

SCLK Frequency

F_SLK

T_SLKL

T_SLKH

T_SLR

32fs

100

–70

48fs

64fs

–

Delay from /PD Input to S_DATA

1/Fclk

Low Duration of FSCLK

High Duration of FSCLK

Delay from SCLK to L/R Edge

–

Delay from Completion of

Calibration to SDATA Valid

T_CSV

–

1/fs

–

FIGURE 3b. DF1760 Power Down and Offset Calibration.

Delay from Falling Edge of

SCLK to SDATA Valid

T_CLKHT_CLKL

T_DSS

–

Delay from SCLK to FSYNC

Edge

2.0V

1.4V

0.8V

T_SF

–70

100

Delay from Rising Edge of

SCLK to SDATA Valid

T_DSV

–

T_LH

T_HL

Delay from SDATA Valid to

Rising Edge of SCLK

SYSTEM CLOCK: 256fs

DESCRIPTION

T_SDR

–

NAME MIN

TYP

–

MAX UNITS

FIGURE 3e. Timing of Slave Mode, DF1760.

Low Level Duration

High Level Duration

SYSTEM CLOCK: 384fs

DESCRIPTION

T_CLKL

T_CLKH

–

<LRSC = “H”

Power

NAME MIN

TYP

MAX UNITS

Low Level Duration

High Level Duration

Rise Time

T_CLKL

T_CLKH

T_LH

–

L/R

T_SP

Fall Time

T_HL

–

T_PDW

FIGURE3c. SystemClockTimingRequirementsofDF1760.

<LRSC = “L”

T_DSV

Power

SCLK

T_DSV

T_DSS

L/R

SDATA

L/R

T_SP

T_SLR

T_SDR

T_PDW

T_SF

FSYNC

APPLIES TO

MODE

DESCRIPTION

NAME

MIN

TYP

MAX UNITS⁽¹⁾

DESCRIPTION

NAME MIN

TYP

64fs

MAX UNITS

Power on to PD ↑

T_PDW

1/fs

Master/Slave

Slave

SCLK Frequency

F_SLK

–

PD ↑ to L/R ↑

(LRSC = “H”)

T_SP

–1

1/Fclk

SCLK Frequency Duty Cycle

FSYNC Frequency

–

F_SYNC

–

2fs

PD ↑ to L/R ↓

(LRSC = “L”)

Slave

FSYNC Frequency Duty Cycle

Delay from SCLK to L/R Edge

–

T_SLR

T_DSS

T_SF

–20

–

NOTE: (1) fs: sampling rate. Fclk: system clock frequency.

Delay from Falling Edge of

SCLK to SDATA Valid

FIGURE 3f. Power On and Mode Reset Timing.

–

Delay from SCLK to FSYNC

Edge

–20

100

Delay from Rising Edge of

SCLK to SDATA Valid

T_SDR

Delay from SDATA Valid to

Rising Edge of SCLK

T_DSV

–

FIGURE 3d. Output Timing of Master Mode, DF1760.

PCM1760P/U DF1760P/U

The DF1760 accepts the four-bit 64fs noise shaped data

stream from the PCM1760 and decimates to 1/16 with an

initial filter, and then decimates to 1fs 20-bit data using a 4x

oversampling filter.

THEORY OF OPERATION

MULTI-BIT ENHANCED NOISE SHAPING

A block diagram of a typical 1-bit delta-sigma modulator is

shown in Figure 4.

The PCM1760 and DF1760 combination achieves a dy-

namic range of 108dB and SNR of 110dB even with a

single-ended input.

In Figure 4, the quantizer consists of a single bit which has

two possible states, either “0” or “1”. The input signal is

sampled at a much higher sample rate than the nyquist

sampling frequency. The quantizer output data stream is

digitally filtered for higher resolution nyquist data. The

theoretical SNR is determined by the number of the order of

the integrator and the oversampling rate.

(2)

DF1760

Integrator

Quantizer

Input

Output

∫

(1)

z^–1

FIGURE 4. Single Stage 1-Bit Delta-Sigma.

(1)

Integrator

nBit

Input

Output

ADC

∫

PCM1760

nBit

DAC

(1)

FIGURE 5. Single Stage Multi-bit Delta-Sigma.

Digital

Common

Analog

Common

+5V

There is a practical limit to increasing the numbers of order

of the integrator due to an inherent oscillation in the modu-

lator. There is also a limit to increasing the sample rate due

to the increase in jitter sensitivity associated with high clock

frequencies.

+5V

GND

Power Supply

–5V

Power Supply

NOTE: (1) Tantalum 3.3µF. (2) Ceramic 0.1µF.

The PCM1760 utilizes a four-bit quantizer instead of the

conventional one-bit method. The quantizing noise of a four-

bit quantizer is 1/16 of the one-bit version. Using the four-

bit quantizer allows for a lesser order number of the integra-

tor and a lower oversampling rate to achieve similar perfor-

mance to that of a more complex one-bit system.

FIGURE 7. Recommended Power Supply Connection and

Decoupling.

LAYOUT PRECAUTIONS

Analog common and digital common of the PCM1760 are

not connected internally. These should be connected to-

gether with the common of the DF1760 as close to the unit

as possible, preferably to a large ground plane under the

PCM1760.

A block diagram of the PCM1760 modulator is shown in

Figure 6. The PCM1760 is a fourth-order integrator that

samples at 64x oversampling, and samples left and right

channel input signal simultaneously.

The use of a separate +5V supply is recommended for the

PCM1760 and DF1760, and to connect the common at one

point as described above. Low impedance analog and digital

commons returns are essential for better performance.

2nd Order

Integrator

2nd Order

Integrator

4Bits

ADC

Input

Output

∫∫

The power supplies should be bypassed with tantalum ca-

pacitors as close as possible to the units. See Figure 7 for

recommended common connections and power supplies

bypassing.

4Bits

DAC

FIGURE 6. Multi-bit Enhanced Noise Shaping.

PCM1760P/U DF1760P/U

OUTPUT TONE ELIMINATION

When the sampling frequency (fs) is between 40kHz and 50 kHz

and the L/R relative offset voltage (∆Vs) is less than or equal to

0.05% of full scale range, the PCM1760 may output a tone

similar to an idle tone. This tone is very low and its frequency

depends on the input L/R relative offset voltage, ∆Vs. This

tone never occurs when the sampling frequency (fs) is 32kHz.

R_IN1-L

2.2kΩ

V_IL= –20mV ±10%

PCM1760

To avoid this tone, the offset voltage should be summed

using an amplifier, buffer, active low pass filter, etc., to

cause the input L/R relative offset voltage (∆Vs) to be

greater than 0.05% of full scale range.

_IN1-R

2.2kΩ

V_IR= +10mV ±10%

It is recommended that:

(A) Sum offset at both L/R channels

Lch: V_IL= –20mV ±10%

Rch: V_IR= +10mV ±10%

(B) Sum offset at L channel

Lch: V_IL= –30mV ±10%

FIGURE 8. Application Example to Eliminate the Tone

(offset voltage implementation for both chan-

nels).

Rch: V_IR= ±1mV (by a precircuit)

When FSR = 5V (±2.5V).

Figure 8 shows an application circuit for summing the offset

at both L/R channels.

OFFSET ERROR CALIBRATION

The offset voltage of the PCM1760 and the input stage of

the system can be compensated by using the calibration

mode of the DF1760. Offset calibration is shown in Figure

10. An optional analog switch is driven by a CAL output of

the DF1760. The PD input of the DF1760 is used to initiate

the calibration cycle.

Alternately, Figure 9 shows an application circuit for use

when fs = 48kHz which changes the external integrator

circuit of the PCM1760.

MODULATOR COMPONENTS

AND SAMPLING FREQUENCY

The PCM1760/DF1760 are capable to 30kHz to 50kHz fs

sampling frequency by condition with external components

value which are shown in Basic Connection Diagram.

ANALOG INPUT AND DIGITAL OUTPUT

Ideal output digital code range for 20-bit resolution is from

8000H (–Full Scale) to 7FFFFH (+Full Scale).

The characteristics of the modulator’s integrator can be set

by external components. The values in the block diagram on

page five are recommended for optimized performance.

Low leakage, low voltage coefficient capacitors are recom-

mended for integration capacitors.

The DF1760, combined with 70000H (±FSR) of the

PCM1760, produces a digital output code range at ±FSR

input of 90000H (–FSR).

The relationship between analog input and digital output is

shown in Table I.

The tolerance of external components should be better than ±2%.

C₁

C₂

C₃

C₄

CZ₁

RT₁

RZ₁

RT₂

RZ₂

R_IN1

R_IN2

R_IN1= 2.2kΩ

RT₂= 2.2kΩ

C₁, C₂, C₃, C₄= 1200pF

RT₁= 470Ω

RZ₁= 470Ω

OP1

OP2

PCM1760

CZ₁= 220pF

R_IN2= 1.3kΩ

RZ₂= 910Ω

FIGURE 9. Application Example to Eliminate the Tone (alternative modulator's integrator circuit. Only for fs = 48kHz).

PCM1760P/U DF1760P/U

POWER-ON RESET AND MODE RESET

ANALOG INPUT

CONDITION

DIGITAL OUTPUT

The timing requirements for POWER-ON RESET and

MODE RESET are shown in Figure 3f. The DF1760 re-

quires POWER-ON RESET when power is applied or re-

stored. MODE RESET is required when any of the follow-

ing has been changed: system clock, master/slave mode,

output data format, L/R clock, calibration after POWER-ON

in slave mode.

+2.55V

+Max Input

Overflow

+FSR

72000H

70000H to 72000H⁽²⁾

70000H

+2.50V to +2.55V

+2.50V

BPZ (Ideal)

–FSR

00000H⁽¹⁾

–2.50V

90000H

82FFFH to 82000H⁽²⁾

–2.83V to –2.85V

–2.85V

Overflow

–Max Input

82000H

NOTES: (1) Incase of BPZ Error = 0. (2) Overflow detection level is over

70000H or under 82FFFH of digital output code.

This reset should be done by holding the /PD input (pin 21)

low for more than 2/fs. Suggested reset circuits are given in

Figures 11, 12 and 13.

TABLE I. Output Codes.

POWER SUPPLY SEQUENCING

CLOCK INPUT

The PCM1760 requires ±V_CCand ±V_DDpower supplies. To

avoid any possibility of latch-up, the ±V_CCand ±V_DDpower

should all be applied simultaneously or the +V_CCand +V_DD

After power is applied to the DF1760, the system clock

should be provided continuously. The DF1760 employs a

dynamic logic architecture.

applied first followed by –V_CCand –V_DD

Analog Input

V_OS

V_OSPCM1760

DF1760

CAL PD

ANALOG INPUT

+fs

BPZ

–fs

+fs

V_OS

BPZ

–fs

+fs

FIGURE 10. Illustration of Offset Calibration.

PCM1760P/U DF1760P/U

Power-On Reset Circuit

V_DD

DF1760P/U

S/M

10kΩ

/PD

/PD_IN

V_DD

(1)

/PD_OUT

/PD_IN

SDATA

L/R

SDATA

L/R

1588

SCLK

10kΩ

47µF

NOTE: (1) External /PD input: Time "L" > 2/fs.

FIGURE 11. Master Mode Reset Circuit.

Power-On Reset Circuit

V_DD

DF1760P/U

V_DD

S/M

V_DD

10kΩ

/PD_IN

V_DD

/PD_OUT

/PD

LRSC

SDATA

L/R

(1)

/PD_IN

V_DD

CLK

SDATA

L/R

1588

SCLK

74HC74

10kΩ

L/R

47µF

NOTE: (1) External /PD input: Time "L" > 2/fs.

FIGURE 12. Slave Mode Reset Circuit, (LRSC = H).

Power-On Reset Circuit

DF1760P/U

V_DD

S/M

/PD

V_DD

10kΩ

/PD_IN

V_DD

/PD_OUT

LRSC

(1)

/PD_IN

CLK

SDATA

L/R

SDATA

L/R

1588

SCLK

74HC74

L/R

47µF

NOTE: (1) External /PD input: Time "L" > 2/fs.

FIGURE 13. Slave Mode Reset Circuit, (LRSC = L).

PCM1760P/U DF1760P/U

TIMING CHARACTERISTICS

256fs

D₃

D₂

Lch

Rch

D₁

D₀

LRCK

STROBE

FIGURE 14. Input and Output Format of the DF1760 and PCM1760.

L/R (I)

SCLK (I)

FSYNC (I)

SDATA (O)

L M

FIGURE 15a. Slave Mode and SCLK = 32fs. (Output format of the DF1760).

L/R (I)

SCLK (I)

FSYNC (I)

• MSB First 20-Bit (1)

SDATA (O)

• MSB First 20-Bit (2)

SDATA (O)

• MSB First 16-Bit

SDATA (O)

• LSB First 20-Bit

SDATA (O)

FIGURE 15b. Slave Mode and SCLK = 48fs.

PCM1760P/U DF1760P/U

L/R (1)

SCLK (1)

FSYNC (1)

• MSB First 20-Bit (1)

SDATA (0)

• MSB First 20-Bit (2)

SDATA (0)

• MSB First 16-Bit

SDATA (0)

• LSB First 20-Bit

SDATA (0)

FIGURE 15c. Slave Mode and SCLK = 64fs.

L/R (0)

SCLK (0)

• MSB First 20 Bit (1)

FSYNC (0)

SDATA (0)

• MSB First 20 Bit (2)

FSYNC (0)

SDATA (0)

• MSB First 16 Bit

FSYNC (0)

SDATA (0)

• LSB First 20 Bit

FSYNC (0)

SDATA (0)

FIGURE 15d. Master Mode.

PCM1760P/U DF1760P/U

PACKAGE OPTION ADDENDUM

www.ti.com

7-Jun-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

DF1760P

DF1760U

NRND

PDIP

Pb-Free (RoHS)

Call TI

N / A for Pkg Type

Level-3-260C-168 HR

Call TI

Samples Not Available

Pb-Free (RoHS)

PCM1760P

PDIP

SOIC

NTD

TBD

PCM1760P-L

PCM1760U

Call TI

PCM1760U-L

PCM1760U-L/1K

PCM1760U/1K

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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DF1760U [TI]

相关型号：

DF1760U/1KE6

DF1775S50

DF179S

DF17A(1.0H)-30DP-0.5V(51)

DF17A(1.0H)-60DP-0.5V(51)

DF17A(1.0H)-80DP-0.5V(51)

DF17A(2.0)-120DP-0.5V(51)

DF17A(2.0)-40DP-0.5V(51)

DF17A(2.0)-40DP-0.5V(57)

DF17A(3.0)-100DS-0.5V(51)

DF17A(3.0)-120DS-0.5V(51)

DF17A(3.0)-20DS-0.5V(51)