ADS803E_技术文档

®

ADS803

ADS803U

ADS803E

12-Bit, 5MHz Sampling

TM

ANALOG-TO-DIGITAL CONVERTER

● FLEXIBLE INPUT RANGE

FEATURES

● HIGH SFDR: 82dB at NYQUIST

● OVER-RANGE INDICATOR

● HIGH SNR: 69dB

APPLICATIONS

● IF AND BASEBAND DIGITIZATION

● CCD IMAGING SCANNERS

● TEST INSTRUMENTATION

● LOW POWER: 115mW

● LOW DLE: 0.25LSB

●

SMALL 28-LEAD SSOP AND SOIC PACKAGES

DESCRIPTION

range in between the 2Vp-p and 5Vp-p input ranges or to use

external reference. The ADS803 also provides an overrange indica-

tor flag to indicate an input range that exceeds the full-scale input

range of the converter. This flag can be used to reduce the gain of

the front end gain-ranging circuitry.

The ADS803 is a high-speed, high dynamic range, 12-bit pipelined

analog-to-digital converter. This converter includes a high-band-

width track/hold that gives excellent spurious performance up to

and beyond the Nyquist rate. This high-bandwidth, linear track/hold

minimizes harmonics and has low jitter, leading to excellent SNR

performance. The ADS803 is also pin-compatible with the 10MHz

ADS804 and the 20MHz ADS805.

The ADS803 employs digital error correction techniques to provide

excellent differential linearity for demanding imaging applications.

Its low distortion and high SNR give the extra margin needed for

communications, medical imaging, video and test instrumentation

applications. The ADS803 is available in 28-lead SSOP and SOIC

packages.

The ADS803 provides an internal reference and can be programmed

for a 2Vp-p input range for the best spurious performance and ease

of driving. Alternatively, the 5Vp-p input range can be used for the

lowest input referred noise of 0.09 LSBs rms giving superior

imaging performance. There is also a capability to set the input

+V_S

CLK

VDRV

ADS803

Timing Circuitry

V_IN

IN

D0

12-Bit

Pipelined

A/D Core

Error

Correction

Logic

3-State

Outputs

•

T/H

IN

D11

CM

OVR

Reference Ladder

and Driver

Reference and

Mode Select

REFT

V_REF

SEL

REFB

OE

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

FAXLine: (800) 548-6133 (US/Canada Only)

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

•

Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1398C

Printed in U.S.A. October, 1998

SPECIFICATIONS

At T_A= full specified temperature range, V_S= +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified.

ADS803U

TYP

ADS803E

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

(1)

RESOLUTION

12 Guaranteed

–40 to +85

✻

Bits

SPECIFIED TEMPERATURE RANGE

–40 to +85

°C

CONVERSION CHARACTERISTICS

Sample Rate

Data Latency

10k

5M

✻

Samples/s

Clk Cycles

6

✻

ANALOG INPUT

Single-Ended Input Range

Standard Optional Single-Ended Input Range

Common-Mode Voltage

Standard Optional Common-Mode Voltage

Input Capacitance

1.5

0

3.5

5

✻

V

pF

MHz

2.5

1

20

270

✻

Track-Mode Input Bandwidth

–3dBFS Input

DYNAMIC CHARACTERISTICS

Differential Linearity Error (Largest Code Error)

f = 500kHz

±0.25

±0.75

✻

LSB

No Missing Codes

Guaranteed

Spurious Free Dynamic Range⁽²⁾

f = 2.48MHz (–1dB input)

Two-Tone Intermodulation Distortion⁽⁴⁾

f = 1.8M and 1.9M (–7dBFS each tone)

Signal-to-Noise Ratio (SNR)

f = 2.48MHz (–1dB input)

Signal-to-(Noise + Distortion) (SINAD)

f = 2.48MHz (–1dB input)

Effective Number of Bits at 2.48MHz⁽⁵⁾

Input Referred Noise

74

82

74

✻

dBFS

dBc

66.5

65

69

✻

dB

68

11

0.09

0.23

✻

dB

Bits

LSBs rms

0V to 5V Input

1.5V to 3.5V Input

Integral Nonlinearity Error

f = 500kHz

Aperture Delay Time

Aperture Jitter

Overvoltage Recovery Time

Full-Scale Step Acquisition Time

±1

1

4

2

50

±2

✻

LSB

ns

ps rms

ns

1.5 x FS Input

ns

DIGITAL INPUTS

Logic Family

CMOS Compatible

Convert Command

Start Conversion

Rising Edge of Convert Clock Rising Edge of Convert Clock

High Level Input Current (V_IN= 5V)⁽⁶⁾

Low Level Input Current (V_IN= 0V)

High Level Input Voltage

Low Level Input Voltage

Input Capacitance

100

±10

✻

µA

V

pF

+3.5

✻

+1.0

✻

5

✻

DIGITAL OUTPUTS

Logic Family

CMOS/TTL Compatible

V

Logic Coding

Straight Offset Binary

Low Output Voltage

High Output Voltage

3-State Enable Time

3-State Disable Time

Output Capacitance

(I_OL= 50µA)

(I_OL= 1.6mA)

(I_OH= 50µA)

(I_OH= 0.5mA)

OE = L

0.1

0.4

✻

V

+4.5

+2.4

✻

V

20

2

5

40

10

✻

ns

pF

OE = H

ACCURACY (5Vp-p Input Range)

Zero Error (Referred to –FS)

Zero Error Drift (Referred to –FS)

Gain Error⁽⁷⁾

At 25°C

0.2

±5

±1.5

±2.0

±1.5

✻

%FS

ppm/°C

%FS

ppm/°C

%FS

ppm/°C

dB

kΩ

mV

Gain Error Drift⁽⁷⁾

±15

✻

Gain Error⁽⁸⁾

Gain Error Drift⁽⁸⁾

Power Supply Rejection of Gain

Reference Input Resistance

Internal Voltage Reference Tolerance (V_REF= 2.5V)

Internal Voltage Reference Tolerance (V_REF= 1.0V)

At 25°C

±15

82

1.6

✻

∆ V_S= ±5%

60

✻

At 25°C

±35

±14

✻

®

ADS803

2

SPECIFICATIONS (CONT)

At T_A= full specified temperature range, V_S= +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified.

ADS803U

TYP

ADS803E

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

POWER SUPPLY REQUIREMENTS

Supply Voltage: +V_S

Supply Current: +I_S

Power Dissipation

Operating

+4.7

+5.0

23

115

5.3

27

135

✻

V

mA

mW

Thermal Resistance, θ_JA

28-Lead SOIC

28-Lead SSOP

75

°C/W

50

NOTES: (1) An asterisk (✻) indicates same specifications as the ADS803U. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic.

(3) dBFS means dB relative to full scale. (4) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it

is referred to the magnitude of the two-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (6) Internal 50kΩ pull-

down resistor. (7) Includes internal reference. (8) Excludes internal reference.

ABSOLUTE MAXIMUM RATINGS

+V_S....................................................................................................... +6V

ELECTROSTATIC

DISCHARGE SENSITIVITY

Analog Input ........................................................... (–0.3V) to (+V_S+0.3V)

Logic Input ............................................................. (–0.3V) to (+V_S+0.3V)

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature ..................................................................... +150°C

and installation procedures can cause damage.

DEMO BOARD ORDERING INFORMATION

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PRODUCT

DEMO BOARD

ADS803U

DEM-ADS80xU

PACKAGE/ORDERING INFORMATION

PACKAGE

SPECIFIED

DRAWING

NUMBER⁽¹⁾

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA

PRODUCT

PACKAGE

ADS803U

ADS803E

"

SO-28 Surface Mount

SSOP-28 Surface Mount

"

217

324

"

–40°C to +85°C

ADS803U

ADS803E

"

ADS803U

ADS803E

ADS803E/1K

Rails

Tape and Reel

"

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. For detailed Tape and Reel

mechanical information refer to Appendix B of Burr-Brown IC Data Book.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

®

ADS803

3

PIN CONFIGURATION

PIN DESCRIPTIONS

DESIGNATOR

DESCRIPTION

Top View

SOIC/SSOP

1

OVR

B1

Over Range Indicator

Data Bit 1 (MSB)

Data Bit 2

2

3

B2

OVR

B1

B2

B3

B4

B5

B6

B7

B8

1

2

3

4

5

6

7

8

9

28 VDRV

27 +V_S

26 GND

25 IN

4

B3

Data Bit 3

5

B4

Data Bit 4

6

B5

Data Bit 5

7

B6

Data Bit 6

8

B7

Data Bit 7

9

B8

Data Bit 8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

B9

Data Bit 9

24 GND

23 IN

B10

B11

B12

CLK

OE

Data Bit 10

Data Bit 11

Data Bit 12 (LSB)

Convert Clock Input

Output Enable

+5V Supply

22 REFT

21 CM

ADS803

+V_S

GND

SEL

V_REF

REFB

CM

20 REFB

19 VREF

18 SEL

17 GND

16 +V_S

15 OE

Ground

Input Range Select

Reference Voltage Select

Bottom Reference

Common-Mode Voltage

Top Reference

Complementary Analog Input

Analog Ground

Analog Input (+)

Analog Ground

+5V Supply

B9 10

B10 11

B11 12

B12 13

CLK 14

REFT

IN

GND

IN

GND

+V_S

VDRV

Output Driver Voltage

TIMING DIAGRAM

N+2

N+1

N+4

N+3

Analog In

N+7

N+5

N

N+6

t_L

t_H

t_D

t_CONV

Clock

6 Clock Cycles

N–4 N–3

t₂

Data Out

N–6

N–5

N–2

N-1

N

N+1

Data Invalid

t₁

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t_CONV

t_L

t_H

t_D

t₁

Convert Clock Period

Clock Pulse Low

Clock Pulse High

200

96

100µs

ns

99

3

Aperture Delay

Data Hold Time, C_L= 0pF

New Data Delay Time, C_L= 15pF max

3.9

t₂

12

®

ADS803

4

TYPICAL PERFORMANCE CURVES

At T_A= full specified temperature range, V_S= +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified.

SPECTRAL PERFORMANCE

f_IN= 500kHz

SPECTRAL PERFORMANCE

f_IN= 2.48MHz

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

0

0.5

1.0

1.5

2.0

2.5

0

0.5

1.0

1.5

2.0

2.5

Frequency (MHz)

DIFFERENTIAL LINEARITY ERROR

f_IN= 500kHz

FREQUENCY SPECTRUM

1.0

0.5

0

–20

f₁= 1.8MHz at –7dB

f₂= 1.9MHz at –7dB

IMD (3) = –74dBc

–40

0

–60

–80

–0.5

–1.0

–100

–120

0

1024

2048

3072

4096

0

0.5

1.0

1.5

2.0

2.5

Output Code

Frequency (MHz)

INTEGRAL LINEARITY ERROR

SWEPT POWER SFDR

4.0

2.0

100

80

60

40

20

0

f_IN= 2.48MHz

f_IN= 500kHz

dBFS

0

dBc

–2.0

–4.0

0

1024

2048

3072

4096

–60

–50

–40

–30

–20

–10

0

Output Code

Input Amplitude (dBFS)

®

ADS803

5

TYPICAL PERFORMANCE CURVES

At T_A= full specified temperature range, V_S= +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified.

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

SFDR

(Differential Input, V_IN= 5Vp-p)

85

80

75

70

65

60

85

80

75

70

65

60

SFDR

SNR

0.1

1

10

0.1

1

10

Frequency (MHz)

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

SPURIOUS FREE DYNAMIC RANGE

vs TEMPERATURE

0.40

85

80

75

70

f_IN= 500kHz

0.30

0.20

0.10

f_IN= 2.48MHz

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

Temperature (°C)

SIGNAL-TO-NOISE RATIO AND

POWER DISSIPATION vs TEMPERATURE

SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE

117

116

115

114

72

70

68

66

64

f_IN= 500kHz

SNR

f_IN= 500kHz

SINAD

f_IN= 2.48MHz

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

Temperature (°C)

®

ADS803

6

TYPICAL PERFORMANCE CURVES

At T_A= full specified temperature range, V_S= +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified.

OUTPUT NOISE HISTOGRAM

(DC Input, V_IN= 2Vp-p)

(DC Input, V_IN= 5Vp-p Range)

800k

600k

400k

200k

0

800k

600k

400k

200k

0

N-2

N-1

N

N+1

N+2

N-2

N-1

N

N+1

N+2

Code

®

ADS803

7

input of the ADS803 will be beneficial in almost all interface

configurations. This will de-couple the op amp’s output

from the capacitive load and avoid gain peaking, which can

result in increased noise. For best spurious and distortion

performance, the resistor value should be kept below 50Ω.

Furthermore, the series resistor together with the 100pF

capacitor, establish a passive low-pass filter, limiting the

bandwidth for the wideband noise thus help improving the

SNR performance.

APPLICATION INFORMATION

DRIVING THE ANALOG INPUT

The ADS803 allows its analog inputs to be driven either

single-ended or differentially. The focus of the following

discussion is on the single-ended configuration. Typically,

its implementation is easier to achieve and the rated speci-

fications for the ADS803 are characterized using the single-

ended mode of operation.

DC-COUPLED WITHOUT LEVEL SHIFT

AC-COUPLED INPUT CONFIGURATION

In some applications the analog input signal may already be

biased at a level which complies with the selected input

range and reference level of the ADS803. In this case, it is

only necessary to provide an adequately low source imped-

ance to the selected input, IN or IN. Always consider

wideband op amps since their output impedance will stay

low over a wide range of frequencies. For those applications

requiring the driving amplifier to provide a signal amplifica-

tion, with a gain ≥ 3, consider using the decompensated

voltage feedback op amp OPA643.

Given in Figure 1 is the circuit example of the most common

interface configuration for the ADS803. With the V_REFpin

connected to the SEL pin, the full-scale input range is

defined to be 2Vp-p. This signal is ac-coupled in single-

ended form to the ADS803 using the low-distortion voltage

feedback amplifier OPA642. As is generally necessary for

single-supply components, operating the ADS803 with a

full-scale input signal swing requires a level-shift of the

amplifier’s zero centered analog signal to comply with the

A/D’s input range requirements. Using a DC blocking ca-

pacitor between the output of the driving amplifier and the

converter’s input, a simple level-shifting scheme can be

implemented. In this configuration, the top and bottom

references (REFT, REFB) provide an output voltage of +3V

and +2V, respectively. Here, two resistor pairs (2x 2kΩ) are

used to create a common-mode voltage of approximately

+2.5V to bias the inputs of the ADS803 (IN, IN) to the

required DC voltage.

DC-COUPLED WITH LEVEL SHIFT

Several applications may require that the bandwidth of the

signal path includes DC, in which case the signal has to be

DC-coupled to the A/D converter. In order to accomplish

this, the interface circuit has to provide a DC-level shift. The

circuit shown in Figure 2 employs an op amp, A1, to sum the

ground centered input signal with a required DC offset. The

ADS803 typically operates with a +2.5V common-mode

voltage, which is established at the center tap of the ladder

and connected to the IN input of the converter. Amplifier A1

operates in inverting configuration. Here resistors R₁and

R₂set the DC-bias level for A1. Because of the op amp’s

noise gain of +2V/V, assuming R_F= R_IN, the DC offset

voltage applied to its non-inverting input has to be divided

down to +1.25V, resulting in a DC output voltage of +2.5V.

An advantage of ac-coupling is that the driving amplifier

still operates with a ground-based signal swing. This will

keep the distortion performance at its optimum since the

signal swing stays within the linear region of the op amp and

sufficient headroom to the supply rails can be maintained.

Consider using the inverting gain configuration to eliminate

CMR induced errors of the amplifier. The addition of a small

series resistor (R_S) between the output of the op amp and the

+5V –5V

REFT

(+3V)

2kΩ

R_S

24.9Ω

2Vp-p 0.1µF

V_IN

0V

+V_IN

–V_IN

IN

OPA642

100pF

R_F

402Ω

ADS803

R_G

402Ω

+2.5V_DC

IN

0.1µF

(+2V) (+1V)

2kΩ

SEL

REFB

V_REF

FIGURE 1. AC-Coupled Input Configuration for 2Vp-p Input Swing and Common-Mode Voltage at +2.5V Derived from

Internal Top and Bottom Reference.

®

ADS803

8

R_F

REFT

R_IN

+1V

0

2kΩ

+V_S

R_S

24.9Ω

V_IN

IN

OPA681

–1V

2Vp-p

100pF

ADS803

R₁

R₂

+V_S

+2.5V

+

0.1µF

10µF

0.1µF

(+1V)

REFB

V_REF

SEL

2kΩ

NOTE: R_F= R_IN, G = –1

FIGURE 2. DC-Coupled, Single-Ended Input Configuration with DC-Level Shift.

DC voltage differences between the IN and IN inputs of the

ADS803 effectively will produce an offset, which can be

corrected for by adjusting the values of resistors R₁and R₂.

The bias current of the op amp may also result in an

undesired offset. The selection criteria of the appropriate op

amp should include the input bias current, output voltage

R_G

0.1µF

22Ω

1:n

V_IN

IN

100pF

swing, distortion and noise specification. Note that in this

example the overall signal phase is inverted. To re-establish

the original signal polarity it is always possible to inter-

change the IN and IN connections.

R_T

ADS803

22Ω

CM

100pF

SINGLE-ENDED-TO-DIFFERENTIAL

CONFIGURATION (TRANSFORMER COUPLED)

+

4.7µF

0.1µF

In order to select the best suited interface circuit for the

ADS803, the performance requirements must be known. If

an ac-coupled input is needed for a particular application,

the next step is to determine the method of applying the

FIGURE 3. Transformer Coupled Input

signal; either single-ended or differentially. The differential

input configuration may provide a noticeable advantage of

achieving good SFDR performance based on the fact that in

the differential mode the signal swing can be reduced to half

of the swing required for single-ended drive. Secondly, by

driving the ADS803 differentially, the even-order harmonics

will be reduced. Figure 3 shows the schematic for the

suggested transformer coupled interface circuit. The resistor

across the secondary side (R_T) should be set to get an input

impedance match (e.g., R_T= n²• R_G).

gain for the internal reference buffer. For more design

flexibility, the internal reference can be shut off and an

external reference voltage used. Table I provides an over-

view of the possible reference options and pin configura-

tions.

INPUT

FULL-SCALE

RANGE

REQUIRED

V_REF

MODE

CONNECT

TO

Internal

2Vp-p

5Vp-p

+1V

SEL

V_REF

GND

REFERENCE OPERATION

+2.5V

Integrated into the ADS803 is a bandgap reference circuit

including logic that provides either a +1V or +2.5V refer-

ence output, by simply selecting the corresponding pin-strap

configuration. Different reference voltages can be generated

by the use of two external resistors, which will set a different

2V≤ FSR < 5V

1V < V_REF< 2.5V

V_REF= 1 + (R₁/R₂)

R₁

R₂

V_REFand SEL

SEL and GND

FSR = 2 x V_REF

External

1V < FSR < 5V

0.5V < V_REF< 2.5V

SEL

+V_S

V_REF

Ext. V_REF

TABLE I. Selected Reference Configuration Examples.

®

ADS803

9

Disable

Switch

SEL

V_REF

1V_DC

to A/D

REFT

CM

Resistor Network

and Switches

800Ω

Bandgap

and Logic

Reference

Driver

REFB

to A/D

ADS803

FIGURE 4. Equivalent Reference Circuit.

A simple model of the internal reference circuit is shown in

Figure 4. The internal blocks are a 1V-bandgap voltage

reference, buffer, the resistive reference ladder and the

drivers for the top and bottom reference which supply the

necessary current to the internal nodes. As shown, the output

of the buffer appears at the V_REFpin. The full-scale input

operation with all reference configurations, it is necessary to

provide solid bypassing to the reference pins in order to keep

the clock feedthrough to a minimum. Figure 5 shows the

recommended decoupling network.

span of the ADS803 is determined by the voltage at V_REF

,

according to the equation (1):

Full-Scale Input Span = 2 x V_REF

(1)

Note that the current drive capability of this amplifier is

limited to approximately 1mA and should not be used to

drive low loads. The programmable reference circuit is

controlled by the voltage applied to the select pin (SEL).

Refer to Table I for an overview.

REFT

IN

0.1µF

R₁

CMV

ADS803

R₂

IN

REFB

0.1µF

The top reference (REFT) and the bottom reference (REFB)

are brought out mainly for external bypassing. For proper

FIGURE 6. Alternative Circuit to Generate CM Voltage.

ADS803

In addition, the common-mode voltage (CMV) may be used

as a reference level to provide the appropriate offset for the

driving circuitry. However, care must be taken not to appre-

ciably load this node, which is not buffered and has a high

impedance. An alternate method of generating a common-

mode voltage is given in Figure 6. Here, two external

precision resistors (tolerance 1% or better) are located be-

tween the top and bottom reference pins. The common-

mode level will appear at the midpoint. The output buffers

of the top and bottom reference are designed to supply

approximately 2mA of output current.

REFT

REFB

CM

V_REF

0.1µF

+

10µF

+

10µF

0.1µF

FIGURE 5. Recommended Reference Bypassing Scheme.

®

ADS803

10

SELECTING THE INPUT RANGE AND

REFERENCE

EXTERNAL REFERENCE OPERATION

Depending on the application requirements, it might be

advantageous to operate the ADS803 with an external refer-

ence. This may improve the DC accuracy if the external

reference circuitry is superior in its drift and accuracy. To

use the ADS803 with an external reference, the user must

disable the internal reference (see Figure 10). By connecting

the SEL pin to +V_S, the internal logic will shut down the

internal reference. At the same time, the output of the

internal reference buffer is disconnected from the V_REFpin,

which now must be driven with the external reference. Note

that a similar bypassing scheme should be maintained as

described for the internal reference operation.

Figures 7 through 9 show a selection of circuits for the most

common input ranges when using the internal reference of

the ADS803. All examples are for single-ended input and

operate with a nominal common-mode voltage of +2.5V.

5V

V_IN

IN

0V

ADS803

V_REF

SEL

4.5V

V_IN

+2.5V

IN

0.5V

ADS803

+2.5V ext.

FIGURE 7. Internal Reference with 0V to 5V Input Range.

REF1004

+2.5V

IN

V_REF

SEL

+5V

+

0.1µF

10µF

1.24kΩ

+2V_DC

3.5V

4.99kΩ

V_IN

IN

1.5V

ADS803

FIGURE 10. External Reference, Input Range 0.5V to 4.5V

(4Vp-p), with +2.5V Common-Mode Voltage.

+2.5V ext.

V_REF

+1V

SEL

DIGITAL INPUTS AND OUTPUTS

Over Range (OVR)

FIGURE 8. Internal Reference with 1.5V to 3.5V Input

Range.

One feature of the ADS803 is its ‘Over Range’ digital output

(OVR). This pin can be used to monitor any out-of-range

condition, which occurs every time the applied analog input

voltage exceeds the input range (set by V_REF). The OVR

output is LOW when the input voltage is within the defined

input range. It becomes HIGH when the input voltage is

beyond the input range. This is the case when the input

voltage is either below the bottom reference voltage or

above the top reference voltage. OVR will remain active

until the analog input returns to its normal signal range and

another conversion is completed. Using the MSB and its

complement in conjunction with OVR, a simple clue logic

can be built that detects the overrange and underrange

conditions (see Figure 11). It should be noted that OVR is a

digital output which is updated along with the bit informa-

tion corresponding to the particular sampling incidence of

the analog signal. Therefore, the OVR data is subject to the

same pipeline delay (latency) as the digital data.

4V

IN

1V

ADS803

+2.5V ext.

IN

V_REF

SEL

R₁

5kΩ

R₁

R₂

+1.5V

V_REF= 1V 1 +

R₂

10kΩ

FSR = 2 x V_REF

FIGURE 9. Internal Reference with 1V to 4V Input Range.

®

ADS803

11

necessary, external buffers or latches may be used which

provide the added benefit of isolating the ADS803 from any

digital noise activities on the bus coupling back high fre-

quency noise. In addition, resistors in series with each data

line may help maintain the ac performance of the ADS803.

Their use depends on the capacitive loading seen by the

converter. Values in the range of 100Ω to 200Ω will limit

the instantaneous current the output stage has to provide for

recharging the parasitic capacitances, as the output levels

change from L to H or H to L.

MSB

OVR

Over = H

Under = H

GROUNDING AND DECOUPLING

FIGURE 11. External Logic for Decoding Under- and

Overrange Conditions.

Proper grounding and bypassing, short lead length, and the

use of ground planes are particularly important for high

frequency designs. Multi-layer PC boards are recommended

for best performance since they offer distinct advantages

like minimizing ground impedance, separation of signal

layers by ground layers, etc. It is recommended that the

analog and digital ground pins of the ADS803 be joined

together at the IC and be connected only to the analog

ground of the system.

CLOCK INPUT REQUIREMENTS

Clock jitter is critical to the SNR performance of high speed,

high resolution analog-to-digital converters. It leads to aper-

ture jitter (t_A) which adds noise to the signal being con-

verted. The ADS803 samples the input signal on the rising

edge of the CLK input. Therefore, this edge should have the

lowest possible jitter. The jitter noise contribution to total

SNR is given by the following equation. If this value is near

your system requirements, input clock jitter must be re-

duced.

The ADS803 has analog and digital supply pins, however,

the converter should be treated as an analog component and

all supply pins should be powered by the analog supply. This

will ensure the most consistent results, since digital supply

lines often carry high levels of noise that would otherwise be

coupled into the converter and degrade the achievable per-

formance.

1

JitterSNR = 20log

rmssignaltormsnoise

2πƒ _INt_A

Because of the pipeline architecture, the converter also

generates high frequency current transients and noise that

are fed back into the supply and reference lines. This

requires that the supply and reference pins be sufficiently

bypassed. Figure 12 shows the recommended decoupling

scheme for the analog supplies. In most cases, 0.1µF ce-

ramic chip capacitors are adequate to keep the impedance

low over a wide frequency range. Their effectiveness largely

depends on the proximity to the individual supply pin.

Therefore, they should be located as close to the supply pins

as possible. In addition, a larger size bipolar capacitor (1 to

22µF) should be placed on the PC board in close proximity

to the converter circuit.

Where: ƒ_INis Input Signal Frequency

t_Ais rms Clock Jitter

Particularly in undersampling applications, special consider-

ation should be given to clock jitter. The clock input should

be treated as an analog input in order to achieve the highest

level of performance. Any overshoot or undershoot of the

clock signal may cause degradation of the performance.

When digitizing at high sampling rates, the clock should

have a 50% duty cycle (t_H= t_L), along with fast rise and fall

times of 2ns or less.

DIGITAL OUTPUTS

The digital outputs of the ADS803 are designed to be

compatible with both high speed TTL and CMOS logic

families. The driver stage for the digital outputs is sup-

plied through a separate supply pin, VDRV, which is not

connected to the analog supply pins. By adjusting the

voltage on VDRV, the digital output levels will vary

respectively. Therefore, it is possible to operate the ADS803

on a +5V analog supply while interfacing the digital

outputs to 3V logic.

ADS803

+V_S

27

GND

26

+V_S

16

GND

17

VDRV

28

0.1µF

2.2µF

+

It is recommended to keep the capacitive loading on the data

lines as low as possible (≤ 15pF). Larger capacitive loads

demand higher charging currents as the outputs are chang-

ing. Those high current surges can feed back to the analog

portion of the ADS803 and influence the performance. If

+5V

+5V/+3V

FIGURE 12. Recommended Bypassing for Analog Supply

Pins.

®

ADS803

12


型号：	ADS803E
厂家：	BURR-BROWN CORPORATION
描述：	12-Bit, 5MHz Sampling ANALOG-TO-DIGITAL CONVERTER 12位， 5MHz的采样模拟数字转换器转换器光电二极管
文件：	总12页 (文件大小：257K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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