HCPL-7860 [AVAGO]
The HCPL-7860/HCPL-786J Optically Isolated Modulator and HCPL-0872 Digital Interface IC or digital filter together form an isolated programmable two-chip analog-to-digital converter.; 的HCPL- 7860 / HCPL- 786J光隔离调制器和HCPL- 0872的数字接口集成电路或数字滤波器一起形成的分离的可编程双芯片的模拟 - 数字转换器。
| 型号： | HCPL-7860 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | The HCPL-7860/HCPL-786J Optically Isolated Modulator and HCPL-0872 Digital Interface IC or digital filter together form an isolated programmable two-chip analog-to-digital converter. |
| 文件： | 总18页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-7860/HCPL-786J
Optically Isolated Sigma-Delta (S-D) Modulator
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
ꢃ 12-bit Linearity
The HCPL-7860/HCPL-786J Optically Isolated Modulator
and HCPL-0872 Digital Interface IC or digital filter together
form an isolated programmable two-chip analog-to-digital
converter. The isolated modulator allows direct measure-
ment of motor phase currents in power inverters.
ꢃ 200 ns Conversion Time
(Pre-Trigger Mode 2 with HCPL-0872)
ꢃ 12-bit Effective Resolution with 5 ꢄs Signal Delay
(14-bit with 102 ꢄs) (with HCPL-0872)
In operation, the HCPL-7860/HCPL-786J Isolated Modula-
tor converts a low-bandwidth analog input into a high-
speed one-bit data stream by means of a Sigma-Delta
(ꢀꢁꢂ) over-sampling modulator. This modulation provides
for high noise margins and excellent immunity against
isolation-mode transients. The modulator data and on-
chip sampling clock are encoded and transmitted across
the isolation boundary where they are recovered and de-
coded into separate high-speed clock and data channels.
ꢃ Fast 3 ꢄs Over-Range Detection (with HCPL-0872)
ꢃ
200 mV Input Range with Single 5 V Supply
ꢃ 1% Internal Reference Voltage Matching
ꢃ Offset Calibration (with HCPL-0872)
ꢃ -40°C to +85°C Operating Temperature Range
ꢃ 15 kV/ꢄs Isolation Transient Immunity
ꢃ Safety Approval: UL 1577, CSA and IEC/EN/DIN EN
60747-5-2
Applications
ꢃ Motor Phase and Rail Current Sensing
ꢃ Data Acquisition Systems
ꢃ Industrial Process Control
ꢃ Inverter Current Sensing
ꢃ General Purpose Current Sensing and Monitoring
1
2
8
7
6
5
SIGMA
DELTA
MOD./
HCPL-0872
or
Digital Filter
MCU
or
DSP
Input
Current
DECODE
ENCODE
3
4
HCPL-7860
NOTE: A 0.1 μF bypass capacitor must be connected between pins VDD1 and GND1 and between pins VDD2 and GND2.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation, which may be induced by ESD.
Pin Description
ISOLATION
BOUNDARY
VDD1
VIN+
VIN-
NC
GND2
NC
1
2
3
4
5
6
7
8
16
15
VDD1
VDD2
1
2
3
4
8
7
6
5
14 VDD2
SIGMA-
DELTA
13 MCLK
VIN+
V IN-
MCLK
MDAT
GND2
SIGMA-
DECODER
MOD./
DELTA
MOD./
ENCODE
NC
NC
12
11
ENCODER
DECODE
NC
MDAT
NC
10 NC
GND2
GND1
SHIELD
GND1
9
HCPL-7860
HCPL-786J
Symbol
VDD1
VIN+
Description
Symbol
VDD2
Description
Supply voltage input (4.5 V to 5.5 V)
Supply voltage input (4.5 V to 5.5 V)
Clock output (10 MHz typical)
Serial data output
Positive input ( 200 mV recommended)
MCLK
MDAT
GND2
VIN-
Negative input (normally connected to GND1)
Input ground
GND1
Output ground
Note: NC = No connection. Leave floating.
Ordering Information
HCPL-7860 is UL Recognized with 3750 Vrms for 1 minute per UL1577. HCPL-786J is UL Recognized with 5000 Vrms for
1 minute per UL1577.
Option
RoHS
Compliant
Non-RoHS
Compliant
Surface
Mount
Gull
Wing
Tape
& Reel
IEC/EN/DIN EN
60747-5-2
Part number
Package
Quantity
HCPL-7860
-000E
-300E
-500E
-000E
-500E
No option
#300
300 mil
DIP-8
X
X
X
X
X
50 per tube
50 per tube
1000 per reel
45 per tube
850 per reel
X
X
X
X
#500
X
X
HCPL-786J
No option
#500
SO-16
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7860-500E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN
EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-786J to order product of SO-16 package in tube packaging and non-RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation‘#XXX’is used for existing products, while (new) products launched since 15th July 2001 and RoHS
compliant option will use ‘-XXXE’.
2
Package Outline Drawings
8-pin DIP Package
9.80 0.25
(0.386 0.010ꢀ
8
7
6
5
4
REFERENCE VOLTAGE
MATCHING SUFFIX*
TYPE NUMBER
A 7860X
YYWW
DATE CODE
1
2
3
PIN ONE
1.19 (0.047ꢀ MAX.
1.78 (0.070ꢀ MAX.
7.62 0.25
(0.300 0.010ꢀ
6.35 0.25
(0.250 0.010ꢀ
3.56 0.13
(0.140 0.005ꢀ
4.70 (0.185ꢀ MAX.
0.51 (0.020ꢀ MIN.
2.92 (0.115ꢀ MIN.
1.080 0.320
(0.043 0.013ꢀ
0.65 (0.025ꢀ MAX.
0.20 (0.008ꢀ
0.33 (0.013ꢀ
2.54 0.25
(0.100 0.010ꢀ
5° TYP.
DIMENSIONS IN MILLIMETERS AND (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20mils) MAX.
NOTE: INITIAL OR CONTINUED VARIATION IN THE COLOUR OF THE HCPL-7860/HCPL-786J’S WHITE MOLD
COMPOUND ISNORMAL AND DOES NOT AFFECT DEVICE PERFORMANCE OR RELIABILITY.
*ALL UNITS WITHIN EACH HCPL-7860 STANDARD PACKAGING INCREMENT (EITHER 50 PER TUBE OR 1000 PER
REEL) HAVEA COMMON MARKING SUFFIX TO REPRESENT A REFERENCE VOLTAGE MATCHING OF 1%. AN
ABSOLUTEREFERENCE VOLTAGE TOLERANCE OF 4% IS GUARANTEED BETWEEN STANDARD PACKAGING
INCREMENTS.
3
8-pin Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
1.016 (0.040ꢀ
9.80 0.25
(0.386 0.010ꢀ
6
5
8
1
7
6.350 0.25
(0.250 0.010ꢀ
10.9 (0.430ꢀ
2.0 (0.080ꢀ
2
3
4
1.27 (0.050ꢀ
9.65 0.25
1.780
(0.070ꢀ
MAX.
(0.380 0.010ꢀ
1.19
(0.047ꢀ
MAX.
7.62 0.25
(0.300 0.010ꢀ
0.20 (0.008ꢀ
0.33 (0.013ꢀ
3.56 0.13
(0.140 0.005ꢀ
1.080 0.320
(0.043 0.013ꢀ
0.635 0.25
(0.025 0.010ꢀ
12° NOM.
2.540
(0.100ꢀ
BSC
0.51 0.130
(0.020 0.005ꢀ
DIMENSIONS IN MILLIMETERS (INCHESꢀ.
TOLERANCES (UNLESS OTHERWISE SPECIFIEDꢀ:
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004ꢀ
xx.xx = 0.01
xx.xxx = 0.005
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 milsꢀ MAX.
16-Lead Surface Mount
LAND PATTERN RECOMMENDATION
0.64 (0.025ꢀ
0.457
(0.018ꢀ
1.270
(0.050ꢀ
16 15 14 13 12 11 10
9
TYPE NUMBER
DATE CODE
A 786J
YYWW
7.493 0.254
(0.295 0.010ꢀ
11.63 (0.458ꢀ
2.16 (0.085ꢀ
1
2
3
4
5
6
7
8
10.312 0.254
(0.406 0.10ꢀ
ALL LEADS
8.763 0.254
(0.345 0.010ꢀ
TO BE
9°
COPLANAR
0.002
3.505 0.127
(0.138 0.005ꢀ
0-8°
0.457
0.203 0.076
(0.008 0.003ꢀ
STANDOFF
(0.018ꢀ
0.025 MIN.
10.363 0.254
(0.408 0.010ꢀ
DIMENSIONS IN MILLIMETERS AND (INCHESꢀ.
NOTE: Initial and continued variation in the color of the HCPL-786J's white mold compound is normal
and does not affect device performance or reliability.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 milsꢀ MAX.
4
Solder Reflow Temperature Profile
300
PREHEATING RATE 3˚C + 1˚Cꢀ-0.5˚CꢀSEC.
REFLOW HEATING RATE 2.5˚C 0.5˚CꢀSEC.
PEAK
TEMP.
245˚C
PEAK
TEMP.
240˚C
PEAK
TEMP.
230˚C
200
100
2.5˚C 0.5˚CꢀSEC.
SOLDERING
TIME
200˚C
30
160˚C
150˚C
140˚C
SEC.
30
SEC.
3˚C + 1˚Cꢀ-0.5˚C
PREHEATING TIME
150˚C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
Note: Use of non-chlorine-activated fluxes is highly recommended.
Recommended Lead Free IR Profile
TIME WITHIN 5˚C of ACTUAL
PEAK TEMPERATURE
t
p
20-40 SEC.
260 +0/-5˚C
Tp
TL
217˚C
RAMP-UP
3˚C/SEC. MAX.
RAMP-DOWN
6˚C/SEC. MAX.
150 - 200˚C
Tsmax
Tsmin
ts
tL
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25˚C to PEAK
TIME (SECONDS)
NOTES:
THE TIME FROM 25˚C to PEAK TEMPERATURE = 8 MINUTES MAX.
smax = 200˚C, Tsmin = 150˚C
T
Note: Use of non-chlorine-activated fluxes is highly recommended.
Regulatory Information
The HCPL-7860/HCPL-786J has been approved by the following organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2
UL
Approval under UL 1577, component recognition pro-
gram. File E55361.
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
(VDE 0884 Teil 2):2003-01.
5
[1]
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics
Description
Symbol
HCPL-7860 HCPL-786J
Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ꢅ 300 Vrms
I - IV
I - III
I - III
I - II
I - IV
I - IV
I - IV
I - III
for rated mains voltage ꢅ 450 Vrms
for rated mains voltage ꢅ 600 Vrms
for rated mains voltage ꢅ 1000 Vrms
Climatic Classification
40/85/21
2
40/85/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
VIORM
VPR
891
1230
2306
Vpeak
Vpeak
Input to Output Test Voltage, Method b [2]
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec,
Partial discharge < 5 pC
1670
Input to Output Test Voltage, Method a[2]
VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec,
Partial discharge < 5 pC
VPR
1425
6000
1968
8000
Vpeak
Vpeak
Highest Allowable Overvoltage(Transient Overvoltage tini = 60 sec)
VIOTM
Safety-limiting values - maximum values allowed in the event of a failure.
Case Temperature
Input Current [3]
Output Power [3]
TS
175
400
600
175
400
600
°C
mA
mW
IS, INPUT
PS, OUTPUT
Insulation Resistance at TS, VIO = 500 V
RS
>109
>109
ꢆ
Notes:
800
700
600
500
400
300
1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must
be ensured by protective circuits within the application. Surface Mount Classifications is Class
A in accordance with CECC00802.
2. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog,
under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-2) for a detailed descrip-
tion of Method a and Method b partial discharge test profiles.
P
(mWꢀ
S
IS (mAꢀ
3. Refer to the following figure for dependence of P and I on ambient temperature.
S
S
200
100
0
0
25 50 75 100 125 150 175 200
TS - CASE TEMPERATURE - o
C
Insulation and Safety Related Specifications
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
Parameter
Symbol
DIP-8
SO-16
Units
Conditions
Minimum External Air Gap L(101)
(Clearance)
7.4
8.3
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking L(102)
(Creepage)
8.0
0.5
8.3
0.5
mm
mm
Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal Plastic
Gap (Internal Clearance)
Through insulation distance conductor to conductor,
usually the straight line distance thickness between
the emitter and detector.
Tracking Resistance
(Comparative Tracking
Index)
CTI
>175
IIIa
>175
IIIa
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
6
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Note
Storage Temperature
TS
-55
125
°C
Ambient Operating Temperature
Supply Voltages
TA
-40
0
85
°C
V
VDD1, VDD2
5.5
Steady-State Input Voltage
Two Second Transient Input Voltage
Output Voltages
VIN+, VIN-
-2.0
-6.0
-0.5
VDD1 + 0.5
V
1
MCLK, MDAT
V
DD2 + 0.5
V
Lead Solder Temperature
Solder Reflow Temperature Profile
260°C for 10 sec., 1.6 mm below seating plane
See Maximum Solder Reflow Thermal Profile section
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Note
Ambient Operating Temperature
TA
-40
+85
°C
Supply Voltages
Input Voltage
VDD1, VDD2
4.5
5.5
V
VIN+, VIN-
-200
+200
mV
1
Electrical Specifications (DCꢀ
Unless otherwise noted, all specifications are at V = 0 V and V = 0 V, all Typical specifications are at T = 25°C and
IN+
IN-
A
V
DD1
V
DD1
= V
= 5 V, and all Minimum and Maximum specifications apply over the following ranges: T = -40°C to +85°C,
D
D
2
A
= 4.5 to 5.5 V and V
= 4.5 to 5.5 V.
DD2
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Fig.
Note
Average Input Bias Current
IIN
-0.8
ꢀA
1
3
Average Input Resistance
RIN
450
60
k ꢆ
3
4
Input DC Common-Mode
Rejection Ratio
CMRRIN
dB
Output Logic High Voltage
Output Logic Low Voltage
Output Short Circuit Current
VOH
VOL
3.9
4.9
0.1
30
V
IOUT = -100 ꢀA
IOUT = 1.6 mA
0.6
V
|IOSC
|
mA
VOUT = VDD2
or GND2
5
6
Input Supply Current
Output Supply Current
Output Clock Frequency
Data Hold Time
IDD1
IDD2
fCLK
10
10
10
15
15
mA
mA
MHz
ns
VIN+ = -350 mV
to +350 mV
2
3
4
15
8.2
13.2
tHDDAT
7
3
Electrical Specifications (Tested with HCPL-0872 or Sinc Filterꢀ
Unless otherwise noted, all specifications are at V = -200 mV to +200 mV and V = 0 V; all Typical specifications are
IN+
IN-
at T = 25°C and V
= V
= 5 V, and all Minimum and Maximum specifications apply over the following ranges: T =
A
DD1
D
D
2
A
-40°C to +85°C, V
= 4.5 to 5.5 V and V
= 4.5 to 5.5 V.
DD1
DD2
STATIC CHARACTERISTICS
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Fig. Note
Resolution
15
bits
7
Integral Nonlinearity
INL
3
30
0.14
1
LSB
%
5
6
8
8
9
0.01
Differential Nonlinearity
DNL
VOS
LSB
mV
ꢀV/°C
mV/V
mV
%
Uncalibrated Input Offset
Offset Drift vs. Temperature
Offset drift vs. VDD1
-3
0
3
VIN+ = 0 V
VIN+ = 0 V
VIN+ = 0 V
7
7
7
8
8
dVOS/dTA
dVOS/dVDD1
VREF
2
10
10
0.12
320
Internal Reference Voltage
Absolute Reference Voltage Tolerance
-4
4
2
2
Reference Voltage
Matching
HCPL-7860
HCPL-786J
-1
-2
1
2
%
TA = 25°C.
8
%
V
REF Drift vs. Temperature
dVREF/dTA
60
ppm/°C.
%
8
8
VREF Drift vs. VDD1
dVREF/dVDD1
0.2
Full Scale Input Range
-VREF
-200
+VREF mV
+200 mV
11
Recommended Input Voltage Range
DYNAMIC CHARACTERISTICS (Digital Interface IC HCPL-0872 is set to Conversion Mode 3.ꢀ
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Fig.
Note
Signal-to-Noise Ratio
SNR
62
73
dB
VIN+ = 35 Hz,
400 mVpk-pk
9,10
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Effective Number of Bits
Conversion Time
THD
SND
ENOB
tC2
-67
66
12
0.2
19
39
19
3.0
10
dB
dB
bits
ꢀs
(141 mVrms
)
sine wave.
10
11
12
13
13
0.8
23
47
23
4.2
Pre-Trigger Mode 2
Pre-Trigger Mode 1
Pre-Trigger Mode 0
1,12
1,12
1,12
13
tC1
ꢀs
tC0
ꢀs
Signal Delay
tDSIG
tOVR1
ꢀs
14
15
16
Over-Range Detect Time
2.0
ꢀs
VIN+ = 0 to 400mV
step waveform
14
Threshold Detect Time (default tTHR1
configuration)
ꢀs
Signal Bandwidth
BW
18
15
22
20
kHz
15
17
18
Isolation Transient Immunity
CMR
kV/ꢀs
VISO = 1 kV
8
Package Characteristics
Parameter
Symbol
Device
Min.
Typ.
Max.
Units
Conditions
Note
Input-Output Momentary
Withstand Voltage*
VISO
HCPL-7860 3750
HCPL-786J 5000
1012
Vrms
RH ≤ 50%, t = 1 min; 19, 20
TA = 25°C
Input-Output Resistance
RI-O
1013
ꢆ
V
I-O = 500 Vdc
20
1011
TA = 100°C
f = 1 MHz
Input-Output Capacitance
CI-O
1.4
96
pF
20
Input IC Junction-to-Case
Thermal Resistance
ꢇjci
°C/W
Thermocouple located at center
underside of package
Output IC Junction-to-Case
Thermal Resistance
ꢇjco
114
°C/W
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level
safety specification, or Avago Technologies Application Note 1074, “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. If V (pin 3) is brought above V
- 2 V with respect to GND1 an internal optical-coupling test mode may be activated. This test mode is not
IN-
DD1
intended for customer use.
2. All units within each HCPL-7860 standard packaging increment (either 50 per tube or 1000 per reel) have a Reference Voltage Matching of 1%.
An Absolute Reference Voltage Tolerance of 4% is guaranteed between standard packaging increments.
3. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown.
4. CMRR is defined as the ratio of the gain for differential inputs applied between V and V to the gain for common-mode inputs applied to both
IN
IN+
IN-
V
IN+
and V with respect to input ground GND1.
IN-
5. Short-circuit current is the amount of output current generated when either output is shorted to V
recommended.
or GND2. Use under these conditions is not
DD2
6. Data hold time is amount of time that the data output MDAT will stay stable following the rising edge of output clock MCLK.
7. Resolution is defined as the total number of output bits. The useable accuracy of any A/D converter is a function of its linearity and signal-to-noise
ratio, rather than how many total bits it has.
8. Integral nonlinearity is defined as one-half the peak-to-peak deviation of the best-fit line through the transfer curve for V = -200 mV to +200 mV,
IN+
expressed either as the number of LSBs or as a percent of measured input range (400 mV).
9. Differential nonlinearity is defined as the deviation of the actual difference from the ideal difference between midpoints of successive output codes,
expressed in LSBs.
10. Data sheet value is the average magnitude of the difference in offset voltage from T =25°C to T = 85°C, expressed in microvolts per °C. Three
A
A
standard deviation from typical value is less than 6 ꢄV/°C.
11. Beyond the full-scale input range the output is either all zeroes or all ones.
12. The effective number of bits (or effective resolution) is defined by the equation ENOB = (SNR-1.76)/6.02 and represents the resolution of an ideal,
quantization-noise limited A/D converter with the same SNR.
13. Conversion time is defined as the time from when the convert start signal CS is brought low to when SDAT goes high, indicating that output data
is ready to be clocked out. This can be as small as a few cycles of the isolated modulator clock and is determined by the frequency of the isolated
modulator clock and the selected Conversion and Pre-Trigger modes. For determining the true signal delay characteristics of the A/D converter for
closed-loop phase margin calculations, the signal delay specification should be used.
14. Signal delay is defined as the effective delay of the input signal through the Isolated A/D converter. It can be measured by applying a -200 mV to
200 mV step at the input of modulator and adjusting the relative delay of the convert start signal CS so that the output of the converter is at mid
scale. The signal delay is the elapsed time from when the step signal is applied at the input to when output data is ready at the end of the conver-
sion cycle. The signal delay is the most important specification for determining the true signal delay characteristics of the A/D converter and should
be used for determining phase margins in closed-loop applications. The signal delay is determined by the frequency of the modulator clock and
which Conversion Mode is selected, and is independent of the selected Pre-Trigger Mode and, therefore, conversion time.
15. The minimum and maximum overrange detection time is determined by the frequency of the channel 1 isolated modulator clock.
16. The minimum and maximum threshold detection time is determined by the user-defined configuration of the adjustable threshold detection circuit
and the frequency of the channel 1 isolated modulator clock. See the Applications Information section for further detail. The specified times apply
for the default configuration.
17. The signal bandwidth is the frequency at which the magnitude of the output signal has decreased 3 dB below its low-frequency value. The signal
bandwidth is determined by the frequency of the modulator clock and the selected Conversion Mode.
18. The isolation transient immunity (also known as Common-Mode Rejection) specifies the minimum rate-of-rise of an isolation-mode signal applied
across the isolation boundary beyond which the modulator clock or data signals are corrupted.
19. In accordance with UL1577, for devices with minimum V specified at 3750 Vrms(HCPL-7860) or 5000 Vmrs (HCPL-786J) , each isolated modulator
ISO
(optocoupler) is proof-tested by applying an insulation test voltage greater than 4500 Vrms (HCPL-7860) or 6000 Vrms (HCPl-786J) for one second.
This test is performed before the Method b, 100% production test for partial discharge shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristics
Table.
20. This is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together.
9
1
0
10.5
-40 °C
25 °C
85 °C
-1
-2
-3
-4
-5
-6
-7
-8
-9
10.0
9.5
9.0
8.5
8.0
-6
-4
-2
0
2
6
-400
-200
0
200
400
4
V
- V
IN
VIN - mV
Figure 1. IIN vs. VIN.
Figure 2. IDD1 vs. VIN.
9.4
9.2
9.0
8.8
8.6
8.4
8.2
10.0
9.8
9.6
9.4
9.2
9.0
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
-40 °C
25 °C
85 °C
8.8
8.6
8.0
-400
-200
0
200
400
-40
-15
10
35
60
85
VIN - mV
TEMPERATURE - °C
Figure 3. IDD2 vs. VIN.
Figure 4. Clock Frequency vs. Temperature.
7
0.02
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
V
V
V
DD1 = 4.5 V
DD1 = 5.0 V
DD1 = 5.5 V
0.018
0.016
0.014
0.012
0.01
6
5
4
3
2
0.008
0.006
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE - °C
TEMPERATURE - °C
Figure 6. INL (%ꢀ vs. Temperature
Figure 5. INL (Bitsꢀ vs. Temperature
10
150
100
50
0.8
0.6
0.4
0.2
0
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
0
-50
-100
-150
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
-0.2
-0.4
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE - °C
TEMPERATURE - °C
Figure 7. Offset Change vs. Temperature
Figure 8. VREF Change vs. Temperature
68
67
66
65
64
63
80
75
70
65
60
55
50
45
V
V
V
DD1 = 4.5 V
DD1 = 5.0 V
DD1 = 5.5 V
62
61
-40
-15
10
35
60
85
1
2
3
5
4
TEMPERATURE - °C
CONVERSION MODE #
Figure 9. SNR vs. Temperature
Figure 10. SNR vs. Conversion Mode.
14
200
180
160
140
120
100
80
PRE-TRIGGER MODE 0
PRE-TRIGGER MODE 1
PRE-TRIGGER MODE 2
13
12
11
10
60
40
9
8
20
0
1
2
3
4
5
1
2
3
4
5
CONVERSION MODE #
CONVERSION MODE #
Figure 11. Effective Resolution vs. Conversion Mode.
Figure 12. Conversion Time vs. Conversion Mode.
11
100
90
80
70
60
50
40
V
(200 mV/DIV.ꢀ
IN+
OVR1 (200 mV/DIV.ꢀ
THR1
(2 V/DIV.ꢀ
30
20
10
0
1
2
3
4
5
2 μs/DIV.
CONVERSION MODE #
Figure 13. Signal Delay vs. Conversion Mode.
Figure 14. Over-Range and Threshold Detect Times.
100
90
80
70
60
50
40
Application Information
Digital Current Sensing
As shown in Figure 16, using the Isolated 2-chip A/D con-
verter to sense current can be as simple as connecting a
current-sensing resistor, or shunt, to the input and reading
output data through the 3-wire serial output interface.
By choosing the appropriate shunt resistance, any range
of current can be monitored, from less than 1 A to more
than 100 A.
30
20
10
0
4
5
1
2
3
Even better performance can be achieved by fully utilizing
the more advanced features of the Isolated A/D converter,
such as the pre-trigger circuit, which can reduce conver-
sion time to less than 1 ꢄs, the fast over-range detector
for quickly detecting short circuits, different conversion
modes giving various resolution/speed trade-offs, offset
calibration mode to eliminate initial offset from measure-
ments, and an adjustable threshold detector for detecting
non-short circuit overload conditions.
CONVERSION MODE #
Figure 15. Signal Bandwidth vs. Conversion Mode.
NON-ISOLATED
+ 5 V
ISOLATED
+ 5 V
CCLK
VDD
CHAN
SCLK
SDAT
CS
CLAT
+
VDD1
VIN+
VIN-
VDD2
MCLK
MDAT
CDAT
INPUT
CURRENT
3-WIRE
SERIAL
INTERFACE
MCLK1
MDAT1
MCLK2
MDAT2
GND
R SHUNT
0.02
C1
0.1 μF
C2
0.1 μF
+
THR1
OVR1
RESET
GND1
GND2
C3
10 μF
HCPL-7860ꢀ
HCPL-786J
HCPL-0872
Figure 16. Typical Application Circuit.
12
Product Description
The HCPL-7860/HCPL-786J Isolated Modulator (optocou-
pler) uses sigma-delta modulation to convert an analog
input signal into a high-speed (10 MHz) single-bit digital
data stream; the time average of the modulator’s single-
bit data is directly proportional to the input signal. The
isolated modulator’s other main function is to provide
galvanic isolation between the analog input and the digital
output. An internal voltage reference determines the full-
scale analog input range of the modulator (approximately
320 mV); an input range of 200 mV is recommended
to achieve optimal performance.
five conversion modes, which have different combina-
tions of speed and resolution to achieve the desired level
of performance. Other functions of the HCPL-0872 Digital
Interface IC include a Phase Locked Loop based pre-trigger
circuit that can either give more precise control of the ef-
fective sampling time or reduce conversion time to less
than 1 ꢄs, a fast over-range detection circuit that rapidly
indicates when the magnitude of the input signal is be-
yond full-scale, an adjustable threshold detection circuit
that indicates when the magnitude of the input signal is
above a user adjustable threshold level, an offset calibra-
tion circuit, and a second multiplexed input that allows a
second Isolated Modulator to be used with a single Digital
Interface IC.
HCPL-7860/HCPL-786J can be used together with HCPL-
0872, Digital Interface IC or a digital filter. The primary
functions of the HCPL-0872 Digital Interface IC are to de-
rive a multi-bit output signal by averaging the single-bit
modulator data, as well as to provide a direct microcon-
troller interface. The effective resolution of the multi-bit
output signal is a function of the length of time (measured
in modulator clock cycles) over which the average is taken;
averaging over longer periods of time results in higher
resolution. The Digital Interface IC can be configured for
The digital output format of the Isolated A/D Converter is
15 bits of unsigned binary data. The input full-scale range
and code assignment is shown in Table 1 below. Although
the output contains 15 bits of data, the effective resolution
is lower and is determined by selected conversion mode as
shown in Table 2 below.
Table 1. Input Full-Scale Range and Code Assignment.
Analog Input
Full Scale Range
Minimum Step Size
+Full Scale
Voltage Input
640 mV
20 ꢀV
Digital Output
32768 LSBs
1 LSB
+320 mV
0 mV
111111111111111
100000000000000
000000000000000
Zero
-Full Scale
-320 mV
Table 2. Isolated A/D Converter Typical Performance Characteristics.
Conversion Time (μsꢀ
Pre-Trigger Mode
Signal-to-
Noise Ratio
(dBꢀ
Effective
Resolution
(bitsꢀ
Signal
Delay(μsꢀ
Signal Band-
width (kHzꢀ
Conversion Mode
0
1
2
1
83
79
73
66
53
13.5
12.8
11.9
10.7
8.5
205
102
102
51
19
10
5
3.4
6.9
22
45
90
2
3
4
5
103
39
51
19
10
5
0.2
20
10
Notes: Bold italic type indicates Default values.
13
Power Supplies and Bypassing
An inexpensive 78L05 three-terminal regulator can also be
used to reduce the floating supply voltage to 5 V. To help
attenuate high-frequency power supply noise or ripple, a
resistor or inductor can be used in series with the input of
the regulator to form a low-pass filter with the regulator’s
input bypass capacitor.
The recommended application circuit is shown in Figure
17. A floating power supply (which in many applications
could be the same supply that is used to drive the high-
side power transistor) is regulated to 5 V using a simple
zener diode (D1); the value of resistor R1 should be chosen
to supply sufficient current from the existing floating sup-
ply. The voltage from the current sensing resistor or shunt
(Rsense) is applied to the input of the HCPL-7860/HCPL-
786J (U2) through an RC anti-aliasing filter (R2 and C2). And
finally, the output clock and data of the isolated modulator
are connected to the digital interface IC. Although the
application circuit is relatively simple, a few recommenda-
tions should be followed to ensure optimal performance.
As shown in Figure 17, 0.1 ꢄF bypass capacitors (C1 and
C3) should be located as close as possible to the input
and output power-supply pins of the isolated modulator
(U2). The bypass capacitors are required because of the
high-speed digital nature of the signals inside the isolated
modulator. A 0.01 ꢄF bypass capacitor (C2) is also recom-
mended at the input due to the switched-capacitor nature
of the input circuit. The input bypass capacitor also forms
part of the anti-aliasing filter, which is recommended to
prevent high-frequency noise from aliasing down to lower
frequencies and interfering with the input signal.
The power supply for the isolated modulator is most
often obtained from the same supply used to power the
power transistor gate drive circuit. If a dedicated supply is
required, in many cases it is possible to add an additional
winding on an existing transformer. Otherwise, some sort
of simple isolated supply can be used, such as a line pow-
ered transformer or a high-frequency DC-DC converter.
FLOATING
POSITIVE
SUPPLY
+ 5 V
HV+
GATE DRIVE
CIRCUIT
R1
CCLK
VDD
CHAN
SCLK
SDAT
CS
C1
D1
5.1 V
CLAT
0.1 μF
VDD1
VIN+
VIN-
VDD2
MCLK
MDAT
CDAT
R2 39 Ω
MCLK1
MDAT1
MCLK2
MDAT2
GND
MOTOR
+
-
THR1
OVR1
RESET
C3
0.1 μF
GND1
GND2
C2
0.01 μF
RSENSE
HCPL-7860ꢀ
HCPL-786J
TO
CONTROL
CIRCUIT
HCPL-0872
HV-
Figure 17. Recommended Application Circuit.
14
PC Board Layout
The maximum average power dissipation in the shunt
can also be easily calculated by multiplying the shunt
resistance times the square of the maximum RMS current,
which is about 1 W in the previous example.
The design of the printed circuit board (PCB) should follow
good layout practices, such as keeping bypass capacitors
close to the supply pins, keeping output signals away
from input signals, the use of ground and power planes,
etc. In addition, the layout of the PCB can also affect the
isolation transient immunity (CMR) of the isolated modu-
lator, due primarily to stray capacitive coupling between
the input and the output circuits. To obtain optimal CMR
performance, the layout of the PC board should minimize
any stray coupling by maintaining the maximum possible
distance between the input and output sides of the circuit
and ensuring that any ground or power plane on the PC
board does not pass directly below or extend much wider
than the body of the isolated modulator.
If the power dissipation in the shunt is too high, the resis-
tance of the shunt can be decreased below the maximum
value to decrease power dissipation. The minimum value
of the shunt is limited by precision and accuracy require-
ments of the design. As the shunt value is reduced, the
output voltage across the shunt is also reduced, which
means that the offset and noise, which are fixed, become
a larger percentage of the signal amplitude. The selected
value of the shunt will fall somewhere between the mini-
mum and maximum values, depending on the particular
requirements of a specific design.
Shunt Resistors
When sensing currents large enough to cause significant
heating of the shunt, the temperature coefficient (tempco)
of the shunt can introduce nonlinearity due to the sig-
nal dependent temperature rise of the shunt. The effect
increases as the shunt-to-ambient thermal resistance
increases. This effect can be minimized either by reducing
the thermal resistance of the shunt or by using a shunt
with a lower tempco. Lowering the thermal resistance can
be accomplished by repositioning the shunt on the PC
board, by using larger PC board traces to carry away more
heat, or by using a heat sink.
The current-sensing shunt resistor should have low re-
sistance (to minimize power dissipation), low inductance
(to minimize di/dt induced voltage spikes which could
adversely affect operation), and reasonable tolerance (to
maintain overall circuit accuracy). Choosing a particular
value for the shunt is usually a compromise between
minimizing power dissipation and maximizing accuracy.
Smaller shunt resistances decrease power dissipation,
while larger shunt resistances can improve circuit accuracy
by utilizing the full input range of the isolated modulator.
The first step in selecting a shunt is determining how much
current the shunt will be sensing. The graph in Figure 18
shows the RMS current in each phase of a three-phase
induction motor as a function of average motor output
power (in horsepower, hp) and motor drive supply volt-
age. The maximum value of the shunt is determined by the
current being measured and the maximum recommended
input voltage of the isolated modulator. The maximum
shunt resistance can be calculated by taking the maximum
recommended input voltage and dividing by the peak cur-
rent that the shunt should see during normal operation.
For example, if a motor will have a maximum RMS current
of 10 A and can experience up to 50% overloads during
normal operation, then the peak current is 21.1 A (= 10 x
1.414 x 1.5). Assuming a maximum input voltage of 200
mV, the maximum value of shunt resistance in this case
would be about 10 mꢆ.
40
440
35
30
25
20
15
380
220
120
10
5
0
0
5
10
15
20
25
30
35
MOTOR PHASE CURRENT - A (rmsꢀ
Figure 18. Motor Output Horsepower vs. Motor Phase Current and Supply
Voltage.
15
For a two-terminal shunt, as the value of shunt resistance the increased power dissipation at higher currents.
decreases, the resistance of the leads becomes a signifi-
When laying out a PC board for the shunts, a couple of
cant percentage of the total shunt resistance. This has two
points should be kept in mind. The Kelvin connections
primary effects on shunt accuracy. First, the effective resis-
to the shunt should be brought together under the body
tance of the shunt can become dependent on factors such
of the shunt and then run very close to each other to the
as how long the leads are, how they are bent, how far they
input of the isolated modulator; this minimizes the loop
are inserted into the board, and how far solder wicks up
area of the connection and reduces the possibility of stray
the lead during assembly (these issues will be discussed in
magnetic fields from interfering with the measured signal.
more detail shortly). Second, the leads are typically made
If the shunt is not located on the same PC board as the
from a material such as copper, which has a much higher
isolated modulator circuit, a tightly twisted pair of wires
tempco than the material from which the resistive element
can accomplish the same thing.
itself is made, resulting in a higher tempco for the shunt
overall. Both of these effects are eliminated when a four- Also, multiple layers of the PC board can be used to in-
terminal shunt is used. A four-terminal shunt has two ad- crease current carrying capacity. Numerous plated-through
ditional terminals that are Kelvin-connected directly across
vias should surround each non-Kelvin terminal of the shunt
the resistive element itself; these two terminals are used to help distribute the current between the layers of the PC
to monitor the voltage across the resistive element while board. The PC board should use 2 or 4 oz. copper for the
the other two terminals are used to carry the load current.
layers, resulting in a current carrying capacity in excess of
Because of the Kelvin connection, any voltage drops across 20 A. Making the current carrying traces on the PC board
the leads carrying the load current should have no impact fairly large can also improve the shunt’s power dissipa-
on the measured voltage.
tion capability by acting as a heat sink. Liberal use of vias
where the load current enters and exits the PC board is
also recommended.
Several four-terminal shunts from Isotek (Isabellenhütte)
suitable for sensing currents in motor drives up to 71
Arms (71 hp or 53 kW) are shown in Table 3; the maximum
current and motor power range for each of the PBV series
shunts are indicated. For shunt resistances from 50 mꢆ
down to 10 mꢆ, the maximum current is limited by the
input voltage range of the isolated modulator. For the 5
mꢆ and 2 mꢆ shunts, a heat sink may be required due to
Table 3. Isotek (Isabellenhütteꢀ Four-Terminal Shunt Summary.
Maximum RMS Cur-
rent
Motor Power Range
120 V - 440 V
Shunt Resistance
Tol.
AC
AC
Shunt Resistor
Part Number
mꢆ
%
A
hp
kW
PBV-R050-0.5
PBV-R020-0.5
PBV-R010-0.5
PBV-R005-0.5
PBV-R002-0.5
50
0.5
3
0.8 - 3
2 - 7
0.6 - 2
0.6 - 2
20
10
5
0.5
0.5
0.5
0.5
7
14
4 - 14
3 - 10
25 [28]
39 [71]
7 - 25 [8 - 28]
11 - 39 [19 - 71]
5 - 19 [6 - 21]
8 - 29 [14 - 53]
2
Note: Values in brackets are with a heatsink for the shunt.
16
Shunt Connections
In some applications, however, supply currents flowing
through the power-supply return path may cause offset
or noise problems. In this case, better performance may
The recommended method for connecting the isolated
modulator to the shunt resistor is shown in Figure 17. V
IN+
(pin 2 of the HPCL-7860/HCPL-786J) is connected to the
be obtained by connecting V
and V directly across
positive terminal of the shunt resistor, while V (pin 3) is
IN+
IN-
IN-
the shunt resistor with two conductors, and connecting
GND1 to the shunt resistor with a third conductor for the
power-supply return path, as shown in Figure 19. When
connected this way, both input pins should be bypassed.
To minimize electromagnetic interference of the sense sig-
nal, all of the conductors (whether two or three are used)
connecting the isolated modulator to the sense resistor
should be either twisted pair wire or closely spaced traces
on a PC board.
shorted to GND1 with the power-supply return path func-
tioning as the sense line to the negative terminal of the
current shunt. This allows a single pair of wires or PC board
traces to connect the isolated modulator circuit to the
shunt resistor. By referencing the input circuit to the nega-
tive side of the sense resistor, any load current induced
noise transients on the shunt are seen as a common-mode
signal and will not interfere with the current-sense signal.
This is important because the large load currents flowing
through the motor drive, along with the parasitic induc-
tances inherent in the wiring of the circuit, can generate
both noise spikes and offsets that are relatively large com-
pared to the small voltages that are being measured across
the current shunt.
The 39 ꢆ resistor in series with the input lead (R2) forms
a lowpass anti-aliasing filter with the 0.01 ꢄF input bypass
capacitor (C2) with a 400 kHz bandwidth. The resistor per-
forms another important function as well; it dampens any
ringing which might be present in the circuit formed by
the shunt, the input bypass capacitor, and the inductance
of wires or traces connecting the two. Undamped ringing
of the input circuit near the input sampling frequency can
alias into the baseband producing what might appear to
be noise at the output of the device.
If the same power supply is used both for the gate drive cir-
cuit and for the current sensing circuit, it is very important
that the connection from GND1 of the isolated modulator
to the sense resistor be the only return path for supply cur-
rent to the gate drive power supply in order to eliminate
potential ground loop problems. The only direct connec-
tion between the isolated modulator circuit and the gate
drive circuit should be the positive power supply line.
FLOATING
POSITIVE
SUPPLY
HV+
GATE DRIVE
CIRCUIT
R1
D1
5.1 V
C1
0.1 μF
R2a 39 Ω
VDD1
VIN+
VIN-
VDD2
R2b 39 Ω
MCLK
MDAT
MOTOR
+
-
GND1 GND2
C2a
0.01 μF
C2b
0.01 μF
RSENSE
HCPL-7860ꢀ
HCPL-786J
HV-
Figure 19. Schematic for Three Conductor Shunt Connection.
17
Voltage Sensing
The HCPL-7860/HCPL-786J Isolated Modulator can also
be used to isolate signals with amplitudes larger than its
recommended input range with the use of a resistive volt-
age divider at its input. The only restrictions are that the
impedance of the divider be relatively small (less than 1
kꢆ) so that the input resistance (280 kꢆ) and input bias
current (1 ꢄA) do not affect the accuracy of the measure-
ment. An input bypass capacitor is still required, although
the 39 ꢆ series damping resistor is not (the resistance of
the voltage divider provides the same function). The low-
pass filter formed by the divider resistance and the input
bypass capacitor may limit the achievable bandwidth. To
obtain higher bandwidth, the input bypass capacitor (C2)
can be reduced, but it should not be reduced much below
1000 pF to maintain adequate input bypassing of the iso-
lated modulator.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. Obsoletes 5989-2166EN
AV02-0409EN - March 28, 2011
相关型号：
HCPL-786J
The HCPL-7860/HCPL-786J Optically Isolated Modulator and HCPL-0872 Digital Interface IC or digital filter together form an isolated programmable two-chip analog-to-digital converter.
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